content
stringlengths 1
1.04M
⌀ |
|---|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
use work.io_bus_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity usb_host_io is
generic (
g_simulation : boolean := false );
port (
ulpi_clock : in std_logic;
ulpi_reset : in std_logic;
-- ULPI Interface
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
-- LED interface
usb_busy : out std_logic;
-- register interface bus
sys_clock : in std_logic;
sys_reset : in std_logic;
sys_io_req : in t_io_req;
sys_io_resp : out t_io_resp );
end usb_host_io;
architecture wrap of usb_host_io is
signal descr_addr : std_logic_vector(8 downto 0);
signal descr_rdata : std_logic_vector(31 downto 0);
signal descr_wdata : std_logic_vector(31 downto 0);
signal descr_en : std_logic;
signal descr_we : std_logic;
signal buf_addr : std_logic_vector(10 downto 0);
signal buf_rdata : std_logic_vector(7 downto 0);
signal buf_wdata : std_logic_vector(7 downto 0);
signal buf_en : std_logic;
signal buf_we : std_logic;
signal tx_busy : std_logic;
signal tx_ack : std_logic;
signal send_token : std_logic;
signal send_handsh : std_logic;
signal tx_pid : std_logic_vector(3 downto 0);
signal tx_token : std_logic_vector(10 downto 0);
signal send_data : std_logic;
signal no_data : std_logic;
signal user_data : std_logic_vector(7 downto 0);
signal user_last : std_logic;
signal user_next : std_logic;
signal rx_pid : std_logic_vector(3 downto 0) := X"0";
signal rx_token : std_logic_vector(10 downto 0) := (others => '0');
signal valid_token : std_logic := '0';
signal valid_handsh : std_logic := '0';
signal valid_packet : std_logic := '0';
signal data_valid : std_logic := '0';
signal data_start : std_logic := '0';
signal data_out : std_logic_vector(7 downto 0) := X"12";
signal rx_error : std_logic := '0';
signal tx_data : std_logic_vector(7 downto 0) := X"00";
signal tx_last : std_logic := '0';
signal tx_valid : std_logic := '0';
signal tx_start : std_logic := '0';
signal tx_next : std_logic := '0';
signal rx_data : std_logic_vector(7 downto 0);
signal status : std_logic_vector(7 downto 0);
signal rx_last : std_logic;
signal rx_valid : std_logic;
signal rx_store : std_logic;
signal rx_register : std_logic;
signal reg_read : std_logic := '0';
signal reg_write : std_logic;
signal reg_ack : std_logic;
signal reg_addr : std_logic_vector(5 downto 0);
signal reg_wdata : std_logic_vector(7 downto 0);
-- signal reset_pkt : std_logic;
-- signal reset_valid : std_logic;
-- signal reset_last : std_logic;
-- signal reset_data : std_logic_vector(7 downto 0);
signal send_reset_data : std_logic;
signal reset_last : std_logic;
signal reset_data : std_logic_vector(7 downto 0);
signal reset_done : std_logic;
signal sof_enable : std_logic;
signal scan_enable : std_logic;
signal speed : std_logic_vector(1 downto 0);
signal abort : std_logic;
signal sys_addr_i : std_logic_vector(sys_io_req.address'range);
signal sys_buf_en : std_logic;
signal sys_descr_en : std_logic;
signal sys_sel_d : std_logic_vector(2 downto 0);
signal sys_buf_rdata : std_logic_vector(7 downto 0);
signal sys_descr_rdata : std_logic_vector(7 downto 0);
signal sys_cmd_read : std_logic;
signal sys_cmd_write : std_logic;
signal sys_cmd_rdata : std_logic_vector(7 downto 0);
signal sys_cmd_full : std_logic;
signal sys_cmd_count : std_logic_vector(2 downto 0);
signal sys_resp_get : std_logic;
signal sys_resp_data : std_logic_vector(8 downto 0);
signal sys_resp_empty : std_logic;
signal cmd_get : std_logic;
signal cmd_empty : std_logic;
signal cmd_data : std_logic_vector(7 downto 0);
signal resp_put : std_logic;
signal resp_full : std_logic;
signal resp_data : std_logic_vector(8 downto 0);
begin
i_host: entity work.ulpi_host
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- Descriptor RAM interface
descr_addr => descr_addr,
descr_rdata => descr_rdata,
descr_wdata => descr_wdata,
descr_en => descr_en,
descr_we => descr_we,
-- Buffer RAM interface
buf_addr => buf_addr,
buf_rdata => buf_rdata,
buf_wdata => buf_wdata,
buf_en => buf_en,
buf_we => buf_we,
-- Transmit Path Interface
tx_busy => tx_busy,
tx_ack => tx_ack,
-- Interface to send tokens and handshakes
send_token => send_token,
send_handsh => send_handsh,
tx_pid => tx_pid,
tx_token => tx_token,
-- Interface to send data packets
send_data => send_data,
no_data => no_data,
user_data => user_data,
user_last => user_last,
user_next => user_next,
-- Interface to bus reset unit
reset_done => reset_done,
sof_enable => sof_enable,
scan_enable => scan_enable,
speed => speed,
abort => abort,
-- Receive Path Interface
rx_pid => rx_pid,
rx_token => rx_token,
valid_token => valid_token,
valid_handsh => valid_handsh,
valid_packet => valid_packet,
data_valid => data_valid,
data_start => data_start,
data_out => data_out,
rx_error => rx_error );
i_descr_ram: RAMB16_S9_S36
port map (
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_descr_en,
WEA => sys_io_req.write,
ADDRA => sys_addr_i(10 downto 0),
DIA => sys_io_req.data,
DIPA => "0",
DOA => sys_descr_rdata,
CLKB => ulpi_clock,
SSRB => ulpi_reset,
ENB => descr_en,
WEB => descr_we,
ADDRB => descr_addr,
DIB => descr_wdata,
DIPB => X"0",
DOB => descr_rdata );
i_buf_ram: RAMB16_S9_S9
port map (
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_buf_en,
WEA => sys_io_req.write,
ADDRA => sys_addr_i(10 downto 0),
DIA => sys_io_req.data,
DIPA => "0",
DOA => sys_buf_rdata,
CLKB => ulpi_clock,
SSRB => ulpi_reset,
ENB => buf_en,
WEB => buf_we,
ADDRB => buf_addr(10 downto 0),
DIB => buf_wdata,
DIPB => "0",
DOB => buf_rdata );
i_tx: entity work.ulpi_tx
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- Bus Interface
tx_start => tx_start,
tx_last => tx_last,
tx_valid => tx_valid,
tx_next => tx_next,
tx_data => tx_data,
-- Status
speed => speed,
status => status,
busy => tx_busy,
tx_ack => tx_ack,
-- Interface to send tokens
send_token => send_token,
send_handsh => send_handsh,
pid => tx_pid,
token => tx_token,
-- Interface to send data packets
send_data => send_data,
user_data => user_data,
user_last => user_last,
user_next => user_next,
-- Interface to read/write registers and reset packets
send_reset_data => send_reset_data,
reset_data => reset_data(0),
reset_last => reset_last );
i_rx: entity work.ulpi_rx
generic map (
g_allow_token => false )
port map (
clock => ulpi_clock,
reset => ulpi_reset,
rx_data => rx_data,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store,
pid => rx_pid,
token => rx_token,
valid_token => valid_token,
valid_handsh => valid_handsh,
valid_packet => valid_packet,
data_out => data_out,
data_valid => data_valid,
data_start => data_start,
error => rx_error );
i_bus: entity work.ulpi_bus
port map (
clock => ulpi_clock,
reset => ulpi_reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
status => status,
-- register interface
reg_read => reg_read,
reg_write => reg_write,
reg_address => reg_addr,
reg_wdata => reg_wdata,
reg_ack => reg_ack,
-- stream interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_last => rx_last,
rx_register => rx_register,
rx_store => rx_store,
rx_valid => rx_valid );
i_reset: entity work.bus_reset
generic map (
g_simulation => g_simulation )
port map (
clock => ulpi_clock,
reset => ulpi_reset,
reset_done => reset_done,
sof_enable => sof_enable,
scan_enable => scan_enable,
speed => speed,
abort => abort,
-- Command / response interface
cmd_get => cmd_get,
cmd_empty => cmd_empty,
cmd_data => cmd_data,
resp_put => resp_put,
resp_full => resp_full,
resp_data => resp_data,
-- status
status => status,
usb_busy => usb_busy,
-- register interface
reg_read => reg_read,
reg_write => reg_write,
reg_rdata => rx_data,
reg_wdata => reg_wdata,
reg_address => reg_addr,
reg_ack => reg_ack,
-- interface to packet transmitter
send_packet => send_reset_data,
user_data => reset_data,
user_last => reset_last,
user_valid => open );
i_cmd_fifo: entity work.async_fifo
generic map (
g_data_width => 8,
g_depth_bits => 3,
g_count_bits => 3,
g_threshold => 3,
g_storage => "distributed" )
port map (
-- write port signals (synchronized to write clock)
wr_clock => sys_clock,
wr_reset => sys_reset,
wr_en => sys_cmd_write,
wr_din => sys_io_req.data,
wr_flush => '0',
wr_count => sys_cmd_count,
wr_full => open,
wr_almost_full => sys_cmd_full,
wr_error => open,
wr_inhibit => open,
-- read port signals (synchronized to read clock)
rd_clock => ulpi_clock,
rd_reset => ulpi_reset,
rd_en => cmd_get,
rd_dout => cmd_data,
rd_count => open,
rd_empty => cmd_empty,
rd_almost_empty => open,
rd_error => open );
i_resp_fifo: entity work.async_fifo
generic map (
g_data_width => 9,
g_depth_bits => 3,
g_count_bits => 3,
g_threshold => 3,
g_storage => "distributed" )
port map (
-- write port signals (synchronized to write clock)
wr_clock => ulpi_clock,
wr_reset => ulpi_reset,
wr_en => resp_put,
wr_din => resp_data,
wr_flush => '0',
wr_count => open,
wr_full => resp_full,
wr_almost_full => open,
wr_error => open,
wr_inhibit => open,
-- read port signals (synchronized to read clock)
rd_clock => sys_clock,
rd_reset => sys_reset,
rd_en => sys_resp_get,
rd_dout => sys_resp_data,
rd_count => open,
rd_empty => sys_resp_empty,
rd_almost_empty => open,
rd_error => open );
-- BUS INTERFACE --
-- command / response output word generator
process(sys_clock)
begin
if rising_edge(sys_clock) then
sys_resp_get <= '0';
case sys_io_req.address(1 downto 0) is
when "00" =>
sys_cmd_rdata <= sys_resp_data(7 downto 0);
when "01" =>
sys_cmd_rdata <= not sys_resp_empty & "000000" & sys_resp_data(8);
when "10" =>
sys_cmd_rdata <= sys_cmd_full & "0000" & sys_cmd_count;
when "11" =>
sys_cmd_rdata <= X"00";
sys_resp_get <= sys_cmd_read; -- if reading, we'll pull one
when others =>
null;
end case;
end if;
end process;
sys_addr_i(sys_addr_i'high downto 0) <= std_logic_vector(sys_io_req.address(sys_addr_i'range));
sys_buf_en <= (sys_io_req.read or sys_io_req.write) and sys_io_req.address(12);
sys_descr_en <= (sys_io_req.read or sys_io_req.write) and not sys_io_req.address(12) and not sys_io_req.address(11);
sys_cmd_read <= sys_io_req.read and not sys_io_req.address(12) and sys_io_req.address(11);
sys_cmd_write <= sys_io_req.write and not sys_io_req.address(12) and sys_io_req.address(11);
process(sys_clock)
begin
if rising_edge(sys_clock) then
sys_io_resp.ack <= sys_io_req.read or sys_io_req.write;
sys_sel_d <= sys_io_req.read & std_logic_vector(sys_io_req.address(12 downto 11));
end if;
end process;
with sys_sel_d select sys_io_resp.data <=
sys_buf_rdata when "110" | "111",
sys_descr_rdata when "100",
sys_cmd_rdata when "101",
X"00" when others;
end wrap;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
use work.io_bus_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity usb_host_io is
generic (
g_simulation : boolean := false );
port (
ulpi_clock : in std_logic;
ulpi_reset : in std_logic;
-- ULPI Interface
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
-- LED interface
usb_busy : out std_logic;
-- register interface bus
sys_clock : in std_logic;
sys_reset : in std_logic;
sys_io_req : in t_io_req;
sys_io_resp : out t_io_resp );
end usb_host_io;
architecture wrap of usb_host_io is
signal descr_addr : std_logic_vector(8 downto 0);
signal descr_rdata : std_logic_vector(31 downto 0);
signal descr_wdata : std_logic_vector(31 downto 0);
signal descr_en : std_logic;
signal descr_we : std_logic;
signal buf_addr : std_logic_vector(10 downto 0);
signal buf_rdata : std_logic_vector(7 downto 0);
signal buf_wdata : std_logic_vector(7 downto 0);
signal buf_en : std_logic;
signal buf_we : std_logic;
signal tx_busy : std_logic;
signal tx_ack : std_logic;
signal send_token : std_logic;
signal send_handsh : std_logic;
signal tx_pid : std_logic_vector(3 downto 0);
signal tx_token : std_logic_vector(10 downto 0);
signal send_data : std_logic;
signal no_data : std_logic;
signal user_data : std_logic_vector(7 downto 0);
signal user_last : std_logic;
signal user_next : std_logic;
signal rx_pid : std_logic_vector(3 downto 0) := X"0";
signal rx_token : std_logic_vector(10 downto 0) := (others => '0');
signal valid_token : std_logic := '0';
signal valid_handsh : std_logic := '0';
signal valid_packet : std_logic := '0';
signal data_valid : std_logic := '0';
signal data_start : std_logic := '0';
signal data_out : std_logic_vector(7 downto 0) := X"12";
signal rx_error : std_logic := '0';
signal tx_data : std_logic_vector(7 downto 0) := X"00";
signal tx_last : std_logic := '0';
signal tx_valid : std_logic := '0';
signal tx_start : std_logic := '0';
signal tx_next : std_logic := '0';
signal rx_data : std_logic_vector(7 downto 0);
signal status : std_logic_vector(7 downto 0);
signal rx_last : std_logic;
signal rx_valid : std_logic;
signal rx_store : std_logic;
signal rx_register : std_logic;
signal reg_read : std_logic := '0';
signal reg_write : std_logic;
signal reg_ack : std_logic;
signal reg_addr : std_logic_vector(5 downto 0);
signal reg_wdata : std_logic_vector(7 downto 0);
-- signal reset_pkt : std_logic;
-- signal reset_valid : std_logic;
-- signal reset_last : std_logic;
-- signal reset_data : std_logic_vector(7 downto 0);
signal send_reset_data : std_logic;
signal reset_last : std_logic;
signal reset_data : std_logic_vector(7 downto 0);
signal reset_done : std_logic;
signal sof_enable : std_logic;
signal scan_enable : std_logic;
signal speed : std_logic_vector(1 downto 0);
signal abort : std_logic;
signal sys_addr_i : std_logic_vector(sys_io_req.address'range);
signal sys_buf_en : std_logic;
signal sys_descr_en : std_logic;
signal sys_sel_d : std_logic_vector(2 downto 0);
signal sys_buf_rdata : std_logic_vector(7 downto 0);
signal sys_descr_rdata : std_logic_vector(7 downto 0);
signal sys_cmd_read : std_logic;
signal sys_cmd_write : std_logic;
signal sys_cmd_rdata : std_logic_vector(7 downto 0);
signal sys_cmd_full : std_logic;
signal sys_cmd_count : std_logic_vector(2 downto 0);
signal sys_resp_get : std_logic;
signal sys_resp_data : std_logic_vector(8 downto 0);
signal sys_resp_empty : std_logic;
signal cmd_get : std_logic;
signal cmd_empty : std_logic;
signal cmd_data : std_logic_vector(7 downto 0);
signal resp_put : std_logic;
signal resp_full : std_logic;
signal resp_data : std_logic_vector(8 downto 0);
begin
i_host: entity work.ulpi_host
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- Descriptor RAM interface
descr_addr => descr_addr,
descr_rdata => descr_rdata,
descr_wdata => descr_wdata,
descr_en => descr_en,
descr_we => descr_we,
-- Buffer RAM interface
buf_addr => buf_addr,
buf_rdata => buf_rdata,
buf_wdata => buf_wdata,
buf_en => buf_en,
buf_we => buf_we,
-- Transmit Path Interface
tx_busy => tx_busy,
tx_ack => tx_ack,
-- Interface to send tokens and handshakes
send_token => send_token,
send_handsh => send_handsh,
tx_pid => tx_pid,
tx_token => tx_token,
-- Interface to send data packets
send_data => send_data,
no_data => no_data,
user_data => user_data,
user_last => user_last,
user_next => user_next,
-- Interface to bus reset unit
reset_done => reset_done,
sof_enable => sof_enable,
scan_enable => scan_enable,
speed => speed,
abort => abort,
-- Receive Path Interface
rx_pid => rx_pid,
rx_token => rx_token,
valid_token => valid_token,
valid_handsh => valid_handsh,
valid_packet => valid_packet,
data_valid => data_valid,
data_start => data_start,
data_out => data_out,
rx_error => rx_error );
i_descr_ram: RAMB16_S9_S36
port map (
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_descr_en,
WEA => sys_io_req.write,
ADDRA => sys_addr_i(10 downto 0),
DIA => sys_io_req.data,
DIPA => "0",
DOA => sys_descr_rdata,
CLKB => ulpi_clock,
SSRB => ulpi_reset,
ENB => descr_en,
WEB => descr_we,
ADDRB => descr_addr,
DIB => descr_wdata,
DIPB => X"0",
DOB => descr_rdata );
i_buf_ram: RAMB16_S9_S9
port map (
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_buf_en,
WEA => sys_io_req.write,
ADDRA => sys_addr_i(10 downto 0),
DIA => sys_io_req.data,
DIPA => "0",
DOA => sys_buf_rdata,
CLKB => ulpi_clock,
SSRB => ulpi_reset,
ENB => buf_en,
WEB => buf_we,
ADDRB => buf_addr(10 downto 0),
DIB => buf_wdata,
DIPB => "0",
DOB => buf_rdata );
i_tx: entity work.ulpi_tx
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- Bus Interface
tx_start => tx_start,
tx_last => tx_last,
tx_valid => tx_valid,
tx_next => tx_next,
tx_data => tx_data,
-- Status
speed => speed,
status => status,
busy => tx_busy,
tx_ack => tx_ack,
-- Interface to send tokens
send_token => send_token,
send_handsh => send_handsh,
pid => tx_pid,
token => tx_token,
-- Interface to send data packets
send_data => send_data,
user_data => user_data,
user_last => user_last,
user_next => user_next,
-- Interface to read/write registers and reset packets
send_reset_data => send_reset_data,
reset_data => reset_data(0),
reset_last => reset_last );
i_rx: entity work.ulpi_rx
generic map (
g_allow_token => false )
port map (
clock => ulpi_clock,
reset => ulpi_reset,
rx_data => rx_data,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store,
pid => rx_pid,
token => rx_token,
valid_token => valid_token,
valid_handsh => valid_handsh,
valid_packet => valid_packet,
data_out => data_out,
data_valid => data_valid,
data_start => data_start,
error => rx_error );
i_bus: entity work.ulpi_bus
port map (
clock => ulpi_clock,
reset => ulpi_reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
status => status,
-- register interface
reg_read => reg_read,
reg_write => reg_write,
reg_address => reg_addr,
reg_wdata => reg_wdata,
reg_ack => reg_ack,
-- stream interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_last => rx_last,
rx_register => rx_register,
rx_store => rx_store,
rx_valid => rx_valid );
i_reset: entity work.bus_reset
generic map (
g_simulation => g_simulation )
port map (
clock => ulpi_clock,
reset => ulpi_reset,
reset_done => reset_done,
sof_enable => sof_enable,
scan_enable => scan_enable,
speed => speed,
abort => abort,
-- Command / response interface
cmd_get => cmd_get,
cmd_empty => cmd_empty,
cmd_data => cmd_data,
resp_put => resp_put,
resp_full => resp_full,
resp_data => resp_data,
-- status
status => status,
usb_busy => usb_busy,
-- register interface
reg_read => reg_read,
reg_write => reg_write,
reg_rdata => rx_data,
reg_wdata => reg_wdata,
reg_address => reg_addr,
reg_ack => reg_ack,
-- interface to packet transmitter
send_packet => send_reset_data,
user_data => reset_data,
user_last => reset_last,
user_valid => open );
i_cmd_fifo: entity work.async_fifo
generic map (
g_data_width => 8,
g_depth_bits => 3,
g_count_bits => 3,
g_threshold => 3,
g_storage => "distributed" )
port map (
-- write port signals (synchronized to write clock)
wr_clock => sys_clock,
wr_reset => sys_reset,
wr_en => sys_cmd_write,
wr_din => sys_io_req.data,
wr_flush => '0',
wr_count => sys_cmd_count,
wr_full => open,
wr_almost_full => sys_cmd_full,
wr_error => open,
wr_inhibit => open,
-- read port signals (synchronized to read clock)
rd_clock => ulpi_clock,
rd_reset => ulpi_reset,
rd_en => cmd_get,
rd_dout => cmd_data,
rd_count => open,
rd_empty => cmd_empty,
rd_almost_empty => open,
rd_error => open );
i_resp_fifo: entity work.async_fifo
generic map (
g_data_width => 9,
g_depth_bits => 3,
g_count_bits => 3,
g_threshold => 3,
g_storage => "distributed" )
port map (
-- write port signals (synchronized to write clock)
wr_clock => ulpi_clock,
wr_reset => ulpi_reset,
wr_en => resp_put,
wr_din => resp_data,
wr_flush => '0',
wr_count => open,
wr_full => resp_full,
wr_almost_full => open,
wr_error => open,
wr_inhibit => open,
-- read port signals (synchronized to read clock)
rd_clock => sys_clock,
rd_reset => sys_reset,
rd_en => sys_resp_get,
rd_dout => sys_resp_data,
rd_count => open,
rd_empty => sys_resp_empty,
rd_almost_empty => open,
rd_error => open );
-- BUS INTERFACE --
-- command / response output word generator
process(sys_clock)
begin
if rising_edge(sys_clock) then
sys_resp_get <= '0';
case sys_io_req.address(1 downto 0) is
when "00" =>
sys_cmd_rdata <= sys_resp_data(7 downto 0);
when "01" =>
sys_cmd_rdata <= not sys_resp_empty & "000000" & sys_resp_data(8);
when "10" =>
sys_cmd_rdata <= sys_cmd_full & "0000" & sys_cmd_count;
when "11" =>
sys_cmd_rdata <= X"00";
sys_resp_get <= sys_cmd_read; -- if reading, we'll pull one
when others =>
null;
end case;
end if;
end process;
sys_addr_i(sys_addr_i'high downto 0) <= std_logic_vector(sys_io_req.address(sys_addr_i'range));
sys_buf_en <= (sys_io_req.read or sys_io_req.write) and sys_io_req.address(12);
sys_descr_en <= (sys_io_req.read or sys_io_req.write) and not sys_io_req.address(12) and not sys_io_req.address(11);
sys_cmd_read <= sys_io_req.read and not sys_io_req.address(12) and sys_io_req.address(11);
sys_cmd_write <= sys_io_req.write and not sys_io_req.address(12) and sys_io_req.address(11);
process(sys_clock)
begin
if rising_edge(sys_clock) then
sys_io_resp.ack <= sys_io_req.read or sys_io_req.write;
sys_sel_d <= sys_io_req.read & std_logic_vector(sys_io_req.address(12 downto 11));
end if;
end process;
with sys_sel_d select sys_io_resp.data <=
sys_buf_rdata when "110" | "111",
sys_descr_rdata when "100",
sys_cmd_rdata when "101",
X"00" when others;
end wrap;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 2
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
component math_core
-- lingkang: must declare a component, unless ISE won't synthesize a black box
port (
clk : in std_logic;
rst : in std_logic;
ain : in std_logic_vector(0 to C_SLV_DWIDTH-1);
bin : in std_logic_vector(0 to C_SLV_DWIDTH-1);
result : out std_logic_vector(0 to C_SLV_DWIDTH-1);
statistic : out std_logic_vector(0 to C_SLV_DWIDTH-1) -- lingkang
);
end component math_core;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 1);
signal slv_reg_read_sel : std_logic_vector(0 to 1);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal result : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal statistic : std_logic_vector(0 to C_SLV_DWIDTH-1); -- lingkang
begin
--USER logic implementation added here
math_core_i : math_core
port map (
clk => Bus2IP_Clk,
rst => Bus2IP_Reset,
ain => slv_reg0,
bin => slv_reg1,
result => result,
statistic => statistic -- lingkang
);
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 1);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 1);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
else
case slv_reg_write_sel is
when "10" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "01" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, result, statistic ) is
begin
case slv_reg_read_sel is
when "10" => slv_ip2bus_data <= result;
when "01" => slv_ip2bus_data <= statistic; -- lingkang
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else (others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 2
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
component math_core
-- lingkang: must declare a component, unless ISE won't synthesize a black box
port (
clk : in std_logic;
rst : in std_logic;
ain : in std_logic_vector(0 to C_SLV_DWIDTH-1);
bin : in std_logic_vector(0 to C_SLV_DWIDTH-1);
result : out std_logic_vector(0 to C_SLV_DWIDTH-1);
statistic : out std_logic_vector(0 to C_SLV_DWIDTH-1) -- lingkang
);
end component math_core;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 1);
signal slv_reg_read_sel : std_logic_vector(0 to 1);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal result : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal statistic : std_logic_vector(0 to C_SLV_DWIDTH-1); -- lingkang
begin
--USER logic implementation added here
math_core_i : math_core
port map (
clk => Bus2IP_Clk,
rst => Bus2IP_Reset,
ain => slv_reg0,
bin => slv_reg1,
result => result,
statistic => statistic -- lingkang
);
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 1);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 1);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
else
case slv_reg_write_sel is
when "10" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "01" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, result, statistic ) is
begin
case slv_reg_read_sel is
when "10" => slv_ip2bus_data <= result;
when "01" => slv_ip2bus_data <= statistic; -- lingkang
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else (others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 2
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
component math_core
-- lingkang: must declare a component, unless ISE won't synthesize a black box
port (
clk : in std_logic;
rst : in std_logic;
ain : in std_logic_vector(0 to C_SLV_DWIDTH-1);
bin : in std_logic_vector(0 to C_SLV_DWIDTH-1);
result : out std_logic_vector(0 to C_SLV_DWIDTH-1);
statistic : out std_logic_vector(0 to C_SLV_DWIDTH-1) -- lingkang
);
end component math_core;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 1);
signal slv_reg_read_sel : std_logic_vector(0 to 1);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal result : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal statistic : std_logic_vector(0 to C_SLV_DWIDTH-1); -- lingkang
begin
--USER logic implementation added here
math_core_i : math_core
port map (
clk => Bus2IP_Clk,
rst => Bus2IP_Reset,
ain => slv_reg0,
bin => slv_reg1,
result => result,
statistic => statistic -- lingkang
);
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 1);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 1);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
else
case slv_reg_write_sel is
when "10" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "01" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, result, statistic ) is
begin
case slv_reg_read_sel is
when "10" => slv_ip2bus_data <= result;
when "01" => slv_ip2bus_data <= statistic; -- lingkang
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else (others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
--
-- Copyright 1991-2015 Mentor Graphics Corporation
--
-- All Rights Reserved.
--
-- THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
-- MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
--
entity test_counter is
PORT ( count : BUFFER bit_vector(8 downto 1));
end;
architecture only of test_counter is
COMPONENT counter
PORT ( count : BUFFER bit_vector(8 downto 1);
clk : IN bit;
reset : IN bit);
END COMPONENT ;
SIGNAL clk : bit := '0';
SIGNAL reset : bit := '0';
begin
dut : counter
PORT MAP (
count => count,
clk => clk,
reset => reset );
clock : PROCESS
begin
wait for 10 ns; clk <= not clk;
end PROCESS clock;
stimulus : PROCESS
begin
wait for 5 ns; reset <= '1';
wait for 4 ns; reset <= '0';
wait;
end PROCESS stimulus;
end only;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: netcomp
-- File: netcomp.vhd
-- Author: Jiri Gaisler - Aeroflex Gaisler
-- Description: Declaration of netlists components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use work.gencomp.all;
package netcomp is
---------------------------------------------------------------------------
-- netlists ---------------------------------------------------------------
---------------------------------------------------------------------------
component grusbhc_net is
generic (
tech : integer := 0;
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
memtech : integer range 0 to NTECH := DEFMEMTECH;
memsel : integer := 0;
syncprst : integer range 0 to 1 := 0;
sysfreq : integer := 65000;
pcidev : integer range 0 to 1 := 0;
debug : integer := 0;
debug_abits : integer := 12);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- grusb_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((nports*2)-1) downto 0);
termsel : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataho : out std_logic_vector(((nports*8)-1) downto 0);
validho : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
datao : out std_logic_vector(((nports*8)-1) downto 0);
utm_rst : out std_logic_vector((nports-1) downto 0);
dctrlo : out std_logic_vector((nports-1) downto 0);
suspendm : out std_ulogic;
dbus16_8 : out std_ulogic;
dppulldown : out std_ulogic;
dmpulldown : out std_ulogic;
idpullup : out std_ulogic;
dischrgvbus : out std_ulogic;
chrgvbus : out std_ulogic;
txbitstuffenable : out std_ulogic;
txbitstuffenableh : out std_ulogic;
fslsserialmode : out std_ulogic;
txenablen : out std_ulogic;
txdat : out std_ulogic;
txse0 : out std_ulogic;
-- grusb_in_type_vector unwrapped
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datahi : in std_logic_vector(((nports*8)-1) downto 0);
validhi : in std_logic_vector((nports-1) downto 0);
hostdisc : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
datai : in std_logic_vector(((nports*8)-1) downto 0);
urstdrive : in std_logic_vector((nports-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
bufsel : out std_ulogic;
-- scan signals
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic;
-- debug signals
debug_raddr : out std_logic_vector(15 downto 0);
debug_waddr : out std_logic_vector(15 downto 0);
debug_wdata : out std_logic_vector(31 downto 0);
debug_we : out std_ulogic;
debug_rdata : in std_logic_vector(31 downto 0));
end component;
component grspwc_net
generic(
tech : integer := 0;
sysfreq : integer := 40000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(9 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspwc2_net is
generic(
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1;
tech : integer;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk : in std_logic_vector(1 downto 0);
txclk : in std_ulogic;
txclkn : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--time iface
tickin : in std_logic;
tickinraw : in std_logic;
timein : in std_logic_vector(7 downto 0);
tickindone : out std_logic;
tickout : out std_logic;
tickoutraw : out std_logic;
timeout : out std_logic_vector(7 downto 0);
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(9 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(9 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic;
testrst : in std_logic;
testen : in std_logic;
rxdav : out std_logic;
rxdataout : out std_logic_vector(8 downto 0);
loopback : out std_logic
);
end component;
component grlfpw_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component grfpw_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 2 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component leon3ft_net
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0
);
port (
clk : in std_ulogic;
gclk : in std_ulogic;
rstn : in std_ulogic;
ahbix : in ahb_mst_in_type;
ahbox : out ahb_mst_out_type;
ahbsix : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
irqo_fpen: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_ulogic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss: out std_ulogic;
dbgo_istat_tmiss: out std_ulogic;
dbgo_istat_chold: out std_ulogic;
dbgo_istat_mhold: out std_ulogic;
dbgo_dstat_cmiss: out std_ulogic;
dbgo_dstat_tmiss: out std_ulogic;
dbgo_dstat_chold: out std_ulogic;
dbgo_dstat_mhold: out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic
);
end component;
component ftmctrl_net
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
edac : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0;
writefb : integer := 0;
wsshift : integer := 0;
tech : integer := 0
);
port (
rst: in Std_ULogic;
clk: in Std_ULogic;
ahbsi: in ahb_slv_in_type;
ahbso: out ahb_slv_out_type;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
memi_data: in Std_Logic_Vector(31 downto 0);
memi_brdyn: in Std_Logic;
memi_bexcn: in Std_Logic;
memi_writen: in Std_Logic;
memi_wrn: in Std_Logic_Vector(3 downto 0);
memi_bwidth: in Std_Logic_Vector(1 downto 0);
memi_sd: in Std_Logic_Vector(63 downto 0);
memi_cb: in Std_Logic_Vector(15 downto 0);
memi_scb: in Std_Logic_Vector(15 downto 0);
memi_edac: in Std_Logic;
memo_address: out Std_Logic_Vector(31 downto 0);
memo_data: out Std_Logic_Vector(31 downto 0);
memo_sddata: out Std_Logic_Vector(63 downto 0);
memo_ramsn: out Std_Logic_Vector(7 downto 0);
memo_ramoen: out Std_Logic_Vector(7 downto 0);
memo_ramn: out Std_ULogic;
memo_romn: out Std_ULogic;
memo_mben: out Std_Logic_Vector(3 downto 0);
memo_iosn: out Std_Logic;
memo_romsn: out Std_Logic_Vector(7 downto 0);
memo_oen: out Std_Logic;
memo_writen: out Std_Logic;
memo_wrn: out Std_Logic_Vector(3 downto 0);
memo_bdrive: out Std_Logic_Vector(3 downto 0);
memo_vbdrive: out Std_Logic_Vector(31 downto 0);
memo_svbdrive: out Std_Logic_Vector(63 downto 0);
memo_read: out Std_Logic;
memo_sa: out Std_Logic_Vector(14 downto 0);
memo_cb: out Std_Logic_Vector(15 downto 0);
memo_scb: out Std_Logic_Vector(15 downto 0);
memo_vcdrive: out Std_Logic_Vector(15 downto 0);
memo_svcdrive: out Std_Logic_Vector(15 downto 0);
memo_ce: out Std_ULogic;
sdo_sdcke: out Std_Logic_Vector( 1 downto 0);
sdo_sdcsn: out Std_Logic_Vector( 1 downto 0);
sdo_sdwen: out Std_ULogic;
sdo_rasn: out Std_ULogic;
sdo_casn: out Std_ULogic;
sdo_dqm: out Std_Logic_Vector( 7 downto 0);
wpo_wprothit: in Std_ULogic);
end component;
component ssrctrl_net
generic (
tech: Integer := 0;
bus16: Integer := 1);
port (
rst: in Std_Logic;
clk: in Std_Logic;
n_ahbsi_hsel: in Std_Logic_Vector(0 to 15);
n_ahbsi_haddr: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hwrite: in Std_Logic;
n_ahbsi_htrans: in Std_Logic_Vector(1 downto 0);
n_ahbsi_hsize: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hburst: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hwdata: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hprot: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hready: in Std_Logic;
n_ahbsi_hmaster: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hmastlock:in Std_Logic;
n_ahbsi_hmbsel: in Std_Logic_Vector(0 to 3);
n_ahbsi_hirq: in Std_Logic_Vector(31 downto 0);
n_ahbso_hready: out Std_Logic;
n_ahbso_hresp: out Std_Logic_Vector(1 downto 0);
n_ahbso_hrdata: out Std_Logic_Vector(31 downto 0);
n_ahbso_hsplit: out Std_Logic_Vector(15 downto 0);
n_ahbso_hirq: out Std_Logic_Vector(31 downto 0);
n_apbi_psel: in Std_Logic_Vector(0 to 15);
n_apbi_penable: in Std_Logic;
n_apbi_paddr: in Std_Logic_Vector(31 downto 0);
n_apbi_pwrite: in Std_Logic;
n_apbi_pwdata: in Std_Logic_Vector(31 downto 0);
n_apbi_pirq: in Std_Logic_Vector(31 downto 0);
n_apbo_prdata: out Std_Logic_Vector(31 downto 0);
n_apbo_pirq: out Std_Logic_Vector(31 downto 0);
n_sri_data: in Std_Logic_Vector(31 downto 0);
n_sri_brdyn: in Std_Logic;
n_sri_bexcn: in Std_Logic;
n_sri_writen: in Std_Logic;
n_sri_wrn: in Std_Logic_Vector(3 downto 0);
n_sri_bwidth: in Std_Logic_Vector(1 downto 0);
n_sri_sd: in Std_Logic_Vector(63 downto 0);
n_sri_cb: in Std_Logic_Vector(7 downto 0);
n_sri_scb: in Std_Logic_Vector(7 downto 0);
n_sri_edac: in Std_Logic;
n_sro_address: out Std_Logic_Vector(31 downto 0);
n_sro_data: out Std_Logic_Vector(31 downto 0);
n_sro_sddata: out Std_Logic_Vector(63 downto 0);
n_sro_ramsn: out Std_Logic_Vector(7 downto 0);
n_sro_ramoen: out Std_Logic_Vector(7 downto 0);
n_sro_ramn: out Std_Logic;
n_sro_romn: out Std_Logic;
n_sro_mben: out Std_Logic_Vector(3 downto 0);
n_sro_iosn: out Std_Logic;
n_sro_romsn: out Std_Logic_Vector(7 downto 0);
n_sro_oen: out Std_Logic;
n_sro_writen: out Std_Logic;
n_sro_wrn: out Std_Logic_Vector(3 downto 0);
n_sro_bdrive: out Std_Logic_Vector(3 downto 0);
n_sro_vbdrive: out Std_Logic_Vector(31 downto 0);
n_sro_svbdrive: out Std_Logic_Vector(63 downto 0);
n_sro_read: out Std_Logic;
n_sro_sa: out Std_Logic_Vector(14 downto 0);
n_sro_cb: out Std_Logic_Vector(7 downto 0);
n_sro_scb: out Std_Logic_Vector(7 downto 0);
n_sro_vcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_svcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_ce: out Std_Logic);
end component;
component ftsrctrl_net
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0;
srbanks : integer range 1 to 8 := 1;
banksz : integer range 0 to 15 := 15;
rombanks : integer range 1 to 8 := 1;
rombanksz : integer range 0 to 15 := 15;
rombankszdef : integer range 0 to 15 := 15;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 1 := 1;
errcnt : integer range 0 to 1 := 0;
cntbits : integer range 1 to 8 := 1;
wsreg : integer := 0;
oepol : integer := 0;
prom8en : integer := 0;
netlist : integer := 0;
tech : integer := 0
);
port (
rst: in Std_ULogic;
clk: in Std_ULogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri_data: in Std_Logic_Vector(31 downto 0); -- Data bus address
sri_brdyn: in Std_Logic;
sri_bexcn: in Std_Logic;
sri_writen: in Std_Logic;
sri_wrn: in Std_Logic_Vector(3 downto 0);
sri_bwidth: in Std_Logic_Vector(1 downto 0);
sri_sd: in Std_Logic_Vector(63 downto 0);
sri_cb: in Std_Logic_Vector(15 downto 0);
sri_scb: in Std_Logic_Vector(15 downto 0);
sri_edac: in Std_Logic;
sro_address: out Std_Logic_Vector(31 downto 0);
sro_data: out Std_Logic_Vector(31 downto 0);
sro_sddata: out Std_Logic_Vector(63 downto 0);
sro_ramsn: out Std_Logic_Vector(7 downto 0);
sro_ramoen: out Std_Logic_Vector(7 downto 0);
sro_ramn: out Std_ULogic;
sro_romn: out Std_ULogic;
sro_mben: out Std_Logic_Vector(3 downto 0);
sro_iosn: out Std_Logic;
sro_romsn: out Std_Logic_Vector(7 downto 0);
sro_oen: out Std_Logic;
sro_writen: out Std_Logic;
sro_wrn: out Std_Logic_Vector(3 downto 0);
sro_bdrive: out Std_Logic_Vector(3 downto 0);
sro_vbdrive: out Std_Logic_Vector(31 downto 0); --vector bus drive
sro_svbdrive: out Std_Logic_Vector(63 downto 0); --vector bus drive sdram
sro_read: out Std_Logic;
sro_sa: out Std_Logic_Vector(14 downto 0);
sro_cb: out Std_Logic_Vector(15 downto 0);
sro_scb: out Std_Logic_Vector(15 downto 0);
sro_vcdrive: out Std_Logic_Vector(15 downto 0); --vector bus drive cb
sro_svcdrive: out Std_Logic_Vector(15 downto 0); --vector bus drive cb sdram
sro_ce: out Std_ULogic;
sdo_sdcke: out Std_Logic_Vector( 1 downto 0); -- clk en
sdo_sdcsn: out Std_Logic_Vector( 1 downto 0); -- chip sel
sdo_sdwen: out Std_ULogic; -- write en
sdo_rasn: out Std_ULogic; -- row addr stb
sdo_casn: out Std_ULogic; -- col addr stb
sdo_dqm: out Std_Logic_Vector(15 downto 0); -- data i/o mask
sdo_bdrive: out Std_ULogic; -- bus drive
sdo_qdrive: out Std_ULogic; -- bus drive
sdo_vbdrive: out Std_Logic_Vector(31 downto 0); -- vector bus drive
sdo_address: out Std_Logic_Vector(16 downto 2); -- address out
sdo_data: out Std_Logic_Vector(127 downto 0); -- data out
sdo_cb: out Std_Logic_Vector(15 downto 0);
sdo_ce: out Std_ULogic;
sdo_ba: out Std_Logic_Vector(2 downto 0)); -- bank address
end component;
component grlfpw4_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0;
wrt : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(63 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(63 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component grfpw4_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 2 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(63 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(63 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component spictrl_net
generic (
tech : integer range 0 to NTECH := 0;
fdepth : integer range 1 to 7 := 1;
slvselen : integer range 0 to 1 := 0;
slvselsz : integer range 1 to 32 := 1;
oepol : integer range 0 to 1 := 0;
odmode : integer range 0 to 1 := 0;
automode : integer range 0 to 1 := 0;
acntbits : integer range 1 to 32 := 32;
aslvsel : integer range 0 to 1 := 0;
twen : integer range 0 to 1 := 1;
maxwlen : integer range 0 to 15 := 0;
automask0 : integer := 0;
automask1 : integer := 0;
automask2 : integer := 0;
automask3 : integer := 0);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbi_testen : in std_ulogic;
apbi_testrst : in std_ulogic;
apbi_scanen : in std_ulogic;
apbi_testoen : in std_ulogic;
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_pirq : out std_ulogic;
spii_miso : in std_ulogic;
spii_mosi : in std_ulogic;
spii_sck : in std_ulogic;
spii_spisel : in std_ulogic;
spii_astart : in std_ulogic;
spii_cstart : in std_ulogic;
spio_miso : out std_ulogic;
spio_misooen : out std_ulogic;
spio_mosi : out std_ulogic;
spio_mosioen : out std_ulogic;
spio_sck : out std_ulogic;
spio_sckoen : out std_ulogic;
spio_enable : out std_ulogic;
spio_astart : out std_ulogic;
spio_aready : out std_ulogic;
slvsel : out std_logic_vector((slvselsz-1) downto 0));
end component;
component leon4_net
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 31 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0
);
port (
clk : in std_ulogic;
gclk : in std_ulogic;
hclken : in std_ulogic;
rstn : in std_ulogic;
ahbix : in ahb_mst_in_type;
ahbox : out ahb_mst_out_type;
ahbsix : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqi_rstvec: in std_logic_vector(31 downto 12);
irqi_iact: in std_ulogic;
irqi_index: in std_logic_vector(3 downto 0);
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
irqo_fpen: out std_ulogic;
irqo_idle: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_ulogic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss: out std_ulogic;
dbgo_istat_tmiss: out std_ulogic;
dbgo_istat_chold: out std_ulogic;
dbgo_istat_mhold: out std_ulogic;
dbgo_dstat_cmiss: out std_ulogic;
dbgo_dstat_tmiss: out std_ulogic;
dbgo_dstat_chold: out std_ulogic;
dbgo_dstat_mhold: out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic);
end component;
component grpci2_phy_net is
generic(
tech : integer := DEFMEMTECH;
oepol : integer := 0;
bypass : integer range 0 to 1 := 1;
netlist : integer := 0
);
port(
pciclk : in std_logic;
pcii_rst : in std_ulogic;
pcii_gnt : in std_ulogic;
pcii_idsel : in std_ulogic;
pcii_ad : in std_logic_vector(31 downto 0);
pcii_cbe : in std_logic_vector(3 downto 0);
pcii_frame : in std_ulogic;
pcii_irdy : in std_ulogic;
pcii_trdy : in std_ulogic;
pcii_devsel : in std_ulogic;
pcii_stop : in std_ulogic;
pcii_lock : in std_ulogic;
pcii_perr : in std_ulogic;
pcii_serr : in std_ulogic;
pcii_par : in std_ulogic;
pcii_host : in std_ulogic;
pcii_pci66 : in std_ulogic;
pcii_pme_status : in std_ulogic;
pcii_int : in std_logic_vector(3 downto 0);
phyi_pcirstout : in std_logic;
phyi_pciasyncrst : in std_logic;
phyi_pcisoftrst : in std_logic_vector(2 downto 0);
phyi_pciinten : in std_logic_vector(3 downto 0);
phyi_m_request : in std_logic;
phyi_m_mabort : in std_logic;
phyi_pr_m_fstate : in std_logic_vector(1 downto 0);
phyi_pr_m_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_0_last : in std_logic;
phyi_pr_m_cfifo_0_stlast : in std_logic;
phyi_pr_m_cfifo_0_hold : in std_logic;
phyi_pr_m_cfifo_0_valid : in std_logic;
phyi_pr_m_cfifo_0_err : in std_logic;
phyi_pr_m_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_1_last : in std_logic;
phyi_pr_m_cfifo_1_stlast : in std_logic;
phyi_pr_m_cfifo_1_hold : in std_logic;
phyi_pr_m_cfifo_1_valid : in std_logic;
phyi_pr_m_cfifo_1_err : in std_logic;
phyi_pr_m_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_2_last : in std_logic;
phyi_pr_m_cfifo_2_stlast : in std_logic;
phyi_pr_m_cfifo_2_hold : in std_logic;
phyi_pr_m_cfifo_2_valid : in std_logic;
phyi_pr_m_cfifo_2_err : in std_logic;
phyi_pv_m_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_0_last : in std_logic;
phyi_pv_m_cfifo_0_stlast : in std_logic;
phyi_pv_m_cfifo_0_hold : in std_logic;
phyi_pv_m_cfifo_0_valid : in std_logic;
phyi_pv_m_cfifo_0_err : in std_logic;
phyi_pv_m_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_1_last : in std_logic;
phyi_pv_m_cfifo_1_stlast : in std_logic;
phyi_pv_m_cfifo_1_hold : in std_logic;
phyi_pv_m_cfifo_1_valid : in std_logic;
phyi_pv_m_cfifo_1_err : in std_logic;
phyi_pv_m_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_2_last : in std_logic;
phyi_pv_m_cfifo_2_stlast : in std_logic;
phyi_pv_m_cfifo_2_hold : in std_logic;
phyi_pv_m_cfifo_2_valid : in std_logic;
phyi_pv_m_cfifo_2_err : in std_logic;
phyi_pr_m_addr : in std_logic_vector(31 downto 0);
phyi_pr_m_cbe_data : in std_logic_vector(3 downto 0);
phyi_pr_m_cbe_cmd : in std_logic_vector(3 downto 0);
phyi_pr_m_first : in std_logic_vector(1 downto 0);
phyi_pv_m_term : in std_logic_vector(1 downto 0);
phyi_pr_m_ltimer : in std_logic_vector(7 downto 0);
phyi_pr_m_burst : in std_logic;
phyi_pr_m_abort : in std_logic_vector(0 downto 0);
phyi_pr_m_perren : in std_logic_vector(0 downto 0);
phyi_pr_m_done_fifo : in std_logic;
phyi_t_abort : in std_logic;
phyi_t_ready : in std_logic;
phyi_t_retry : in std_logic;
phyi_pr_t_state : in std_logic_vector(2 downto 0);
phyi_pv_t_state : in std_logic_vector(2 downto 0);
phyi_pr_t_fstate : in std_logic_vector(1 downto 0);
phyi_pr_t_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_0_last : in std_logic;
phyi_pr_t_cfifo_0_stlast : in std_logic;
phyi_pr_t_cfifo_0_hold : in std_logic;
phyi_pr_t_cfifo_0_valid : in std_logic;
phyi_pr_t_cfifo_0_err : in std_logic;
phyi_pr_t_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_1_last : in std_logic;
phyi_pr_t_cfifo_1_stlast : in std_logic;
phyi_pr_t_cfifo_1_hold : in std_logic;
phyi_pr_t_cfifo_1_valid : in std_logic;
phyi_pr_t_cfifo_1_err : in std_logic;
phyi_pr_t_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_2_last : in std_logic;
phyi_pr_t_cfifo_2_stlast : in std_logic;
phyi_pr_t_cfifo_2_hold : in std_logic;
phyi_pr_t_cfifo_2_valid : in std_logic;
phyi_pr_t_cfifo_2_err : in std_logic;
phyi_pv_t_diswithout : in std_logic;
phyi_pr_t_stoped : in std_logic;
phyi_pr_t_lcount : in std_logic_vector(2 downto 0);
phyi_pr_t_first_word : in std_logic;
phyi_pr_t_cur_acc_0_read : in std_logic;
phyi_pv_t_hold_write : in std_logic;
phyi_pv_t_hold_reset : in std_logic;
phyi_pr_conf_comm_perren : in std_logic;
phyi_pr_conf_comm_serren : in std_logic;
pcio_aden : out std_ulogic;
pcio_vaden : out std_logic_vector(31 downto 0);
pcio_cbeen : out std_logic_vector(3 downto 0);
pcio_frameen : out std_ulogic;
pcio_irdyen : out std_ulogic;
pcio_trdyen : out std_ulogic;
pcio_devselen : out std_ulogic;
pcio_stopen : out std_ulogic;
pcio_ctrlen : out std_ulogic;
pcio_perren : out std_ulogic;
pcio_paren : out std_ulogic;
pcio_reqen : out std_ulogic;
pcio_locken : out std_ulogic;
pcio_serren : out std_ulogic;
pcio_inten : out std_ulogic;
pcio_vinten : out std_logic_vector(3 downto 0);
pcio_req : out std_ulogic;
pcio_ad : out std_logic_vector(31 downto 0);
pcio_cbe : out std_logic_vector(3 downto 0);
pcio_frame : out std_ulogic;
pcio_irdy : out std_ulogic;
pcio_trdy : out std_ulogic;
pcio_devsel : out std_ulogic;
pcio_stop : out std_ulogic;
pcio_perr : out std_ulogic;
pcio_serr : out std_ulogic;
pcio_par : out std_ulogic;
pcio_lock : out std_ulogic;
pcio_power_state : out std_logic_vector(1 downto 0);
pcio_pme_enable : out std_ulogic;
pcio_pme_clear : out std_ulogic;
pcio_int : out std_ulogic;
pcio_rst : out std_ulogic;
phyo_pciv_rst : out std_ulogic;
phyo_pciv_gnt : out std_ulogic;
phyo_pciv_idsel : out std_ulogic;
phyo_pciv_ad : out std_logic_vector(31 downto 0);
phyo_pciv_cbe : out std_logic_vector(3 downto 0);
phyo_pciv_frame : out std_ulogic;
phyo_pciv_irdy : out std_ulogic;
phyo_pciv_trdy : out std_ulogic;
phyo_pciv_devsel : out std_ulogic;
phyo_pciv_stop : out std_ulogic;
phyo_pciv_lock : out std_ulogic;
phyo_pciv_perr : out std_ulogic;
phyo_pciv_serr : out std_ulogic;
phyo_pciv_par : out std_ulogic;
phyo_pciv_host : out std_ulogic;
phyo_pciv_pci66 : out std_ulogic;
phyo_pciv_pme_status : out std_ulogic;
phyo_pciv_int : out std_logic_vector(3 downto 0);
phyo_pr_m_state : out std_logic_vector(2 downto 0);
phyo_pr_m_last : out std_logic_vector(1 downto 0);
phyo_pr_m_hold : out std_logic_vector(1 downto 0);
phyo_pr_m_term : out std_logic_vector(1 downto 0);
phyo_pr_t_hold : out std_logic_vector(0 downto 0);
phyo_pr_t_stop : out std_logic;
phyo_pr_t_abort : out std_logic;
phyo_pr_t_diswithout : out std_logic;
phyo_pr_t_addr_perr : out std_logic;
phyo_pcirsto : out std_logic_vector(0 downto 0);
phyo_pr_po_ad : out std_logic_vector(31 downto 0);
phyo_pr_po_aden : out std_logic_vector(31 downto 0);
phyo_pr_po_cbe : out std_logic_vector(3 downto 0);
phyo_pr_po_cbeen : out std_logic_vector(3 downto 0);
phyo_pr_po_frame : out std_logic;
phyo_pr_po_frameen : out std_logic;
phyo_pr_po_irdy : out std_logic;
phyo_pr_po_irdyen : out std_logic;
phyo_pr_po_trdy : out std_logic;
phyo_pr_po_trdyen : out std_logic;
phyo_pr_po_stop : out std_logic;
phyo_pr_po_stopen : out std_logic;
phyo_pr_po_devsel : out std_logic;
phyo_pr_po_devselen : out std_logic;
phyo_pr_po_par : out std_logic;
phyo_pr_po_paren : out std_logic;
phyo_pr_po_perr : out std_logic;
phyo_pr_po_perren : out std_logic;
phyo_pr_po_lock : out std_logic;
phyo_pr_po_locken : out std_logic;
phyo_pr_po_req : out std_logic;
phyo_pr_po_reqen : out std_logic;
phyo_pr_po_serren : out std_logic;
phyo_pr_po_inten : out std_logic;
phyo_pr_po_vinten : out std_logic_vector(3 downto 0);
phyo_pio_rst : out std_ulogic;
phyo_pio_gnt : out std_ulogic;
phyo_pio_idsel : out std_ulogic;
phyo_pio_ad : out std_logic_vector(31 downto 0);
phyo_pio_cbe : out std_logic_vector(3 downto 0);
phyo_pio_frame : out std_ulogic;
phyo_pio_irdy : out std_ulogic;
phyo_pio_trdy : out std_ulogic;
phyo_pio_devsel : out std_ulogic;
phyo_pio_stop : out std_ulogic;
phyo_pio_lock : out std_ulogic;
phyo_pio_perr : out std_ulogic;
phyo_pio_serr : out std_ulogic;
phyo_pio_par : out std_ulogic;
phyo_pio_host : out std_ulogic;
phyo_pio_pci66 : out std_ulogic;
phyo_pio_pme_status : out std_ulogic;
phyo_pio_int : out std_logic_vector(3 downto 0);
phyo_poo_ad : out std_logic_vector(31 downto 0);
phyo_poo_aden : out std_logic_vector(31 downto 0);
phyo_poo_cbe : out std_logic_vector(3 downto 0);
phyo_poo_cbeen : out std_logic_vector(3 downto 0);
phyo_poo_frame : out std_logic;
phyo_poo_frameen : out std_logic;
phyo_poo_irdy : out std_logic;
phyo_poo_irdyen : out std_logic;
phyo_poo_trdy : out std_logic;
phyo_poo_trdyen : out std_logic;
phyo_poo_stop : out std_logic;
phyo_poo_stopen : out std_logic;
phyo_poo_devsel : out std_logic;
phyo_poo_devselen : out std_logic;
phyo_poo_par : out std_logic;
phyo_poo_paren : out std_logic;
phyo_poo_perr : out std_logic;
phyo_poo_perren : out std_logic;
phyo_poo_lock : out std_logic;
phyo_poo_locken : out std_logic;
phyo_poo_req : out std_logic;
phyo_poo_reqen : out std_logic;
phyo_poo_serren : out std_logic;
phyo_poo_inten : out std_logic;
phyo_poo_vinten : out std_logic_vector(3 downto 0)
);
end component;
end;
|
----------------------------------------------------------------------------
-- Author: Sam Bobrowicz, Albert Fazakas
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
-- Design Name:
-- Module Name: MicDisplay - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.math_real.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MicDisplay is
Generic (
X_WIDTH : integer := 1000;
Y_HEIGHT : integer := 375;
X_START : integer range 2 to (Integer'high) := 25;
Y_START : integer := 512;
PXLCLK_FREQ_HZ : integer := 108000000;
H_MAX : integer := 1688;
SAMPLE_RATE_DIV : integer := 4096;
BG_COLOR : STD_LOGIC_VECTOR (11 downto 0) := x"FFF";
ACTIVE_COLOR : STD_LOGIC_VECTOR (11 downto 0) := x"008"
);
Port ( CLK_I : in STD_LOGIC;
SYSCLK : in STD_LOGIC;
MIC_M_DATA_I : in STD_LOGIC;
MIC_M_CLK_RISING : IN STD_LOGIC;
H_COUNT_I : in STD_LOGIC_VECTOR (11 downto 0);
V_COUNT_I : in STD_LOGIC_VECTOR (11 downto 0);
RED_O : out STD_LOGIC_VECTOR (3 downto 0);
GREEN_O : out STD_LOGIC_VECTOR (3 downto 0);
BLUE_O : out STD_LOGIC_VECTOR (3 downto 0)
);
end MicDisplay;
architecture Behavioral of MicDisplay is
--SAMPLE_OFFSET accounts for the offset from center caused by scaling the microphone sensitivity
--Calculated for HEIGHT=375 and sensitivy=3x, accounts for overflow in sample_reg
constant SAMPLE_OFFSET : integer := 105; --95
-- Microphone display frame limits
constant MIC_LEFT : natural := X_START - 1;
constant MIC_RIGHT : natural := X_START + X_WIDTH + 1;
constant MIC_TOP : natural := Y_START - 1;
constant MIC_BOTTOM : natural := Y_START + Y_HEIGHT + 1;
-----------------------------------------------------------------------------------------------------------
--dependent constants
-----------------------------------------------------------------------------------------------------------
-- Number of bits needed to store the samples
constant SAMPLE_WIDTH : integer := natural(ceil(LOG2(real(Y_HEIGHT))));
constant SR_WIDTH : integer := (Y_HEIGHT);
-- The time needed to draw the microphone display window is Y_HEIGHT * (H_MAX / PXLCLK_FREQ_HZ)
-- in our case 375 * (1688/108000000) = 5.861mS
-- The sample frequency is PXLCLK_FREQ_HZ/SAMPLE_RATE_DIV = 26367.18 Hz, therefore the sample period
-- is 37.92 uS.
-- While the microphone display is active, the samples should be stored in a buffer region which is not
-- read during the microphone display. Therefore we need an extra buffer size called padding.
-- The needed padding size therefore is the time needed to draw the microphone window diwided by
-- the sample time, i.e. (Y_HEIGHT * H_MAX)/SAMPLE_RATE_DIV = 154.54 ~ 155
constant BUF_PADDING_NEEDED : natural := natural(ceil((real(Y_HEIGHT) * real(H_MAX))/(real(SAMPLE_RATE_DIV))));
-- Total buffer size needed
constant BUF_DEPTH_NEEDED : natural := X_WIDTH + BUF_PADDING_NEEDED;
-- The sample buffer will be implemented in a BRAM, therefore the buffer size will be a power of two
constant BUF_ADDR_WIDTH : natural := natural(ceil(LOG2(real(BUF_DEPTH_NEEDED))));
-- Size of the whole buffer
constant BUF_DEPTH : integer := 2**BUF_ADDR_WIDTH;
-- Extra buffer size used as buffer padding
constant BUF_PADDING : integer := (BUF_DEPTH - X_WIDTH) ;
-- Create a BRAM to store and display samples
type SAMPLE_MEM_TYPE is array ((BUF_DEPTH - 1) downto 0) of std_logic_vector((SAMPLE_WIDTH - 1) downto 0);
signal sample_buf_ram : SAMPLE_MEM_TYPE;
-- Force BRAM implementation for sample_buf_ram
attribute RAM_STYLE : string;
attribute RAM_STYLE of sample_buf_ram: signal is "BLOCK";
-- RAM Write Enable
signal en_wr_sample_buf_ram : std_logic;
-- Data read from the memory
signal rd_data : std_logic_vector (SAMPLE_WIDTH - 1 downto 0);
-- Memory write address
signal wr_addr_reg : natural range 0 to (BUF_DEPTH - 1) := 0;
-- Memory read current address
signal rd_addr_reg : natural range 0 to (BUF_DEPTH - 1) := 0;
-- Memory read starting address
-- This will be set at BUF_PADDING distance from the write address value
-- at the beginning of drawing the audio frame
signal rd_frame_start_reg : natural range 0 to (BUF_DEPTH - 1) := 0;
-- Synchronize the MIC_M_CLK_RISING signal, coming from the 100MHz Clock Domain
signal mic_m_clk_rising_sync1, mic_m_clk_rising_sync0, mic_m_clk_rising_sync : std_logic;
-- The MIC_M_CLK_RISING signal legth is two SYSCLK (100MHz) periods length,
-- therefore create a one-shot signal
signal mic_m_clk_rising_os : std_logic;
-- Sample window register - shift register for the microphone data
signal mic_sr_reg : std_logic_vector (SR_WIDTH - 1 downto 0) := (others=>'0');
-- Sample register data
signal sample_reg : std_logic_vector (SAMPLE_WIDTH - 1 downto 0) := (others=>'0');
-- Counter for the sample rate
signal clk_cntr_reg : integer range 0 to SAMPLE_RATE_DIV - 1 := 0;
-- R, G and B output signal, each on 4 bits
signal color_out : std_logic_vector (11 downto 0);
begin
-------------------------------------------
------------ MIC ------------------
-------------------------------------------
-- sinchronize MIC_M_CLK_RISING
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
mic_m_clk_rising_sync1 <= MIC_M_CLK_RISING;
mic_m_clk_rising_sync0 <= mic_m_clk_rising_sync1;
mic_m_clk_rising_sync <= mic_m_clk_rising_sync0;
end if;
end process;
-- create the one-shot signal for MIC_M_CLK_RISING
mic_m_clk_rising_os <= mic_m_clk_rising_sync0 AND (NOT mic_m_clk_rising_sync);
--Create the sample rate counter
--mclk = 2 MHz, sample rate = 108MHz / 4096 = ~26.367 KHz
process(SYSCLK)
begin
if (rising_edge(SYSCLK)) then
if clk_cntr_reg = SAMPLE_RATE_DIV - 1 then
clk_cntr_reg <= 0;
else
clk_cntr_reg <= clk_cntr_reg + 1;
end if;
end if;
end process;
--Enable write sample to RAM (triggered every 1/26367 seconds)
en_wr_sample_buf_ram <= '1' when clk_cntr_reg = SAMPLE_RATE_DIV - 1 else '0';
-------------------------------------------
-- Shift in Microphone data
-------------------------------------------
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if MIC_M_CLK_RISING_OS = '1' then
--Shift new data into the sample window
mic_sr_reg(0) <= MIC_M_DATA_I;
mic_sr_reg(SR_WIDTH - 1 downto 1) <= mic_sr_reg((SR_WIDTH - 2) downto 0);
--Monitor the sample window by updating the value of the sample reg each
--time data is shifted.
if ((mic_sr_reg(SR_WIDTH - 1) = '0') and (MIC_M_DATA_I = '1')) then
sample_reg <= sample_reg + 3;
elsif ((mic_sr_reg(SR_WIDTH - 1) = '1') and (MIC_M_DATA_I = '0')) then
sample_reg <= sample_reg - 3;
end if;
end if;
end if;
end process;
-------------------------------------------
-- Increment and wrap around write address
-------------------------------------------
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if en_wr_sample_buf_ram = '1' then
if (wr_addr_reg = (BUF_DEPTH - 1)) then
wr_addr_reg <= 0;
else
wr_addr_reg <= wr_addr_reg + 1;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------------
-- Set the starting RAM read address for this frame.
-- This is done at the beginning of the first line on which the window is drawn.
-- This mechanism prevents tearing of the frame that would occur
-- if a new audio sample was captured while the frame is being drawn.
--------------------------------------------------------------------------------
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (H_COUNT_I = 0 and V_COUNT_I = Y_START) then
--Wrap the address if necessary
if ((wr_addr_reg + BUF_PADDING) >= BUF_DEPTH) then
rd_frame_start_reg <= (wr_addr_reg + BUF_PADDING) - BUF_DEPTH;
else
rd_frame_start_reg <= (wr_addr_reg + BUF_PADDING);
end if;
end if;
end if;
end process;
-------------------------------------------
-- Increment and wrap around read address
-------------------------------------------
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (H_COUNT_I = (X_START - 1)) then
rd_addr_reg <= rd_frame_start_reg;
elsif (rd_addr_reg = (BUF_DEPTH - 1)) then
rd_addr_reg <= 0;
else
rd_addr_reg <= rd_addr_reg + 1;
end if;
end if;
end process;
------------------------------------------
-- Dual-Port BRAM read and write process
------------------------------------------
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if en_wr_sample_buf_ram = '1' then
sample_buf_ram(wr_addr_reg) <= sample_reg + SAMPLE_OFFSET;
end if;
rd_data <= sample_buf_ram(rd_addr_reg);
end if;
end process;
color_out <= ACTIVE_COLOR when ((((V_COUNT_I - Y_START) - rd_data) <= 3) or (((rd_data + Y_START) - V_COUNT_I) <= 3)) else
BG_COLOR;
--
-- Assign Outputs
RED_O <= color_out(11 downto 8) when (H_COUNT_I > MIC_LEFT and H_COUNT_I < MIC_RIGHT)
and (V_COUNT_I < MIC_BOTTOM and V_COUNT_I > MIC_TOP)
else x"F";
GREEN_O <= color_out(7 downto 4) when (H_COUNT_I > MIC_LEFT and H_COUNT_I < MIC_RIGHT)
and (V_COUNT_I < MIC_BOTTOM and V_COUNT_I > MIC_TOP)
else x"F";
BLUE_O <= color_out(3 downto 0) when (H_COUNT_I > MIC_LEFT and H_COUNT_I < MIC_RIGHT)
and (V_COUNT_I < MIC_BOTTOM and V_COUNT_I > MIC_TOP)
else x"F";
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc636.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:49 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:13 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:28 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00636ent IS
END c03s04b01x00p01n01i00636ent;
ARCHITECTURE c03s04b01x00p01n01i00636arch OF c03s04b01x00p01n01i00636ent IS
type four_value is ('Z','0','1','X');
type four_value_vector is array (natural range <>) of four_value;
type four_value_vector_file is file of four_value_vector;
constant C38 : four_value_vector := ('1','0','1','0');
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : four_value_vector_file open read_mode is "iofile.39";
variable v : four_value_vector(0 to 3);
variable len : natural;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v,len);
assert(len = 4) report "wrong length passed during read operation";
if (v /= C38) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00636"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00636 - File reading operation (four_value_vector file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00636arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc636.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:49 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:13 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:28 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00636ent IS
END c03s04b01x00p01n01i00636ent;
ARCHITECTURE c03s04b01x00p01n01i00636arch OF c03s04b01x00p01n01i00636ent IS
type four_value is ('Z','0','1','X');
type four_value_vector is array (natural range <>) of four_value;
type four_value_vector_file is file of four_value_vector;
constant C38 : four_value_vector := ('1','0','1','0');
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : four_value_vector_file open read_mode is "iofile.39";
variable v : four_value_vector(0 to 3);
variable len : natural;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v,len);
assert(len = 4) report "wrong length passed during read operation";
if (v /= C38) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00636"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00636 - File reading operation (four_value_vector file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00636arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc636.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:49 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:13 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:28 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00636ent IS
END c03s04b01x00p01n01i00636ent;
ARCHITECTURE c03s04b01x00p01n01i00636arch OF c03s04b01x00p01n01i00636ent IS
type four_value is ('Z','0','1','X');
type four_value_vector is array (natural range <>) of four_value;
type four_value_vector_file is file of four_value_vector;
constant C38 : four_value_vector := ('1','0','1','0');
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : four_value_vector_file open read_mode is "iofile.39";
variable v : four_value_vector(0 to 3);
variable len : natural;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v,len);
assert(len = 4) report "wrong length passed during read operation";
if (v /= C38) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00636"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00636 - File reading operation (four_value_vector file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00636arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:41:56 04/03/2016
-- Design Name:
-- Module Name: DC_Toplevel - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DC_Toplevel is
port( CLK: in STD_LOGIC;
DATA: in STD_LOGIC_VECTOR(3 downto 0);
ADR: in STD_LOGIC_VECTOR(3 downto 0);
DATA_OUT : out STD_LOGIC_VECTOR(7 downto 0));
end DC_Toplevel;
architecture Structural of DC_Toplevel is
signal ENABLE : STD_LOGIC := '1';
signal RESET : STD_LOGIC := '0';
signal CONTROL : STD_LOGIC_VECTOR (1 downto 0) := (OTHERS => '0');
signal MUXED : STD_LOGIC_VECTOR(3 downto 0) := (OTHERS => '0');
signal DC1_SIG : STD_LOGIC_VECTOR(3 downto 0) := (OTHERS => '0');
signal DC2_SIG : STD_LOGIC_VECTOR(3 downto 0) := (OTHERS => '0');
signal DC3_SIG : STD_LOGIC_VECTOR(3 downto 0) := (OTHERS => '0');
--signal MUXED_ADR : STD_LOGIC_VECTOR(3 downto 0) := (OTHERS => '0');
signal ADR1_SIG : STD_LOGIC_VECTOR(3 downto 0) := (OTHERS => '0');
signal ADR2_SIG : STD_LOGIC_VECTOR(3 downto 0) := (OTHERS => '0');
signal ADR3_SIG : STD_LOGIC_VECTOR(3 downto 0) := (OTHERS => '0');
begin
DATA_OUT <= DC1_SIG & ADR1_SIG;
HOUSTON: entity work.DC_CTL
port map( CLK => CLK,
RA => ADR,
-- RB : in STD_LOGIC_VECTOR (3 downto 0);
RA0 => ADR1_SIG,
RA1 => ADR2_SIG,
RA2 => ADR3_SIG,
-- OPC : in STD_LOGIC_VECTOR (3 downto 0);
OP1_SEL => CONTROL);
-- OP2_SEL : out STD_LOGIC_VECTOR (1 downto 0));
DC1_Reg: entity work.PipelineRegisters
generic map(dataWidth => 4)
port map( Clk => CLK,
Ena => ENABLE,
Rst => RESET,
Din => MUXED,
Dout => DC1_SIG);
ADR1_Reg: entity work.PipelineRegisters
generic map(dataWidth => 4)
port map( Clk => CLK,
Ena => ENABLE,
Rst => RESET,
Din => ADR,
Dout => ADR1_SIG);
DC2_Reg: entity work.PipelineRegisters
generic map(dataWidth => 4)
port map( Clk => CLK,
Ena => ENABLE,
Rst => RESET,
Din => DC1_SIG,
Dout => DC2_SIG);
ADR2_Reg: entity work.PipelineRegisters
generic map(dataWidth => 4)
port map( Clk => CLK,
Ena => ENABLE,
Rst => RESET,
Din => ADR1_SIG,
Dout => ADR2_SIG);
DC3_Reg: entity work.PipelineRegisters
generic map(dataWidth => 4)
port map( Clk => CLK,
Ena => ENABLE,
Rst => RESET,
Din => DC2_SIG,
Dout => DC3_SIG);
ADR3_Reg: entity work.PipelineRegisters
generic map(dataWidth => 4)
port map( Clk => CLK,
Ena => ENABLE,
Rst => RESET,
Din => ADR2_SIG,
Dout => ADR3_SIG);
with CONTROL select MUXED <=
DATA when "00",
DC1_SIG when "01",
DC2_SIG when "10",
DC3_SIG when "11",
DATA when OTHERS;
end Structural;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dpram1r is
port (raddr : natural range 0 to 3;
rbit : natural range 0 to 7;
rdat : out std_logic;
waddr : natural range 0 to 3;
wdat : std_logic_vector (7 downto 0);
clk : std_logic);
end dpram1r;
architecture behav of dpram1r is
type memtype is array (0 to 3) of std_logic_vector (7 downto 0);
signal mem : memtype;
begin
process (clk)
begin
if rising_edge (clk) then
rdat <= mem (raddr)(rbit);
mem (waddr) <= wdat;
end if;
end process;
end behav;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lWJHvBT8DgkNbFHSuw19NASjZWRim3cU/o/JIpBKQidKh7zoQlwGsVK97NwheUuDsu5LsXP7nSLP
hcBo37ENgQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
gCWDen+F4i7DQAnKc06JR0QZPNT3ulwTbIpNFUJxEmZI94QbJdv7WuS7X/Bzyp1LwkTRRyO/t4Qt
JV5F/ObUcJO1i1GCi8H8TFywwPwHLvuzlr03CtLR7cw+d68I1Wbj9xBclI9Dp2qsK9CRNjlQ/wOl
xU1A4oruZ7D/QftxCUA=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bkp01UwKvcRDI2wqmK01joALOf0O5xsPWh5cppm6sWzduYVozCl/VcTPfteAJV/N1XIyWrnxSyQJ
75VrWqFpxQUJKy4yZqBydatnGmKLz6iZeE/UtcD05m05igSfmQ9CKpMthcdRiMKJo+7S5KgwD0vc
bmutM4jZVIELvouYfnQrdlCzr49nDQri0daGopyTXE8RAxJkVy/6hr0Fwp8BXg04mTVE212Gx3xI
iqxCqes58TZR/iviXTMl/W4/Fk/f9u3CfCpr1EpefrGaw1fbZDx3q9dCNrH6SFxiRPkh5r05ZuRJ
SZCszOeJxVYDQsFXU9jtAinRidI7qv0I3xUkwA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
EgsLMQJWrkWWDeZKBpb9k6+Fl2D915QAnfUzIHcF1dQubpEOJ/6j1/Ok6mNVHV+Juf3PinvPJ1GN
NFP7AheqLlSEndjSFdWjiwc17GY0t9tRBRDp7JaAcTdGJU6hG0XTWqKBd3I6zfwLbfqiHmTdnXN6
C9WFXYI7kCacTdeqN3g=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RRXwEbMizZGYYC8gbqe21zreWfhQeNbrrTtG5t5YcwbRhecwr/lRClAmkB/moFG03eIPcERuDwFC
3qyjNGh+LDw++Hcdiens8h8y0la8p3Ho8ktUz09m8tLPLqE6a9UTeoOCRdhaSWvsXGUaa5iQQr7X
16fZViePKj4F2dwHvQrshHi3M7OQzqzvSmQ6aZXQwBlYHrPH1/CzBFBOSdDdKdoaqyEpjakpSp9L
OpIVgDIawvB5yjkmw4Pp/0/307/VqsCtC0tTIjHXV43PU6dUWdKZGo6yHlQR4+1LZyUbPQAcftr4
hlVQziq3IRCpzjXhk7B/dnic9p82X0kW2B01Lg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10992)
`protect data_block
d65p9+/6mBZZMaBMQcDhbX/UPTT8bNcq9duiKtJrJAd5NGZQgJJ3iI5GKp6NdfcIZ+/mf0+yC6cG
E/9pnRCK/JTkTlqQwo3/sqIJ9XiQLFKp12TiFWizZpbhOJMcYgjyYWgfmtzVKQxYZGCQdgYbb6Mu
wTlclEj/DMMCVTvz4zVAuVdJhClz4jFbEn9a3tmkTXizOllQLHcB+8JwCKzo5FU8FFyGT+X5aj07
gOFRXL+OwuaQFgTJHRpa1oyUFNnbHi8aZRn4VWU6T1Nz/OLXsSHIYUxpKEKqSNynTGZ8armietaM
P908TQeONXWK0W7gwrDQcTpUP8gqN0O/dXfsOTTjt9V7I0XCy9Pp4w6VU8Vs12teZs+SphNbyNUc
TSOuDDwWlPl8LJu1Yzx96qdQUw8jP1HMqytWyrFNJS5T6DPQ3q478vLjnIuXBPW6K0g5tq+dnN/O
aP0P/Hz+3GyEPAfEeNveEn+JwmTx5dttCQ4BXFkEfrDgEO5ipsZWgxOapkzgPQiyhNsAb+4Ridzk
ySyyJCqpdMM70mSANcTdR/bFIiBA8NbPnq6IWSJQeKuYA3NQfN7jnKVgqJzuytJgob9S3MwqHk2M
mbqRMCMlm7tgpPtajzFXiHHQ1K+Rmy/AArLRkhxujXn3TPBeD6nRSAa5e4Emuxhto+qXchBhR0uW
vWN3HOyGkDufpAR/FcmNgWS65MhcvnxruJ7ARgnwZVd8O7rfq1kVSV0RukzQPLCtNzZvYn9h0/om
4YgKXgTKDhUxeOGKtkKq6333obMoVydKAi/SUOAF+91VY+ic0GpcmQct7SHhHK0ZT1marx4SdMfA
MgQFgqGkT1Kr1xei99Rij+miJPl08Q3M59MG5IQuc5EQBAaChBHP/zwTTQ7tChGrqCKI86QsbcJP
gxl+/hLqsI+LogEIZycJKtJEO/WRDtttpzVjEnHEl1wlQATHfsCquid9rI2ODk3Qth1UqHjkL2g4
OYPPed2bwBWWCP9O5DKWpFxjWExkunOt5sKlVI36jos2LQabY76zIEKD4+DEC6CkuZ/AQ4XCo08G
hjjIJlNtR1vkymmMxXaXqQEzH7QscvRiBC0xo4+Swkg7FjRLiM6liFicKh/qIAiDZj35zntvcW8v
oFIjNoT4hAv/OPUpJOV1JOEvmiqszjHJ4wfzr1RPL6YBsK/lNJjSBl8AsEjt7iMWu6KpiqcWnxBF
akxAdBggsCNuOBMCZ+FG6KdFRIpv3EgHJKVcwpKr4BtpmfPdY+FrH3RvITliCXdxNzNusvj+m8ck
YTmDvjRPZhXj29Z9GOReapge/yBkzZSwNVT7tE8/TUl4fINMtMzWGKn3IhNMCUiNBygUXPiAuBOp
+FmFo+8Qmbaihvd23EP8C3OT5kZI+52weDe1SXtpp0tAHqrzb7xogmAicqp7Kbx5hhyMT6MWCPYP
xUWRmKzM90xoqN8TtBfO8zX8kFul3vOWiLXrt3WE0syrPp74/8EzaMdUIZd9GJIH5448FSti8iDj
FlyX/SCZX4vmVL+IxFE9rPKnbmjmNeguphOQ5tKu1Iyzl6YZvQtbb7i+lVNBo7fZwy6vuoXEFo0c
lqYWQbMzXwVLeRYfWWwQhA4iXD4AT5ifzvrh7JSrXeeikC6WTjHZzpChXtnVKQ7s8TudRb7KWIQR
FSiDmqSmScKo+72LG4pogMS484tOBX8ZD8Xzsd0hWDl/5xhEKtr5CfYemJ/bORVOHA/L8vv1HbTY
vxoqKniTGsrwc/DcEKN1jjRCuK+V+UevmUq2/J3Ekn8xsysS3MZ/8S16u9i/E+1KtGRPcKzQC/fZ
KXecxz41re/xZN5y4GuPZRbM5HMMlIMdc50p6hq9yMfk80U91zIomBC3WkR3uXOR9EGI3K1w2eRe
A/QDtrhPvMLHozJYdqNzkPq5W4dZnsVG+tpj3WEybdSoS6Mh4dzfA8wFyCEcA8OGAloFTJsYpLzR
xERX1OxZ5wXjWltmMfvKC4/tE9Hz6OAEhr3+o+byQ9QwvfHVAUiajWB+XBQJcvX+0Lilr9bcSZVt
8vRGcxyDL+7Zp/+HnkSvYmzyJf4vQFSPNLR0NloB+oOAeYh7Sck2mt4b6Bid/H+odCJuanQx/i7P
gJonF00evw7cZGGu/3nCje7W27jhIPqfyTl1wIywCBWqF+1NimfhdlVzcvbl/nnxWCn/FOMeKKvf
d28WY2g0Xb8uXIpu12iqkg7jbM+c6FD3+pzJU6J57c1DLY7D8v+xRLXNJoaW9DYbOAxprOiosjdf
8onv4BiBWXrw1oIYLkuVXBQmIrtLTOAEre2qC+iA4ZJ/sMl9iVKCA3XWmz5aaL809zCVEgvzW/+a
tiSD4uyKcp19Kux7qfH7YlzjXMamIiV79bkFttx6lLWgj301yg9e/tvizOlfL6H5wIjRPaMmEaK7
lQ4uyywh0nx6P4dE3MWeYkb6Wte0JRMgmOwBy0h0zRSUAPU2fVUoKMWhCx3c0XuCVxrspQs+WujK
KV6dTikY4v7OLn9V7dIJytgkDIRrPbHY0phKs9DVhm5i2p7m3QydHBe5Eq9leOtghMM25upFb0vv
bzKDldHYN0abrvbNDP9LhSIzpHhJWgO9rBPwOlzdko44p2JnW++easkmq32WulqVuHl20oGuzkxF
mdndThe5z12xrkP5Se95YRbeo8aI+XcupWw6FHX6xxgzkdXS1F8eo79IZEXdfrT8HdH5aLQyUwDV
ag2m0Epz1lV1Fn6TX/sCQD+bT1Rlb1WRjXVPrUs88rwstTQYvFEOXVUEd9pW4K+rbwnoJjiznc4y
8XNzB5eW3IibA+W7crXN0o5tFPJTtxEkW1S17sSsmimGAN12ysfQC4NNqz/7jK3wqnwp98zt2MSc
J+LOswu0Iic+5J5a0I4VxPFBgl7HIYZp5XolsEjvrEU902VWP2dEW77aDjComsr/YkCIgoC8k/It
wfNGa2VcedTvTXiYG01wMzz3HP9VtiwP1AcRc0bsFr/HVlHO+f3ASKxwgljRFa2MeuzCB+LiZ3pu
b4+J0rFKO3UHNS27UbekD4zmK9/yWw5RG7OEKzK3225PtZhkRo+VhMhjKF9iak579tqMf8wMkoj1
vxT2Hyjw5fQWxZua5fa1Yxqvr4lOKtPbBDIbpxMbW9+wL57pou9xVSNMlXsitZ044yyh5fS+YKNt
fGb3Zyicj8By7iNnmpIY1A+ovtVq5tfMlRL5JznVSSu+2VO2Qpec5hyypz5YkZwMXhN6EGbiOU7o
yOUIctFb22oxr3MM2zzIExqqBee/CAtJKRL/DHX8Vy8c8BaRMKYD7H91H0fU5IElL9QKzfvo13Fj
A1KLi7z7+BLouc9gc9DbxtckKgs6ZKYYllBRaw9DKTCJsmlS22rlknssASjXnOl54AqGQg963cRl
nBH58ZFhQWeF7Kh2vAfjoO7icSxM7IKY/MI8cN5aIjGyTnJHMd46Zalttcl4eJbMVXXfCw19DFAW
TYG8ZlCHBi9KHqPlOt8igJS0FlYByfGT2ysY6VmKDLXnKuvbRjrQbjvRDMMDI+x0YTCgfRenr2Yv
6DdVoaXpIlxJx4Bq2hmegLB4pgHoBooNzXoW4NQUWh3IEC/j5ZTV8myviDJpYlZt4UnyfRAD7IcT
rNMHTI3tZgzV8mVpJyd76GOzaIZg1ajKM6hrjKlnsKpflElqaqXGcj+MuWvg/2bZ4XbA4KlZ9+5D
v9065oNAcIBe1T+2eyfVMjfx0qHxXvfufeci3Q6/q6OO9nGdh3Sd8BZL3IHnawghISLdHSeqwmnf
JW5n0IfNF2gd/Gf+V/NwMFiOa5IL6QRXZazsjp0AxBU98e/+Up4aXBS4Dlf5V1nESFxnc1bqT4UD
Mjb17BQUAV4yydB+mFVmsl0engm07LqoU4G3KQkVu8qGZH58+p8no87DF8eHnF+lEO+JuPStnQYs
sZf7MZtuLLWd16lXXRAj/EdYzgDtePHQyvBtaEf7ocCFPBZ7U6Bxdje+n2cdZ/ak4kO3EHyNJabY
EUOQVdYoQhdAyAvtUaBA9Ei+HxOxOoIstXQ6J1FBAUt0h7yIurVFLFu5lIi0qCCas6MLdalIXLxc
mm8aRKKzssDGI05CXy9FJCCoR4s23s9L2ZLg3F6piV+r07uyJHmp4lX/OR7hWeqwVYzbXiXLhBzx
9V0JUSyspcp7c5CRA9BboYac3MZWFv6wTOMnn+Zeb62g/ned8GgLegbsGIU9hNMty1XQlEKYTfOv
N3ygU2myXn2aCwqIQVTZPHW2g1yhM9QAcKw9jEHrEUXnwbyDttMHMxnHO9+spS/GRUlY+7jLdJrW
2fsm4c1oUsXrFxuMZmBx0O96V3tzPzIQg0qFB7zNH19mAiiTC33ALqetkrfYj/Vh/WRU7imHzKM4
ExaeSRWjX9yfJHw3na+kx5adU6IY7/mpWSdE/iDFmRBMh4bgh7J3+YkAe2r0ZaJwfjmHLv6JfzQV
YblrkmZ1x+fauNjNizFhFnMJR2ok3b42yfppg+LFers4FC8R2p7dkS2dJqO7XnvTxIRY/OrquEdb
SKjOQB+8C6hC9imX2bfLZ5aZG37YPH1F9gYFfujv2hYfXI2CumG5lephLkCiypPqwoFZXk6Lnjao
steReotDUFyR46qYATd+AIPpmnmHYKqKfrg6qwT0KoZqqjm76zasDTAVsPyYQPUibMbmBURuBdko
68zMyxBvcrD+ZmJvcKLQwFnRO6a06pwYz+qyUvOE4DdmsR/nXlH1iAyOBJEo28ccazzB74H71mpH
e93/XBdjiplNIP+gN0k2Ov3lHcLlhflb/8L0BoVcCXt7vfxv4c5uNdz3OG0JgqXJibGXDkGZVRFc
yIRmJIbtFSDwWBfShyL3S5aL3f/ZCrE7c/Pqtq9+TCqG2tnE+u6PDS75QZaRlPO1YaKz6u0v0RZH
t9VzPBUg7sMNwKszvlIisp9TlteGBGKQimJMvAsYjMSTa+T33tb2CTlHPaZIMHpFzPphdibiAWJN
w/xX6YhgASkaf5bqK/sv2MiKdcT8iRkg9anCimOnWQXSobGeCyt3GBKs4jNh87Z3LK3xfd4oads+
K7yOZEj4JUJIxiZBUFOh4aX+94J25TmEwl8u5WGrj0J1KUpYzfcpEF8afo5396u1GKUhHkWomv/2
eVyfzHmEcgey2E1ZViT5Y2m9jF+qBtXA9tJRys+H5BqwYPXfEaUmR0vHVJXaQsgVm04qPrNzkODE
ndCZ/v5S2EGBN3mFP9nMtENTASsan4qZP1iiDsDCx7gcn18wdn8X3swgIw/0yVZ7tXU/eQb66/2G
dXwa/R+whQaQyM3xPK252LF9wdjDOS6L7pUunSRpJ7QBV9cHzVGprsKlfAcUNN1nCj+/Ojw7DHUv
tgU/GQjhFAF3sSbeQwpX+CDqFiqoDpKlxhe86h6SYFRkq81qwsbOHVm69IKHDjDOC6eIT1d0Ycx/
9/bhQhzMz5xtBAXC/E5jWgPRWMmJfyLMBJdwEODrHM+LjknFdYYbaAvs+2T4pCjtjPdYTRn6Ti/+
plkL2QklgyMOD9u/cu8ZdnOZePNJGQ9Y2AgMKuuz/6rrixB2ogtPqPRqkpLRQLw5uOvMlCJRl0aP
14hDatjRn5+dQRS9o6v3RiT7a5HELQw7OLp25qUy29Tm/GPSqAgcXj3qvXEyTvgTsCXJpz8uk7GP
VQYVXwzBiMyMRsLZil+9ZLfbb3yPzl7SVBlqBJIs5JW/CJ8Oxas50jdTZHk7XLFbJNsr/LwzRUki
hSiWDscfWA0UOzOl3Q8RjQcanI9R4oRaV+42RP6RPvK3iXGpuCrLNFHQ/bZJWs6dLqkGCKtVzeYF
bNp4Yj+KOfpQMCpNSXewp3DFRdZqCukPbKYAJiSGXMfl9tjXaYqzQzzgHtLP1I9ViaMoZ76qzHfS
bmgYWhF5baraVlR/BrleC5gDc1TUoxDgIKf7PZwAyqR9jY0v8RJzGvvhYnFJB4hg4T2eHEVEZ2xd
dGn91xV5DzCzFd3V5TC2XCmLU2tPmap7UNu9Qe+FlthlbI72o9BtImCJuTQZZ9OizTkM7Bsrb0Jb
pUw8fcx0ORPKi/8PMnlb4Y6prLN0FVJNKDukrJMqG4liJ/pOMXZLL1/Z8/XvuBE2KT7JM6yZ5xGF
UqEbcgfDn5XN/cpxuX1SVJU316aOWFMs2j6NqI1QBn7zLuZbYP3KhwrtnardClO+NXCTrirPdwEO
MvzF0rZQGBZZ1ovXilJ06afSWlx9pEzcm8NkYGH+xnW4L87M8e48/gVMzeZFLKca0+dieVAgKHp6
8Cb/vN0NIs1vCSD3Bp/jOaoHsqPF2x0B/QlCdE7ytuUGP4RE0JksnLxPUz4uhJz3rdoFRzTRx1OX
IG2ucaRfUd57Q4x5NSaanMYvK0j7087SuBWyd+LX+ohuAT9cHCu3zXptwv86Qkf4oWdbHHLDyr5P
ky841WjyWcGP8INReVfqQhz86MhcGxB5h5Dl9/0srl61mmNrPJ4wuV/cnRh/+G+OrSzQNQi1KueD
M7HNj0ObUJj8RByG+mnJnZ3mNGx8CI9RiD/cUfajxRAyV8vVQf18bcUy1SZUnOl/dgstWlPwiJT1
+hP8Sk4PefWdV6jvvZZ1gAFCxRFUp5FsNjA0/gNwF2AfkA+k8OeqZdfbrERkuKQVtFYRDoK2p4HO
5wHKdaEWB3/IRbtCxUxB64cWyXKUPLi6zuGx7J1L04vhuV12HQL/r+Ilw+BI3cBO3ee86683Ago9
RRBj038qUh0nGb160MHOlJ6JWrz0k3roTdHkZ3bH0zgEeVkAO233zwFUL8CSzkHO4/sIXRcg9TjS
mKU/M+A/eldbilHUrfd4vP7A3AQtK5MbgODrq9LlRplTBfpvEV2WdjwOFTBPRf9+asdC3uda3LTt
1DozRsHtHTAZRbH8FwTUP+u5pVVGEdyhOcpawmGnEQM2NTMuckNs3PqQnL35ZayNfRbf3b5U1Kwa
22NEfU78gvwTkmIU0+7Q9L3wgR8/5dSpj05qut0zJ/6H9N5IgoTbz6LiL6lPpmIr1C66zOqPo4rN
UZJ5E+dqyp8e3J+bnEf3WzJF6vVwJuUTvBlxCe2Wv4LvmyvW8f5eIE2DB9at1YNaZ4VonXgCY7WM
JfQVDtQj8HjMSYk4vjW9h052kJx87A09jf8d/VJUocn8UzNAkNg3x3H5f5TWxLNwLvo1XTUtZ2H8
RBxCJMQqDI1/miXVGAcA6RBNNi5nCZWEU/U7alOuPS58jhgNZ4QVNOYEErIwaJ3BbRsJ6QCwhyB6
V3fyRL9T6QcTSCjG1hpYdqNUF24iWRSHOsIrhsKJfbhYD+/1IQOw4F6BqB8ANa3SsLvNAlB88eLQ
ztkOaSepJCVOdbATMvYyFdt84LCEvAOd6+IHk3B7K8eZSCf5JYN8LeQouQg6c411eS3Etm/okxby
Ip8fRco/mM9FSa1JVVWXh6POd5MumeBoTdbPErFRJ4huhbqCBFaHZZrwaRdopox/3jeHXmLjh9B4
e7m8tqRUOZzsP4Y1zUlAY/hk7h+gC+lw0KIMaDQYUUHCYISCCvvs7GRwleGhBFPpI8Mj5BJSQLcU
Hxsl//SDBpKabh3myM392iElsW+A0kySoSsFRM+aN4cVlerqfiksTja+LcnWhzbUetRT07KcNF/J
OO3pEau6uYwoxoXGr7BQgm4YnJethikNpoGYnNUC+ZpKbutx25uGfVjVkBbQN706gzJgzocLWzlt
f14TMtLKKMBxBR3N/iCYJC9JcuZtgncHAvfIN/QOi5dcBlSboF1I8mvL15vOlxyOVjXTX7dCoLaN
9U+7zy2lv8XpxKPBh9bpAv8B0Mtd67LpjW3pIXXcynmZBBHJgGK4DavDmdQ6ZzHSwtBfU2LJyXES
6xvVBcKDRT6x4bNdMZxN4N3ARTw1sDARq+Dil0Hw0KsFx+3vPg15jC+mKlSIDrfUSKPeEuzci6p1
onoxNdW+z8qXT5OVImbSYVwDAEDO8hYo/3mng8guIVdH7TCArGRQiYwCVkIDjUTTV2j90+euwABe
3X6Vi6dNwvbnttYP9Sh4ayBdeSsSM6fSNLAKTQ15LFc/9d4D7IcEv/BjD/unwr29a5LJJ1YcFX8a
y7lbCPiHOrjemWmA3jqsTMaeFG9yA1KYsH4zHpG9Vze4KmJr1u+664qzyiUBaQ82Fvd8oxaJyS2T
u4r6MS7fppRYpSdM/VYTo/fmE2up4SflOYKxnZVD2jOxIgTCPAzULwnfX2g2L/aeXkdt9n2ldQaN
BZ0pytkfED4LR1E7kCLQB/fyyLKfErjtl09xfMpaKk2NGxZucjgJEcpxQDhqRXUcHzQ4Nj1rfwmF
1L0yxGjx2UeZMWA8NGYSon7HJb6oOQcA0rTu3+Eb7aEXxF1b/BoqWwXegYl+2NDlOOl2fE5NvRzZ
+NQnet0yRZQ7CC7O9Ja4Mi6t5IEKs1lCTgE51W4d9FXEvJfMY5FK0gapRAhBLQu8IPVsrdBbKfKn
cFiZm1z7dxgUi3UObOlsL5ImnHf91CDh85A+rdbrgxQjdkHDwZwj9YzLkwiuyzveg/xn6I8ouJbJ
YWfy9J9sfUa6pVPYSjlIhSViZqd2YjqAcJi25s91rPDbL8F/YfOA6I2HhRm/SC+Kt8VYhoDVqnBd
8qIiIqaJNy6OheYyTkFyCn7BBD2ACiJ4hCHjHhvKIXUx5DS6/VaJ2iUC/AjUV+zgEcWmRu6CSCZI
QmYF4ObWJ2uO7W5IZf+eHCl8Ql40kgUgHCTj9DiFMJ3sdZC/p3PV4U7gqzlGTgnnNZJmz/0yPD9r
tdojLoleKfSqGX4eXAaTz0ArgmWl3VMp+V9lLKyZ8R5O9aoTnAwP1IuEw3K5UkILbRr+Zht5v9Fs
hxmDcSgHdGQk4cqb7NuARxK0mijN5LeMrw4o5OE6L3yrQ9ALghuUP2C1lvrNJNV4ViC5lqrV4Vy0
FRJ4RMGsOQJfBPyYCw7tIKvLEZ4hRI3cGqATZQeWVDE/Qj0pFQ/d1apOoEcFLgBvk1cZKlyypNtH
C2Nfk3A4YodQmseMrqgLzQ+Z72OQ2+UcUGi7Sk28HjLvXYulx5B1P8kXkU3DAinlw9pWnOc0jicD
8J2k3DU4kJ8P7d9etQno8CqWpbTroXdWdQtziLfUB3XTgm18bLQd0oJ729wSzGs8UI/VMah7YFqQ
kKd0XNMBlo3t0O56llkX6WNsVB+JM0O+zKjwr7PjxxAg6wPmqD8fVy514TkP7KDyGt3WMWpf4RVc
HDSarl2/gSg46XwhMQNBWZZoQzRUErVRW+03vtSQgiX/8pA8BtRwQSzJvWKbn/VnqVgKoeJJi+XY
MY8RiAXI9KrMLkWaB1SoccTsZ8RI1mf6CrQ6aV8UHOU6Qw0nFghqn9oMxItKhU13b1n+gevNzyv3
Npj6efr/Kx666aivj4InmzMTMvyE9ZoHYsk6IFHkJKLYCWAoH17LCrJe0ewuQ923G1UjH1oU820f
RbmpNKthUNbox8AqZCMakGEiEQ5tuMind8UE3OYWGA5WAhIYCRm1U0glPhq/eB1AXtZH5GLpoKJi
F5+xYxuWQIjnTBAFhP9gYBnKhQqZFapI3hfjP2GgjxBmWs6kum0f4n/f1oZxMOC8qjajONtAYgox
Ye6XUx3KRIWJp8OeaUu/z2A/iO6spD4beYDvdaPifQeOA/t+UcoN6aIuSeLoU0bGXXI7JoVmJw3w
2ZMxdBWCR/iZHQX7EZgDJIrj65AmKEeBMHxaVX1nCS7k3RFUDXJelaVqbn0V+sPyvEMFSmPnOlAG
soTtgUuh1RmShfCtQYMYL8Tr/htBEP5KUSmHb2oRibNUYZYgD1cQHb3gYEByqJNvz0BTZcfzMM5n
p4RcG6uJPESDGqbO1I8JPulBzX22WROMW0pa85pgsnNRa7+xLSmeFQRTk+8dvlmGs+G0jOcmPusm
QC9cb85LShVl3vdq/6+cFid+xgE2h+J81KeCyGbIw7+dK2q+PKpJtaPjsBEO+5E6dBug1Odv4g1P
lIbK1o5bjNttlPv+WPchTFu13jjWtRjzUu95GKb9QfOEuHCkQ3O3gdTxyaqt3Qnb8TTw0xPZYkfe
SV8z/1FZtIJimFhwB8W2bWATCjW/dSPAwyDXiSRsKAuHL3K4K6ipdlNH3UEVUac6nHH9ul4QfWHo
3Xafh5L/Gc0CDDrz1hSyBlj5eIGqcRZb6+6djK8qB9XVTV73dSyQzTWHpw6KCfzAaqoFjD3sK238
NNMnKEiRyqi+RTSPr3EOO+DBJEKi49vgfsTSJM8FeLHj3QIxL02u6GlEa3I0eUBUdyLGz3jlNzER
A169WupipFpIpKFKtUCGRR60nsc8uLw4tQqaVDZscr2P5o7NqFW1z7dXpCRnPwilto57V8EJ63Ox
g284PGck5cMYKPFCu/5pEj7EI6HHfxazTDfaBoxqBhc02NAymXdgE3ox3eMEWtCGxOfCbLWXZFJ0
Bcq2JDUrmEtjNz1CQPm6Oar0PZeI0rDFKl7YK3mz7+whL0Pm6oukDOYSzAwZ8dkQSluyHVrygHd/
6QlFb3jxgqMuPF2Lxfb+Ic+RNlvyO9qtnj/ohU8lGZYhx2e4Te3wZ9qihKDkDwIJRvgXP9YlOIGj
7hSGZL7UQ7yOTJ7iCv4L8nq4hHXdfmExOQY6dPzAytSB8dV9CkHAs/m0ZTAdAsnq8RbIqRgqk06N
Xp4JY2UgGuUdFgW0KX+UOCInKzdA8HlbjyJhWy8NH9ACNswntlutXbiczY2pdgnaR9U4rQUUl87s
1WnaF8XV6Bo/8xxDo85emoFRbg5arUCRj94Gv2Tdx+agQ1QLFPtIdwqutnpE3Xh5j94P8Wlep7Mb
wxzYXagUjkUOLMMczrGvkDpUB51NLTtOSDRaED6vmBKbFsoF5SdAV7t4rLVy6MtBj7ipBq3viJOc
R610sD6cphOecpyS3ifO2pKDLIvlKD+6k6bEw94xPG5FpGzoqWsWQ5fFRBq91qSOHDmV0jZsLzse
4uW3rx3OiC/ERbo9uOnxedF92bhotroF2XETBaU3O/e4Vw1JNWqmUQ3Gu06Q5p47hN2BwHr6em1b
8mTg7OVC9tzrtJwPCANfcQPBdnTmZ+aszJnW1M1mFVe1JP60CYssHCCfpqF2GQ7Ekp+LdOYPK5bE
QXjctNnYtO7zDs8WAGnSPcaXnKTgptjUY0FSliw/iMmNf8G6q+RpElj22G3zcYsvQRHX2Kj9B6zw
ABaD2ACVix2jq+1lt9qAkW4TPXNjitfm4ZSwtMLxUrZK8nP8ewok7gFaBEtMwsIvRLhmfVIISjZ1
Fxu4cufjR2288zSGh5g+EsJ1LtNFkmDZafjxxdD9/G3nbYf90LqV2ar3/L3Qo9yqDRgbqVoflbOD
AYanZ8A9cR7YchZVgktoD6Knsqx/74Wrd95SyTkKXrWD+Xujzqz7f3RdU0fWs+hM7rdZztnYTSxX
1xkAUU/mazeweyXlDrpvJmDLPLcfjr89Y5GeXtLWr5zcouECcldiK/LePhxynXM5ww9zwDBZLsIM
Zkk3xnJxhqd6faFkxvxf65NnnYuDzwRoXmee69pYRhD/Xi+13+PIzlAMXqkpeXpmiJXYENGLUzNj
pG9Jc8iA+tGi0bHlJAYLpW2gYVmP4T+ouSi/eJCyRLW1BESeTLwauK3qznP8HUoy+HDei3k5iHYc
iuxz+8HHW/ftzmZPe2EJKIm+uQ6KHfpPXK4hrFCxlWg4q8WGsZh/Vn6MfBuDpPj5uz/leB9acikj
/uG/QH5OnO0IqywvCnd2lVqMhHjGbYm9cgM5pWRNo5zMXInpJ8s7EyJKF2sMRB3PJDfOsL4QPYxv
9Fsh2e1lpB4R9Itw9Xjtfbzi6gmXRZnmDycMTHVm0FlZ2QFe19OcdcKgVrYfY85/rCz4d5dOwcAP
q1wX+I0V98YYSVA/h2npk3v+xMULe8uJf4DANkTMy2dS6ewl/2zeU4ZxN5TW92aoHOVvHWYzb2Km
AXI772PSI6D7Ip+xS0Id6waq1FRTAIbbYHqAHZdhAXy4vkKXec/BFmn9GxrqPLb3vbxSRdCgzxz/
sicFm2jzhqOAGWx8x1KlDhSvrL+h5HdiUA/Tnt/ISzjQzVaOxaqUDdG4htGfSFMUCln4VXtTtKho
MXP7xWMqyfTon8XT492jicEy+D5CH15ORRrWnr1UiGE/qxt+V62obU37jSARHGWTCpjslaZHtfQL
Y/uaALTPGgi/cqeX9UGMN3Vsls339HCptzIz7di0bb2/f5p/OSCAW5EaDJ40OCw5+0xy60XAmgNZ
N8e6U2XZQXt9mV2Ihy686enxv4J5LRtgMtIh0LPeyiJca7pXr8lIurUCh8c2woDiMBT+taZgEKjT
5DRGhRbgutu0T5bWxu1xKZL4tAQWJIOrH79kK+mLD+uEd+S0PZ+Uk6nSIk+y7f30yoBcEXIm/SdW
4rKJ3OahTxJZTug2y+YG2W7w76xj3Mv2jLKQLp5+cKXj6Jsy3TncHCpEq+PPfZBAziz02fJ/l/5S
k7brnSl3ePzSB9qQ3Ng3t0jYbtN7MAET0HWj2FcApgZP4Z/IK51vtp5b4BepFagGz/E7iXA/7JfW
TtQG70a5b7FDmmK9LGlSnoZYhNQEzaR4mm2SiFFiIt+9GuycTTtcelwVrjk4jK9+xowZNYlD7RFa
tmdzsUCDFJ3FGlsDJ78fJEPHNCEPUOY1fJaHIjubilCn2B2LwaG/+q4XIKqwPyTa3Vg/KUoLvXia
ZLudklu9wO5vEyp7dVmp1mV7MTX16ThvBst8Row1oBZtCv2CuqpAfJxg5Mh4fC+WQaIK5zModBZj
scB8CCwjBsWu05wBp4Vzw50FLCseOUJ5taXGz64sZSXYKs5dB3Q8Dxj2zlzaxC8oNmbyf0q4OZeC
vI/VWcoOvbNdIfgXi5RNHvF+tQHpobDRFDrKUzIPjVjDdHk/1FasVe/p/kEYjSKxQdmw0wJJ2nVw
GRHga13gGuTay/kXshtwRLPVU5dhwE/zkoTOFmOlgB8DKg7lPBgFuOIPRToVeePd0jz/L7Nx2M58
cwT07E5GcF80Xa3u8OTyBvUYDiL83EeKadawEICN5XL4JP+DEt2HX7CeVSl4vF2FzkQg+ots3T7H
VEJlGCToSE67mgWY6/PagsxgsYMOjJyGy1aTU6fJ/cQqKpbgOQuA5rrjhPYQjGP/RAtFz2cq0ezM
WSkcxfi62vX+fXufMHRnEe5in8PQ9oCt50HJxf8+xeQ8nqB8FTMzbPd3/mKbjnFZiyCKLiZ7uiXc
I7MixJ2c/AOpvlEy7FrNT1msh8N9zmvewPnkvgkEWJilUl3KT8KVrwFHRcGDC3SNDdi4DHwOxXMc
6VP4TWGKZJ288yYW0JBPWp7dyAO90xiBIIIPu9NIks644w+XF+UahKcMD4XKP4U/wTlMVg90mIyS
aoGQuH5yJCXE6XBEnc9RurQvfIIvZgN204xiEJk++0wZGqwyom3+YLDBy0ZGdVBPb1SK3qy5+1O7
TMjG7LGyy4gFzoQs3ad0LDbpN0uPehQPzy/9FYwQDz2hdJ+NDv6+jOTo/IgF29tPR9IXIG0LrOEV
QuWsY65sJXMvaaMGHQCkNRKqrQb1RQu1ZaSqY0XmkDa9XcETUQMBm+TMeCgAl117Qgb6KmoDZiDZ
ATiXmCwPGEuA4H7uau5lbIrLmxlaIcHUYvS0JVVL3vORdZpUJvaBkijD1sAxqnk0NMojN5C13WAc
SEbipiUqjvgkB1ohOJKdlJUo7g8wGCFcR9SrzzmCFctpBRKGX4pK9K+hYDfsQA7hU0is8hQQ4mbm
/0phd5jqxRbnPO0zAvJQ/nL5YYDsrHUhrcCgRAKy+fl2ocuT1SbHwmyFs/HyALTKSouMENAAQGKS
VPCqrEHqrIUUDtKM8cCu1kUr8viwiWNfBy4GZ3umFyOvkF/O9WicsI8LRBotih+mrSAYEqhNu7Ol
inIJufzsDkVnbGuUkGKnV0fUVHXHLpI4NGXZn02saGQEzLeUzYOKCQYmQW/lizgXQAjEsqPzmh1y
CG2ZAsKeilkCHTp3ISwOBRmDUpRq9aWNHkhy5orpcB0HdcFXDpV9lcY8OP1kreiDMitI4oK5xkNt
yITcnegDMRW0WDtT02TZEzTpp1Z2r5Wfqnm3Zii1RdbHDFtTZl4YCFKbSuhc6hyj22U/OxW+cw8E
WU6eYiY5wpiFS0sHGBaUSlmFEzOsCQGHIkk7+Wyv6Kd3JXhoXKZzKeaaOO53cnAqVSBpfeBELo12
eyaB+vfKtJLZCjczazgg0BMaTyMumrsJaDRLx0MNXSfA4iHhTrHsbshCMbQxsp75V3i9XsDwMzhh
01YFdIN1br/MO4Ed3pfaKJfFRLjTeXiZEwWRM+zPmAmkBbRS9m0zdm3MYQWA00jvYv2dtqk0VEU+
0U3BQnkxOwxh5UKscK3jhcfUkYxi6UWrUu6xGNn8mBd2jgsP9n25qhaJOl/hQhAPIhXchF0S39qy
/7BP4DMr6WRaRaj1WmsieQGcoUdbaVbCvpBF6NafazVujj8trgXpL+S1IAtH3P3qUmuM7MNMhtpj
EBPGreVFzv/Lvf+uUTBat+TmvqosX5jxIkA+W5kJoORd3nof0sEMYbzGQGLjKfEf
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lWJHvBT8DgkNbFHSuw19NASjZWRim3cU/o/JIpBKQidKh7zoQlwGsVK97NwheUuDsu5LsXP7nSLP
hcBo37ENgQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
gCWDen+F4i7DQAnKc06JR0QZPNT3ulwTbIpNFUJxEmZI94QbJdv7WuS7X/Bzyp1LwkTRRyO/t4Qt
JV5F/ObUcJO1i1GCi8H8TFywwPwHLvuzlr03CtLR7cw+d68I1Wbj9xBclI9Dp2qsK9CRNjlQ/wOl
xU1A4oruZ7D/QftxCUA=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bkp01UwKvcRDI2wqmK01joALOf0O5xsPWh5cppm6sWzduYVozCl/VcTPfteAJV/N1XIyWrnxSyQJ
75VrWqFpxQUJKy4yZqBydatnGmKLz6iZeE/UtcD05m05igSfmQ9CKpMthcdRiMKJo+7S5KgwD0vc
bmutM4jZVIELvouYfnQrdlCzr49nDQri0daGopyTXE8RAxJkVy/6hr0Fwp8BXg04mTVE212Gx3xI
iqxCqes58TZR/iviXTMl/W4/Fk/f9u3CfCpr1EpefrGaw1fbZDx3q9dCNrH6SFxiRPkh5r05ZuRJ
SZCszOeJxVYDQsFXU9jtAinRidI7qv0I3xUkwA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
EgsLMQJWrkWWDeZKBpb9k6+Fl2D915QAnfUzIHcF1dQubpEOJ/6j1/Ok6mNVHV+Juf3PinvPJ1GN
NFP7AheqLlSEndjSFdWjiwc17GY0t9tRBRDp7JaAcTdGJU6hG0XTWqKBd3I6zfwLbfqiHmTdnXN6
C9WFXYI7kCacTdeqN3g=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RRXwEbMizZGYYC8gbqe21zreWfhQeNbrrTtG5t5YcwbRhecwr/lRClAmkB/moFG03eIPcERuDwFC
3qyjNGh+LDw++Hcdiens8h8y0la8p3Ho8ktUz09m8tLPLqE6a9UTeoOCRdhaSWvsXGUaa5iQQr7X
16fZViePKj4F2dwHvQrshHi3M7OQzqzvSmQ6aZXQwBlYHrPH1/CzBFBOSdDdKdoaqyEpjakpSp9L
OpIVgDIawvB5yjkmw4Pp/0/307/VqsCtC0tTIjHXV43PU6dUWdKZGo6yHlQR4+1LZyUbPQAcftr4
hlVQziq3IRCpzjXhk7B/dnic9p82X0kW2B01Lg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10992)
`protect data_block
d65p9+/6mBZZMaBMQcDhbX/UPTT8bNcq9duiKtJrJAd5NGZQgJJ3iI5GKp6NdfcIZ+/mf0+yC6cG
E/9pnRCK/JTkTlqQwo3/sqIJ9XiQLFKp12TiFWizZpbhOJMcYgjyYWgfmtzVKQxYZGCQdgYbb6Mu
wTlclEj/DMMCVTvz4zVAuVdJhClz4jFbEn9a3tmkTXizOllQLHcB+8JwCKzo5FU8FFyGT+X5aj07
gOFRXL+OwuaQFgTJHRpa1oyUFNnbHi8aZRn4VWU6T1Nz/OLXsSHIYUxpKEKqSNynTGZ8armietaM
P908TQeONXWK0W7gwrDQcTpUP8gqN0O/dXfsOTTjt9V7I0XCy9Pp4w6VU8Vs12teZs+SphNbyNUc
TSOuDDwWlPl8LJu1Yzx96qdQUw8jP1HMqytWyrFNJS5T6DPQ3q478vLjnIuXBPW6K0g5tq+dnN/O
aP0P/Hz+3GyEPAfEeNveEn+JwmTx5dttCQ4BXFkEfrDgEO5ipsZWgxOapkzgPQiyhNsAb+4Ridzk
ySyyJCqpdMM70mSANcTdR/bFIiBA8NbPnq6IWSJQeKuYA3NQfN7jnKVgqJzuytJgob9S3MwqHk2M
mbqRMCMlm7tgpPtajzFXiHHQ1K+Rmy/AArLRkhxujXn3TPBeD6nRSAa5e4Emuxhto+qXchBhR0uW
vWN3HOyGkDufpAR/FcmNgWS65MhcvnxruJ7ARgnwZVd8O7rfq1kVSV0RukzQPLCtNzZvYn9h0/om
4YgKXgTKDhUxeOGKtkKq6333obMoVydKAi/SUOAF+91VY+ic0GpcmQct7SHhHK0ZT1marx4SdMfA
MgQFgqGkT1Kr1xei99Rij+miJPl08Q3M59MG5IQuc5EQBAaChBHP/zwTTQ7tChGrqCKI86QsbcJP
gxl+/hLqsI+LogEIZycJKtJEO/WRDtttpzVjEnHEl1wlQATHfsCquid9rI2ODk3Qth1UqHjkL2g4
OYPPed2bwBWWCP9O5DKWpFxjWExkunOt5sKlVI36jos2LQabY76zIEKD4+DEC6CkuZ/AQ4XCo08G
hjjIJlNtR1vkymmMxXaXqQEzH7QscvRiBC0xo4+Swkg7FjRLiM6liFicKh/qIAiDZj35zntvcW8v
oFIjNoT4hAv/OPUpJOV1JOEvmiqszjHJ4wfzr1RPL6YBsK/lNJjSBl8AsEjt7iMWu6KpiqcWnxBF
akxAdBggsCNuOBMCZ+FG6KdFRIpv3EgHJKVcwpKr4BtpmfPdY+FrH3RvITliCXdxNzNusvj+m8ck
YTmDvjRPZhXj29Z9GOReapge/yBkzZSwNVT7tE8/TUl4fINMtMzWGKn3IhNMCUiNBygUXPiAuBOp
+FmFo+8Qmbaihvd23EP8C3OT5kZI+52weDe1SXtpp0tAHqrzb7xogmAicqp7Kbx5hhyMT6MWCPYP
xUWRmKzM90xoqN8TtBfO8zX8kFul3vOWiLXrt3WE0syrPp74/8EzaMdUIZd9GJIH5448FSti8iDj
FlyX/SCZX4vmVL+IxFE9rPKnbmjmNeguphOQ5tKu1Iyzl6YZvQtbb7i+lVNBo7fZwy6vuoXEFo0c
lqYWQbMzXwVLeRYfWWwQhA4iXD4AT5ifzvrh7JSrXeeikC6WTjHZzpChXtnVKQ7s8TudRb7KWIQR
FSiDmqSmScKo+72LG4pogMS484tOBX8ZD8Xzsd0hWDl/5xhEKtr5CfYemJ/bORVOHA/L8vv1HbTY
vxoqKniTGsrwc/DcEKN1jjRCuK+V+UevmUq2/J3Ekn8xsysS3MZ/8S16u9i/E+1KtGRPcKzQC/fZ
KXecxz41re/xZN5y4GuPZRbM5HMMlIMdc50p6hq9yMfk80U91zIomBC3WkR3uXOR9EGI3K1w2eRe
A/QDtrhPvMLHozJYdqNzkPq5W4dZnsVG+tpj3WEybdSoS6Mh4dzfA8wFyCEcA8OGAloFTJsYpLzR
xERX1OxZ5wXjWltmMfvKC4/tE9Hz6OAEhr3+o+byQ9QwvfHVAUiajWB+XBQJcvX+0Lilr9bcSZVt
8vRGcxyDL+7Zp/+HnkSvYmzyJf4vQFSPNLR0NloB+oOAeYh7Sck2mt4b6Bid/H+odCJuanQx/i7P
gJonF00evw7cZGGu/3nCje7W27jhIPqfyTl1wIywCBWqF+1NimfhdlVzcvbl/nnxWCn/FOMeKKvf
d28WY2g0Xb8uXIpu12iqkg7jbM+c6FD3+pzJU6J57c1DLY7D8v+xRLXNJoaW9DYbOAxprOiosjdf
8onv4BiBWXrw1oIYLkuVXBQmIrtLTOAEre2qC+iA4ZJ/sMl9iVKCA3XWmz5aaL809zCVEgvzW/+a
tiSD4uyKcp19Kux7qfH7YlzjXMamIiV79bkFttx6lLWgj301yg9e/tvizOlfL6H5wIjRPaMmEaK7
lQ4uyywh0nx6P4dE3MWeYkb6Wte0JRMgmOwBy0h0zRSUAPU2fVUoKMWhCx3c0XuCVxrspQs+WujK
KV6dTikY4v7OLn9V7dIJytgkDIRrPbHY0phKs9DVhm5i2p7m3QydHBe5Eq9leOtghMM25upFb0vv
bzKDldHYN0abrvbNDP9LhSIzpHhJWgO9rBPwOlzdko44p2JnW++easkmq32WulqVuHl20oGuzkxF
mdndThe5z12xrkP5Se95YRbeo8aI+XcupWw6FHX6xxgzkdXS1F8eo79IZEXdfrT8HdH5aLQyUwDV
ag2m0Epz1lV1Fn6TX/sCQD+bT1Rlb1WRjXVPrUs88rwstTQYvFEOXVUEd9pW4K+rbwnoJjiznc4y
8XNzB5eW3IibA+W7crXN0o5tFPJTtxEkW1S17sSsmimGAN12ysfQC4NNqz/7jK3wqnwp98zt2MSc
J+LOswu0Iic+5J5a0I4VxPFBgl7HIYZp5XolsEjvrEU902VWP2dEW77aDjComsr/YkCIgoC8k/It
wfNGa2VcedTvTXiYG01wMzz3HP9VtiwP1AcRc0bsFr/HVlHO+f3ASKxwgljRFa2MeuzCB+LiZ3pu
b4+J0rFKO3UHNS27UbekD4zmK9/yWw5RG7OEKzK3225PtZhkRo+VhMhjKF9iak579tqMf8wMkoj1
vxT2Hyjw5fQWxZua5fa1Yxqvr4lOKtPbBDIbpxMbW9+wL57pou9xVSNMlXsitZ044yyh5fS+YKNt
fGb3Zyicj8By7iNnmpIY1A+ovtVq5tfMlRL5JznVSSu+2VO2Qpec5hyypz5YkZwMXhN6EGbiOU7o
yOUIctFb22oxr3MM2zzIExqqBee/CAtJKRL/DHX8Vy8c8BaRMKYD7H91H0fU5IElL9QKzfvo13Fj
A1KLi7z7+BLouc9gc9DbxtckKgs6ZKYYllBRaw9DKTCJsmlS22rlknssASjXnOl54AqGQg963cRl
nBH58ZFhQWeF7Kh2vAfjoO7icSxM7IKY/MI8cN5aIjGyTnJHMd46Zalttcl4eJbMVXXfCw19DFAW
TYG8ZlCHBi9KHqPlOt8igJS0FlYByfGT2ysY6VmKDLXnKuvbRjrQbjvRDMMDI+x0YTCgfRenr2Yv
6DdVoaXpIlxJx4Bq2hmegLB4pgHoBooNzXoW4NQUWh3IEC/j5ZTV8myviDJpYlZt4UnyfRAD7IcT
rNMHTI3tZgzV8mVpJyd76GOzaIZg1ajKM6hrjKlnsKpflElqaqXGcj+MuWvg/2bZ4XbA4KlZ9+5D
v9065oNAcIBe1T+2eyfVMjfx0qHxXvfufeci3Q6/q6OO9nGdh3Sd8BZL3IHnawghISLdHSeqwmnf
JW5n0IfNF2gd/Gf+V/NwMFiOa5IL6QRXZazsjp0AxBU98e/+Up4aXBS4Dlf5V1nESFxnc1bqT4UD
Mjb17BQUAV4yydB+mFVmsl0engm07LqoU4G3KQkVu8qGZH58+p8no87DF8eHnF+lEO+JuPStnQYs
sZf7MZtuLLWd16lXXRAj/EdYzgDtePHQyvBtaEf7ocCFPBZ7U6Bxdje+n2cdZ/ak4kO3EHyNJabY
EUOQVdYoQhdAyAvtUaBA9Ei+HxOxOoIstXQ6J1FBAUt0h7yIurVFLFu5lIi0qCCas6MLdalIXLxc
mm8aRKKzssDGI05CXy9FJCCoR4s23s9L2ZLg3F6piV+r07uyJHmp4lX/OR7hWeqwVYzbXiXLhBzx
9V0JUSyspcp7c5CRA9BboYac3MZWFv6wTOMnn+Zeb62g/ned8GgLegbsGIU9hNMty1XQlEKYTfOv
N3ygU2myXn2aCwqIQVTZPHW2g1yhM9QAcKw9jEHrEUXnwbyDttMHMxnHO9+spS/GRUlY+7jLdJrW
2fsm4c1oUsXrFxuMZmBx0O96V3tzPzIQg0qFB7zNH19mAiiTC33ALqetkrfYj/Vh/WRU7imHzKM4
ExaeSRWjX9yfJHw3na+kx5adU6IY7/mpWSdE/iDFmRBMh4bgh7J3+YkAe2r0ZaJwfjmHLv6JfzQV
YblrkmZ1x+fauNjNizFhFnMJR2ok3b42yfppg+LFers4FC8R2p7dkS2dJqO7XnvTxIRY/OrquEdb
SKjOQB+8C6hC9imX2bfLZ5aZG37YPH1F9gYFfujv2hYfXI2CumG5lephLkCiypPqwoFZXk6Lnjao
steReotDUFyR46qYATd+AIPpmnmHYKqKfrg6qwT0KoZqqjm76zasDTAVsPyYQPUibMbmBURuBdko
68zMyxBvcrD+ZmJvcKLQwFnRO6a06pwYz+qyUvOE4DdmsR/nXlH1iAyOBJEo28ccazzB74H71mpH
e93/XBdjiplNIP+gN0k2Ov3lHcLlhflb/8L0BoVcCXt7vfxv4c5uNdz3OG0JgqXJibGXDkGZVRFc
yIRmJIbtFSDwWBfShyL3S5aL3f/ZCrE7c/Pqtq9+TCqG2tnE+u6PDS75QZaRlPO1YaKz6u0v0RZH
t9VzPBUg7sMNwKszvlIisp9TlteGBGKQimJMvAsYjMSTa+T33tb2CTlHPaZIMHpFzPphdibiAWJN
w/xX6YhgASkaf5bqK/sv2MiKdcT8iRkg9anCimOnWQXSobGeCyt3GBKs4jNh87Z3LK3xfd4oads+
K7yOZEj4JUJIxiZBUFOh4aX+94J25TmEwl8u5WGrj0J1KUpYzfcpEF8afo5396u1GKUhHkWomv/2
eVyfzHmEcgey2E1ZViT5Y2m9jF+qBtXA9tJRys+H5BqwYPXfEaUmR0vHVJXaQsgVm04qPrNzkODE
ndCZ/v5S2EGBN3mFP9nMtENTASsan4qZP1iiDsDCx7gcn18wdn8X3swgIw/0yVZ7tXU/eQb66/2G
dXwa/R+whQaQyM3xPK252LF9wdjDOS6L7pUunSRpJ7QBV9cHzVGprsKlfAcUNN1nCj+/Ojw7DHUv
tgU/GQjhFAF3sSbeQwpX+CDqFiqoDpKlxhe86h6SYFRkq81qwsbOHVm69IKHDjDOC6eIT1d0Ycx/
9/bhQhzMz5xtBAXC/E5jWgPRWMmJfyLMBJdwEODrHM+LjknFdYYbaAvs+2T4pCjtjPdYTRn6Ti/+
plkL2QklgyMOD9u/cu8ZdnOZePNJGQ9Y2AgMKuuz/6rrixB2ogtPqPRqkpLRQLw5uOvMlCJRl0aP
14hDatjRn5+dQRS9o6v3RiT7a5HELQw7OLp25qUy29Tm/GPSqAgcXj3qvXEyTvgTsCXJpz8uk7GP
VQYVXwzBiMyMRsLZil+9ZLfbb3yPzl7SVBlqBJIs5JW/CJ8Oxas50jdTZHk7XLFbJNsr/LwzRUki
hSiWDscfWA0UOzOl3Q8RjQcanI9R4oRaV+42RP6RPvK3iXGpuCrLNFHQ/bZJWs6dLqkGCKtVzeYF
bNp4Yj+KOfpQMCpNSXewp3DFRdZqCukPbKYAJiSGXMfl9tjXaYqzQzzgHtLP1I9ViaMoZ76qzHfS
bmgYWhF5baraVlR/BrleC5gDc1TUoxDgIKf7PZwAyqR9jY0v8RJzGvvhYnFJB4hg4T2eHEVEZ2xd
dGn91xV5DzCzFd3V5TC2XCmLU2tPmap7UNu9Qe+FlthlbI72o9BtImCJuTQZZ9OizTkM7Bsrb0Jb
pUw8fcx0ORPKi/8PMnlb4Y6prLN0FVJNKDukrJMqG4liJ/pOMXZLL1/Z8/XvuBE2KT7JM6yZ5xGF
UqEbcgfDn5XN/cpxuX1SVJU316aOWFMs2j6NqI1QBn7zLuZbYP3KhwrtnardClO+NXCTrirPdwEO
MvzF0rZQGBZZ1ovXilJ06afSWlx9pEzcm8NkYGH+xnW4L87M8e48/gVMzeZFLKca0+dieVAgKHp6
8Cb/vN0NIs1vCSD3Bp/jOaoHsqPF2x0B/QlCdE7ytuUGP4RE0JksnLxPUz4uhJz3rdoFRzTRx1OX
IG2ucaRfUd57Q4x5NSaanMYvK0j7087SuBWyd+LX+ohuAT9cHCu3zXptwv86Qkf4oWdbHHLDyr5P
ky841WjyWcGP8INReVfqQhz86MhcGxB5h5Dl9/0srl61mmNrPJ4wuV/cnRh/+G+OrSzQNQi1KueD
M7HNj0ObUJj8RByG+mnJnZ3mNGx8CI9RiD/cUfajxRAyV8vVQf18bcUy1SZUnOl/dgstWlPwiJT1
+hP8Sk4PefWdV6jvvZZ1gAFCxRFUp5FsNjA0/gNwF2AfkA+k8OeqZdfbrERkuKQVtFYRDoK2p4HO
5wHKdaEWB3/IRbtCxUxB64cWyXKUPLi6zuGx7J1L04vhuV12HQL/r+Ilw+BI3cBO3ee86683Ago9
RRBj038qUh0nGb160MHOlJ6JWrz0k3roTdHkZ3bH0zgEeVkAO233zwFUL8CSzkHO4/sIXRcg9TjS
mKU/M+A/eldbilHUrfd4vP7A3AQtK5MbgODrq9LlRplTBfpvEV2WdjwOFTBPRf9+asdC3uda3LTt
1DozRsHtHTAZRbH8FwTUP+u5pVVGEdyhOcpawmGnEQM2NTMuckNs3PqQnL35ZayNfRbf3b5U1Kwa
22NEfU78gvwTkmIU0+7Q9L3wgR8/5dSpj05qut0zJ/6H9N5IgoTbz6LiL6lPpmIr1C66zOqPo4rN
UZJ5E+dqyp8e3J+bnEf3WzJF6vVwJuUTvBlxCe2Wv4LvmyvW8f5eIE2DB9at1YNaZ4VonXgCY7WM
JfQVDtQj8HjMSYk4vjW9h052kJx87A09jf8d/VJUocn8UzNAkNg3x3H5f5TWxLNwLvo1XTUtZ2H8
RBxCJMQqDI1/miXVGAcA6RBNNi5nCZWEU/U7alOuPS58jhgNZ4QVNOYEErIwaJ3BbRsJ6QCwhyB6
V3fyRL9T6QcTSCjG1hpYdqNUF24iWRSHOsIrhsKJfbhYD+/1IQOw4F6BqB8ANa3SsLvNAlB88eLQ
ztkOaSepJCVOdbATMvYyFdt84LCEvAOd6+IHk3B7K8eZSCf5JYN8LeQouQg6c411eS3Etm/okxby
Ip8fRco/mM9FSa1JVVWXh6POd5MumeBoTdbPErFRJ4huhbqCBFaHZZrwaRdopox/3jeHXmLjh9B4
e7m8tqRUOZzsP4Y1zUlAY/hk7h+gC+lw0KIMaDQYUUHCYISCCvvs7GRwleGhBFPpI8Mj5BJSQLcU
Hxsl//SDBpKabh3myM392iElsW+A0kySoSsFRM+aN4cVlerqfiksTja+LcnWhzbUetRT07KcNF/J
OO3pEau6uYwoxoXGr7BQgm4YnJethikNpoGYnNUC+ZpKbutx25uGfVjVkBbQN706gzJgzocLWzlt
f14TMtLKKMBxBR3N/iCYJC9JcuZtgncHAvfIN/QOi5dcBlSboF1I8mvL15vOlxyOVjXTX7dCoLaN
9U+7zy2lv8XpxKPBh9bpAv8B0Mtd67LpjW3pIXXcynmZBBHJgGK4DavDmdQ6ZzHSwtBfU2LJyXES
6xvVBcKDRT6x4bNdMZxN4N3ARTw1sDARq+Dil0Hw0KsFx+3vPg15jC+mKlSIDrfUSKPeEuzci6p1
onoxNdW+z8qXT5OVImbSYVwDAEDO8hYo/3mng8guIVdH7TCArGRQiYwCVkIDjUTTV2j90+euwABe
3X6Vi6dNwvbnttYP9Sh4ayBdeSsSM6fSNLAKTQ15LFc/9d4D7IcEv/BjD/unwr29a5LJJ1YcFX8a
y7lbCPiHOrjemWmA3jqsTMaeFG9yA1KYsH4zHpG9Vze4KmJr1u+664qzyiUBaQ82Fvd8oxaJyS2T
u4r6MS7fppRYpSdM/VYTo/fmE2up4SflOYKxnZVD2jOxIgTCPAzULwnfX2g2L/aeXkdt9n2ldQaN
BZ0pytkfED4LR1E7kCLQB/fyyLKfErjtl09xfMpaKk2NGxZucjgJEcpxQDhqRXUcHzQ4Nj1rfwmF
1L0yxGjx2UeZMWA8NGYSon7HJb6oOQcA0rTu3+Eb7aEXxF1b/BoqWwXegYl+2NDlOOl2fE5NvRzZ
+NQnet0yRZQ7CC7O9Ja4Mi6t5IEKs1lCTgE51W4d9FXEvJfMY5FK0gapRAhBLQu8IPVsrdBbKfKn
cFiZm1z7dxgUi3UObOlsL5ImnHf91CDh85A+rdbrgxQjdkHDwZwj9YzLkwiuyzveg/xn6I8ouJbJ
YWfy9J9sfUa6pVPYSjlIhSViZqd2YjqAcJi25s91rPDbL8F/YfOA6I2HhRm/SC+Kt8VYhoDVqnBd
8qIiIqaJNy6OheYyTkFyCn7BBD2ACiJ4hCHjHhvKIXUx5DS6/VaJ2iUC/AjUV+zgEcWmRu6CSCZI
QmYF4ObWJ2uO7W5IZf+eHCl8Ql40kgUgHCTj9DiFMJ3sdZC/p3PV4U7gqzlGTgnnNZJmz/0yPD9r
tdojLoleKfSqGX4eXAaTz0ArgmWl3VMp+V9lLKyZ8R5O9aoTnAwP1IuEw3K5UkILbRr+Zht5v9Fs
hxmDcSgHdGQk4cqb7NuARxK0mijN5LeMrw4o5OE6L3yrQ9ALghuUP2C1lvrNJNV4ViC5lqrV4Vy0
FRJ4RMGsOQJfBPyYCw7tIKvLEZ4hRI3cGqATZQeWVDE/Qj0pFQ/d1apOoEcFLgBvk1cZKlyypNtH
C2Nfk3A4YodQmseMrqgLzQ+Z72OQ2+UcUGi7Sk28HjLvXYulx5B1P8kXkU3DAinlw9pWnOc0jicD
8J2k3DU4kJ8P7d9etQno8CqWpbTroXdWdQtziLfUB3XTgm18bLQd0oJ729wSzGs8UI/VMah7YFqQ
kKd0XNMBlo3t0O56llkX6WNsVB+JM0O+zKjwr7PjxxAg6wPmqD8fVy514TkP7KDyGt3WMWpf4RVc
HDSarl2/gSg46XwhMQNBWZZoQzRUErVRW+03vtSQgiX/8pA8BtRwQSzJvWKbn/VnqVgKoeJJi+XY
MY8RiAXI9KrMLkWaB1SoccTsZ8RI1mf6CrQ6aV8UHOU6Qw0nFghqn9oMxItKhU13b1n+gevNzyv3
Npj6efr/Kx666aivj4InmzMTMvyE9ZoHYsk6IFHkJKLYCWAoH17LCrJe0ewuQ923G1UjH1oU820f
RbmpNKthUNbox8AqZCMakGEiEQ5tuMind8UE3OYWGA5WAhIYCRm1U0glPhq/eB1AXtZH5GLpoKJi
F5+xYxuWQIjnTBAFhP9gYBnKhQqZFapI3hfjP2GgjxBmWs6kum0f4n/f1oZxMOC8qjajONtAYgox
Ye6XUx3KRIWJp8OeaUu/z2A/iO6spD4beYDvdaPifQeOA/t+UcoN6aIuSeLoU0bGXXI7JoVmJw3w
2ZMxdBWCR/iZHQX7EZgDJIrj65AmKEeBMHxaVX1nCS7k3RFUDXJelaVqbn0V+sPyvEMFSmPnOlAG
soTtgUuh1RmShfCtQYMYL8Tr/htBEP5KUSmHb2oRibNUYZYgD1cQHb3gYEByqJNvz0BTZcfzMM5n
p4RcG6uJPESDGqbO1I8JPulBzX22WROMW0pa85pgsnNRa7+xLSmeFQRTk+8dvlmGs+G0jOcmPusm
QC9cb85LShVl3vdq/6+cFid+xgE2h+J81KeCyGbIw7+dK2q+PKpJtaPjsBEO+5E6dBug1Odv4g1P
lIbK1o5bjNttlPv+WPchTFu13jjWtRjzUu95GKb9QfOEuHCkQ3O3gdTxyaqt3Qnb8TTw0xPZYkfe
SV8z/1FZtIJimFhwB8W2bWATCjW/dSPAwyDXiSRsKAuHL3K4K6ipdlNH3UEVUac6nHH9ul4QfWHo
3Xafh5L/Gc0CDDrz1hSyBlj5eIGqcRZb6+6djK8qB9XVTV73dSyQzTWHpw6KCfzAaqoFjD3sK238
NNMnKEiRyqi+RTSPr3EOO+DBJEKi49vgfsTSJM8FeLHj3QIxL02u6GlEa3I0eUBUdyLGz3jlNzER
A169WupipFpIpKFKtUCGRR60nsc8uLw4tQqaVDZscr2P5o7NqFW1z7dXpCRnPwilto57V8EJ63Ox
g284PGck5cMYKPFCu/5pEj7EI6HHfxazTDfaBoxqBhc02NAymXdgE3ox3eMEWtCGxOfCbLWXZFJ0
Bcq2JDUrmEtjNz1CQPm6Oar0PZeI0rDFKl7YK3mz7+whL0Pm6oukDOYSzAwZ8dkQSluyHVrygHd/
6QlFb3jxgqMuPF2Lxfb+Ic+RNlvyO9qtnj/ohU8lGZYhx2e4Te3wZ9qihKDkDwIJRvgXP9YlOIGj
7hSGZL7UQ7yOTJ7iCv4L8nq4hHXdfmExOQY6dPzAytSB8dV9CkHAs/m0ZTAdAsnq8RbIqRgqk06N
Xp4JY2UgGuUdFgW0KX+UOCInKzdA8HlbjyJhWy8NH9ACNswntlutXbiczY2pdgnaR9U4rQUUl87s
1WnaF8XV6Bo/8xxDo85emoFRbg5arUCRj94Gv2Tdx+agQ1QLFPtIdwqutnpE3Xh5j94P8Wlep7Mb
wxzYXagUjkUOLMMczrGvkDpUB51NLTtOSDRaED6vmBKbFsoF5SdAV7t4rLVy6MtBj7ipBq3viJOc
R610sD6cphOecpyS3ifO2pKDLIvlKD+6k6bEw94xPG5FpGzoqWsWQ5fFRBq91qSOHDmV0jZsLzse
4uW3rx3OiC/ERbo9uOnxedF92bhotroF2XETBaU3O/e4Vw1JNWqmUQ3Gu06Q5p47hN2BwHr6em1b
8mTg7OVC9tzrtJwPCANfcQPBdnTmZ+aszJnW1M1mFVe1JP60CYssHCCfpqF2GQ7Ekp+LdOYPK5bE
QXjctNnYtO7zDs8WAGnSPcaXnKTgptjUY0FSliw/iMmNf8G6q+RpElj22G3zcYsvQRHX2Kj9B6zw
ABaD2ACVix2jq+1lt9qAkW4TPXNjitfm4ZSwtMLxUrZK8nP8ewok7gFaBEtMwsIvRLhmfVIISjZ1
Fxu4cufjR2288zSGh5g+EsJ1LtNFkmDZafjxxdD9/G3nbYf90LqV2ar3/L3Qo9yqDRgbqVoflbOD
AYanZ8A9cR7YchZVgktoD6Knsqx/74Wrd95SyTkKXrWD+Xujzqz7f3RdU0fWs+hM7rdZztnYTSxX
1xkAUU/mazeweyXlDrpvJmDLPLcfjr89Y5GeXtLWr5zcouECcldiK/LePhxynXM5ww9zwDBZLsIM
Zkk3xnJxhqd6faFkxvxf65NnnYuDzwRoXmee69pYRhD/Xi+13+PIzlAMXqkpeXpmiJXYENGLUzNj
pG9Jc8iA+tGi0bHlJAYLpW2gYVmP4T+ouSi/eJCyRLW1BESeTLwauK3qznP8HUoy+HDei3k5iHYc
iuxz+8HHW/ftzmZPe2EJKIm+uQ6KHfpPXK4hrFCxlWg4q8WGsZh/Vn6MfBuDpPj5uz/leB9acikj
/uG/QH5OnO0IqywvCnd2lVqMhHjGbYm9cgM5pWRNo5zMXInpJ8s7EyJKF2sMRB3PJDfOsL4QPYxv
9Fsh2e1lpB4R9Itw9Xjtfbzi6gmXRZnmDycMTHVm0FlZ2QFe19OcdcKgVrYfY85/rCz4d5dOwcAP
q1wX+I0V98YYSVA/h2npk3v+xMULe8uJf4DANkTMy2dS6ewl/2zeU4ZxN5TW92aoHOVvHWYzb2Km
AXI772PSI6D7Ip+xS0Id6waq1FRTAIbbYHqAHZdhAXy4vkKXec/BFmn9GxrqPLb3vbxSRdCgzxz/
sicFm2jzhqOAGWx8x1KlDhSvrL+h5HdiUA/Tnt/ISzjQzVaOxaqUDdG4htGfSFMUCln4VXtTtKho
MXP7xWMqyfTon8XT492jicEy+D5CH15ORRrWnr1UiGE/qxt+V62obU37jSARHGWTCpjslaZHtfQL
Y/uaALTPGgi/cqeX9UGMN3Vsls339HCptzIz7di0bb2/f5p/OSCAW5EaDJ40OCw5+0xy60XAmgNZ
N8e6U2XZQXt9mV2Ihy686enxv4J5LRtgMtIh0LPeyiJca7pXr8lIurUCh8c2woDiMBT+taZgEKjT
5DRGhRbgutu0T5bWxu1xKZL4tAQWJIOrH79kK+mLD+uEd+S0PZ+Uk6nSIk+y7f30yoBcEXIm/SdW
4rKJ3OahTxJZTug2y+YG2W7w76xj3Mv2jLKQLp5+cKXj6Jsy3TncHCpEq+PPfZBAziz02fJ/l/5S
k7brnSl3ePzSB9qQ3Ng3t0jYbtN7MAET0HWj2FcApgZP4Z/IK51vtp5b4BepFagGz/E7iXA/7JfW
TtQG70a5b7FDmmK9LGlSnoZYhNQEzaR4mm2SiFFiIt+9GuycTTtcelwVrjk4jK9+xowZNYlD7RFa
tmdzsUCDFJ3FGlsDJ78fJEPHNCEPUOY1fJaHIjubilCn2B2LwaG/+q4XIKqwPyTa3Vg/KUoLvXia
ZLudklu9wO5vEyp7dVmp1mV7MTX16ThvBst8Row1oBZtCv2CuqpAfJxg5Mh4fC+WQaIK5zModBZj
scB8CCwjBsWu05wBp4Vzw50FLCseOUJ5taXGz64sZSXYKs5dB3Q8Dxj2zlzaxC8oNmbyf0q4OZeC
vI/VWcoOvbNdIfgXi5RNHvF+tQHpobDRFDrKUzIPjVjDdHk/1FasVe/p/kEYjSKxQdmw0wJJ2nVw
GRHga13gGuTay/kXshtwRLPVU5dhwE/zkoTOFmOlgB8DKg7lPBgFuOIPRToVeePd0jz/L7Nx2M58
cwT07E5GcF80Xa3u8OTyBvUYDiL83EeKadawEICN5XL4JP+DEt2HX7CeVSl4vF2FzkQg+ots3T7H
VEJlGCToSE67mgWY6/PagsxgsYMOjJyGy1aTU6fJ/cQqKpbgOQuA5rrjhPYQjGP/RAtFz2cq0ezM
WSkcxfi62vX+fXufMHRnEe5in8PQ9oCt50HJxf8+xeQ8nqB8FTMzbPd3/mKbjnFZiyCKLiZ7uiXc
I7MixJ2c/AOpvlEy7FrNT1msh8N9zmvewPnkvgkEWJilUl3KT8KVrwFHRcGDC3SNDdi4DHwOxXMc
6VP4TWGKZJ288yYW0JBPWp7dyAO90xiBIIIPu9NIks644w+XF+UahKcMD4XKP4U/wTlMVg90mIyS
aoGQuH5yJCXE6XBEnc9RurQvfIIvZgN204xiEJk++0wZGqwyom3+YLDBy0ZGdVBPb1SK3qy5+1O7
TMjG7LGyy4gFzoQs3ad0LDbpN0uPehQPzy/9FYwQDz2hdJ+NDv6+jOTo/IgF29tPR9IXIG0LrOEV
QuWsY65sJXMvaaMGHQCkNRKqrQb1RQu1ZaSqY0XmkDa9XcETUQMBm+TMeCgAl117Qgb6KmoDZiDZ
ATiXmCwPGEuA4H7uau5lbIrLmxlaIcHUYvS0JVVL3vORdZpUJvaBkijD1sAxqnk0NMojN5C13WAc
SEbipiUqjvgkB1ohOJKdlJUo7g8wGCFcR9SrzzmCFctpBRKGX4pK9K+hYDfsQA7hU0is8hQQ4mbm
/0phd5jqxRbnPO0zAvJQ/nL5YYDsrHUhrcCgRAKy+fl2ocuT1SbHwmyFs/HyALTKSouMENAAQGKS
VPCqrEHqrIUUDtKM8cCu1kUr8viwiWNfBy4GZ3umFyOvkF/O9WicsI8LRBotih+mrSAYEqhNu7Ol
inIJufzsDkVnbGuUkGKnV0fUVHXHLpI4NGXZn02saGQEzLeUzYOKCQYmQW/lizgXQAjEsqPzmh1y
CG2ZAsKeilkCHTp3ISwOBRmDUpRq9aWNHkhy5orpcB0HdcFXDpV9lcY8OP1kreiDMitI4oK5xkNt
yITcnegDMRW0WDtT02TZEzTpp1Z2r5Wfqnm3Zii1RdbHDFtTZl4YCFKbSuhc6hyj22U/OxW+cw8E
WU6eYiY5wpiFS0sHGBaUSlmFEzOsCQGHIkk7+Wyv6Kd3JXhoXKZzKeaaOO53cnAqVSBpfeBELo12
eyaB+vfKtJLZCjczazgg0BMaTyMumrsJaDRLx0MNXSfA4iHhTrHsbshCMbQxsp75V3i9XsDwMzhh
01YFdIN1br/MO4Ed3pfaKJfFRLjTeXiZEwWRM+zPmAmkBbRS9m0zdm3MYQWA00jvYv2dtqk0VEU+
0U3BQnkxOwxh5UKscK3jhcfUkYxi6UWrUu6xGNn8mBd2jgsP9n25qhaJOl/hQhAPIhXchF0S39qy
/7BP4DMr6WRaRaj1WmsieQGcoUdbaVbCvpBF6NafazVujj8trgXpL+S1IAtH3P3qUmuM7MNMhtpj
EBPGreVFzv/Lvf+uUTBat+TmvqosX5jxIkA+W5kJoORd3nof0sEMYbzGQGLjKfEf
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lWJHvBT8DgkNbFHSuw19NASjZWRim3cU/o/JIpBKQidKh7zoQlwGsVK97NwheUuDsu5LsXP7nSLP
hcBo37ENgQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
gCWDen+F4i7DQAnKc06JR0QZPNT3ulwTbIpNFUJxEmZI94QbJdv7WuS7X/Bzyp1LwkTRRyO/t4Qt
JV5F/ObUcJO1i1GCi8H8TFywwPwHLvuzlr03CtLR7cw+d68I1Wbj9xBclI9Dp2qsK9CRNjlQ/wOl
xU1A4oruZ7D/QftxCUA=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bkp01UwKvcRDI2wqmK01joALOf0O5xsPWh5cppm6sWzduYVozCl/VcTPfteAJV/N1XIyWrnxSyQJ
75VrWqFpxQUJKy4yZqBydatnGmKLz6iZeE/UtcD05m05igSfmQ9CKpMthcdRiMKJo+7S5KgwD0vc
bmutM4jZVIELvouYfnQrdlCzr49nDQri0daGopyTXE8RAxJkVy/6hr0Fwp8BXg04mTVE212Gx3xI
iqxCqes58TZR/iviXTMl/W4/Fk/f9u3CfCpr1EpefrGaw1fbZDx3q9dCNrH6SFxiRPkh5r05ZuRJ
SZCszOeJxVYDQsFXU9jtAinRidI7qv0I3xUkwA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
EgsLMQJWrkWWDeZKBpb9k6+Fl2D915QAnfUzIHcF1dQubpEOJ/6j1/Ok6mNVHV+Juf3PinvPJ1GN
NFP7AheqLlSEndjSFdWjiwc17GY0t9tRBRDp7JaAcTdGJU6hG0XTWqKBd3I6zfwLbfqiHmTdnXN6
C9WFXYI7kCacTdeqN3g=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RRXwEbMizZGYYC8gbqe21zreWfhQeNbrrTtG5t5YcwbRhecwr/lRClAmkB/moFG03eIPcERuDwFC
3qyjNGh+LDw++Hcdiens8h8y0la8p3Ho8ktUz09m8tLPLqE6a9UTeoOCRdhaSWvsXGUaa5iQQr7X
16fZViePKj4F2dwHvQrshHi3M7OQzqzvSmQ6aZXQwBlYHrPH1/CzBFBOSdDdKdoaqyEpjakpSp9L
OpIVgDIawvB5yjkmw4Pp/0/307/VqsCtC0tTIjHXV43PU6dUWdKZGo6yHlQR4+1LZyUbPQAcftr4
hlVQziq3IRCpzjXhk7B/dnic9p82X0kW2B01Lg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10992)
`protect data_block
d65p9+/6mBZZMaBMQcDhbX/UPTT8bNcq9duiKtJrJAd5NGZQgJJ3iI5GKp6NdfcIZ+/mf0+yC6cG
E/9pnRCK/JTkTlqQwo3/sqIJ9XiQLFKp12TiFWizZpbhOJMcYgjyYWgfmtzVKQxYZGCQdgYbb6Mu
wTlclEj/DMMCVTvz4zVAuVdJhClz4jFbEn9a3tmkTXizOllQLHcB+8JwCKzo5FU8FFyGT+X5aj07
gOFRXL+OwuaQFgTJHRpa1oyUFNnbHi8aZRn4VWU6T1Nz/OLXsSHIYUxpKEKqSNynTGZ8armietaM
P908TQeONXWK0W7gwrDQcTpUP8gqN0O/dXfsOTTjt9V7I0XCy9Pp4w6VU8Vs12teZs+SphNbyNUc
TSOuDDwWlPl8LJu1Yzx96qdQUw8jP1HMqytWyrFNJS5T6DPQ3q478vLjnIuXBPW6K0g5tq+dnN/O
aP0P/Hz+3GyEPAfEeNveEn+JwmTx5dttCQ4BXFkEfrDgEO5ipsZWgxOapkzgPQiyhNsAb+4Ridzk
ySyyJCqpdMM70mSANcTdR/bFIiBA8NbPnq6IWSJQeKuYA3NQfN7jnKVgqJzuytJgob9S3MwqHk2M
mbqRMCMlm7tgpPtajzFXiHHQ1K+Rmy/AArLRkhxujXn3TPBeD6nRSAa5e4Emuxhto+qXchBhR0uW
vWN3HOyGkDufpAR/FcmNgWS65MhcvnxruJ7ARgnwZVd8O7rfq1kVSV0RukzQPLCtNzZvYn9h0/om
4YgKXgTKDhUxeOGKtkKq6333obMoVydKAi/SUOAF+91VY+ic0GpcmQct7SHhHK0ZT1marx4SdMfA
MgQFgqGkT1Kr1xei99Rij+miJPl08Q3M59MG5IQuc5EQBAaChBHP/zwTTQ7tChGrqCKI86QsbcJP
gxl+/hLqsI+LogEIZycJKtJEO/WRDtttpzVjEnHEl1wlQATHfsCquid9rI2ODk3Qth1UqHjkL2g4
OYPPed2bwBWWCP9O5DKWpFxjWExkunOt5sKlVI36jos2LQabY76zIEKD4+DEC6CkuZ/AQ4XCo08G
hjjIJlNtR1vkymmMxXaXqQEzH7QscvRiBC0xo4+Swkg7FjRLiM6liFicKh/qIAiDZj35zntvcW8v
oFIjNoT4hAv/OPUpJOV1JOEvmiqszjHJ4wfzr1RPL6YBsK/lNJjSBl8AsEjt7iMWu6KpiqcWnxBF
akxAdBggsCNuOBMCZ+FG6KdFRIpv3EgHJKVcwpKr4BtpmfPdY+FrH3RvITliCXdxNzNusvj+m8ck
YTmDvjRPZhXj29Z9GOReapge/yBkzZSwNVT7tE8/TUl4fINMtMzWGKn3IhNMCUiNBygUXPiAuBOp
+FmFo+8Qmbaihvd23EP8C3OT5kZI+52weDe1SXtpp0tAHqrzb7xogmAicqp7Kbx5hhyMT6MWCPYP
xUWRmKzM90xoqN8TtBfO8zX8kFul3vOWiLXrt3WE0syrPp74/8EzaMdUIZd9GJIH5448FSti8iDj
FlyX/SCZX4vmVL+IxFE9rPKnbmjmNeguphOQ5tKu1Iyzl6YZvQtbb7i+lVNBo7fZwy6vuoXEFo0c
lqYWQbMzXwVLeRYfWWwQhA4iXD4AT5ifzvrh7JSrXeeikC6WTjHZzpChXtnVKQ7s8TudRb7KWIQR
FSiDmqSmScKo+72LG4pogMS484tOBX8ZD8Xzsd0hWDl/5xhEKtr5CfYemJ/bORVOHA/L8vv1HbTY
vxoqKniTGsrwc/DcEKN1jjRCuK+V+UevmUq2/J3Ekn8xsysS3MZ/8S16u9i/E+1KtGRPcKzQC/fZ
KXecxz41re/xZN5y4GuPZRbM5HMMlIMdc50p6hq9yMfk80U91zIomBC3WkR3uXOR9EGI3K1w2eRe
A/QDtrhPvMLHozJYdqNzkPq5W4dZnsVG+tpj3WEybdSoS6Mh4dzfA8wFyCEcA8OGAloFTJsYpLzR
xERX1OxZ5wXjWltmMfvKC4/tE9Hz6OAEhr3+o+byQ9QwvfHVAUiajWB+XBQJcvX+0Lilr9bcSZVt
8vRGcxyDL+7Zp/+HnkSvYmzyJf4vQFSPNLR0NloB+oOAeYh7Sck2mt4b6Bid/H+odCJuanQx/i7P
gJonF00evw7cZGGu/3nCje7W27jhIPqfyTl1wIywCBWqF+1NimfhdlVzcvbl/nnxWCn/FOMeKKvf
d28WY2g0Xb8uXIpu12iqkg7jbM+c6FD3+pzJU6J57c1DLY7D8v+xRLXNJoaW9DYbOAxprOiosjdf
8onv4BiBWXrw1oIYLkuVXBQmIrtLTOAEre2qC+iA4ZJ/sMl9iVKCA3XWmz5aaL809zCVEgvzW/+a
tiSD4uyKcp19Kux7qfH7YlzjXMamIiV79bkFttx6lLWgj301yg9e/tvizOlfL6H5wIjRPaMmEaK7
lQ4uyywh0nx6P4dE3MWeYkb6Wte0JRMgmOwBy0h0zRSUAPU2fVUoKMWhCx3c0XuCVxrspQs+WujK
KV6dTikY4v7OLn9V7dIJytgkDIRrPbHY0phKs9DVhm5i2p7m3QydHBe5Eq9leOtghMM25upFb0vv
bzKDldHYN0abrvbNDP9LhSIzpHhJWgO9rBPwOlzdko44p2JnW++easkmq32WulqVuHl20oGuzkxF
mdndThe5z12xrkP5Se95YRbeo8aI+XcupWw6FHX6xxgzkdXS1F8eo79IZEXdfrT8HdH5aLQyUwDV
ag2m0Epz1lV1Fn6TX/sCQD+bT1Rlb1WRjXVPrUs88rwstTQYvFEOXVUEd9pW4K+rbwnoJjiznc4y
8XNzB5eW3IibA+W7crXN0o5tFPJTtxEkW1S17sSsmimGAN12ysfQC4NNqz/7jK3wqnwp98zt2MSc
J+LOswu0Iic+5J5a0I4VxPFBgl7HIYZp5XolsEjvrEU902VWP2dEW77aDjComsr/YkCIgoC8k/It
wfNGa2VcedTvTXiYG01wMzz3HP9VtiwP1AcRc0bsFr/HVlHO+f3ASKxwgljRFa2MeuzCB+LiZ3pu
b4+J0rFKO3UHNS27UbekD4zmK9/yWw5RG7OEKzK3225PtZhkRo+VhMhjKF9iak579tqMf8wMkoj1
vxT2Hyjw5fQWxZua5fa1Yxqvr4lOKtPbBDIbpxMbW9+wL57pou9xVSNMlXsitZ044yyh5fS+YKNt
fGb3Zyicj8By7iNnmpIY1A+ovtVq5tfMlRL5JznVSSu+2VO2Qpec5hyypz5YkZwMXhN6EGbiOU7o
yOUIctFb22oxr3MM2zzIExqqBee/CAtJKRL/DHX8Vy8c8BaRMKYD7H91H0fU5IElL9QKzfvo13Fj
A1KLi7z7+BLouc9gc9DbxtckKgs6ZKYYllBRaw9DKTCJsmlS22rlknssASjXnOl54AqGQg963cRl
nBH58ZFhQWeF7Kh2vAfjoO7icSxM7IKY/MI8cN5aIjGyTnJHMd46Zalttcl4eJbMVXXfCw19DFAW
TYG8ZlCHBi9KHqPlOt8igJS0FlYByfGT2ysY6VmKDLXnKuvbRjrQbjvRDMMDI+x0YTCgfRenr2Yv
6DdVoaXpIlxJx4Bq2hmegLB4pgHoBooNzXoW4NQUWh3IEC/j5ZTV8myviDJpYlZt4UnyfRAD7IcT
rNMHTI3tZgzV8mVpJyd76GOzaIZg1ajKM6hrjKlnsKpflElqaqXGcj+MuWvg/2bZ4XbA4KlZ9+5D
v9065oNAcIBe1T+2eyfVMjfx0qHxXvfufeci3Q6/q6OO9nGdh3Sd8BZL3IHnawghISLdHSeqwmnf
JW5n0IfNF2gd/Gf+V/NwMFiOa5IL6QRXZazsjp0AxBU98e/+Up4aXBS4Dlf5V1nESFxnc1bqT4UD
Mjb17BQUAV4yydB+mFVmsl0engm07LqoU4G3KQkVu8qGZH58+p8no87DF8eHnF+lEO+JuPStnQYs
sZf7MZtuLLWd16lXXRAj/EdYzgDtePHQyvBtaEf7ocCFPBZ7U6Bxdje+n2cdZ/ak4kO3EHyNJabY
EUOQVdYoQhdAyAvtUaBA9Ei+HxOxOoIstXQ6J1FBAUt0h7yIurVFLFu5lIi0qCCas6MLdalIXLxc
mm8aRKKzssDGI05CXy9FJCCoR4s23s9L2ZLg3F6piV+r07uyJHmp4lX/OR7hWeqwVYzbXiXLhBzx
9V0JUSyspcp7c5CRA9BboYac3MZWFv6wTOMnn+Zeb62g/ned8GgLegbsGIU9hNMty1XQlEKYTfOv
N3ygU2myXn2aCwqIQVTZPHW2g1yhM9QAcKw9jEHrEUXnwbyDttMHMxnHO9+spS/GRUlY+7jLdJrW
2fsm4c1oUsXrFxuMZmBx0O96V3tzPzIQg0qFB7zNH19mAiiTC33ALqetkrfYj/Vh/WRU7imHzKM4
ExaeSRWjX9yfJHw3na+kx5adU6IY7/mpWSdE/iDFmRBMh4bgh7J3+YkAe2r0ZaJwfjmHLv6JfzQV
YblrkmZ1x+fauNjNizFhFnMJR2ok3b42yfppg+LFers4FC8R2p7dkS2dJqO7XnvTxIRY/OrquEdb
SKjOQB+8C6hC9imX2bfLZ5aZG37YPH1F9gYFfujv2hYfXI2CumG5lephLkCiypPqwoFZXk6Lnjao
steReotDUFyR46qYATd+AIPpmnmHYKqKfrg6qwT0KoZqqjm76zasDTAVsPyYQPUibMbmBURuBdko
68zMyxBvcrD+ZmJvcKLQwFnRO6a06pwYz+qyUvOE4DdmsR/nXlH1iAyOBJEo28ccazzB74H71mpH
e93/XBdjiplNIP+gN0k2Ov3lHcLlhflb/8L0BoVcCXt7vfxv4c5uNdz3OG0JgqXJibGXDkGZVRFc
yIRmJIbtFSDwWBfShyL3S5aL3f/ZCrE7c/Pqtq9+TCqG2tnE+u6PDS75QZaRlPO1YaKz6u0v0RZH
t9VzPBUg7sMNwKszvlIisp9TlteGBGKQimJMvAsYjMSTa+T33tb2CTlHPaZIMHpFzPphdibiAWJN
w/xX6YhgASkaf5bqK/sv2MiKdcT8iRkg9anCimOnWQXSobGeCyt3GBKs4jNh87Z3LK3xfd4oads+
K7yOZEj4JUJIxiZBUFOh4aX+94J25TmEwl8u5WGrj0J1KUpYzfcpEF8afo5396u1GKUhHkWomv/2
eVyfzHmEcgey2E1ZViT5Y2m9jF+qBtXA9tJRys+H5BqwYPXfEaUmR0vHVJXaQsgVm04qPrNzkODE
ndCZ/v5S2EGBN3mFP9nMtENTASsan4qZP1iiDsDCx7gcn18wdn8X3swgIw/0yVZ7tXU/eQb66/2G
dXwa/R+whQaQyM3xPK252LF9wdjDOS6L7pUunSRpJ7QBV9cHzVGprsKlfAcUNN1nCj+/Ojw7DHUv
tgU/GQjhFAF3sSbeQwpX+CDqFiqoDpKlxhe86h6SYFRkq81qwsbOHVm69IKHDjDOC6eIT1d0Ycx/
9/bhQhzMz5xtBAXC/E5jWgPRWMmJfyLMBJdwEODrHM+LjknFdYYbaAvs+2T4pCjtjPdYTRn6Ti/+
plkL2QklgyMOD9u/cu8ZdnOZePNJGQ9Y2AgMKuuz/6rrixB2ogtPqPRqkpLRQLw5uOvMlCJRl0aP
14hDatjRn5+dQRS9o6v3RiT7a5HELQw7OLp25qUy29Tm/GPSqAgcXj3qvXEyTvgTsCXJpz8uk7GP
VQYVXwzBiMyMRsLZil+9ZLfbb3yPzl7SVBlqBJIs5JW/CJ8Oxas50jdTZHk7XLFbJNsr/LwzRUki
hSiWDscfWA0UOzOl3Q8RjQcanI9R4oRaV+42RP6RPvK3iXGpuCrLNFHQ/bZJWs6dLqkGCKtVzeYF
bNp4Yj+KOfpQMCpNSXewp3DFRdZqCukPbKYAJiSGXMfl9tjXaYqzQzzgHtLP1I9ViaMoZ76qzHfS
bmgYWhF5baraVlR/BrleC5gDc1TUoxDgIKf7PZwAyqR9jY0v8RJzGvvhYnFJB4hg4T2eHEVEZ2xd
dGn91xV5DzCzFd3V5TC2XCmLU2tPmap7UNu9Qe+FlthlbI72o9BtImCJuTQZZ9OizTkM7Bsrb0Jb
pUw8fcx0ORPKi/8PMnlb4Y6prLN0FVJNKDukrJMqG4liJ/pOMXZLL1/Z8/XvuBE2KT7JM6yZ5xGF
UqEbcgfDn5XN/cpxuX1SVJU316aOWFMs2j6NqI1QBn7zLuZbYP3KhwrtnardClO+NXCTrirPdwEO
MvzF0rZQGBZZ1ovXilJ06afSWlx9pEzcm8NkYGH+xnW4L87M8e48/gVMzeZFLKca0+dieVAgKHp6
8Cb/vN0NIs1vCSD3Bp/jOaoHsqPF2x0B/QlCdE7ytuUGP4RE0JksnLxPUz4uhJz3rdoFRzTRx1OX
IG2ucaRfUd57Q4x5NSaanMYvK0j7087SuBWyd+LX+ohuAT9cHCu3zXptwv86Qkf4oWdbHHLDyr5P
ky841WjyWcGP8INReVfqQhz86MhcGxB5h5Dl9/0srl61mmNrPJ4wuV/cnRh/+G+OrSzQNQi1KueD
M7HNj0ObUJj8RByG+mnJnZ3mNGx8CI9RiD/cUfajxRAyV8vVQf18bcUy1SZUnOl/dgstWlPwiJT1
+hP8Sk4PefWdV6jvvZZ1gAFCxRFUp5FsNjA0/gNwF2AfkA+k8OeqZdfbrERkuKQVtFYRDoK2p4HO
5wHKdaEWB3/IRbtCxUxB64cWyXKUPLi6zuGx7J1L04vhuV12HQL/r+Ilw+BI3cBO3ee86683Ago9
RRBj038qUh0nGb160MHOlJ6JWrz0k3roTdHkZ3bH0zgEeVkAO233zwFUL8CSzkHO4/sIXRcg9TjS
mKU/M+A/eldbilHUrfd4vP7A3AQtK5MbgODrq9LlRplTBfpvEV2WdjwOFTBPRf9+asdC3uda3LTt
1DozRsHtHTAZRbH8FwTUP+u5pVVGEdyhOcpawmGnEQM2NTMuckNs3PqQnL35ZayNfRbf3b5U1Kwa
22NEfU78gvwTkmIU0+7Q9L3wgR8/5dSpj05qut0zJ/6H9N5IgoTbz6LiL6lPpmIr1C66zOqPo4rN
UZJ5E+dqyp8e3J+bnEf3WzJF6vVwJuUTvBlxCe2Wv4LvmyvW8f5eIE2DB9at1YNaZ4VonXgCY7WM
JfQVDtQj8HjMSYk4vjW9h052kJx87A09jf8d/VJUocn8UzNAkNg3x3H5f5TWxLNwLvo1XTUtZ2H8
RBxCJMQqDI1/miXVGAcA6RBNNi5nCZWEU/U7alOuPS58jhgNZ4QVNOYEErIwaJ3BbRsJ6QCwhyB6
V3fyRL9T6QcTSCjG1hpYdqNUF24iWRSHOsIrhsKJfbhYD+/1IQOw4F6BqB8ANa3SsLvNAlB88eLQ
ztkOaSepJCVOdbATMvYyFdt84LCEvAOd6+IHk3B7K8eZSCf5JYN8LeQouQg6c411eS3Etm/okxby
Ip8fRco/mM9FSa1JVVWXh6POd5MumeBoTdbPErFRJ4huhbqCBFaHZZrwaRdopox/3jeHXmLjh9B4
e7m8tqRUOZzsP4Y1zUlAY/hk7h+gC+lw0KIMaDQYUUHCYISCCvvs7GRwleGhBFPpI8Mj5BJSQLcU
Hxsl//SDBpKabh3myM392iElsW+A0kySoSsFRM+aN4cVlerqfiksTja+LcnWhzbUetRT07KcNF/J
OO3pEau6uYwoxoXGr7BQgm4YnJethikNpoGYnNUC+ZpKbutx25uGfVjVkBbQN706gzJgzocLWzlt
f14TMtLKKMBxBR3N/iCYJC9JcuZtgncHAvfIN/QOi5dcBlSboF1I8mvL15vOlxyOVjXTX7dCoLaN
9U+7zy2lv8XpxKPBh9bpAv8B0Mtd67LpjW3pIXXcynmZBBHJgGK4DavDmdQ6ZzHSwtBfU2LJyXES
6xvVBcKDRT6x4bNdMZxN4N3ARTw1sDARq+Dil0Hw0KsFx+3vPg15jC+mKlSIDrfUSKPeEuzci6p1
onoxNdW+z8qXT5OVImbSYVwDAEDO8hYo/3mng8guIVdH7TCArGRQiYwCVkIDjUTTV2j90+euwABe
3X6Vi6dNwvbnttYP9Sh4ayBdeSsSM6fSNLAKTQ15LFc/9d4D7IcEv/BjD/unwr29a5LJJ1YcFX8a
y7lbCPiHOrjemWmA3jqsTMaeFG9yA1KYsH4zHpG9Vze4KmJr1u+664qzyiUBaQ82Fvd8oxaJyS2T
u4r6MS7fppRYpSdM/VYTo/fmE2up4SflOYKxnZVD2jOxIgTCPAzULwnfX2g2L/aeXkdt9n2ldQaN
BZ0pytkfED4LR1E7kCLQB/fyyLKfErjtl09xfMpaKk2NGxZucjgJEcpxQDhqRXUcHzQ4Nj1rfwmF
1L0yxGjx2UeZMWA8NGYSon7HJb6oOQcA0rTu3+Eb7aEXxF1b/BoqWwXegYl+2NDlOOl2fE5NvRzZ
+NQnet0yRZQ7CC7O9Ja4Mi6t5IEKs1lCTgE51W4d9FXEvJfMY5FK0gapRAhBLQu8IPVsrdBbKfKn
cFiZm1z7dxgUi3UObOlsL5ImnHf91CDh85A+rdbrgxQjdkHDwZwj9YzLkwiuyzveg/xn6I8ouJbJ
YWfy9J9sfUa6pVPYSjlIhSViZqd2YjqAcJi25s91rPDbL8F/YfOA6I2HhRm/SC+Kt8VYhoDVqnBd
8qIiIqaJNy6OheYyTkFyCn7BBD2ACiJ4hCHjHhvKIXUx5DS6/VaJ2iUC/AjUV+zgEcWmRu6CSCZI
QmYF4ObWJ2uO7W5IZf+eHCl8Ql40kgUgHCTj9DiFMJ3sdZC/p3PV4U7gqzlGTgnnNZJmz/0yPD9r
tdojLoleKfSqGX4eXAaTz0ArgmWl3VMp+V9lLKyZ8R5O9aoTnAwP1IuEw3K5UkILbRr+Zht5v9Fs
hxmDcSgHdGQk4cqb7NuARxK0mijN5LeMrw4o5OE6L3yrQ9ALghuUP2C1lvrNJNV4ViC5lqrV4Vy0
FRJ4RMGsOQJfBPyYCw7tIKvLEZ4hRI3cGqATZQeWVDE/Qj0pFQ/d1apOoEcFLgBvk1cZKlyypNtH
C2Nfk3A4YodQmseMrqgLzQ+Z72OQ2+UcUGi7Sk28HjLvXYulx5B1P8kXkU3DAinlw9pWnOc0jicD
8J2k3DU4kJ8P7d9etQno8CqWpbTroXdWdQtziLfUB3XTgm18bLQd0oJ729wSzGs8UI/VMah7YFqQ
kKd0XNMBlo3t0O56llkX6WNsVB+JM0O+zKjwr7PjxxAg6wPmqD8fVy514TkP7KDyGt3WMWpf4RVc
HDSarl2/gSg46XwhMQNBWZZoQzRUErVRW+03vtSQgiX/8pA8BtRwQSzJvWKbn/VnqVgKoeJJi+XY
MY8RiAXI9KrMLkWaB1SoccTsZ8RI1mf6CrQ6aV8UHOU6Qw0nFghqn9oMxItKhU13b1n+gevNzyv3
Npj6efr/Kx666aivj4InmzMTMvyE9ZoHYsk6IFHkJKLYCWAoH17LCrJe0ewuQ923G1UjH1oU820f
RbmpNKthUNbox8AqZCMakGEiEQ5tuMind8UE3OYWGA5WAhIYCRm1U0glPhq/eB1AXtZH5GLpoKJi
F5+xYxuWQIjnTBAFhP9gYBnKhQqZFapI3hfjP2GgjxBmWs6kum0f4n/f1oZxMOC8qjajONtAYgox
Ye6XUx3KRIWJp8OeaUu/z2A/iO6spD4beYDvdaPifQeOA/t+UcoN6aIuSeLoU0bGXXI7JoVmJw3w
2ZMxdBWCR/iZHQX7EZgDJIrj65AmKEeBMHxaVX1nCS7k3RFUDXJelaVqbn0V+sPyvEMFSmPnOlAG
soTtgUuh1RmShfCtQYMYL8Tr/htBEP5KUSmHb2oRibNUYZYgD1cQHb3gYEByqJNvz0BTZcfzMM5n
p4RcG6uJPESDGqbO1I8JPulBzX22WROMW0pa85pgsnNRa7+xLSmeFQRTk+8dvlmGs+G0jOcmPusm
QC9cb85LShVl3vdq/6+cFid+xgE2h+J81KeCyGbIw7+dK2q+PKpJtaPjsBEO+5E6dBug1Odv4g1P
lIbK1o5bjNttlPv+WPchTFu13jjWtRjzUu95GKb9QfOEuHCkQ3O3gdTxyaqt3Qnb8TTw0xPZYkfe
SV8z/1FZtIJimFhwB8W2bWATCjW/dSPAwyDXiSRsKAuHL3K4K6ipdlNH3UEVUac6nHH9ul4QfWHo
3Xafh5L/Gc0CDDrz1hSyBlj5eIGqcRZb6+6djK8qB9XVTV73dSyQzTWHpw6KCfzAaqoFjD3sK238
NNMnKEiRyqi+RTSPr3EOO+DBJEKi49vgfsTSJM8FeLHj3QIxL02u6GlEa3I0eUBUdyLGz3jlNzER
A169WupipFpIpKFKtUCGRR60nsc8uLw4tQqaVDZscr2P5o7NqFW1z7dXpCRnPwilto57V8EJ63Ox
g284PGck5cMYKPFCu/5pEj7EI6HHfxazTDfaBoxqBhc02NAymXdgE3ox3eMEWtCGxOfCbLWXZFJ0
Bcq2JDUrmEtjNz1CQPm6Oar0PZeI0rDFKl7YK3mz7+whL0Pm6oukDOYSzAwZ8dkQSluyHVrygHd/
6QlFb3jxgqMuPF2Lxfb+Ic+RNlvyO9qtnj/ohU8lGZYhx2e4Te3wZ9qihKDkDwIJRvgXP9YlOIGj
7hSGZL7UQ7yOTJ7iCv4L8nq4hHXdfmExOQY6dPzAytSB8dV9CkHAs/m0ZTAdAsnq8RbIqRgqk06N
Xp4JY2UgGuUdFgW0KX+UOCInKzdA8HlbjyJhWy8NH9ACNswntlutXbiczY2pdgnaR9U4rQUUl87s
1WnaF8XV6Bo/8xxDo85emoFRbg5arUCRj94Gv2Tdx+agQ1QLFPtIdwqutnpE3Xh5j94P8Wlep7Mb
wxzYXagUjkUOLMMczrGvkDpUB51NLTtOSDRaED6vmBKbFsoF5SdAV7t4rLVy6MtBj7ipBq3viJOc
R610sD6cphOecpyS3ifO2pKDLIvlKD+6k6bEw94xPG5FpGzoqWsWQ5fFRBq91qSOHDmV0jZsLzse
4uW3rx3OiC/ERbo9uOnxedF92bhotroF2XETBaU3O/e4Vw1JNWqmUQ3Gu06Q5p47hN2BwHr6em1b
8mTg7OVC9tzrtJwPCANfcQPBdnTmZ+aszJnW1M1mFVe1JP60CYssHCCfpqF2GQ7Ekp+LdOYPK5bE
QXjctNnYtO7zDs8WAGnSPcaXnKTgptjUY0FSliw/iMmNf8G6q+RpElj22G3zcYsvQRHX2Kj9B6zw
ABaD2ACVix2jq+1lt9qAkW4TPXNjitfm4ZSwtMLxUrZK8nP8ewok7gFaBEtMwsIvRLhmfVIISjZ1
Fxu4cufjR2288zSGh5g+EsJ1LtNFkmDZafjxxdD9/G3nbYf90LqV2ar3/L3Qo9yqDRgbqVoflbOD
AYanZ8A9cR7YchZVgktoD6Knsqx/74Wrd95SyTkKXrWD+Xujzqz7f3RdU0fWs+hM7rdZztnYTSxX
1xkAUU/mazeweyXlDrpvJmDLPLcfjr89Y5GeXtLWr5zcouECcldiK/LePhxynXM5ww9zwDBZLsIM
Zkk3xnJxhqd6faFkxvxf65NnnYuDzwRoXmee69pYRhD/Xi+13+PIzlAMXqkpeXpmiJXYENGLUzNj
pG9Jc8iA+tGi0bHlJAYLpW2gYVmP4T+ouSi/eJCyRLW1BESeTLwauK3qznP8HUoy+HDei3k5iHYc
iuxz+8HHW/ftzmZPe2EJKIm+uQ6KHfpPXK4hrFCxlWg4q8WGsZh/Vn6MfBuDpPj5uz/leB9acikj
/uG/QH5OnO0IqywvCnd2lVqMhHjGbYm9cgM5pWRNo5zMXInpJ8s7EyJKF2sMRB3PJDfOsL4QPYxv
9Fsh2e1lpB4R9Itw9Xjtfbzi6gmXRZnmDycMTHVm0FlZ2QFe19OcdcKgVrYfY85/rCz4d5dOwcAP
q1wX+I0V98YYSVA/h2npk3v+xMULe8uJf4DANkTMy2dS6ewl/2zeU4ZxN5TW92aoHOVvHWYzb2Km
AXI772PSI6D7Ip+xS0Id6waq1FRTAIbbYHqAHZdhAXy4vkKXec/BFmn9GxrqPLb3vbxSRdCgzxz/
sicFm2jzhqOAGWx8x1KlDhSvrL+h5HdiUA/Tnt/ISzjQzVaOxaqUDdG4htGfSFMUCln4VXtTtKho
MXP7xWMqyfTon8XT492jicEy+D5CH15ORRrWnr1UiGE/qxt+V62obU37jSARHGWTCpjslaZHtfQL
Y/uaALTPGgi/cqeX9UGMN3Vsls339HCptzIz7di0bb2/f5p/OSCAW5EaDJ40OCw5+0xy60XAmgNZ
N8e6U2XZQXt9mV2Ihy686enxv4J5LRtgMtIh0LPeyiJca7pXr8lIurUCh8c2woDiMBT+taZgEKjT
5DRGhRbgutu0T5bWxu1xKZL4tAQWJIOrH79kK+mLD+uEd+S0PZ+Uk6nSIk+y7f30yoBcEXIm/SdW
4rKJ3OahTxJZTug2y+YG2W7w76xj3Mv2jLKQLp5+cKXj6Jsy3TncHCpEq+PPfZBAziz02fJ/l/5S
k7brnSl3ePzSB9qQ3Ng3t0jYbtN7MAET0HWj2FcApgZP4Z/IK51vtp5b4BepFagGz/E7iXA/7JfW
TtQG70a5b7FDmmK9LGlSnoZYhNQEzaR4mm2SiFFiIt+9GuycTTtcelwVrjk4jK9+xowZNYlD7RFa
tmdzsUCDFJ3FGlsDJ78fJEPHNCEPUOY1fJaHIjubilCn2B2LwaG/+q4XIKqwPyTa3Vg/KUoLvXia
ZLudklu9wO5vEyp7dVmp1mV7MTX16ThvBst8Row1oBZtCv2CuqpAfJxg5Mh4fC+WQaIK5zModBZj
scB8CCwjBsWu05wBp4Vzw50FLCseOUJ5taXGz64sZSXYKs5dB3Q8Dxj2zlzaxC8oNmbyf0q4OZeC
vI/VWcoOvbNdIfgXi5RNHvF+tQHpobDRFDrKUzIPjVjDdHk/1FasVe/p/kEYjSKxQdmw0wJJ2nVw
GRHga13gGuTay/kXshtwRLPVU5dhwE/zkoTOFmOlgB8DKg7lPBgFuOIPRToVeePd0jz/L7Nx2M58
cwT07E5GcF80Xa3u8OTyBvUYDiL83EeKadawEICN5XL4JP+DEt2HX7CeVSl4vF2FzkQg+ots3T7H
VEJlGCToSE67mgWY6/PagsxgsYMOjJyGy1aTU6fJ/cQqKpbgOQuA5rrjhPYQjGP/RAtFz2cq0ezM
WSkcxfi62vX+fXufMHRnEe5in8PQ9oCt50HJxf8+xeQ8nqB8FTMzbPd3/mKbjnFZiyCKLiZ7uiXc
I7MixJ2c/AOpvlEy7FrNT1msh8N9zmvewPnkvgkEWJilUl3KT8KVrwFHRcGDC3SNDdi4DHwOxXMc
6VP4TWGKZJ288yYW0JBPWp7dyAO90xiBIIIPu9NIks644w+XF+UahKcMD4XKP4U/wTlMVg90mIyS
aoGQuH5yJCXE6XBEnc9RurQvfIIvZgN204xiEJk++0wZGqwyom3+YLDBy0ZGdVBPb1SK3qy5+1O7
TMjG7LGyy4gFzoQs3ad0LDbpN0uPehQPzy/9FYwQDz2hdJ+NDv6+jOTo/IgF29tPR9IXIG0LrOEV
QuWsY65sJXMvaaMGHQCkNRKqrQb1RQu1ZaSqY0XmkDa9XcETUQMBm+TMeCgAl117Qgb6KmoDZiDZ
ATiXmCwPGEuA4H7uau5lbIrLmxlaIcHUYvS0JVVL3vORdZpUJvaBkijD1sAxqnk0NMojN5C13WAc
SEbipiUqjvgkB1ohOJKdlJUo7g8wGCFcR9SrzzmCFctpBRKGX4pK9K+hYDfsQA7hU0is8hQQ4mbm
/0phd5jqxRbnPO0zAvJQ/nL5YYDsrHUhrcCgRAKy+fl2ocuT1SbHwmyFs/HyALTKSouMENAAQGKS
VPCqrEHqrIUUDtKM8cCu1kUr8viwiWNfBy4GZ3umFyOvkF/O9WicsI8LRBotih+mrSAYEqhNu7Ol
inIJufzsDkVnbGuUkGKnV0fUVHXHLpI4NGXZn02saGQEzLeUzYOKCQYmQW/lizgXQAjEsqPzmh1y
CG2ZAsKeilkCHTp3ISwOBRmDUpRq9aWNHkhy5orpcB0HdcFXDpV9lcY8OP1kreiDMitI4oK5xkNt
yITcnegDMRW0WDtT02TZEzTpp1Z2r5Wfqnm3Zii1RdbHDFtTZl4YCFKbSuhc6hyj22U/OxW+cw8E
WU6eYiY5wpiFS0sHGBaUSlmFEzOsCQGHIkk7+Wyv6Kd3JXhoXKZzKeaaOO53cnAqVSBpfeBELo12
eyaB+vfKtJLZCjczazgg0BMaTyMumrsJaDRLx0MNXSfA4iHhTrHsbshCMbQxsp75V3i9XsDwMzhh
01YFdIN1br/MO4Ed3pfaKJfFRLjTeXiZEwWRM+zPmAmkBbRS9m0zdm3MYQWA00jvYv2dtqk0VEU+
0U3BQnkxOwxh5UKscK3jhcfUkYxi6UWrUu6xGNn8mBd2jgsP9n25qhaJOl/hQhAPIhXchF0S39qy
/7BP4DMr6WRaRaj1WmsieQGcoUdbaVbCvpBF6NafazVujj8trgXpL+S1IAtH3P3qUmuM7MNMhtpj
EBPGreVFzv/Lvf+uUTBat+TmvqosX5jxIkA+W5kJoORd3nof0sEMYbzGQGLjKfEf
`protect end_protected
|
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: memory_mgmt - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity memory_mgmt is
port (
clk : in std_logic;
sclr : in std_logic;
rd : in std_logic;
rd_node_addr : in node_address_type;
rd_centre_list_address : in centre_list_address_type;
rd_k : in centre_index_type;
wr_cent_nd : in std_logic;
wr_cent : in std_logic;
wr_centre_list_address : in centre_list_address_type;
wr_centre_list_data : in centre_index_type;
wr_init_cent : in std_logic;
wr_centre_list_address_init : in centre_list_address_type;
wr_centre_list_data_init : in centre_index_type;
wr_init_node : in std_logic;
wr_node_address_init : in node_address_type;
wr_node_data_init : in node_data_type;
wr_init_pos : in std_logic;
wr_centre_list_pos_address_init : in centre_index_type;
wr_centre_list_pos_data_init : in data_type;
valid : out std_logic;
rd_node_data : out node_data_type;
rd_centre_list_data : out centre_index_type;
rd_centre_list_pos_data : out data_type;
last_centre : out std_logic;
item_read_twice : out std_logic;
rd_centre_list_address_out : out centre_list_address_type
);
end memory_mgmt;
architecture Behavioral of memory_mgmt is
constant CENTRE_LIST_ADDR_BITWIDTH : integer := CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH;
constant MEM_LAT : integer := 3;
constant MEM_POS_LAT : integer := 2;
type rd_state_type is (idle, reading_centre_list);
type wr_state_type is (idle, writing_centre_list);
type centre_index_delay_type is array(0 to MEM_POS_LAT-1) of centre_index_type;
type node_data_delay_type is array(0 to MEM_POS_LAT-1) of node_data_type;
type centre_list_address_delay_type is array(0 to MEM_POS_LAT-1) of centre_list_address_type;
component node_memory_top
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(NODE_POINTER_BITWIDTH-1 downto 0);
dina : in std_logic_vector(3*D*COORD_BITWIDTH+D*COORD_BITWIDTH_EXT+COORD_BITWIDTH+COORD_BITWIDTH_EXT+2*NODE_POINTER_BITWIDTH-1 downto 0);
clkb : in std_logic;
addrb : in std_logic_vector(NODE_POINTER_BITWIDTH-1 downto 0);
doutb : out std_logic_vector(3*D*COORD_BITWIDTH+D*COORD_BITWIDTH_EXT+COORD_BITWIDTH+COORD_BITWIDTH_EXT+2*NODE_POINTER_BITWIDTH-1 downto 0)
);
end component;
component centre_index_memory_top
port (
clk : in std_logic;
sclr : in std_logic;
rd : in std_logic;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(INDEX_BITWIDTH-1 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(INDEX_BITWIDTH-1 DOWNTO 0);
item_read_twice : out std_logic;
item_address : out std_logic_vector(CNTR_POINTER_BITWIDTH-1 downto 0)
);
end component;
component centre_positions_memory
port (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(INDEX_BITWIDTH-1 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(D*COORD_BITWIDTH-1 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(INDEX_BITWIDTH-1 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(D*COORD_BITWIDTH-1 DOWNTO 0)
);
end component;
signal rd_state : rd_state_type;
signal rd_counter_done : std_logic;
signal rd_counter : centre_index_type;
signal wr_state : wr_state_type;
signal wr_counter : centre_index_type;
signal reading_centres : std_logic;
signal delay_line : std_logic_vector(0 to MEM_LAT+MEM_POS_LAT+1-1);
signal rd_centre_list_address_reg : centre_list_address_type;
signal tmp_rd_centre_list_address : std_logic_vector(CENTRE_LIST_ADDR_BITWIDTH-1 downto 0);
signal rd_k_reg : centre_index_type;
signal rd_node_address_reg : node_address_type;
signal wr_centre_list_wea : std_logic;
signal virtual_write_address_reg : std_logic;
signal wr_centre_list_address_mux : centre_list_address_type;
signal wr_centre_list_address_reg : centre_list_address_type;
signal tmp_wr_centre_list_address : std_logic_vector(CENTRE_LIST_ADDR_BITWIDTH-1 downto 0);
signal wr_cent_reg : std_logic;
signal wr_centre_list_data_mux : centre_index_type;
signal wr_centre_list_data_reg : centre_index_type;
signal tmp_item_read_twice : std_logic;
signal tmp_item_address : centre_list_address_type;
signal wr_node_reg : std_logic;
signal wr_node_address_reg : node_address_type;
signal wr_node_data_reg : node_data_type;
signal tmp_wr_node_address : std_logic_vector(NODE_POINTER_BITWIDTH-1 downto 0);
signal tmp_wr_node_data_in : std_logic_vector(3*D*COORD_BITWIDTH+D*COORD_BITWIDTH_EXT+COORD_BITWIDTH+COORD_BITWIDTH_EXT+2*NODE_POINTER_BITWIDTH-1 downto 0);
signal tmp_rd_node_data_out : std_logic_vector(3*D*COORD_BITWIDTH+D*COORD_BITWIDTH_EXT+COORD_BITWIDTH+COORD_BITWIDTH_EXT+2*NODE_POINTER_BITWIDTH-1 downto 0);
signal tmp_rd_node_address : std_logic_vector(NODE_POINTER_BITWIDTH-1 downto 0);
signal node_data_delay : node_data_delay_type;
signal tmp_centre_in : std_logic_vector(INDEX_BITWIDTH-1 downto 0);
signal tmp_centre_out : std_logic_vector(INDEX_BITWIDTH-1 downto 0);
signal centre_out_delay_line : centre_index_delay_type;
signal item_read_twice_delay_line : std_logic_vector(0 to MEM_POS_LAT-1);
signal centre_list_address_delay : centre_list_address_delay_type;
signal tmp_wr_centre_list_pos_data_init : std_logic_vector(D*COORD_BITWIDTH-1 downto 0);
signal tmp_centre_pos_out : std_logic_vector(D*COORD_BITWIDTH-1 downto 0);
begin
fsm_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
rd_state <= idle;
elsif rd_state = idle AND rd = '1' then
rd_state <= reading_centre_list;
elsif rd_state = reading_centre_list AND rd_counter_done = '1' then
rd_state <= idle;
end if;
if sclr = '1' then
wr_state <= idle;
elsif wr_state = idle AND (wr_cent_nd = '1' OR wr_init_cent = '1') then
wr_state <= writing_centre_list;
elsif wr_state = writing_centre_list AND (wr_cent_nd = '0' AND wr_init_cent = '0') then
wr_state <= idle;
end if;
end if;
end process fsm_proc;
counter_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
rd_counter <= (others => '0');
else
if rd_state <= idle then
rd_counter <= (others => '0');
else
rd_counter <= rd_counter+1;
end if;
end if;
if sclr = '1' then
wr_counter <= (others => '0');
else
if wr_state <= idle then
wr_counter <= (others => '0');
elsif wr_cent_reg = '1' then --(wr_cent_nd ='1' AND wr_cent='1') OR wr_init_cent='1' then
wr_counter <= wr_counter+1;
end if;
end if;
end if;
end process counter_proc;
rd_counter_done <= '1' WHEN rd_counter = rd_k_reg AND rd_state = reading_centre_list ELSE '0';
addr_reg_proc : process(clk)
begin
if rising_edge(clk) then
if rd_state = idle AND rd = '1' then
rd_centre_list_address_reg <= rd_centre_list_address;
rd_node_address_reg <= rd_node_addr;
rd_k_reg <= rd_k;
end if;
end if;
end process addr_reg_proc;
-- mux between init and normal wr
wr_centre_list_address_mux <= wr_centre_list_address WHEN wr_init_cent = '0' ELSE wr_centre_list_address_init;
wr_centre_list_data_mux <= wr_centre_list_data WHEN wr_init_cent = '0' ELSE wr_centre_list_data_init;
-- delay buffer wr input by one cycle due to state machine
wr_input_reg_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
wr_cent_reg <= '0';
wr_node_reg <= '0';
else
wr_cent_reg <= (wr_cent_nd AND wr_cent) OR wr_init_cent;
wr_node_reg <= wr_init_node;
end if;
if ((wr_state = idle AND wr_cent_nd = '1') OR wr_init_cent = '1') then
wr_centre_list_address_reg <= wr_centre_list_address_mux;
end if;
if sclr = '1' then
virtual_write_address_reg <= '0';
elsif (wr_state = idle AND wr_cent_nd = '1') then
if wr_centre_list_address = std_logic_vector(to_unsigned(0,CNTR_POINTER_BITWIDTH)) then
virtual_write_address_reg <= '1';
else
virtual_write_address_reg <= '0';
end if;
end if;
wr_centre_list_data_reg <= wr_centre_list_data_mux;
wr_node_address_reg <= wr_node_address_init;
wr_node_data_reg <= wr_node_data_init;
end if;
end process wr_input_reg_proc;
tmp_rd_centre_list_address(CENTRE_LIST_ADDR_BITWIDTH-1 downto INDEX_BITWIDTH) <= std_logic_vector(rd_centre_list_address_reg);
tmp_rd_centre_list_address(INDEX_BITWIDTH-1 downto 0) <= std_logic_vector(rd_counter);
tmp_wr_centre_list_address(CENTRE_LIST_ADDR_BITWIDTH-1 downto INDEX_BITWIDTH) <= std_logic_vector(wr_centre_list_address_reg);
tmp_wr_centre_list_address(INDEX_BITWIDTH-1 downto 0) <= std_logic_vector(wr_counter);
tmp_centre_in <= std_logic_vector(wr_centre_list_data_reg);
wr_centre_list_wea <= wr_cent_reg AND NOT(virtual_write_address_reg);
centre_index_memory_top_inst : centre_index_memory_top
port map (
clk => clk,
sclr => sclr,
rd => reading_centres,
wea(0) => wr_centre_list_wea,
addra => tmp_wr_centre_list_address,
dina => tmp_centre_in,
addrb => tmp_rd_centre_list_address,
doutb => tmp_centre_out,
item_read_twice => tmp_item_read_twice,
item_address => tmp_item_address
);
tmp_rd_node_address <= std_logic_vector(rd_node_address_reg);
tmp_wr_node_address <= std_logic_vector(wr_node_address_reg);
tmp_wr_node_data_in <= nodedata_2_stdlogic(wr_node_data_reg);
node_memory_top_inst : node_memory_top
port map(
clka => clk,
wea(0) => wr_node_reg,
addra => tmp_wr_node_address,
dina => tmp_wr_node_data_in,
clkb => clk,
addrb => tmp_rd_node_address,
doutb => tmp_rd_node_data_out
);
reading_centres <= '1' WHEN rd_state = reading_centre_list ELSE '0';
dely_line_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
delay_line <= (others => '0');
else
delay_line(0) <= reading_centres;
delay_line(1 to MEM_LAT+MEM_POS_LAT+1-1) <= delay_line(0 to MEM_LAT+MEM_POS_LAT+1-2);
centre_out_delay_line(0) <= unsigned(tmp_centre_out);
centre_out_delay_line(1 to MEM_POS_LAT-1) <= centre_out_delay_line(0 to MEM_POS_LAT-2);
node_data_delay(0) <= stdlogic_2_nodedata(tmp_rd_node_data_out);
node_data_delay(1 to MEM_POS_LAT-1) <= node_data_delay(0 to MEM_POS_LAT-2);
item_read_twice_delay_line(0) <= tmp_item_read_twice;
item_read_twice_delay_line(1 to MEM_POS_LAT-1) <= item_read_twice_delay_line(0 to MEM_POS_LAT-2);
centre_list_address_delay(0) <= tmp_item_address;
centre_list_address_delay(1 to MEM_POS_LAT-1) <= centre_list_address_delay(0 to MEM_POS_LAT-2);
end if;
end if;
end process dely_line_proc;
tmp_wr_centre_list_pos_data_init <= datapoint_2_stdlogic(wr_centre_list_pos_data_init);
centre_positions_memory_inst : centre_positions_memory
port map (
clka => clk,
wea(0) => wr_init_pos,
addra => std_logic_vector(wr_centre_list_pos_address_init),
dina => tmp_wr_centre_list_pos_data_init,
clkb => clk,
addrb => tmp_centre_out,
doutb => tmp_centre_pos_out
);
valid <= delay_line(MEM_LAT+MEM_POS_LAT-1);
rd_centre_list_data <= centre_out_delay_line(MEM_POS_LAT-1);
rd_node_data <= node_data_delay(MEM_POS_LAT-1);
rd_centre_list_pos_data <= stdlogic_2_datapoint(tmp_centre_pos_out);
last_centre <= delay_line(MEM_LAT+MEM_POS_LAT-1) AND NOT(delay_line(MEM_LAT+MEM_POS_LAT-2));
item_read_twice <= item_read_twice_delay_line(MEM_POS_LAT-1);
rd_centre_list_address_out <= centre_list_address_delay(MEM_POS_LAT-1);
end Behavioral;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_fwft_96x512_hf_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_fwft_96x512_hf_top is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(96-1 DOWNTO 0);
DOUT : OUT std_logic_vector(96-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end fifo_fwft_96x512_hf_top;
architecture xilinx of fifo_fwft_96x512_hf_top is
SIGNAL clk_i : std_logic;
component fifo_fwft_96x512_hf is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(96-1 DOWNTO 0);
DOUT : OUT std_logic_vector(96-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : fifo_fwft_96x512_hf PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
PROG_EMPTY => prog_empty,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
PACKAGE sgate_pack IS
function sgate_conv_integer(arg : in std_logic_vector)
return integer;
COMPONENT oper_add
GENERIC
(
sgate_representation : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_o : NATURAL
);
PORT
(
a : IN STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(width_b-1 DOWNTO 0);
cin : IN STD_LOGIC;
cout : OUT STD_LOGIC;
o : OUT STD_LOGIC_VECTOR(width_o-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT oper_addsub
GENERIC
(
sgate_representation : NATURAL ;
width_a : NATURAL;
width_b : NATURAL;
width_o : NATURAL
);
PORT
(
a : IN STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(width_b-1 DOWNTO 0);
addnsub : IN STD_LOGIC;
o : OUT STD_LOGIC_VECTOR(width_o-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT mux21
PORT
(
dataa : IN STD_LOGIC;
datab : IN STD_LOGIC;
dataout : OUT STD_LOGIC;
outputselect : IN STD_LOGIC
);
END COMPONENT;
COMPONENT io_buf_tri
PORT
(
datain : IN STD_LOGIC;
dataout : OUT STD_LOGIC;
oe : IN STD_LOGIC
);
END COMPONENT;
COMPONENT io_buf_opdrn
PORT
(
datain : IN STD_LOGIC;
dataout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT tri_bus
GENERIC
(
width_datain : NATURAL;
width_dataout : NATURAL
);
PORT
(
datain : IN STD_LOGIC_VECTOR(width_datain-1 downto 0);
dataout : OUT STD_LOGIC_VECTOR(width_dataout-1 downto 0)
);
END COMPONENT;
COMPONENT oper_mult
GENERIC
(
sgate_representation : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_o : NATURAL
);
PORT
(
a : IN STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(width_b-1 DOWNTO 0);
o : OUT STD_LOGIC_VECTOR(width_o-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT oper_div
GENERIC
(
sgate_representation : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_o : NATURAL
);
PORT
(
a : IN STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(width_b-1 DOWNTO 0);
o : OUT STD_LOGIC_VECTOR(width_o-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT oper_mod
GENERIC
(
sgate_representation : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_o : NATURAL
);
PORT
(
a : IN STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(width_b-1 DOWNTO 0);
o : OUT STD_LOGIC_VECTOR(width_o-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT oper_left_shift
GENERIC
(
width_a : NATURAL;
width_amount : NATURAL;
width_o : NATURAL
);
PORT
(
a : IN STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
amount : IN STD_LOGIC_VECTOR(width_amount-1 DOWNTO 0);
cin : IN STD_LOGIC;
o : OUT STD_LOGIC_VECTOR(width_o-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT oper_right_shift
GENERIC
(
sgate_representation : NATURAL;
width_a : NATURAL;
width_amount : NATURAL;
width_o : NATURAL
);
PORT
(
a : IN STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
amount : IN STD_LOGIC_VECTOR(width_amount-1 DOWNTO 0);
cin : IN STD_LOGIC;
o : OUT STD_LOGIC_VECTOR(width_o-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT oper_rotate_left
GENERIC
(
width_a : NATURAL;
width_amount : NATURAL;
width_o : NATURAL
);
PORT
(
a : IN STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
amount : IN STD_LOGIC_VECTOR(width_amount-1 DOWNTO 0);
o : OUT STD_LOGIC_VECTOR(width_o-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT oper_rotate_right
GENERIC
(
width_a : NATURAL;
width_amount : NATURAL;
width_o : NATURAL
);
PORT
(
a : IN STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
amount : IN STD_LOGIC_VECTOR(width_amount-1 DOWNTO 0);
o : OUT STD_LOGIC_VECTOR(width_o-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT oper_less_than
GENERIC
(
sgate_representation : NATURAL;
width_a : NATURAL;
width_b : NATURAL
);
PORT
(
a : IN STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(width_b-1 DOWNTO 0);
cin : IN STD_LOGIC;
o : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT oper_mux
GENERIC
(
width_sel : NATURAL;
width_data : NATURAL
);
PORT
(
sel : IN STD_LOGIC_VECTOR(width_sel-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(width_data-1 DOWNTO 0);
o : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT oper_selector
GENERIC
(
width_sel : NATURAL;
width_data : NATURAL
);
PORT
(
sel : IN STD_LOGIC_VECTOR(width_sel-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(width_data-1 DOWNTO 0);
o : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT oper_prio_selector
GENERIC
(
width_sel : NATURAL;
width_data : NATURAL
);
PORT
(
sel : IN STD_LOGIC_VECTOR(width_sel-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(width_data-1 DOWNTO 0);
cin : IN STD_LOGIC;
o : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT oper_decoder
GENERIC
(
width_i : NATURAL;
width_o : NATURAL
);
PORT
(
i : IN STD_LOGIC_VECTOR(width_i-1 DOWNTO 0);
o : OUT STD_LOGIC_VECTOR(width_o-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT oper_bus_mux
GENERIC
(
width_a : NATURAL;
width_b : NATURAL;
width_o : NATURAL
);
PORT
(
a : IN STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(width_b-1 DOWNTO 0);
sel : IN STD_LOGIC;
o : OUT STD_LOGIC_VECTOR(width_o-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT oper_latch
PORT
(
datain : IN STD_LOGIC;
aclr : IN STD_LOGIC;
preset : IN STD_LOGIC;
dataout : OUT STD_LOGIC;
latch_enable : IN STD_LOGIC
);
END COMPONENT;
END sgate_pack;
package body sgate_pack is
-- convert std_logic_vector to integer
function sgate_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer := 0;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end sgate_conv_integer;
end sgate_pack;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.3
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convolve_kernel is
generic (
C_S_AXI_CONTROL_ADDR_WIDTH : INTEGER := 4;
C_S_AXI_CONTROL_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
bufw_0_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_0_EN_A : OUT STD_LOGIC;
bufw_0_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_0_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_0_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_0_Clk_A : OUT STD_LOGIC;
bufw_0_Rst_A : OUT STD_LOGIC;
bufw_0_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_0_EN_B : OUT STD_LOGIC;
bufw_0_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_0_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_0_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_0_Clk_B : OUT STD_LOGIC;
bufw_0_Rst_B : OUT STD_LOGIC;
bufw_1_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_1_EN_A : OUT STD_LOGIC;
bufw_1_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_1_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_1_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_1_Clk_A : OUT STD_LOGIC;
bufw_1_Rst_A : OUT STD_LOGIC;
bufw_1_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_1_EN_B : OUT STD_LOGIC;
bufw_1_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_1_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_1_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_1_Clk_B : OUT STD_LOGIC;
bufw_1_Rst_B : OUT STD_LOGIC;
bufw_2_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_2_EN_A : OUT STD_LOGIC;
bufw_2_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_2_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_2_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_2_Clk_A : OUT STD_LOGIC;
bufw_2_Rst_A : OUT STD_LOGIC;
bufw_2_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_2_EN_B : OUT STD_LOGIC;
bufw_2_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_2_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_2_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_2_Clk_B : OUT STD_LOGIC;
bufw_2_Rst_B : OUT STD_LOGIC;
bufw_3_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_3_EN_A : OUT STD_LOGIC;
bufw_3_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_3_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_3_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_3_Clk_A : OUT STD_LOGIC;
bufw_3_Rst_A : OUT STD_LOGIC;
bufw_3_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_3_EN_B : OUT STD_LOGIC;
bufw_3_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_3_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_3_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_3_Clk_B : OUT STD_LOGIC;
bufw_3_Rst_B : OUT STD_LOGIC;
bufw_4_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_4_EN_A : OUT STD_LOGIC;
bufw_4_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_4_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_4_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_4_Clk_A : OUT STD_LOGIC;
bufw_4_Rst_A : OUT STD_LOGIC;
bufw_4_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_4_EN_B : OUT STD_LOGIC;
bufw_4_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_4_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_4_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_4_Clk_B : OUT STD_LOGIC;
bufw_4_Rst_B : OUT STD_LOGIC;
bufw_5_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_5_EN_A : OUT STD_LOGIC;
bufw_5_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_5_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_5_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_5_Clk_A : OUT STD_LOGIC;
bufw_5_Rst_A : OUT STD_LOGIC;
bufw_5_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_5_EN_B : OUT STD_LOGIC;
bufw_5_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_5_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_5_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_5_Clk_B : OUT STD_LOGIC;
bufw_5_Rst_B : OUT STD_LOGIC;
bufw_6_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_6_EN_A : OUT STD_LOGIC;
bufw_6_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_6_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_6_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_6_Clk_A : OUT STD_LOGIC;
bufw_6_Rst_A : OUT STD_LOGIC;
bufw_6_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_6_EN_B : OUT STD_LOGIC;
bufw_6_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_6_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_6_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_6_Clk_B : OUT STD_LOGIC;
bufw_6_Rst_B : OUT STD_LOGIC;
bufw_7_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_7_EN_A : OUT STD_LOGIC;
bufw_7_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_7_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_7_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_7_Clk_A : OUT STD_LOGIC;
bufw_7_Rst_A : OUT STD_LOGIC;
bufw_7_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_7_EN_B : OUT STD_LOGIC;
bufw_7_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_7_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_7_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_7_Clk_B : OUT STD_LOGIC;
bufw_7_Rst_B : OUT STD_LOGIC;
bufw_8_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_8_EN_A : OUT STD_LOGIC;
bufw_8_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_8_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_8_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_8_Clk_A : OUT STD_LOGIC;
bufw_8_Rst_A : OUT STD_LOGIC;
bufw_8_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_8_EN_B : OUT STD_LOGIC;
bufw_8_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_8_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_8_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_8_Clk_B : OUT STD_LOGIC;
bufw_8_Rst_B : OUT STD_LOGIC;
bufw_9_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_9_EN_A : OUT STD_LOGIC;
bufw_9_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_9_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_9_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_9_Clk_A : OUT STD_LOGIC;
bufw_9_Rst_A : OUT STD_LOGIC;
bufw_9_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_9_EN_B : OUT STD_LOGIC;
bufw_9_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_9_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_9_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_9_Clk_B : OUT STD_LOGIC;
bufw_9_Rst_B : OUT STD_LOGIC;
bufw_10_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_10_EN_A : OUT STD_LOGIC;
bufw_10_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_10_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_10_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_10_Clk_A : OUT STD_LOGIC;
bufw_10_Rst_A : OUT STD_LOGIC;
bufw_10_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_10_EN_B : OUT STD_LOGIC;
bufw_10_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_10_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_10_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_10_Clk_B : OUT STD_LOGIC;
bufw_10_Rst_B : OUT STD_LOGIC;
bufw_11_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_11_EN_A : OUT STD_LOGIC;
bufw_11_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_11_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_11_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_11_Clk_A : OUT STD_LOGIC;
bufw_11_Rst_A : OUT STD_LOGIC;
bufw_11_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_11_EN_B : OUT STD_LOGIC;
bufw_11_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_11_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_11_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_11_Clk_B : OUT STD_LOGIC;
bufw_11_Rst_B : OUT STD_LOGIC;
bufw_12_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_12_EN_A : OUT STD_LOGIC;
bufw_12_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_12_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_12_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_12_Clk_A : OUT STD_LOGIC;
bufw_12_Rst_A : OUT STD_LOGIC;
bufw_12_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_12_EN_B : OUT STD_LOGIC;
bufw_12_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_12_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_12_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_12_Clk_B : OUT STD_LOGIC;
bufw_12_Rst_B : OUT STD_LOGIC;
bufi_0_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_0_EN_A : OUT STD_LOGIC;
bufi_0_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_0_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_0_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_0_Clk_A : OUT STD_LOGIC;
bufi_0_Rst_A : OUT STD_LOGIC;
bufi_0_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_0_EN_B : OUT STD_LOGIC;
bufi_0_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_0_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_0_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_0_Clk_B : OUT STD_LOGIC;
bufi_0_Rst_B : OUT STD_LOGIC;
bufi_1_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_1_EN_A : OUT STD_LOGIC;
bufi_1_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_1_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_1_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_1_Clk_A : OUT STD_LOGIC;
bufi_1_Rst_A : OUT STD_LOGIC;
bufi_1_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_1_EN_B : OUT STD_LOGIC;
bufi_1_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_1_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_1_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_1_Clk_B : OUT STD_LOGIC;
bufi_1_Rst_B : OUT STD_LOGIC;
bufi_2_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_2_EN_A : OUT STD_LOGIC;
bufi_2_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_2_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_2_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_2_Clk_A : OUT STD_LOGIC;
bufi_2_Rst_A : OUT STD_LOGIC;
bufi_2_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_2_EN_B : OUT STD_LOGIC;
bufi_2_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_2_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_2_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_2_Clk_B : OUT STD_LOGIC;
bufi_2_Rst_B : OUT STD_LOGIC;
bufo_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_EN_A : OUT STD_LOGIC;
bufo_WEN_A : OUT STD_LOGIC_VECTOR (63 downto 0);
bufo_Din_A : OUT STD_LOGIC_VECTOR (511 downto 0);
bufo_Dout_A : IN STD_LOGIC_VECTOR (511 downto 0);
bufo_Clk_A : OUT STD_LOGIC;
bufo_Rst_A : OUT STD_LOGIC;
bufo_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_EN_B : OUT STD_LOGIC;
bufo_WEN_B : OUT STD_LOGIC_VECTOR (63 downto 0);
bufo_Din_B : OUT STD_LOGIC_VECTOR (511 downto 0);
bufo_Dout_B : IN STD_LOGIC_VECTOR (511 downto 0);
bufo_Clk_B : OUT STD_LOGIC;
bufo_Rst_B : OUT STD_LOGIC;
s_axi_control_AWVALID : IN STD_LOGIC;
s_axi_control_AWREADY : OUT STD_LOGIC;
s_axi_control_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_ADDR_WIDTH-1 downto 0);
s_axi_control_WVALID : IN STD_LOGIC;
s_axi_control_WREADY : OUT STD_LOGIC;
s_axi_control_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH-1 downto 0);
s_axi_control_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH/8-1 downto 0);
s_axi_control_ARVALID : IN STD_LOGIC;
s_axi_control_ARREADY : OUT STD_LOGIC;
s_axi_control_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_ADDR_WIDTH-1 downto 0);
s_axi_control_RVALID : OUT STD_LOGIC;
s_axi_control_RREADY : IN STD_LOGIC;
s_axi_control_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH-1 downto 0);
s_axi_control_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_control_BVALID : OUT STD_LOGIC;
s_axi_control_BREADY : IN STD_LOGIC;
s_axi_control_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of convolve_kernel is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"convolve_kernel,hls_ip_2017_3,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=3.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.384000,HLS_SYN_LAT=5467,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=117,HLS_SYN_FF=72137,HLS_SYN_LUT=50295}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000010";
constant ap_ST_fsm_pp0_stage1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000100";
constant ap_ST_fsm_pp0_stage2 : STD_LOGIC_VECTOR (9 downto 0) := "0000001000";
constant ap_ST_fsm_pp0_stage3 : STD_LOGIC_VECTOR (9 downto 0) := "0000010000";
constant ap_ST_fsm_pp0_stage4 : STD_LOGIC_VECTOR (9 downto 0) := "0000100000";
constant ap_ST_fsm_pp0_stage5 : STD_LOGIC_VECTOR (9 downto 0) := "0001000000";
constant ap_ST_fsm_pp0_stage6 : STD_LOGIC_VECTOR (9 downto 0) := "0010000000";
constant ap_ST_fsm_pp0_stage7 : STD_LOGIC_VECTOR (9 downto 0) := "0100000000";
constant ap_ST_fsm_state76 : STD_LOGIC_VECTOR (9 downto 0) := "1000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv64_FFFFFFFFFFFFFFFF : STD_LOGIC_VECTOR (63 downto 0) := "1111111111111111111111111111111111111111111111111111111111111111";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
constant ap_const_lv32_40 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000000";
constant ap_const_lv32_5F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011111";
constant ap_const_lv32_60 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100000";
constant ap_const_lv32_7F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111111";
constant ap_const_lv32_80 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000000";
constant ap_const_lv32_9F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011111";
constant ap_const_lv32_A0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100000";
constant ap_const_lv32_BF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010111111";
constant ap_const_lv32_C0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011000000";
constant ap_const_lv32_DF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011011111";
constant ap_const_lv32_E0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011100000";
constant ap_const_lv32_FF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011111111";
constant ap_const_lv32_100 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100000000";
constant ap_const_lv32_11F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100011111";
constant ap_const_lv32_120 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100100000";
constant ap_const_lv32_13F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100111111";
constant ap_const_lv32_140 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101000000";
constant ap_const_lv32_15F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101011111";
constant ap_const_lv32_160 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101100000";
constant ap_const_lv32_17F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101111111";
constant ap_const_lv32_180 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110000000";
constant ap_const_lv32_19F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110011111";
constant ap_const_lv3_1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_const_lv3_2 : STD_LOGIC_VECTOR (2 downto 0) := "010";
constant ap_const_lv3_3 : STD_LOGIC_VECTOR (2 downto 0) := "011";
constant ap_const_lv4_4 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_const_lv4_5 : STD_LOGIC_VECTOR (3 downto 0) := "0101";
constant ap_const_lv4_6 : STD_LOGIC_VECTOR (3 downto 0) := "0110";
constant ap_const_lv4_7 : STD_LOGIC_VECTOR (3 downto 0) := "0111";
constant ap_const_lv10_2A3 : STD_LOGIC_VECTOR (9 downto 0) := "1010100011";
constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
constant ap_const_lv8_87 : STD_LOGIC_VECTOR (7 downto 0) := "10000111";
constant ap_const_lv5_1B : STD_LOGIC_VECTOR (4 downto 0) := "11011";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_const_lv6_19 : STD_LOGIC_VECTOR (5 downto 0) := "011001";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv7_32 : STD_LOGIC_VECTOR (6 downto 0) := "0110010";
constant ap_const_lv3_4 : STD_LOGIC_VECTOR (2 downto 0) := "100";
constant ap_const_lv56_0 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
constant ap_const_lv8_2 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_const_lv8_3 : STD_LOGIC_VECTOR (7 downto 0) := "00000011";
constant ap_const_lv8_4 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_const_lv8_5 : STD_LOGIC_VECTOR (7 downto 0) := "00000101";
constant ap_const_lv8_6 : STD_LOGIC_VECTOR (7 downto 0) := "00000110";
constant ap_const_lv8_7 : STD_LOGIC_VECTOR (7 downto 0) := "00000111";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_ready : STD_LOGIC;
signal indvar_flatten1_reg_885 : STD_LOGIC_VECTOR (9 downto 0);
signal i_reg_896 : STD_LOGIC_VECTOR (2 downto 0);
signal indvar_flatten_reg_908 : STD_LOGIC_VECTOR (7 downto 0);
signal j_reg_919 : STD_LOGIC_VECTOR (2 downto 0);
signal row_b_reg_931 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_12_1_fu_1499_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_1_reg_3141 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_block_state2_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state10_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state18_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_state26_pp0_stage0_iter3 : BOOLEAN;
signal ap_block_state34_pp0_stage0_iter4 : BOOLEAN;
signal ap_block_state42_pp0_stage0_iter5 : BOOLEAN;
signal ap_block_state50_pp0_stage0_iter6 : BOOLEAN;
signal ap_block_state58_pp0_stage0_iter7 : BOOLEAN;
signal ap_block_state66_pp0_stage0_iter8 : BOOLEAN;
signal ap_block_state74_pp0_stage0_iter9 : BOOLEAN;
signal ap_block_pp0_stage0_11001 : BOOLEAN;
signal tmp_12_2_fu_1505_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_2_reg_3146 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_3_fu_1511_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_3_reg_3151 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_4_fu_1517_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_4_reg_3156 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_5_fu_1523_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_5_reg_3161 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_6_fu_1529_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_6_reg_3166 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_7_fu_1535_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_7_reg_3171 : STD_LOGIC_VECTOR (3 downto 0);
signal exitcond_flatten1_fu_1541_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter3_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter4_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter6_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter8_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter9_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal indvar_flatten_next1_fu_1547_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal indvar_flatten_next1_reg_3180 : STD_LOGIC_VECTOR (9 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal i_1_fu_1553_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal i_1_reg_3185 : STD_LOGIC_VECTOR (2 downto 0);
signal exitcond_flatten_fu_1559_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten_reg_3190 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_fu_1565_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_reg_3206 : STD_LOGIC_VECTOR (0 downto 0);
signal indvar_flatten_op_fu_1571_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal indvar_flatten_op_reg_3211 : STD_LOGIC_VECTOR (7 downto 0);
signal j_mid_fu_1577_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal j_mid_reg_3216 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_CS_fsm_pp0_stage1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage1 : signal is "none";
signal ap_block_state3_pp0_stage1_iter0 : BOOLEAN;
signal ap_block_state11_pp0_stage1_iter1 : BOOLEAN;
signal ap_block_state19_pp0_stage1_iter2 : BOOLEAN;
signal ap_block_state27_pp0_stage1_iter3 : BOOLEAN;
signal ap_block_state35_pp0_stage1_iter4 : BOOLEAN;
signal ap_block_state43_pp0_stage1_iter5 : BOOLEAN;
signal ap_block_state51_pp0_stage1_iter6 : BOOLEAN;
signal ap_block_state59_pp0_stage1_iter7 : BOOLEAN;
signal ap_block_state67_pp0_stage1_iter8 : BOOLEAN;
signal ap_block_state75_pp0_stage1_iter9 : BOOLEAN;
signal ap_block_pp0_stage1_11001 : BOOLEAN;
signal tmp_1_mid2_v_fu_1584_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_1_mid2_v_reg_3225 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_7_mid_fu_1595_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_mid_reg_3233 : STD_LOGIC_VECTOR (0 downto 0);
signal row_b_mid2_fu_1605_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal row_b_mid2_reg_3245 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_pp0_iter1_row_b_mid2_reg_3245 : STD_LOGIC_VECTOR (4 downto 0);
signal indvar_flatten_next_fu_1613_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal indvar_flatten_next_reg_3252 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_1_fu_1633_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_1_reg_3257 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_pp0_stage2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage2 : signal is "none";
signal ap_block_state4_pp0_stage2_iter0 : BOOLEAN;
signal ap_block_state12_pp0_stage2_iter1 : BOOLEAN;
signal ap_block_state20_pp0_stage2_iter2 : BOOLEAN;
signal ap_block_state28_pp0_stage2_iter3 : BOOLEAN;
signal ap_block_state36_pp0_stage2_iter4 : BOOLEAN;
signal ap_block_state44_pp0_stage2_iter5 : BOOLEAN;
signal ap_block_state52_pp0_stage2_iter6 : BOOLEAN;
signal ap_block_state60_pp0_stage2_iter7 : BOOLEAN;
signal ap_block_state68_pp0_stage2_iter8 : BOOLEAN;
signal ap_block_pp0_stage2_11001 : BOOLEAN;
signal j_1_fu_1642_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal j_1_reg_3264 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_s_fu_1647_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_s_reg_3270 : STD_LOGIC_VECTOR (4 downto 0);
signal row_b_1_fu_1652_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal row_b_1_reg_3276 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_2_fu_1657_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_2_reg_3281 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_pp0_stage3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage3 : signal is "none";
signal ap_block_state5_pp0_stage3_iter0 : BOOLEAN;
signal ap_block_state13_pp0_stage3_iter1 : BOOLEAN;
signal ap_block_state21_pp0_stage3_iter2 : BOOLEAN;
signal ap_block_state29_pp0_stage3_iter3 : BOOLEAN;
signal ap_block_state37_pp0_stage3_iter4 : BOOLEAN;
signal ap_block_state45_pp0_stage3_iter5 : BOOLEAN;
signal ap_block_state53_pp0_stage3_iter6 : BOOLEAN;
signal ap_block_state61_pp0_stage3_iter7 : BOOLEAN;
signal ap_block_state69_pp0_stage3_iter8 : BOOLEAN;
signal ap_block_pp0_stage3_11001 : BOOLEAN;
signal tmp_5_mid2_fu_1662_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_5_mid2_reg_3286 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_1_mid1_fu_1667_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_1_mid1_reg_3294 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_90_fu_1694_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_90_reg_3299 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_3_fu_1706_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_3_reg_3311 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_CS_fsm_pp0_stage4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage4 : signal is "none";
signal ap_block_state6_pp0_stage4_iter0 : BOOLEAN;
signal ap_block_state14_pp0_stage4_iter1 : BOOLEAN;
signal ap_block_state22_pp0_stage4_iter2 : BOOLEAN;
signal ap_block_state30_pp0_stage4_iter3 : BOOLEAN;
signal ap_block_state38_pp0_stage4_iter4 : BOOLEAN;
signal ap_block_state46_pp0_stage4_iter5 : BOOLEAN;
signal ap_block_state54_pp0_stage4_iter6 : BOOLEAN;
signal ap_block_state62_pp0_stage4_iter7 : BOOLEAN;
signal ap_block_state70_pp0_stage4_iter8 : BOOLEAN;
signal ap_block_pp0_stage4_11001 : BOOLEAN;
signal tmp_5_mid2_cast2_fu_1721_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_5_mid2_cast2_reg_3316 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_6_fu_1727_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_6_reg_3321 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_8_fu_1732_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_8_reg_3326 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_12_2_mid1_fu_1748_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_2_mid1_reg_3331 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_130_fu_1753_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_130_reg_3336 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_170_fu_1758_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_170_reg_3341 : STD_LOGIC_VECTOR (9 downto 0);
signal ap_CS_fsm_pp0_stage5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage5 : signal is "none";
signal ap_block_state7_pp0_stage5_iter0 : BOOLEAN;
signal ap_block_state15_pp0_stage5_iter1 : BOOLEAN;
signal ap_block_state23_pp0_stage5_iter2 : BOOLEAN;
signal ap_block_state31_pp0_stage5_iter3 : BOOLEAN;
signal ap_block_state39_pp0_stage5_iter4 : BOOLEAN;
signal ap_block_state47_pp0_stage5_iter5 : BOOLEAN;
signal ap_block_state55_pp0_stage5_iter6 : BOOLEAN;
signal ap_block_state63_pp0_stage5_iter7 : BOOLEAN;
signal ap_block_state71_pp0_stage5_iter8 : BOOLEAN;
signal ap_block_pp0_stage5_11001 : BOOLEAN;
signal tmp_7_fu_1807_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_7_reg_3356 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_12_4_mid1_fu_1840_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_4_mid1_reg_3481 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_5_mid1_fu_1846_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_5_mid1_reg_3486 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_6_mid1_fu_1852_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_6_mid1_reg_3491 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_7_mid1_fu_1858_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_7_mid1_reg_3496 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_210_fu_1876_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_210_reg_3511 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_250_fu_1881_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_250_reg_3516 : STD_LOGIC_VECTOR (9 downto 0);
signal ap_CS_fsm_pp0_stage6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage6 : signal is "none";
signal ap_block_state8_pp0_stage6_iter0 : BOOLEAN;
signal ap_block_state16_pp0_stage6_iter1 : BOOLEAN;
signal ap_block_state24_pp0_stage6_iter2 : BOOLEAN;
signal ap_block_state32_pp0_stage6_iter3 : BOOLEAN;
signal ap_block_state40_pp0_stage6_iter4 : BOOLEAN;
signal ap_block_state48_pp0_stage6_iter5 : BOOLEAN;
signal ap_block_state56_pp0_stage6_iter6 : BOOLEAN;
signal ap_block_state64_pp0_stage6_iter7 : BOOLEAN;
signal ap_block_state72_pp0_stage6_iter8 : BOOLEAN;
signal ap_block_pp0_stage6_11001 : BOOLEAN;
signal tmp_290_fu_1978_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_290_reg_3616 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_330_fu_1983_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_330_reg_3621 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_331_fu_1988_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_331_reg_3626 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_332_fu_1993_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_332_reg_3631 : STD_LOGIC_VECTOR (9 downto 0);
signal ap_CS_fsm_pp0_stage7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage7 : signal is "none";
signal ap_block_state9_pp0_stage7_iter0 : BOOLEAN;
signal ap_block_state17_pp0_stage7_iter1 : BOOLEAN;
signal ap_block_state25_pp0_stage7_iter2 : BOOLEAN;
signal ap_block_state33_pp0_stage7_iter3 : BOOLEAN;
signal ap_block_state41_pp0_stage7_iter4 : BOOLEAN;
signal ap_block_state49_pp0_stage7_iter5 : BOOLEAN;
signal ap_block_state57_pp0_stage7_iter6 : BOOLEAN;
signal ap_block_state65_pp0_stage7_iter7 : BOOLEAN;
signal ap_block_state73_pp0_stage7_iter8 : BOOLEAN;
signal ap_block_pp0_stage7_11001 : BOOLEAN;
signal bufw_0_load_reg_3686 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_load_reg_3693 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_0_load_1_reg_3710 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_reg_3718 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_reg_3735 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_1_load_reg_3752 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_1_load_1_reg_3759 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_2_load_reg_3767 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_2_load_1_reg_3774 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_3_load_reg_3782 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_3_load_1_reg_3789 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_4_load_reg_3797 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_4_load_1_reg_3804 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_5_load_reg_3812 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_5_load_1_reg_3819 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_6_load_reg_3827 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_6_load_1_reg_3834 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_7_load_reg_3842 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_7_load_1_reg_3849 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_8_load_reg_3857 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_8_load_1_reg_3864 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_9_load_reg_3872 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_9_load_1_reg_3879 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_10_load_reg_3887 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_10_load_1_reg_3894 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_11_load_reg_3902 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_11_load_1_reg_3909 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_12_load_reg_3917 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_12_load_1_reg_3924 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_load_1_reg_3931 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_1_reg_3948 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_1_reg_3965 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_0_load_2_reg_4012 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal bufw_1_load_2_reg_4019 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_2_load_2_reg_4026 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_3_load_2_reg_4033 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_4_load_2_reg_4040 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_5_load_2_reg_4047 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_6_load_2_reg_4054 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_7_load_2_reg_4061 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_8_load_2_reg_4068 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_9_load_2_reg_4075 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_10_load_2_reg_4082 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_11_load_2_reg_4089 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_12_load_2_reg_4096 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_load_2_reg_4103 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_2_reg_4120 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_2_reg_4137 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_load_3_reg_4154 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_3_reg_4171 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_3_reg_4188 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_load_4_reg_4205 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_4_reg_4222 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_4_reg_4239 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_load_5_reg_4256 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_5_reg_4273 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_5_reg_4290 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_333_fu_2022_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_333_reg_4307 : STD_LOGIC_VECTOR (7 downto 0);
signal bufo_addr_reg_4317 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_bufo_addr_reg_4317 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_addr_reg_4317 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_addr_reg_4317 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_addr_reg_4317 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_addr_reg_4317 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_addr_reg_4317 : STD_LOGIC_VECTOR (7 downto 0);
signal bufo_addr_1_reg_4322 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_bufo_addr_1_reg_4322 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_addr_1_reg_4322 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_addr_1_reg_4322 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_addr_1_reg_4322 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_addr_1_reg_4322 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_addr_1_reg_4322 : STD_LOGIC_VECTOR (7 downto 0);
signal bufi_0_load_6_reg_4327 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_6_reg_4344 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_6_reg_4361 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_load_7_reg_4378 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_7_reg_4395 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_7_reg_4412 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_addr_2_reg_4429 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_bufo_addr_2_reg_4429 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_addr_2_reg_4429 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_addr_2_reg_4429 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_addr_2_reg_4429 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_addr_2_reg_4429 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_addr_2_reg_4429 : STD_LOGIC_VECTOR (7 downto 0);
signal bufo_addr_3_reg_4434 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_bufo_addr_3_reg_4434 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_addr_3_reg_4434 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_addr_3_reg_4434 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_addr_3_reg_4434 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_addr_3_reg_4434 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_addr_3_reg_4434 : STD_LOGIC_VECTOR (7 downto 0);
signal bufo_addr_4_reg_4439 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_bufo_addr_4_reg_4439 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_addr_4_reg_4439 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_addr_4_reg_4439 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_addr_4_reg_4439 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_addr_4_reg_4439 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_addr_4_reg_4439 : STD_LOGIC_VECTOR (7 downto 0);
signal bufo_addr_5_reg_4444 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_bufo_addr_5_reg_4444 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_addr_5_reg_4444 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_addr_5_reg_4444 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_addr_5_reg_4444 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_addr_5_reg_4444 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_addr_5_reg_4444 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_350_fu_2105_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_350_reg_4449 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_13_reg_4454 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_16_reg_4459 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_reg_4464 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_22_reg_4469 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_25_reg_4474 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_28_reg_4479 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_31_reg_4484 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_34_reg_4489 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_37_reg_4494 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_40_reg_4499 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_43_reg_4504 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_46_reg_4509 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_352_fu_2109_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_352_reg_4514 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_53_reg_4519 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_56_reg_4524 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_59_reg_4529 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_62_reg_4534 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_65_reg_4539 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_68_reg_4544 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_71_reg_4549 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_74_reg_4554 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_77_reg_4559 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_80_reg_4564 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_83_reg_4569 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_86_reg_4574 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_addr_6_reg_4579 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_bufo_addr_6_reg_4579 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_addr_6_reg_4579 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_addr_6_reg_4579 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_addr_6_reg_4579 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_addr_6_reg_4579 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_addr_6_reg_4579 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter8_bufo_addr_6_reg_4579 : STD_LOGIC_VECTOR (7 downto 0);
signal bufo_addr_7_reg_4584 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_bufo_addr_7_reg_4584 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_addr_7_reg_4584 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_addr_7_reg_4584 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_addr_7_reg_4584 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_addr_7_reg_4584 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_addr_7_reg_4584 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter8_bufo_addr_7_reg_4584 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_353_fu_2141_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_353_reg_4589 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_93_reg_4594 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_96_reg_4599 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_99_reg_4604 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_102_reg_4609 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_105_reg_4614 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_108_reg_4619 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_111_reg_4624 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_114_reg_4629 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_117_reg_4634 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_120_reg_4639 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_123_reg_4644 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_126_reg_4649 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_354_fu_2145_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_354_reg_4654 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_133_reg_4659 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_136_reg_4664 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_139_reg_4669 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_142_reg_4674 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_145_reg_4679 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_148_reg_4684 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_151_reg_4689 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_154_reg_4694 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_157_reg_4699 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_160_reg_4704 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_163_reg_4709 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_166_reg_4714 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_355_fu_2149_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_355_reg_4719 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_173_reg_4724 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_176_reg_4729 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_179_reg_4734 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_182_reg_4739 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_185_reg_4744 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_188_reg_4749 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_191_reg_4754 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_194_reg_4759 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_197_reg_4764 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_200_reg_4769 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_203_reg_4774 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_206_reg_4779 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_356_fu_2153_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_356_reg_4784 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_213_reg_4789 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_216_reg_4794 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_219_reg_4799 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_222_reg_4804 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_reg_4809 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_228_reg_4814 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_231_reg_4819 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_234_reg_4824 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_237_reg_4829 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_240_reg_4834 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_243_reg_4839 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_246_reg_4844 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1099_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_349_reg_4849 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1103_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_0_1_reg_4854 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_0_1_reg_4854 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1107_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_1_reg_4859 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1111_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_1_1_reg_4864 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_1_1_reg_4864 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1115_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_2_reg_4869 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1119_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_2_1_reg_4874 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_2_1_reg_4874 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1123_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_3_reg_4879 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1127_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_3_1_reg_4884 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_3_1_reg_4884 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1131_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_4_reg_4889 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1135_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_4_1_reg_4894 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_4_1_reg_4894 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1139_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_5_reg_4899 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1143_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_5_1_reg_4904 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_5_1_reg_4904 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1147_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_6_reg_4909 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1151_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_6_1_reg_4914 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_6_1_reg_4914 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1155_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_7_reg_4919 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1159_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_7_1_reg_4924 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_7_1_reg_4924 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1163_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_8_reg_4929 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1167_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_8_1_reg_4934 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_8_1_reg_4934 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1171_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_9_reg_4939 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1175_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_9_1_reg_4944 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_9_1_reg_4944 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1179_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_s_reg_4949 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1183_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_10_1_reg_4954 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_10_1_reg_4954 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1187_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_10_reg_4959 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1191_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_11_1_reg_4964 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_11_1_reg_4964 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1195_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_11_reg_4969 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1199_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_12_1_reg_4974 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_12_1_reg_4974 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1203_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_reg_4979 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1207_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_1_reg_4984 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1211_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_2_reg_4989 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1215_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_3_reg_4994 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1219_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_4_reg_4999 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1223_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_5_reg_5004 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1227_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_6_reg_5009 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1231_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_7_reg_5014 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1235_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_8_reg_5019 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1239_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_9_reg_5024 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1243_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_s_reg_5029 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1247_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_10_reg_5034 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1251_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_11_reg_5039 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_357_fu_2157_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_357_reg_5044 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_253_reg_5049 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_256_reg_5054 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_259_reg_5059 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_262_reg_5064 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_265_reg_5069 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_268_reg_5074 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_271_reg_5079 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_274_reg_5084 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_277_reg_5089 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_280_reg_5094 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_283_reg_5099 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_286_reg_5104 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_358_fu_2161_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_358_reg_5109 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_293_reg_5114 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_296_reg_5119 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_299_reg_5124 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_302_reg_5129 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_305_reg_5134 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_308_reg_5139 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_311_reg_5144 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_314_reg_5149 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_317_reg_5154 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_320_reg_5159 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_323_reg_5164 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_326_reg_5169 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_fu_2165_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_14_fu_2169_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_17_fu_2173_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_fu_2177_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_23_fu_2181_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_26_fu_2185_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_29_fu_2189_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_32_fu_2193_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_35_fu_2197_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_38_fu_2201_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_41_fu_2205_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_44_fu_2209_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_47_fu_2213_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_51_fu_2217_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_0_1_reg_5244 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal ap_reg_pp0_iter3_tmp_19_1_0_1_reg_5244 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_54_fu_2221_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_1_1_reg_5254 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_1_1_reg_5254 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_57_fu_2225_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_2_1_reg_5264 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_2_1_reg_5264 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_60_fu_2229_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_3_1_reg_5274 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_3_1_reg_5274 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_63_fu_2233_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_4_1_reg_5284 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_4_1_reg_5284 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_66_fu_2237_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_5_1_reg_5294 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_5_1_reg_5294 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_69_fu_2241_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_6_1_reg_5304 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_6_1_reg_5304 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_72_fu_2245_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_7_1_reg_5314 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_7_1_reg_5314 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_75_fu_2249_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_8_1_reg_5324 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_8_1_reg_5324 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_78_fu_2253_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_9_1_reg_5334 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_9_1_reg_5334 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_81_fu_2257_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_10_1_reg_5344 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_10_1_reg_5344 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_84_fu_2261_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_11_1_reg_5354 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_11_1_reg_5354 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_87_fu_2265_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_12_1_reg_5364 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_12_1_reg_5364 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_reg_5369 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_1_reg_5374 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_2_reg_5379 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_3_reg_5384 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_4_reg_5389 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_5_reg_5394 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_6_reg_5399 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_7_reg_5404 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_8_reg_5409 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_9_reg_5414 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_s_reg_5419 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_10_reg_5424 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_11_reg_5429 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_reg_5434 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_1_reg_5439 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_2_reg_5444 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_3_reg_5449 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_4_reg_5454 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_5_reg_5459 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_6_reg_5464 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_7_reg_5469 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_8_reg_5474 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_9_reg_5479 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_s_reg_5484 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_10_reg_5489 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_11_reg_5494 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_91_fu_2269_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_0_1_reg_5504 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_0_1_reg_5504 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_94_fu_2273_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_1_1_reg_5514 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_1_1_reg_5514 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_97_fu_2277_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_2_1_reg_5524 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_2_1_reg_5524 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_100_fu_2281_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_3_1_reg_5534 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_3_1_reg_5534 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_103_fu_2285_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_4_1_reg_5544 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_4_1_reg_5544 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_106_fu_2289_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_5_1_reg_5554 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_5_1_reg_5554 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_109_fu_2293_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_6_1_reg_5564 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_6_1_reg_5564 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_112_fu_2297_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_7_1_reg_5574 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_7_1_reg_5574 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_115_fu_2301_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_8_1_reg_5584 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_8_1_reg_5584 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_118_fu_2305_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_9_1_reg_5594 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_9_1_reg_5594 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_121_fu_2309_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_10_1_reg_5604 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_10_1_reg_5604 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_124_fu_2313_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_11_1_reg_5614 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_11_1_reg_5614 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_127_fu_2317_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_12_1_reg_5624 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_12_1_reg_5624 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_131_fu_2321_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_134_fu_2325_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_137_fu_2329_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_140_fu_2333_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_143_fu_2337_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_146_fu_2341_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_149_fu_2345_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_152_fu_2349_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_155_fu_2353_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_158_fu_2357_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_161_fu_2361_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_164_fu_2365_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_167_fu_2369_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_reg_5694 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_1_reg_5699 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_2_reg_5704 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_3_reg_5709 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_4_reg_5714 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_5_reg_5719 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_6_reg_5724 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_7_reg_5729 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_8_reg_5734 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_9_reg_5739 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_s_reg_5744 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_10_reg_5749 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_11_reg_5754 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_reg_5759 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_1_reg_5764 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_2_reg_5769 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_3_reg_5774 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_4_reg_5779 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_5_reg_5784 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_6_reg_5789 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_7_reg_5794 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_8_reg_5799 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_9_reg_5804 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_s_reg_5809 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_10_reg_5814 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_11_reg_5819 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_0_1_reg_5824 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_0_1_reg_5824 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_1_1_reg_5829 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_1_1_reg_5829 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_2_1_reg_5834 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_2_1_reg_5834 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_3_1_reg_5839 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_3_1_reg_5839 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_4_1_reg_5844 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_4_1_reg_5844 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_5_1_reg_5849 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_5_1_reg_5849 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_6_1_reg_5854 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_6_1_reg_5854 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_7_1_reg_5859 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_7_1_reg_5859 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_8_1_reg_5864 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_8_1_reg_5864 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_9_1_reg_5869 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_9_1_reg_5869 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_10_1_reg_5874 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_10_1_reg_5874 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_11_1_reg_5879 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_11_1_reg_5879 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_12_1_reg_5884 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_12_1_reg_5884 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_171_fu_2373_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_174_fu_2377_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_177_fu_2381_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_180_fu_2385_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_183_fu_2389_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_186_fu_2393_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_189_fu_2397_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_192_fu_2401_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_195_fu_2405_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_198_fu_2409_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_201_fu_2413_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_204_fu_2417_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_207_fu_2421_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_211_fu_2425_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_214_fu_2429_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_217_fu_2433_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_220_fu_2437_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_223_fu_2441_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_226_fu_2445_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_229_fu_2449_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_232_fu_2453_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_235_fu_2457_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_238_fu_2461_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_241_fu_2465_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_244_fu_2469_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_247_fu_2473_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_reg_6019 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_1_reg_6024 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_2_reg_6029 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_3_reg_6034 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_4_reg_6039 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_5_reg_6044 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_6_reg_6049 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_7_reg_6054 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_8_reg_6059 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_9_reg_6064 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_s_reg_6069 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_10_reg_6074 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_11_reg_6079 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_reg_6084 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_1_reg_6089 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_2_reg_6094 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_3_reg_6099 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_4_reg_6104 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_5_reg_6109 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_6_reg_6114 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_7_reg_6119 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_8_reg_6124 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_9_reg_6129 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_s_reg_6134 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_10_reg_6139 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_11_reg_6144 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_0_1_reg_6149 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_0_1_reg_6149 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_1_1_reg_6154 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_1_1_reg_6154 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_2_1_reg_6159 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_2_1_reg_6159 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_3_1_reg_6164 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_3_1_reg_6164 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_4_1_reg_6169 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_4_1_reg_6169 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_5_1_reg_6174 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_5_1_reg_6174 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_6_1_reg_6179 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_6_1_reg_6179 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_7_1_reg_6184 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_7_1_reg_6184 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_8_1_reg_6189 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_8_1_reg_6189 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_9_1_reg_6194 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_9_1_reg_6194 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_10_1_reg_6199 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_10_1_reg_6199 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_11_1_reg_6204 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_11_1_reg_6204 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_12_1_reg_6209 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_12_1_reg_6209 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_0_1_reg_6214 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_0_1_reg_6214 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_1_1_reg_6219 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_1_1_reg_6219 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_2_1_reg_6224 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_2_1_reg_6224 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_3_1_reg_6229 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_3_1_reg_6229 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_4_1_reg_6234 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_4_1_reg_6234 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_5_1_reg_6239 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_5_1_reg_6239 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_6_1_reg_6244 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_6_1_reg_6244 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_7_1_reg_6249 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_7_1_reg_6249 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_8_1_reg_6254 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_8_1_reg_6254 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_9_1_reg_6259 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_9_1_reg_6259 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_10_1_reg_6264 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_10_1_reg_6264 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_11_1_reg_6269 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_11_1_reg_6269 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_12_1_reg_6274 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_12_1_reg_6274 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_251_fu_2477_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_0_1_reg_6284 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_0_1_reg_6284 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_254_fu_2481_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_1_1_reg_6294 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_1_1_reg_6294 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_257_fu_2485_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_2_1_reg_6304 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_2_1_reg_6304 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_260_fu_2489_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_3_1_reg_6314 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_3_1_reg_6314 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_263_fu_2493_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_4_1_reg_6324 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_4_1_reg_6324 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_266_fu_2497_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_5_1_reg_6334 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_5_1_reg_6334 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_269_fu_2501_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_6_1_reg_6344 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_6_1_reg_6344 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_272_fu_2505_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_7_1_reg_6354 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_7_1_reg_6354 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_275_fu_2509_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_8_1_reg_6364 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_8_1_reg_6364 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_278_fu_2513_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_9_1_reg_6374 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_9_1_reg_6374 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_281_fu_2517_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_10_1_reg_6384 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_10_1_reg_6384 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_284_fu_2521_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_11_1_reg_6394 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_11_1_reg_6394 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_287_fu_2525_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_12_1_reg_6404 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_12_1_reg_6404 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_291_fu_2529_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_294_fu_2533_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_297_fu_2537_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_300_fu_2541_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_303_fu_2545_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_306_fu_2549_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_309_fu_2553_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_312_fu_2557_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_315_fu_2561_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_318_fu_2565_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_321_fu_2569_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_324_fu_2573_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_327_fu_2577_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_0_2_reg_6474 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_0_2_reg_6474 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_0_2_reg_6474 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_1_2_reg_6479 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_1_2_reg_6479 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_1_2_reg_6479 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_2_2_reg_6484 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_2_2_reg_6484 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_2_2_reg_6484 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_3_2_reg_6489 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_3_2_reg_6489 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_3_2_reg_6489 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_4_2_reg_6494 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_4_2_reg_6494 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_4_2_reg_6494 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_5_2_reg_6499 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_5_2_reg_6499 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_5_2_reg_6499 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_6_2_reg_6504 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_6_2_reg_6504 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_6_2_reg_6504 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_7_2_reg_6509 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_7_2_reg_6509 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_7_2_reg_6509 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_8_2_reg_6514 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_8_2_reg_6514 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_8_2_reg_6514 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_9_2_reg_6519 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_9_2_reg_6519 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_9_2_reg_6519 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_10_2_reg_6524 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_10_2_reg_6524 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_10_2_reg_6524 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_11_2_reg_6529 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_11_2_reg_6529 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_11_2_reg_6529 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_12_2_reg_6534 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_12_2_reg_6534 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_12_2_reg_6534 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_0_2_reg_6539 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_0_2_reg_6539 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_0_2_reg_6539 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_1_2_reg_6544 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_1_2_reg_6544 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_1_2_reg_6544 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_2_2_reg_6549 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_2_2_reg_6549 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_2_2_reg_6549 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_3_2_reg_6554 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_3_2_reg_6554 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_3_2_reg_6554 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_4_2_reg_6559 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_4_2_reg_6559 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_4_2_reg_6559 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_5_2_reg_6564 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_5_2_reg_6564 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_5_2_reg_6564 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_6_2_reg_6569 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_6_2_reg_6569 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_6_2_reg_6569 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_7_2_reg_6574 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_7_2_reg_6574 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_7_2_reg_6574 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_8_2_reg_6579 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_8_2_reg_6579 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_8_2_reg_6579 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_9_2_reg_6584 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_9_2_reg_6584 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_9_2_reg_6584 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_10_2_reg_6589 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_10_2_reg_6589 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_10_2_reg_6589 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_11_2_reg_6594 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_11_2_reg_6594 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_11_2_reg_6594 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_12_2_reg_6599 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_12_2_reg_6599 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_12_2_reg_6599 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_0_1_reg_6604 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_0_1_reg_6604 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_1_1_reg_6609 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_1_1_reg_6609 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_2_1_reg_6614 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_2_1_reg_6614 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_3_1_reg_6619 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_3_1_reg_6619 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_4_1_reg_6624 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_4_1_reg_6624 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_5_1_reg_6629 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_5_1_reg_6629 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_6_1_reg_6634 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_6_1_reg_6634 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_7_1_reg_6639 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_7_1_reg_6639 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_8_1_reg_6644 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_8_1_reg_6644 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_9_1_reg_6649 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_9_1_reg_6649 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_10_1_reg_6654 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_10_1_reg_6654 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_11_1_reg_6659 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_11_1_reg_6659 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_12_1_reg_6664 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_12_1_reg_6664 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_0_2_reg_6669 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_0_2_reg_6669 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_0_2_reg_6669 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_1_2_reg_6674 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_1_2_reg_6674 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_1_2_reg_6674 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_2_2_reg_6679 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_2_2_reg_6679 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_2_2_reg_6679 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_3_2_reg_6684 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_3_2_reg_6684 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_3_2_reg_6684 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_4_2_reg_6689 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_4_2_reg_6689 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_4_2_reg_6689 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_5_2_reg_6694 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_5_2_reg_6694 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_5_2_reg_6694 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_6_2_reg_6699 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_6_2_reg_6699 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_6_2_reg_6699 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_7_2_reg_6704 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_7_2_reg_6704 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_7_2_reg_6704 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_8_2_reg_6709 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_8_2_reg_6709 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_8_2_reg_6709 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_9_2_reg_6714 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_9_2_reg_6714 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_9_2_reg_6714 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_10_2_reg_6719 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_10_2_reg_6719 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_10_2_reg_6719 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_11_2_reg_6724 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_11_2_reg_6724 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_11_2_reg_6724 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_12_2_reg_6729 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_12_2_reg_6729 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_12_2_reg_6729 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_0_2_reg_6734 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_0_2_reg_6734 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_0_2_reg_6734 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_1_2_reg_6739 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_1_2_reg_6739 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_1_2_reg_6739 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_2_2_reg_6744 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_2_2_reg_6744 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_2_2_reg_6744 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_3_2_reg_6749 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_3_2_reg_6749 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_3_2_reg_6749 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_4_2_reg_6754 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_4_2_reg_6754 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_4_2_reg_6754 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_5_2_reg_6759 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_5_2_reg_6759 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_5_2_reg_6759 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_6_2_reg_6764 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_6_2_reg_6764 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_6_2_reg_6764 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_7_2_reg_6769 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_7_2_reg_6769 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_7_2_reg_6769 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_8_2_reg_6774 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_8_2_reg_6774 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_8_2_reg_6774 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_9_2_reg_6779 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_9_2_reg_6779 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_9_2_reg_6779 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_10_2_reg_6784 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_10_2_reg_6784 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_10_2_reg_6784 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_11_2_reg_6789 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_11_2_reg_6789 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_11_2_reg_6789 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_12_2_reg_6794 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_12_2_reg_6794 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_12_2_reg_6794 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_0_2_reg_6799 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_0_2_reg_6799 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_0_2_reg_6799 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_0_2_reg_6799 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_1_2_reg_6804 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_1_2_reg_6804 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_1_2_reg_6804 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_1_2_reg_6804 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_2_2_reg_6809 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_2_2_reg_6809 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_2_2_reg_6809 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_2_2_reg_6809 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_3_2_reg_6814 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_3_2_reg_6814 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_3_2_reg_6814 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_3_2_reg_6814 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_4_2_reg_6819 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_4_2_reg_6819 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_4_2_reg_6819 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_4_2_reg_6819 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_5_2_reg_6824 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_5_2_reg_6824 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_5_2_reg_6824 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_5_2_reg_6824 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_6_2_reg_6829 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_6_2_reg_6829 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_6_2_reg_6829 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_6_2_reg_6829 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_7_2_reg_6834 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_7_2_reg_6834 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_7_2_reg_6834 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_7_2_reg_6834 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_8_2_reg_6839 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_8_2_reg_6839 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_8_2_reg_6839 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_8_2_reg_6839 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_9_2_reg_6844 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_9_2_reg_6844 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_9_2_reg_6844 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_9_2_reg_6844 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_10_2_reg_6849 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_10_2_reg_6849 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_10_2_reg_6849 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_10_2_reg_6849 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_11_2_reg_6854 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_11_2_reg_6854 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_11_2_reg_6854 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_11_2_reg_6854 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_12_2_reg_6859 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_12_2_reg_6859 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_12_2_reg_6859 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_12_2_reg_6859 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_0_2_reg_6864 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_0_2_reg_6864 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_0_2_reg_6864 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_0_2_reg_6864 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_1_2_reg_6869 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_1_2_reg_6869 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_1_2_reg_6869 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_1_2_reg_6869 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_2_2_reg_6874 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_2_2_reg_6874 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_2_2_reg_6874 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_2_2_reg_6874 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_3_2_reg_6879 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_3_2_reg_6879 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_3_2_reg_6879 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_3_2_reg_6879 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_4_2_reg_6884 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_4_2_reg_6884 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_4_2_reg_6884 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_4_2_reg_6884 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_5_2_reg_6889 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_5_2_reg_6889 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_5_2_reg_6889 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_5_2_reg_6889 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_6_2_reg_6894 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_6_2_reg_6894 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_6_2_reg_6894 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_6_2_reg_6894 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_7_2_reg_6899 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_7_2_reg_6899 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_7_2_reg_6899 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_7_2_reg_6899 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_8_2_reg_6904 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_8_2_reg_6904 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_8_2_reg_6904 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_8_2_reg_6904 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_9_2_reg_6909 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_9_2_reg_6909 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_9_2_reg_6909 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_9_2_reg_6909 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_10_2_reg_6914 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_10_2_reg_6914 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_10_2_reg_6914 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_10_2_reg_6914 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_11_2_reg_6919 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_11_2_reg_6919 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_11_2_reg_6919 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_11_2_reg_6919 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_12_2_reg_6924 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_12_2_reg_6924 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_12_2_reg_6924 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_12_2_reg_6924 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_0_2_reg_6929 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_0_2_reg_6929 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_0_2_reg_6929 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_0_2_reg_6929 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_1_2_reg_6934 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_1_2_reg_6934 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_1_2_reg_6934 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_1_2_reg_6934 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_2_2_reg_6939 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_2_2_reg_6939 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_2_2_reg_6939 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_2_2_reg_6939 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_3_2_reg_6944 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_3_2_reg_6944 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_3_2_reg_6944 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_3_2_reg_6944 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_4_2_reg_6949 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_4_2_reg_6949 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_4_2_reg_6949 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_4_2_reg_6949 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_5_2_reg_6954 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_5_2_reg_6954 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_5_2_reg_6954 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_5_2_reg_6954 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_6_2_reg_6959 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_6_2_reg_6959 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_6_2_reg_6959 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_6_2_reg_6959 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_7_2_reg_6964 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_7_2_reg_6964 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_7_2_reg_6964 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_7_2_reg_6964 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_8_2_reg_6969 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_8_2_reg_6969 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_8_2_reg_6969 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_8_2_reg_6969 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_9_2_reg_6974 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_9_2_reg_6974 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_9_2_reg_6974 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_9_2_reg_6974 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_10_2_reg_6979 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_10_2_reg_6979 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_10_2_reg_6979 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_10_2_reg_6979 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_11_2_reg_6984 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_11_2_reg_6984 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_11_2_reg_6984 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_11_2_reg_6984 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_12_2_reg_6989 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_12_2_reg_6989 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_12_2_reg_6989 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_12_2_reg_6989 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_0_2_reg_6994 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_0_2_reg_6994 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_0_2_reg_6994 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_0_2_reg_6994 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_1_2_reg_6999 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_1_2_reg_6999 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_1_2_reg_6999 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_1_2_reg_6999 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_2_2_reg_7004 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_2_2_reg_7004 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_2_2_reg_7004 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_2_2_reg_7004 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_3_2_reg_7009 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_3_2_reg_7009 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_3_2_reg_7009 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_3_2_reg_7009 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_4_2_reg_7014 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_4_2_reg_7014 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_4_2_reg_7014 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_4_2_reg_7014 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_5_2_reg_7019 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_5_2_reg_7019 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_5_2_reg_7019 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_5_2_reg_7019 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_6_2_reg_7024 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_6_2_reg_7024 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_6_2_reg_7024 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_6_2_reg_7024 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_7_2_reg_7029 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_7_2_reg_7029 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_7_2_reg_7029 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_7_2_reg_7029 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_8_2_reg_7034 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_8_2_reg_7034 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_8_2_reg_7034 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_8_2_reg_7034 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_9_2_reg_7039 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_9_2_reg_7039 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_9_2_reg_7039 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_9_2_reg_7039 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_10_2_reg_7044 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_10_2_reg_7044 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_10_2_reg_7044 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_10_2_reg_7044 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_11_2_reg_7049 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_11_2_reg_7049 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_11_2_reg_7049 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_11_2_reg_7049 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_12_2_reg_7054 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_12_2_reg_7054 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_12_2_reg_7054 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_12_2_reg_7054 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_943_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_351_reg_7059 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
signal grp_fu_947_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_1_reg_7064 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_951_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_2_reg_7069 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_955_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_3_reg_7074 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_959_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_4_reg_7079 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_963_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_5_reg_7084 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_967_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_6_reg_7089 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_971_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_7_reg_7094 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_975_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_8_reg_7099 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_979_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_9_reg_7104 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_983_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_s_reg_7109 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_987_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_10_reg_7114 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_991_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_11_reg_7119 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_995_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_reg_7124 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_999_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_1_reg_7129 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1003_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_2_reg_7134 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1007_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_3_reg_7139 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1011_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_4_reg_7144 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1015_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_5_reg_7149 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1019_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_6_reg_7154 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1023_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_7_reg_7159 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1027_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_8_reg_7164 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1031_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_9_reg_7169 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1035_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_s_reg_7174 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1039_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_10_reg_7179 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1043_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_11_reg_7184 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_reg_7189 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_1_reg_7194 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_2_reg_7199 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_3_reg_7204 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_4_reg_7209 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_5_reg_7214 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_6_reg_7219 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_7_reg_7224 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_8_reg_7229 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_9_reg_7234 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_s_reg_7239 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_10_reg_7244 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_11_reg_7249 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_reg_7254 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_1_reg_7259 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_2_reg_7264 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_3_reg_7269 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_4_reg_7274 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_5_reg_7279 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_6_reg_7284 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_7_reg_7289 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_8_reg_7294 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_9_reg_7299 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_s_reg_7304 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_10_reg_7309 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_11_reg_7314 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_reg_7319 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_1_reg_7324 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_2_reg_7329 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_3_reg_7334 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_4_reg_7339 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_5_reg_7344 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_6_reg_7349 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_7_reg_7354 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_8_reg_7359 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_9_reg_7364 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_s_reg_7369 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_10_reg_7374 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_11_reg_7379 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_reg_7384 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_1_reg_7389 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_2_reg_7394 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_3_reg_7399 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_4_reg_7404 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_5_reg_7409 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_6_reg_7414 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_7_reg_7419 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_8_reg_7424 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_9_reg_7429 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_s_reg_7434 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_10_reg_7439 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_11_reg_7444 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_reg_7449 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
signal tmp_20_6_1_reg_7454 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_2_reg_7459 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_3_reg_7464 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_4_reg_7469 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_5_reg_7474 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_6_reg_7479 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_7_reg_7484 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_8_reg_7489 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_9_reg_7494 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_s_reg_7499 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_10_reg_7504 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_11_reg_7509 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_reg_7514 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_1_reg_7519 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_2_reg_7524 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_3_reg_7529 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_4_reg_7534 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_5_reg_7539 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_6_reg_7544 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_7_reg_7549 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_8_reg_7554 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_9_reg_7559 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_s_reg_7564 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_10_reg_7569 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_11_reg_7574 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_0_1_reg_7579 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter5 : STD_LOGIC := '0';
signal tmp_20_0_1_1_reg_7584 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_2_1_reg_7589 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_3_1_reg_7594 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_4_1_reg_7599 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_5_1_reg_7604 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_6_1_reg_7609 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_7_1_reg_7614 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_8_1_reg_7619 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_9_1_reg_7624 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_10_1_reg_7629 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_11_1_reg_7634 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_12_1_reg_7639 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_0_1_reg_7644 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_1_1_reg_7649 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_2_1_reg_7654 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_3_1_reg_7659 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_4_1_reg_7664 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_5_1_reg_7669 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_6_1_reg_7674 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_7_1_reg_7679 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_8_1_reg_7684 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_9_1_reg_7689 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_10_1_reg_7694 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_11_1_reg_7699 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_12_1_reg_7704 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_0_1_reg_7709 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_1_1_reg_7714 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_2_1_reg_7719 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_3_1_reg_7724 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_4_1_reg_7729 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_5_1_reg_7734 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_6_1_reg_7739 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_7_1_reg_7744 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_8_1_reg_7749 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_9_1_reg_7754 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_10_1_reg_7759 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_11_1_reg_7764 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_12_1_reg_7769 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_0_1_reg_7774 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_1_1_reg_7779 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_2_1_reg_7784 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_3_1_reg_7789 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_4_1_reg_7794 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_5_1_reg_7799 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_6_1_reg_7804 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_7_1_reg_7809 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_8_1_reg_7814 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_9_1_reg_7819 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_10_1_reg_7824 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_11_1_reg_7829 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_12_1_reg_7834 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1047_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_0_1_reg_7839 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1051_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_1_1_reg_7844 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1055_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_2_1_reg_7849 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1059_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_3_1_reg_7854 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1063_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_4_1_reg_7859 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1067_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_5_1_reg_7864 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1071_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_6_1_reg_7869 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1075_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_7_1_reg_7874 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1079_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_8_1_reg_7879 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1083_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_9_1_reg_7884 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1087_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_10_1_reg_7889 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1091_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_11_1_reg_7894 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1095_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_12_1_reg_7899 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_0_1_reg_7904 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_1_1_reg_7909 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_2_1_reg_7914 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_3_1_reg_7919 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_4_1_reg_7924 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_5_1_reg_7929 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_6_1_reg_7934 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_7_1_reg_7939 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_8_1_reg_7944 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_9_1_reg_7949 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_10_1_reg_7954 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_11_1_reg_7959 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_12_1_reg_7964 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_0_1_reg_7969 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_1_1_reg_7974 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_2_1_reg_7979 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_3_1_reg_7984 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_4_1_reg_7989 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_5_1_reg_7994 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_6_1_reg_7999 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_7_1_reg_8004 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_8_1_reg_8009 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_9_1_reg_8014 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_10_1_reg_8019 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_11_1_reg_8024 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_12_1_reg_8029 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_0_1_reg_8034 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter6 : STD_LOGIC := '0';
signal tmp_20_7_1_1_reg_8039 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_2_1_reg_8044 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_3_1_reg_8049 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_4_1_reg_8054 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_5_1_reg_8059 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_6_1_reg_8064 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_7_1_reg_8069 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_8_1_reg_8074 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_9_1_reg_8079 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_10_1_reg_8084 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_11_1_reg_8089 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_12_1_reg_8094 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_0_2_reg_8099 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter7 : STD_LOGIC := '0';
signal tmp_20_0_1_2_reg_8104 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_2_2_reg_8109 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_3_2_reg_8114 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_4_2_reg_8119 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_5_2_reg_8124 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_6_2_reg_8129 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_7_2_reg_8134 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_8_2_reg_8139 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_9_2_reg_8144 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_10_2_reg_8149 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_11_2_reg_8154 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_12_2_reg_8159 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_0_2_reg_8164 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_1_2_reg_8169 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_2_2_reg_8174 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_3_2_reg_8179 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_4_2_reg_8184 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_5_2_reg_8189 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_6_2_reg_8194 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_7_2_reg_8199 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_8_2_reg_8204 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_9_2_reg_8209 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_10_2_reg_8214 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_11_2_reg_8219 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_12_2_reg_8224 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_0_2_reg_8229 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_1_2_reg_8234 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_2_2_reg_8239 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_3_2_reg_8244 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_4_2_reg_8249 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_5_2_reg_8254 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_6_2_reg_8259 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_7_2_reg_8264 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_8_2_reg_8269 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_9_2_reg_8274 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_10_2_reg_8279 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_11_2_reg_8284 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_12_2_reg_8289 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_0_2_reg_8294 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_1_2_reg_8299 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_2_2_reg_8304 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_3_2_reg_8309 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_4_2_reg_8314 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_5_2_reg_8319 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_6_2_reg_8324 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_7_2_reg_8329 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_8_2_reg_8334 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_9_2_reg_8339 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_10_2_reg_8344 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_11_2_reg_8349 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_12_2_reg_8354 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_0_2_reg_8359 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_1_2_reg_8364 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_2_2_reg_8369 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_3_2_reg_8374 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_4_2_reg_8379 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_5_2_reg_8384 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_6_2_reg_8389 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_7_2_reg_8394 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_8_2_reg_8399 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_9_2_reg_8404 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_10_2_reg_8409 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_11_2_reg_8414 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_12_2_reg_8419 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_0_2_reg_8424 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_1_2_reg_8429 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_2_2_reg_8434 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_3_2_reg_8439 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_4_2_reg_8444 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_5_2_reg_8449 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_6_2_reg_8454 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_7_2_reg_8459 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_8_2_reg_8464 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_9_2_reg_8469 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_10_2_reg_8474 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_11_2_reg_8479 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_12_2_reg_8484 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_0_2_reg_8489 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter8 : STD_LOGIC := '0';
signal tmp_20_6_1_2_reg_8494 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_2_2_reg_8499 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_3_2_reg_8504 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_4_2_reg_8509 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_5_2_reg_8514 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_6_2_reg_8519 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_7_2_reg_8524 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_8_2_reg_8529 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_9_2_reg_8534 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_10_2_reg_8539 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_11_2_reg_8544 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_12_2_reg_8549 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_0_2_reg_8554 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_1_2_reg_8559 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_2_2_reg_8564 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_3_2_reg_8569 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_4_2_reg_8574 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_5_2_reg_8579 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_6_2_reg_8584 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_7_2_reg_8589 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_8_2_reg_8594 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_9_2_reg_8599 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_10_2_reg_8604 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_11_2_reg_8609 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_12_2_reg_8614 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_block_pp0_stage0_subdone : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state2 : STD_LOGIC;
signal ap_block_pp0_stage7_subdone : BOOLEAN;
signal ap_block_pp0_stage1_subdone : BOOLEAN;
signal ap_enable_reg_pp0_iter9 : STD_LOGIC := '0';
signal ap_phi_mux_indvar_flatten1_phi_fu_889_p4 : STD_LOGIC_VECTOR (9 downto 0);
signal ap_block_pp0_stage0 : BOOLEAN;
signal ap_phi_mux_i_phi_fu_900_p4 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_phi_mux_indvar_flatten_phi_fu_912_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_mux_j_phi_fu_923_p4 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_phi_mux_row_b_phi_fu_935_p4 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_6_cast_fu_1775_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage5 : BOOLEAN;
signal tmp_8_cast_fu_1791_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_334_cast_fu_1864_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_335_cast_fu_1870_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_330_cast_fu_1910_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage6 : BOOLEAN;
signal tmp_336_cast_fu_1966_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_337_cast_fu_1972_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_338_cast_fu_1998_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage7 : BOOLEAN;
signal tmp_339_cast_fu_2004_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_340_cast_fu_2010_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_341_cast_fu_2016_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_334_fu_2029_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage2 : BOOLEAN;
signal tmp_336_fu_2040_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_338_fu_2054_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage3 : BOOLEAN;
signal tmp_340_fu_2068_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_342_fu_2082_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage4 : BOOLEAN;
signal tmp_344_fu_2096_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_346_fu_2118_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_348_fu_2132_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal bufw_0_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_0_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_1_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_1_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_2_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_2_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_3_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_3_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_4_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_4_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_5_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_5_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_6_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_6_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_7_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_7_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_8_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_8_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_9_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_9_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_10_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_10_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_11_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_11_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_12_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_12_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_49_fu_2620_p14 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_89_fu_2690_p14 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_129_fu_2760_p14 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_169_fu_2830_p14 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_209_fu_2900_p14 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_249_fu_2970_p14 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_289_fu_3040_p14 : STD_LOGIC_VECTOR (415 downto 0);
signal ap_block_pp0_stage1 : BOOLEAN;
signal tmp_329_fu_3110_p14 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_943_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_943_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_947_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_947_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_951_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_951_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_955_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_955_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_959_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_959_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_963_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_963_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_967_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_967_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_971_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_971_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_975_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_975_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_979_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_979_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_983_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_983_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_987_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_987_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_991_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_991_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_995_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_995_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_999_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_999_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1003_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1003_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1007_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1007_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1011_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1011_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1015_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1015_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1019_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1019_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1023_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1023_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1027_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1027_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1031_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1031_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1035_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1035_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1039_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1039_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1043_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1043_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1047_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1047_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1051_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1051_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1055_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1055_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1059_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1059_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1063_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1063_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1067_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1067_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1071_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1071_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1075_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1075_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1079_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1079_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1083_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1083_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1087_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1087_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1091_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1091_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1095_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1095_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1099_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1099_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1103_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1103_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1107_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1107_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1111_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1111_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1115_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1115_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1119_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1119_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1123_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1123_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1127_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1127_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1131_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1131_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1135_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1135_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1139_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1139_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1143_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1143_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1147_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1147_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1151_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1151_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1155_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1155_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1159_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1159_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1163_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1163_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1167_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1167_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1171_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1171_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1175_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1175_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1179_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1179_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1183_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1183_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1187_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1187_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1191_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1191_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1195_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1195_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1199_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1199_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1203_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1203_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1207_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1207_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1211_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1211_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1215_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1215_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1219_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1219_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1223_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1223_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1227_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1227_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1231_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1231_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1235_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1235_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1239_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1239_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1243_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1243_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1247_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1247_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1251_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1251_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1255_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1265_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1275_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1285_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1295_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1305_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1315_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1325_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1335_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1345_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1355_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1365_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1375_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1385_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1395_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1405_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1415_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1425_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1435_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1445_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1455_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1465_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1475_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1485_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_6_cast2_fu_1495_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal not_exitcond_flatten_fu_1590_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_4_fu_1600_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_fu_1622_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_1_mid2_cast_fu_1619_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl2_cast_fu_1629_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_2_cast_mid2_fu_1639_p1 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_10_fu_1672_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_50_fu_1683_p3 : STD_LOGIC_VECTOR (6 downto 0);
signal p_shl_cast_fu_1679_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal p_shl1_cast_fu_1690_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_1_cast_fu_1700_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_5_mid2_cast_fu_1724_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_2_cast_fu_1703_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_13_1_mid_fu_1712_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_13_1_mid2_fu_1738_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_5_mid2_cast1_fu_1718_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_13_1_mid2_cast_fu_1744_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_13_2_mid_fu_1763_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_13_2_mid2_fu_1814_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_3_mid1_fu_1824_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_13_3_mid_fu_1769_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_13_3_mid2_fu_1829_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_6_cast2_mid1_fu_1811_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_2_mid2_cast_fu_1820_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_13_3_mid2_cast_fu_1836_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_13_4_mid_fu_1886_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_4_mid2_fu_1926_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_5_mid_fu_1892_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_5_mid2_fu_1936_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_6_mid_fu_1898_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_6_mid2_fu_1946_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_7_mid_fu_1904_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_7_mid2_fu_1956_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_4_mid2_cast_fu_1932_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_13_5_mid2_cast_fu_1942_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_13_6_mid2_cast_fu_1952_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_13_7_mid2_cast_fu_1962_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_335_fu_2034_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_337_fu_2049_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_339_fu_2063_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_341_fu_2077_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_343_fu_2091_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_350_fu_2105_p0 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_352_fu_2109_p0 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_345_fu_2113_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_347_fu_2127_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_353_fu_2141_p0 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_354_fu_2145_p0 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_355_fu_2149_p0 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_356_fu_2153_p0 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_357_fu_2157_p0 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_358_fu_2161_p0 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_48_fu_2617_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_45_fu_2614_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_42_fu_2611_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_39_fu_2608_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_36_fu_2605_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_33_fu_2602_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_30_fu_2599_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_27_fu_2596_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_24_fu_2593_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_21_fu_2590_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_18_fu_2587_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_15_fu_2584_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_fu_2581_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_88_fu_2687_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_85_fu_2684_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_82_fu_2681_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_79_fu_2678_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_76_fu_2675_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_73_fu_2672_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_70_fu_2669_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_67_fu_2666_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_64_fu_2663_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_61_fu_2660_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_58_fu_2657_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_55_fu_2654_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_52_fu_2651_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_128_fu_2757_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_125_fu_2754_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_122_fu_2751_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_119_fu_2748_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_116_fu_2745_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_113_fu_2742_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_110_fu_2739_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_107_fu_2736_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_104_fu_2733_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_101_fu_2730_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_98_fu_2727_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_95_fu_2724_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_92_fu_2721_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_168_fu_2827_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_165_fu_2824_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_162_fu_2821_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_159_fu_2818_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_156_fu_2815_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_153_fu_2812_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_150_fu_2809_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_147_fu_2806_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_144_fu_2803_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_141_fu_2800_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_138_fu_2797_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_135_fu_2794_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_132_fu_2791_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_208_fu_2897_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_205_fu_2894_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_202_fu_2891_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_199_fu_2888_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_196_fu_2885_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_193_fu_2882_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_190_fu_2879_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_187_fu_2876_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_184_fu_2873_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_181_fu_2870_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_178_fu_2867_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_175_fu_2864_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_172_fu_2861_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_248_fu_2967_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_245_fu_2964_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_242_fu_2961_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_239_fu_2958_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_236_fu_2955_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_233_fu_2952_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_230_fu_2949_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_227_fu_2946_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_224_fu_2943_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_221_fu_2940_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_218_fu_2937_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_215_fu_2934_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_212_fu_2931_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_288_fu_3037_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_285_fu_3034_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_282_fu_3031_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_279_fu_3028_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_276_fu_3025_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_273_fu_3022_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_270_fu_3019_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_267_fu_3016_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_264_fu_3013_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_261_fu_3010_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_258_fu_3007_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_255_fu_3004_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_252_fu_3001_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_328_fu_3107_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_325_fu_3104_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_322_fu_3101_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_319_fu_3098_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_316_fu_3095_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_313_fu_3092_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_310_fu_3089_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_307_fu_3086_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_304_fu_3083_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_301_fu_3080_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_298_fu_3077_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_295_fu_3074_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_292_fu_3071_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state76 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state76 : signal is "none";
signal ap_NS_fsm : STD_LOGIC_VECTOR (9 downto 0);
signal ap_block_pp0_stage2_subdone : BOOLEAN;
signal ap_block_pp0_stage3_subdone : BOOLEAN;
signal ap_block_pp0_stage4_subdone : BOOLEAN;
signal ap_block_pp0_stage5_subdone : BOOLEAN;
signal ap_block_pp0_stage6_subdone : BOOLEAN;
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
component convolve_kernel_fbkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component convolve_kernel_fcud IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component convolve_kernel_control_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC );
end component;
begin
convolve_kernel_control_s_axi_U : component convolve_kernel_control_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_CONTROL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CONTROL_DATA_WIDTH)
port map (
AWVALID => s_axi_control_AWVALID,
AWREADY => s_axi_control_AWREADY,
AWADDR => s_axi_control_AWADDR,
WVALID => s_axi_control_WVALID,
WREADY => s_axi_control_WREADY,
WDATA => s_axi_control_WDATA,
WSTRB => s_axi_control_WSTRB,
ARVALID => s_axi_control_ARVALID,
ARREADY => s_axi_control_ARREADY,
ARADDR => s_axi_control_ARADDR,
RVALID => s_axi_control_RVALID,
RREADY => s_axi_control_RREADY,
RDATA => s_axi_control_RDATA,
RRESP => s_axi_control_RRESP,
BVALID => s_axi_control_BVALID,
BREADY => s_axi_control_BREADY,
BRESP => s_axi_control_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle);
convolve_kernel_fbkb_U1 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_943_p0,
din1 => grp_fu_943_p1,
ce => ap_const_logic_1,
dout => grp_fu_943_p2);
convolve_kernel_fbkb_U2 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_947_p0,
din1 => grp_fu_947_p1,
ce => ap_const_logic_1,
dout => grp_fu_947_p2);
convolve_kernel_fbkb_U3 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_951_p0,
din1 => grp_fu_951_p1,
ce => ap_const_logic_1,
dout => grp_fu_951_p2);
convolve_kernel_fbkb_U4 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_955_p0,
din1 => grp_fu_955_p1,
ce => ap_const_logic_1,
dout => grp_fu_955_p2);
convolve_kernel_fbkb_U5 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_959_p0,
din1 => grp_fu_959_p1,
ce => ap_const_logic_1,
dout => grp_fu_959_p2);
convolve_kernel_fbkb_U6 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_963_p0,
din1 => grp_fu_963_p1,
ce => ap_const_logic_1,
dout => grp_fu_963_p2);
convolve_kernel_fbkb_U7 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_967_p0,
din1 => grp_fu_967_p1,
ce => ap_const_logic_1,
dout => grp_fu_967_p2);
convolve_kernel_fbkb_U8 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_971_p0,
din1 => grp_fu_971_p1,
ce => ap_const_logic_1,
dout => grp_fu_971_p2);
convolve_kernel_fbkb_U9 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_975_p0,
din1 => grp_fu_975_p1,
ce => ap_const_logic_1,
dout => grp_fu_975_p2);
convolve_kernel_fbkb_U10 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_979_p0,
din1 => grp_fu_979_p1,
ce => ap_const_logic_1,
dout => grp_fu_979_p2);
convolve_kernel_fbkb_U11 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_983_p0,
din1 => grp_fu_983_p1,
ce => ap_const_logic_1,
dout => grp_fu_983_p2);
convolve_kernel_fbkb_U12 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_987_p0,
din1 => grp_fu_987_p1,
ce => ap_const_logic_1,
dout => grp_fu_987_p2);
convolve_kernel_fbkb_U13 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_991_p0,
din1 => grp_fu_991_p1,
ce => ap_const_logic_1,
dout => grp_fu_991_p2);
convolve_kernel_fbkb_U14 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_995_p0,
din1 => grp_fu_995_p1,
ce => ap_const_logic_1,
dout => grp_fu_995_p2);
convolve_kernel_fbkb_U15 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_999_p0,
din1 => grp_fu_999_p1,
ce => ap_const_logic_1,
dout => grp_fu_999_p2);
convolve_kernel_fbkb_U16 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1003_p0,
din1 => grp_fu_1003_p1,
ce => ap_const_logic_1,
dout => grp_fu_1003_p2);
convolve_kernel_fbkb_U17 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1007_p0,
din1 => grp_fu_1007_p1,
ce => ap_const_logic_1,
dout => grp_fu_1007_p2);
convolve_kernel_fbkb_U18 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1011_p0,
din1 => grp_fu_1011_p1,
ce => ap_const_logic_1,
dout => grp_fu_1011_p2);
convolve_kernel_fbkb_U19 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1015_p0,
din1 => grp_fu_1015_p1,
ce => ap_const_logic_1,
dout => grp_fu_1015_p2);
convolve_kernel_fbkb_U20 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1019_p0,
din1 => grp_fu_1019_p1,
ce => ap_const_logic_1,
dout => grp_fu_1019_p2);
convolve_kernel_fbkb_U21 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1023_p0,
din1 => grp_fu_1023_p1,
ce => ap_const_logic_1,
dout => grp_fu_1023_p2);
convolve_kernel_fbkb_U22 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1027_p0,
din1 => grp_fu_1027_p1,
ce => ap_const_logic_1,
dout => grp_fu_1027_p2);
convolve_kernel_fbkb_U23 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1031_p0,
din1 => grp_fu_1031_p1,
ce => ap_const_logic_1,
dout => grp_fu_1031_p2);
convolve_kernel_fbkb_U24 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1035_p0,
din1 => grp_fu_1035_p1,
ce => ap_const_logic_1,
dout => grp_fu_1035_p2);
convolve_kernel_fbkb_U25 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1039_p0,
din1 => grp_fu_1039_p1,
ce => ap_const_logic_1,
dout => grp_fu_1039_p2);
convolve_kernel_fbkb_U26 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1043_p0,
din1 => grp_fu_1043_p1,
ce => ap_const_logic_1,
dout => grp_fu_1043_p2);
convolve_kernel_fbkb_U27 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1047_p0,
din1 => grp_fu_1047_p1,
ce => ap_const_logic_1,
dout => grp_fu_1047_p2);
convolve_kernel_fbkb_U28 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1051_p0,
din1 => grp_fu_1051_p1,
ce => ap_const_logic_1,
dout => grp_fu_1051_p2);
convolve_kernel_fbkb_U29 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1055_p0,
din1 => grp_fu_1055_p1,
ce => ap_const_logic_1,
dout => grp_fu_1055_p2);
convolve_kernel_fbkb_U30 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1059_p0,
din1 => grp_fu_1059_p1,
ce => ap_const_logic_1,
dout => grp_fu_1059_p2);
convolve_kernel_fbkb_U31 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1063_p0,
din1 => grp_fu_1063_p1,
ce => ap_const_logic_1,
dout => grp_fu_1063_p2);
convolve_kernel_fbkb_U32 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1067_p0,
din1 => grp_fu_1067_p1,
ce => ap_const_logic_1,
dout => grp_fu_1067_p2);
convolve_kernel_fbkb_U33 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1071_p0,
din1 => grp_fu_1071_p1,
ce => ap_const_logic_1,
dout => grp_fu_1071_p2);
convolve_kernel_fbkb_U34 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1075_p0,
din1 => grp_fu_1075_p1,
ce => ap_const_logic_1,
dout => grp_fu_1075_p2);
convolve_kernel_fbkb_U35 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1079_p0,
din1 => grp_fu_1079_p1,
ce => ap_const_logic_1,
dout => grp_fu_1079_p2);
convolve_kernel_fbkb_U36 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1083_p0,
din1 => grp_fu_1083_p1,
ce => ap_const_logic_1,
dout => grp_fu_1083_p2);
convolve_kernel_fbkb_U37 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1087_p0,
din1 => grp_fu_1087_p1,
ce => ap_const_logic_1,
dout => grp_fu_1087_p2);
convolve_kernel_fbkb_U38 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1091_p0,
din1 => grp_fu_1091_p1,
ce => ap_const_logic_1,
dout => grp_fu_1091_p2);
convolve_kernel_fbkb_U39 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1095_p0,
din1 => grp_fu_1095_p1,
ce => ap_const_logic_1,
dout => grp_fu_1095_p2);
convolve_kernel_fcud_U40 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1099_p0,
din1 => grp_fu_1099_p1,
ce => ap_const_logic_1,
dout => grp_fu_1099_p2);
convolve_kernel_fcud_U41 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1103_p0,
din1 => grp_fu_1103_p1,
ce => ap_const_logic_1,
dout => grp_fu_1103_p2);
convolve_kernel_fcud_U42 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1107_p0,
din1 => grp_fu_1107_p1,
ce => ap_const_logic_1,
dout => grp_fu_1107_p2);
convolve_kernel_fcud_U43 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1111_p0,
din1 => grp_fu_1111_p1,
ce => ap_const_logic_1,
dout => grp_fu_1111_p2);
convolve_kernel_fcud_U44 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1115_p0,
din1 => grp_fu_1115_p1,
ce => ap_const_logic_1,
dout => grp_fu_1115_p2);
convolve_kernel_fcud_U45 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1119_p0,
din1 => grp_fu_1119_p1,
ce => ap_const_logic_1,
dout => grp_fu_1119_p2);
convolve_kernel_fcud_U46 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1123_p0,
din1 => grp_fu_1123_p1,
ce => ap_const_logic_1,
dout => grp_fu_1123_p2);
convolve_kernel_fcud_U47 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1127_p0,
din1 => grp_fu_1127_p1,
ce => ap_const_logic_1,
dout => grp_fu_1127_p2);
convolve_kernel_fcud_U48 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1131_p0,
din1 => grp_fu_1131_p1,
ce => ap_const_logic_1,
dout => grp_fu_1131_p2);
convolve_kernel_fcud_U49 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1135_p0,
din1 => grp_fu_1135_p1,
ce => ap_const_logic_1,
dout => grp_fu_1135_p2);
convolve_kernel_fcud_U50 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1139_p0,
din1 => grp_fu_1139_p1,
ce => ap_const_logic_1,
dout => grp_fu_1139_p2);
convolve_kernel_fcud_U51 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1143_p0,
din1 => grp_fu_1143_p1,
ce => ap_const_logic_1,
dout => grp_fu_1143_p2);
convolve_kernel_fcud_U52 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1147_p0,
din1 => grp_fu_1147_p1,
ce => ap_const_logic_1,
dout => grp_fu_1147_p2);
convolve_kernel_fcud_U53 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1151_p0,
din1 => grp_fu_1151_p1,
ce => ap_const_logic_1,
dout => grp_fu_1151_p2);
convolve_kernel_fcud_U54 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1155_p0,
din1 => grp_fu_1155_p1,
ce => ap_const_logic_1,
dout => grp_fu_1155_p2);
convolve_kernel_fcud_U55 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1159_p0,
din1 => grp_fu_1159_p1,
ce => ap_const_logic_1,
dout => grp_fu_1159_p2);
convolve_kernel_fcud_U56 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1163_p0,
din1 => grp_fu_1163_p1,
ce => ap_const_logic_1,
dout => grp_fu_1163_p2);
convolve_kernel_fcud_U57 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1167_p0,
din1 => grp_fu_1167_p1,
ce => ap_const_logic_1,
dout => grp_fu_1167_p2);
convolve_kernel_fcud_U58 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1171_p0,
din1 => grp_fu_1171_p1,
ce => ap_const_logic_1,
dout => grp_fu_1171_p2);
convolve_kernel_fcud_U59 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1175_p0,
din1 => grp_fu_1175_p1,
ce => ap_const_logic_1,
dout => grp_fu_1175_p2);
convolve_kernel_fcud_U60 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1179_p0,
din1 => grp_fu_1179_p1,
ce => ap_const_logic_1,
dout => grp_fu_1179_p2);
convolve_kernel_fcud_U61 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1183_p0,
din1 => grp_fu_1183_p1,
ce => ap_const_logic_1,
dout => grp_fu_1183_p2);
convolve_kernel_fcud_U62 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1187_p0,
din1 => grp_fu_1187_p1,
ce => ap_const_logic_1,
dout => grp_fu_1187_p2);
convolve_kernel_fcud_U63 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1191_p0,
din1 => grp_fu_1191_p1,
ce => ap_const_logic_1,
dout => grp_fu_1191_p2);
convolve_kernel_fcud_U64 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1195_p0,
din1 => grp_fu_1195_p1,
ce => ap_const_logic_1,
dout => grp_fu_1195_p2);
convolve_kernel_fcud_U65 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1199_p0,
din1 => grp_fu_1199_p1,
ce => ap_const_logic_1,
dout => grp_fu_1199_p2);
convolve_kernel_fcud_U66 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1203_p0,
din1 => grp_fu_1203_p1,
ce => ap_const_logic_1,
dout => grp_fu_1203_p2);
convolve_kernel_fcud_U67 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1207_p0,
din1 => grp_fu_1207_p1,
ce => ap_const_logic_1,
dout => grp_fu_1207_p2);
convolve_kernel_fcud_U68 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1211_p0,
din1 => grp_fu_1211_p1,
ce => ap_const_logic_1,
dout => grp_fu_1211_p2);
convolve_kernel_fcud_U69 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1215_p0,
din1 => grp_fu_1215_p1,
ce => ap_const_logic_1,
dout => grp_fu_1215_p2);
convolve_kernel_fcud_U70 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1219_p0,
din1 => grp_fu_1219_p1,
ce => ap_const_logic_1,
dout => grp_fu_1219_p2);
convolve_kernel_fcud_U71 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1223_p0,
din1 => grp_fu_1223_p1,
ce => ap_const_logic_1,
dout => grp_fu_1223_p2);
convolve_kernel_fcud_U72 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1227_p0,
din1 => grp_fu_1227_p1,
ce => ap_const_logic_1,
dout => grp_fu_1227_p2);
convolve_kernel_fcud_U73 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1231_p0,
din1 => grp_fu_1231_p1,
ce => ap_const_logic_1,
dout => grp_fu_1231_p2);
convolve_kernel_fcud_U74 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1235_p0,
din1 => grp_fu_1235_p1,
ce => ap_const_logic_1,
dout => grp_fu_1235_p2);
convolve_kernel_fcud_U75 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1239_p0,
din1 => grp_fu_1239_p1,
ce => ap_const_logic_1,
dout => grp_fu_1239_p2);
convolve_kernel_fcud_U76 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1243_p0,
din1 => grp_fu_1243_p1,
ce => ap_const_logic_1,
dout => grp_fu_1243_p2);
convolve_kernel_fcud_U77 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1247_p0,
din1 => grp_fu_1247_p1,
ce => ap_const_logic_1,
dout => grp_fu_1247_p2);
convolve_kernel_fcud_U78 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1251_p0,
din1 => grp_fu_1251_p1,
ce => ap_const_logic_1,
dout => grp_fu_1251_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage0_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2)) then
ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state2 xor ap_const_logic_1);
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end if;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter6 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter7 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter8 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter9 <= ap_const_logic_0;
else
if ((((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage1_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter9 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
i_reg_896_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
i_reg_896 <= tmp_1_mid2_v_reg_3225;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
i_reg_896 <= ap_const_lv3_0;
end if;
end if;
end process;
indvar_flatten1_reg_885_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
indvar_flatten1_reg_885 <= indvar_flatten_next1_reg_3180;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
indvar_flatten1_reg_885 <= ap_const_lv10_0;
end if;
end if;
end process;
indvar_flatten_reg_908_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
indvar_flatten_reg_908 <= indvar_flatten_next_reg_3252;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
indvar_flatten_reg_908 <= ap_const_lv8_0;
end if;
end if;
end process;
j_reg_919_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
j_reg_919 <= tmp_5_mid2_reg_3286;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
j_reg_919 <= ap_const_lv3_0;
end if;
end if;
end process;
row_b_reg_931_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
row_b_reg_931 <= row_b_1_reg_3276;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
row_b_reg_931 <= ap_const_lv5_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 <= exitcond_flatten1_reg_3176;
ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter1_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter3_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter2_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter3_tmp_19_1_0_1_reg_5244 <= tmp_19_1_0_1_reg_5244;
ap_reg_pp0_iter3_tmp_19_1_10_1_reg_5344 <= tmp_19_1_10_1_reg_5344;
ap_reg_pp0_iter3_tmp_19_1_11_1_reg_5354 <= tmp_19_1_11_1_reg_5354;
ap_reg_pp0_iter3_tmp_19_1_12_1_reg_5364 <= tmp_19_1_12_1_reg_5364;
ap_reg_pp0_iter3_tmp_19_1_1_1_reg_5254 <= tmp_19_1_1_1_reg_5254;
ap_reg_pp0_iter3_tmp_19_1_2_1_reg_5264 <= tmp_19_1_2_1_reg_5264;
ap_reg_pp0_iter3_tmp_19_1_3_1_reg_5274 <= tmp_19_1_3_1_reg_5274;
ap_reg_pp0_iter3_tmp_19_1_4_1_reg_5284 <= tmp_19_1_4_1_reg_5284;
ap_reg_pp0_iter3_tmp_19_1_5_1_reg_5294 <= tmp_19_1_5_1_reg_5294;
ap_reg_pp0_iter3_tmp_19_1_6_1_reg_5304 <= tmp_19_1_6_1_reg_5304;
ap_reg_pp0_iter3_tmp_19_1_7_1_reg_5314 <= tmp_19_1_7_1_reg_5314;
ap_reg_pp0_iter3_tmp_19_1_8_1_reg_5324 <= tmp_19_1_8_1_reg_5324;
ap_reg_pp0_iter3_tmp_19_1_9_1_reg_5334 <= tmp_19_1_9_1_reg_5334;
ap_reg_pp0_iter4_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter3_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter4_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter6_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter5_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter6_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter8_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter7_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter9_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter8_exitcond_flatten1_reg_3176;
exitcond_flatten1_reg_3176 <= exitcond_flatten1_fu_1541_p2;
tmp_12_1_reg_3141 <= tmp_12_1_fu_1499_p2;
tmp_12_2_reg_3146 <= tmp_12_2_fu_1505_p2;
tmp_12_3_reg_3151 <= tmp_12_3_fu_1511_p2;
tmp_12_4_reg_3156 <= tmp_12_4_fu_1517_p2;
tmp_12_5_reg_3161 <= tmp_12_5_fu_1523_p2;
tmp_12_6_reg_3166 <= tmp_12_6_fu_1529_p2;
tmp_12_7_reg_3171 <= tmp_12_7_fu_1535_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
ap_reg_pp0_iter1_row_b_mid2_reg_3245 <= row_b_mid2_reg_3245;
ap_reg_pp0_iter3_tmp_19_2_0_1_reg_5504 <= tmp_19_2_0_1_reg_5504;
ap_reg_pp0_iter3_tmp_19_2_10_1_reg_5604 <= tmp_19_2_10_1_reg_5604;
ap_reg_pp0_iter3_tmp_19_2_11_1_reg_5614 <= tmp_19_2_11_1_reg_5614;
ap_reg_pp0_iter3_tmp_19_2_12_1_reg_5624 <= tmp_19_2_12_1_reg_5624;
ap_reg_pp0_iter3_tmp_19_2_1_1_reg_5514 <= tmp_19_2_1_1_reg_5514;
ap_reg_pp0_iter3_tmp_19_2_2_1_reg_5524 <= tmp_19_2_2_1_reg_5524;
ap_reg_pp0_iter3_tmp_19_2_3_1_reg_5534 <= tmp_19_2_3_1_reg_5534;
ap_reg_pp0_iter3_tmp_19_2_4_1_reg_5544 <= tmp_19_2_4_1_reg_5544;
ap_reg_pp0_iter3_tmp_19_2_5_1_reg_5554 <= tmp_19_2_5_1_reg_5554;
ap_reg_pp0_iter3_tmp_19_2_6_1_reg_5564 <= tmp_19_2_6_1_reg_5564;
ap_reg_pp0_iter3_tmp_19_2_7_1_reg_5574 <= tmp_19_2_7_1_reg_5574;
ap_reg_pp0_iter3_tmp_19_2_8_1_reg_5584 <= tmp_19_2_8_1_reg_5584;
ap_reg_pp0_iter3_tmp_19_2_9_1_reg_5594 <= tmp_19_2_9_1_reg_5594;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
ap_reg_pp0_iter2_bufo_addr_1_reg_4322(7 downto 3) <= bufo_addr_1_reg_4322(7 downto 3);
ap_reg_pp0_iter2_bufo_addr_reg_4317(7 downto 3) <= bufo_addr_reg_4317(7 downto 3);
ap_reg_pp0_iter3_bufo_addr_1_reg_4322(7 downto 3) <= ap_reg_pp0_iter2_bufo_addr_1_reg_4322(7 downto 3);
ap_reg_pp0_iter3_bufo_addr_reg_4317(7 downto 3) <= ap_reg_pp0_iter2_bufo_addr_reg_4317(7 downto 3);
ap_reg_pp0_iter3_tmp_19_3_0_1_reg_5824 <= tmp_19_3_0_1_reg_5824;
ap_reg_pp0_iter3_tmp_19_3_10_1_reg_5874 <= tmp_19_3_10_1_reg_5874;
ap_reg_pp0_iter3_tmp_19_3_11_1_reg_5879 <= tmp_19_3_11_1_reg_5879;
ap_reg_pp0_iter3_tmp_19_3_12_1_reg_5884 <= tmp_19_3_12_1_reg_5884;
ap_reg_pp0_iter3_tmp_19_3_1_1_reg_5829 <= tmp_19_3_1_1_reg_5829;
ap_reg_pp0_iter3_tmp_19_3_2_1_reg_5834 <= tmp_19_3_2_1_reg_5834;
ap_reg_pp0_iter3_tmp_19_3_3_1_reg_5839 <= tmp_19_3_3_1_reg_5839;
ap_reg_pp0_iter3_tmp_19_3_4_1_reg_5844 <= tmp_19_3_4_1_reg_5844;
ap_reg_pp0_iter3_tmp_19_3_5_1_reg_5849 <= tmp_19_3_5_1_reg_5849;
ap_reg_pp0_iter3_tmp_19_3_6_1_reg_5854 <= tmp_19_3_6_1_reg_5854;
ap_reg_pp0_iter3_tmp_19_3_7_1_reg_5859 <= tmp_19_3_7_1_reg_5859;
ap_reg_pp0_iter3_tmp_19_3_8_1_reg_5864 <= tmp_19_3_8_1_reg_5864;
ap_reg_pp0_iter3_tmp_19_3_9_1_reg_5869 <= tmp_19_3_9_1_reg_5869;
ap_reg_pp0_iter4_bufo_addr_1_reg_4322(7 downto 3) <= ap_reg_pp0_iter3_bufo_addr_1_reg_4322(7 downto 3);
ap_reg_pp0_iter4_bufo_addr_reg_4317(7 downto 3) <= ap_reg_pp0_iter3_bufo_addr_reg_4317(7 downto 3);
ap_reg_pp0_iter5_bufo_addr_1_reg_4322(7 downto 3) <= ap_reg_pp0_iter4_bufo_addr_1_reg_4322(7 downto 3);
ap_reg_pp0_iter5_bufo_addr_reg_4317(7 downto 3) <= ap_reg_pp0_iter4_bufo_addr_reg_4317(7 downto 3);
ap_reg_pp0_iter6_bufo_addr_1_reg_4322(7 downto 3) <= ap_reg_pp0_iter5_bufo_addr_1_reg_4322(7 downto 3);
ap_reg_pp0_iter6_bufo_addr_reg_4317(7 downto 3) <= ap_reg_pp0_iter5_bufo_addr_reg_4317(7 downto 3);
ap_reg_pp0_iter7_bufo_addr_1_reg_4322(7 downto 3) <= ap_reg_pp0_iter6_bufo_addr_1_reg_4322(7 downto 3);
ap_reg_pp0_iter7_bufo_addr_reg_4317(7 downto 3) <= ap_reg_pp0_iter6_bufo_addr_reg_4317(7 downto 3);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
ap_reg_pp0_iter2_bufo_addr_2_reg_4429(7 downto 3) <= bufo_addr_2_reg_4429(7 downto 3);
ap_reg_pp0_iter2_bufo_addr_3_reg_4434(7 downto 3) <= bufo_addr_3_reg_4434(7 downto 3);
ap_reg_pp0_iter3_bufo_addr_2_reg_4429(7 downto 3) <= ap_reg_pp0_iter2_bufo_addr_2_reg_4429(7 downto 3);
ap_reg_pp0_iter3_bufo_addr_3_reg_4434(7 downto 3) <= ap_reg_pp0_iter2_bufo_addr_3_reg_4434(7 downto 3);
ap_reg_pp0_iter3_tmp_19_4_0_1_reg_6149 <= tmp_19_4_0_1_reg_6149;
ap_reg_pp0_iter3_tmp_19_4_10_1_reg_6199 <= tmp_19_4_10_1_reg_6199;
ap_reg_pp0_iter3_tmp_19_4_11_1_reg_6204 <= tmp_19_4_11_1_reg_6204;
ap_reg_pp0_iter3_tmp_19_4_12_1_reg_6209 <= tmp_19_4_12_1_reg_6209;
ap_reg_pp0_iter3_tmp_19_4_1_1_reg_6154 <= tmp_19_4_1_1_reg_6154;
ap_reg_pp0_iter3_tmp_19_4_2_1_reg_6159 <= tmp_19_4_2_1_reg_6159;
ap_reg_pp0_iter3_tmp_19_4_3_1_reg_6164 <= tmp_19_4_3_1_reg_6164;
ap_reg_pp0_iter3_tmp_19_4_4_1_reg_6169 <= tmp_19_4_4_1_reg_6169;
ap_reg_pp0_iter3_tmp_19_4_5_1_reg_6174 <= tmp_19_4_5_1_reg_6174;
ap_reg_pp0_iter3_tmp_19_4_6_1_reg_6179 <= tmp_19_4_6_1_reg_6179;
ap_reg_pp0_iter3_tmp_19_4_7_1_reg_6184 <= tmp_19_4_7_1_reg_6184;
ap_reg_pp0_iter3_tmp_19_4_8_1_reg_6189 <= tmp_19_4_8_1_reg_6189;
ap_reg_pp0_iter3_tmp_19_4_9_1_reg_6194 <= tmp_19_4_9_1_reg_6194;
ap_reg_pp0_iter3_tmp_19_5_0_1_reg_6214 <= tmp_19_5_0_1_reg_6214;
ap_reg_pp0_iter3_tmp_19_5_10_1_reg_6264 <= tmp_19_5_10_1_reg_6264;
ap_reg_pp0_iter3_tmp_19_5_11_1_reg_6269 <= tmp_19_5_11_1_reg_6269;
ap_reg_pp0_iter3_tmp_19_5_12_1_reg_6274 <= tmp_19_5_12_1_reg_6274;
ap_reg_pp0_iter3_tmp_19_5_1_1_reg_6219 <= tmp_19_5_1_1_reg_6219;
ap_reg_pp0_iter3_tmp_19_5_2_1_reg_6224 <= tmp_19_5_2_1_reg_6224;
ap_reg_pp0_iter3_tmp_19_5_3_1_reg_6229 <= tmp_19_5_3_1_reg_6229;
ap_reg_pp0_iter3_tmp_19_5_4_1_reg_6234 <= tmp_19_5_4_1_reg_6234;
ap_reg_pp0_iter3_tmp_19_5_5_1_reg_6239 <= tmp_19_5_5_1_reg_6239;
ap_reg_pp0_iter3_tmp_19_5_6_1_reg_6244 <= tmp_19_5_6_1_reg_6244;
ap_reg_pp0_iter3_tmp_19_5_7_1_reg_6249 <= tmp_19_5_7_1_reg_6249;
ap_reg_pp0_iter3_tmp_19_5_8_1_reg_6254 <= tmp_19_5_8_1_reg_6254;
ap_reg_pp0_iter3_tmp_19_5_9_1_reg_6259 <= tmp_19_5_9_1_reg_6259;
ap_reg_pp0_iter3_tmp_19_6_0_1_reg_6284 <= tmp_19_6_0_1_reg_6284;
ap_reg_pp0_iter3_tmp_19_6_10_1_reg_6384 <= tmp_19_6_10_1_reg_6384;
ap_reg_pp0_iter3_tmp_19_6_11_1_reg_6394 <= tmp_19_6_11_1_reg_6394;
ap_reg_pp0_iter3_tmp_19_6_12_1_reg_6404 <= tmp_19_6_12_1_reg_6404;
ap_reg_pp0_iter3_tmp_19_6_1_1_reg_6294 <= tmp_19_6_1_1_reg_6294;
ap_reg_pp0_iter3_tmp_19_6_2_1_reg_6304 <= tmp_19_6_2_1_reg_6304;
ap_reg_pp0_iter3_tmp_19_6_3_1_reg_6314 <= tmp_19_6_3_1_reg_6314;
ap_reg_pp0_iter3_tmp_19_6_4_1_reg_6324 <= tmp_19_6_4_1_reg_6324;
ap_reg_pp0_iter3_tmp_19_6_5_1_reg_6334 <= tmp_19_6_5_1_reg_6334;
ap_reg_pp0_iter3_tmp_19_6_6_1_reg_6344 <= tmp_19_6_6_1_reg_6344;
ap_reg_pp0_iter3_tmp_19_6_7_1_reg_6354 <= tmp_19_6_7_1_reg_6354;
ap_reg_pp0_iter3_tmp_19_6_8_1_reg_6364 <= tmp_19_6_8_1_reg_6364;
ap_reg_pp0_iter3_tmp_19_6_9_1_reg_6374 <= tmp_19_6_9_1_reg_6374;
ap_reg_pp0_iter4_bufo_addr_2_reg_4429(7 downto 3) <= ap_reg_pp0_iter3_bufo_addr_2_reg_4429(7 downto 3);
ap_reg_pp0_iter4_bufo_addr_3_reg_4434(7 downto 3) <= ap_reg_pp0_iter3_bufo_addr_3_reg_4434(7 downto 3);
ap_reg_pp0_iter5_bufo_addr_2_reg_4429(7 downto 3) <= ap_reg_pp0_iter4_bufo_addr_2_reg_4429(7 downto 3);
ap_reg_pp0_iter5_bufo_addr_3_reg_4434(7 downto 3) <= ap_reg_pp0_iter4_bufo_addr_3_reg_4434(7 downto 3);
ap_reg_pp0_iter6_bufo_addr_2_reg_4429(7 downto 3) <= ap_reg_pp0_iter5_bufo_addr_2_reg_4429(7 downto 3);
ap_reg_pp0_iter6_bufo_addr_3_reg_4434(7 downto 3) <= ap_reg_pp0_iter5_bufo_addr_3_reg_4434(7 downto 3);
ap_reg_pp0_iter7_bufo_addr_2_reg_4429(7 downto 3) <= ap_reg_pp0_iter6_bufo_addr_2_reg_4429(7 downto 3);
ap_reg_pp0_iter7_bufo_addr_3_reg_4434(7 downto 3) <= ap_reg_pp0_iter6_bufo_addr_3_reg_4434(7 downto 3);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
ap_reg_pp0_iter2_bufo_addr_4_reg_4439(7 downto 3) <= bufo_addr_4_reg_4439(7 downto 3);
ap_reg_pp0_iter2_bufo_addr_5_reg_4444(7 downto 3) <= bufo_addr_5_reg_4444(7 downto 3);
ap_reg_pp0_iter3_bufo_addr_4_reg_4439(7 downto 3) <= ap_reg_pp0_iter2_bufo_addr_4_reg_4439(7 downto 3);
ap_reg_pp0_iter3_bufo_addr_5_reg_4444(7 downto 3) <= ap_reg_pp0_iter2_bufo_addr_5_reg_4444(7 downto 3);
ap_reg_pp0_iter3_tmp_19_0_0_2_reg_6474 <= tmp_19_0_0_2_reg_6474;
ap_reg_pp0_iter3_tmp_19_0_10_2_reg_6524 <= tmp_19_0_10_2_reg_6524;
ap_reg_pp0_iter3_tmp_19_0_11_2_reg_6529 <= tmp_19_0_11_2_reg_6529;
ap_reg_pp0_iter3_tmp_19_0_12_2_reg_6534 <= tmp_19_0_12_2_reg_6534;
ap_reg_pp0_iter3_tmp_19_0_1_2_reg_6479 <= tmp_19_0_1_2_reg_6479;
ap_reg_pp0_iter3_tmp_19_0_2_2_reg_6484 <= tmp_19_0_2_2_reg_6484;
ap_reg_pp0_iter3_tmp_19_0_3_2_reg_6489 <= tmp_19_0_3_2_reg_6489;
ap_reg_pp0_iter3_tmp_19_0_4_2_reg_6494 <= tmp_19_0_4_2_reg_6494;
ap_reg_pp0_iter3_tmp_19_0_5_2_reg_6499 <= tmp_19_0_5_2_reg_6499;
ap_reg_pp0_iter3_tmp_19_0_6_2_reg_6504 <= tmp_19_0_6_2_reg_6504;
ap_reg_pp0_iter3_tmp_19_0_7_2_reg_6509 <= tmp_19_0_7_2_reg_6509;
ap_reg_pp0_iter3_tmp_19_0_8_2_reg_6514 <= tmp_19_0_8_2_reg_6514;
ap_reg_pp0_iter3_tmp_19_0_9_2_reg_6519 <= tmp_19_0_9_2_reg_6519;
ap_reg_pp0_iter3_tmp_19_1_0_2_reg_6539 <= tmp_19_1_0_2_reg_6539;
ap_reg_pp0_iter3_tmp_19_1_10_2_reg_6589 <= tmp_19_1_10_2_reg_6589;
ap_reg_pp0_iter3_tmp_19_1_11_2_reg_6594 <= tmp_19_1_11_2_reg_6594;
ap_reg_pp0_iter3_tmp_19_1_12_2_reg_6599 <= tmp_19_1_12_2_reg_6599;
ap_reg_pp0_iter3_tmp_19_1_1_2_reg_6544 <= tmp_19_1_1_2_reg_6544;
ap_reg_pp0_iter3_tmp_19_1_2_2_reg_6549 <= tmp_19_1_2_2_reg_6549;
ap_reg_pp0_iter3_tmp_19_1_3_2_reg_6554 <= tmp_19_1_3_2_reg_6554;
ap_reg_pp0_iter3_tmp_19_1_4_2_reg_6559 <= tmp_19_1_4_2_reg_6559;
ap_reg_pp0_iter3_tmp_19_1_5_2_reg_6564 <= tmp_19_1_5_2_reg_6564;
ap_reg_pp0_iter3_tmp_19_1_6_2_reg_6569 <= tmp_19_1_6_2_reg_6569;
ap_reg_pp0_iter3_tmp_19_1_7_2_reg_6574 <= tmp_19_1_7_2_reg_6574;
ap_reg_pp0_iter3_tmp_19_1_8_2_reg_6579 <= tmp_19_1_8_2_reg_6579;
ap_reg_pp0_iter3_tmp_19_1_9_2_reg_6584 <= tmp_19_1_9_2_reg_6584;
ap_reg_pp0_iter3_tmp_19_7_0_1_reg_6604 <= tmp_19_7_0_1_reg_6604;
ap_reg_pp0_iter3_tmp_19_7_10_1_reg_6654 <= tmp_19_7_10_1_reg_6654;
ap_reg_pp0_iter3_tmp_19_7_11_1_reg_6659 <= tmp_19_7_11_1_reg_6659;
ap_reg_pp0_iter3_tmp_19_7_12_1_reg_6664 <= tmp_19_7_12_1_reg_6664;
ap_reg_pp0_iter3_tmp_19_7_1_1_reg_6609 <= tmp_19_7_1_1_reg_6609;
ap_reg_pp0_iter3_tmp_19_7_2_1_reg_6614 <= tmp_19_7_2_1_reg_6614;
ap_reg_pp0_iter3_tmp_19_7_3_1_reg_6619 <= tmp_19_7_3_1_reg_6619;
ap_reg_pp0_iter3_tmp_19_7_4_1_reg_6624 <= tmp_19_7_4_1_reg_6624;
ap_reg_pp0_iter3_tmp_19_7_5_1_reg_6629 <= tmp_19_7_5_1_reg_6629;
ap_reg_pp0_iter3_tmp_19_7_6_1_reg_6634 <= tmp_19_7_6_1_reg_6634;
ap_reg_pp0_iter3_tmp_19_7_7_1_reg_6639 <= tmp_19_7_7_1_reg_6639;
ap_reg_pp0_iter3_tmp_19_7_8_1_reg_6644 <= tmp_19_7_8_1_reg_6644;
ap_reg_pp0_iter3_tmp_19_7_9_1_reg_6649 <= tmp_19_7_9_1_reg_6649;
ap_reg_pp0_iter4_bufo_addr_4_reg_4439(7 downto 3) <= ap_reg_pp0_iter3_bufo_addr_4_reg_4439(7 downto 3);
ap_reg_pp0_iter4_bufo_addr_5_reg_4444(7 downto 3) <= ap_reg_pp0_iter3_bufo_addr_5_reg_4444(7 downto 3);
ap_reg_pp0_iter4_tmp_19_0_0_2_reg_6474 <= ap_reg_pp0_iter3_tmp_19_0_0_2_reg_6474;
ap_reg_pp0_iter4_tmp_19_0_10_2_reg_6524 <= ap_reg_pp0_iter3_tmp_19_0_10_2_reg_6524;
ap_reg_pp0_iter4_tmp_19_0_11_2_reg_6529 <= ap_reg_pp0_iter3_tmp_19_0_11_2_reg_6529;
ap_reg_pp0_iter4_tmp_19_0_12_2_reg_6534 <= ap_reg_pp0_iter3_tmp_19_0_12_2_reg_6534;
ap_reg_pp0_iter4_tmp_19_0_1_2_reg_6479 <= ap_reg_pp0_iter3_tmp_19_0_1_2_reg_6479;
ap_reg_pp0_iter4_tmp_19_0_2_2_reg_6484 <= ap_reg_pp0_iter3_tmp_19_0_2_2_reg_6484;
ap_reg_pp0_iter4_tmp_19_0_3_2_reg_6489 <= ap_reg_pp0_iter3_tmp_19_0_3_2_reg_6489;
ap_reg_pp0_iter4_tmp_19_0_4_2_reg_6494 <= ap_reg_pp0_iter3_tmp_19_0_4_2_reg_6494;
ap_reg_pp0_iter4_tmp_19_0_5_2_reg_6499 <= ap_reg_pp0_iter3_tmp_19_0_5_2_reg_6499;
ap_reg_pp0_iter4_tmp_19_0_6_2_reg_6504 <= ap_reg_pp0_iter3_tmp_19_0_6_2_reg_6504;
ap_reg_pp0_iter4_tmp_19_0_7_2_reg_6509 <= ap_reg_pp0_iter3_tmp_19_0_7_2_reg_6509;
ap_reg_pp0_iter4_tmp_19_0_8_2_reg_6514 <= ap_reg_pp0_iter3_tmp_19_0_8_2_reg_6514;
ap_reg_pp0_iter4_tmp_19_0_9_2_reg_6519 <= ap_reg_pp0_iter3_tmp_19_0_9_2_reg_6519;
ap_reg_pp0_iter4_tmp_19_1_0_2_reg_6539 <= ap_reg_pp0_iter3_tmp_19_1_0_2_reg_6539;
ap_reg_pp0_iter4_tmp_19_1_10_2_reg_6589 <= ap_reg_pp0_iter3_tmp_19_1_10_2_reg_6589;
ap_reg_pp0_iter4_tmp_19_1_11_2_reg_6594 <= ap_reg_pp0_iter3_tmp_19_1_11_2_reg_6594;
ap_reg_pp0_iter4_tmp_19_1_12_2_reg_6599 <= ap_reg_pp0_iter3_tmp_19_1_12_2_reg_6599;
ap_reg_pp0_iter4_tmp_19_1_1_2_reg_6544 <= ap_reg_pp0_iter3_tmp_19_1_1_2_reg_6544;
ap_reg_pp0_iter4_tmp_19_1_2_2_reg_6549 <= ap_reg_pp0_iter3_tmp_19_1_2_2_reg_6549;
ap_reg_pp0_iter4_tmp_19_1_3_2_reg_6554 <= ap_reg_pp0_iter3_tmp_19_1_3_2_reg_6554;
ap_reg_pp0_iter4_tmp_19_1_4_2_reg_6559 <= ap_reg_pp0_iter3_tmp_19_1_4_2_reg_6559;
ap_reg_pp0_iter4_tmp_19_1_5_2_reg_6564 <= ap_reg_pp0_iter3_tmp_19_1_5_2_reg_6564;
ap_reg_pp0_iter4_tmp_19_1_6_2_reg_6569 <= ap_reg_pp0_iter3_tmp_19_1_6_2_reg_6569;
ap_reg_pp0_iter4_tmp_19_1_7_2_reg_6574 <= ap_reg_pp0_iter3_tmp_19_1_7_2_reg_6574;
ap_reg_pp0_iter4_tmp_19_1_8_2_reg_6579 <= ap_reg_pp0_iter3_tmp_19_1_8_2_reg_6579;
ap_reg_pp0_iter4_tmp_19_1_9_2_reg_6584 <= ap_reg_pp0_iter3_tmp_19_1_9_2_reg_6584;
ap_reg_pp0_iter5_bufo_addr_4_reg_4439(7 downto 3) <= ap_reg_pp0_iter4_bufo_addr_4_reg_4439(7 downto 3);
ap_reg_pp0_iter5_bufo_addr_5_reg_4444(7 downto 3) <= ap_reg_pp0_iter4_bufo_addr_5_reg_4444(7 downto 3);
ap_reg_pp0_iter6_bufo_addr_4_reg_4439(7 downto 3) <= ap_reg_pp0_iter5_bufo_addr_4_reg_4439(7 downto 3);
ap_reg_pp0_iter6_bufo_addr_5_reg_4444(7 downto 3) <= ap_reg_pp0_iter5_bufo_addr_5_reg_4444(7 downto 3);
ap_reg_pp0_iter7_bufo_addr_4_reg_4439(7 downto 3) <= ap_reg_pp0_iter6_bufo_addr_4_reg_4439(7 downto 3);
ap_reg_pp0_iter7_bufo_addr_5_reg_4444(7 downto 3) <= ap_reg_pp0_iter6_bufo_addr_5_reg_4444(7 downto 3);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
ap_reg_pp0_iter2_bufo_addr_6_reg_4579(7 downto 3) <= bufo_addr_6_reg_4579(7 downto 3);
ap_reg_pp0_iter2_bufo_addr_7_reg_4584(7 downto 3) <= bufo_addr_7_reg_4584(7 downto 3);
ap_reg_pp0_iter3_bufo_addr_6_reg_4579(7 downto 3) <= ap_reg_pp0_iter2_bufo_addr_6_reg_4579(7 downto 3);
ap_reg_pp0_iter3_bufo_addr_7_reg_4584(7 downto 3) <= ap_reg_pp0_iter2_bufo_addr_7_reg_4584(7 downto 3);
ap_reg_pp0_iter3_tmp_19_2_0_2_reg_6669 <= tmp_19_2_0_2_reg_6669;
ap_reg_pp0_iter3_tmp_19_2_10_2_reg_6719 <= tmp_19_2_10_2_reg_6719;
ap_reg_pp0_iter3_tmp_19_2_11_2_reg_6724 <= tmp_19_2_11_2_reg_6724;
ap_reg_pp0_iter3_tmp_19_2_12_2_reg_6729 <= tmp_19_2_12_2_reg_6729;
ap_reg_pp0_iter3_tmp_19_2_1_2_reg_6674 <= tmp_19_2_1_2_reg_6674;
ap_reg_pp0_iter3_tmp_19_2_2_2_reg_6679 <= tmp_19_2_2_2_reg_6679;
ap_reg_pp0_iter3_tmp_19_2_3_2_reg_6684 <= tmp_19_2_3_2_reg_6684;
ap_reg_pp0_iter3_tmp_19_2_4_2_reg_6689 <= tmp_19_2_4_2_reg_6689;
ap_reg_pp0_iter3_tmp_19_2_5_2_reg_6694 <= tmp_19_2_5_2_reg_6694;
ap_reg_pp0_iter3_tmp_19_2_6_2_reg_6699 <= tmp_19_2_6_2_reg_6699;
ap_reg_pp0_iter3_tmp_19_2_7_2_reg_6704 <= tmp_19_2_7_2_reg_6704;
ap_reg_pp0_iter3_tmp_19_2_8_2_reg_6709 <= tmp_19_2_8_2_reg_6709;
ap_reg_pp0_iter3_tmp_19_2_9_2_reg_6714 <= tmp_19_2_9_2_reg_6714;
ap_reg_pp0_iter3_tmp_19_3_0_2_reg_6734 <= tmp_19_3_0_2_reg_6734;
ap_reg_pp0_iter3_tmp_19_3_10_2_reg_6784 <= tmp_19_3_10_2_reg_6784;
ap_reg_pp0_iter3_tmp_19_3_11_2_reg_6789 <= tmp_19_3_11_2_reg_6789;
ap_reg_pp0_iter3_tmp_19_3_12_2_reg_6794 <= tmp_19_3_12_2_reg_6794;
ap_reg_pp0_iter3_tmp_19_3_1_2_reg_6739 <= tmp_19_3_1_2_reg_6739;
ap_reg_pp0_iter3_tmp_19_3_2_2_reg_6744 <= tmp_19_3_2_2_reg_6744;
ap_reg_pp0_iter3_tmp_19_3_3_2_reg_6749 <= tmp_19_3_3_2_reg_6749;
ap_reg_pp0_iter3_tmp_19_3_4_2_reg_6754 <= tmp_19_3_4_2_reg_6754;
ap_reg_pp0_iter3_tmp_19_3_5_2_reg_6759 <= tmp_19_3_5_2_reg_6759;
ap_reg_pp0_iter3_tmp_19_3_6_2_reg_6764 <= tmp_19_3_6_2_reg_6764;
ap_reg_pp0_iter3_tmp_19_3_7_2_reg_6769 <= tmp_19_3_7_2_reg_6769;
ap_reg_pp0_iter3_tmp_19_3_8_2_reg_6774 <= tmp_19_3_8_2_reg_6774;
ap_reg_pp0_iter3_tmp_19_3_9_2_reg_6779 <= tmp_19_3_9_2_reg_6779;
ap_reg_pp0_iter3_tmp_19_4_0_2_reg_6799 <= tmp_19_4_0_2_reg_6799;
ap_reg_pp0_iter3_tmp_19_4_10_2_reg_6849 <= tmp_19_4_10_2_reg_6849;
ap_reg_pp0_iter3_tmp_19_4_11_2_reg_6854 <= tmp_19_4_11_2_reg_6854;
ap_reg_pp0_iter3_tmp_19_4_12_2_reg_6859 <= tmp_19_4_12_2_reg_6859;
ap_reg_pp0_iter3_tmp_19_4_1_2_reg_6804 <= tmp_19_4_1_2_reg_6804;
ap_reg_pp0_iter3_tmp_19_4_2_2_reg_6809 <= tmp_19_4_2_2_reg_6809;
ap_reg_pp0_iter3_tmp_19_4_3_2_reg_6814 <= tmp_19_4_3_2_reg_6814;
ap_reg_pp0_iter3_tmp_19_4_4_2_reg_6819 <= tmp_19_4_4_2_reg_6819;
ap_reg_pp0_iter3_tmp_19_4_5_2_reg_6824 <= tmp_19_4_5_2_reg_6824;
ap_reg_pp0_iter3_tmp_19_4_6_2_reg_6829 <= tmp_19_4_6_2_reg_6829;
ap_reg_pp0_iter3_tmp_19_4_7_2_reg_6834 <= tmp_19_4_7_2_reg_6834;
ap_reg_pp0_iter3_tmp_19_4_8_2_reg_6839 <= tmp_19_4_8_2_reg_6839;
ap_reg_pp0_iter3_tmp_19_4_9_2_reg_6844 <= tmp_19_4_9_2_reg_6844;
ap_reg_pp0_iter4_bufo_addr_6_reg_4579(7 downto 3) <= ap_reg_pp0_iter3_bufo_addr_6_reg_4579(7 downto 3);
ap_reg_pp0_iter4_bufo_addr_7_reg_4584(7 downto 3) <= ap_reg_pp0_iter3_bufo_addr_7_reg_4584(7 downto 3);
ap_reg_pp0_iter4_tmp_19_2_0_2_reg_6669 <= ap_reg_pp0_iter3_tmp_19_2_0_2_reg_6669;
ap_reg_pp0_iter4_tmp_19_2_10_2_reg_6719 <= ap_reg_pp0_iter3_tmp_19_2_10_2_reg_6719;
ap_reg_pp0_iter4_tmp_19_2_11_2_reg_6724 <= ap_reg_pp0_iter3_tmp_19_2_11_2_reg_6724;
ap_reg_pp0_iter4_tmp_19_2_12_2_reg_6729 <= ap_reg_pp0_iter3_tmp_19_2_12_2_reg_6729;
ap_reg_pp0_iter4_tmp_19_2_1_2_reg_6674 <= ap_reg_pp0_iter3_tmp_19_2_1_2_reg_6674;
ap_reg_pp0_iter4_tmp_19_2_2_2_reg_6679 <= ap_reg_pp0_iter3_tmp_19_2_2_2_reg_6679;
ap_reg_pp0_iter4_tmp_19_2_3_2_reg_6684 <= ap_reg_pp0_iter3_tmp_19_2_3_2_reg_6684;
ap_reg_pp0_iter4_tmp_19_2_4_2_reg_6689 <= ap_reg_pp0_iter3_tmp_19_2_4_2_reg_6689;
ap_reg_pp0_iter4_tmp_19_2_5_2_reg_6694 <= ap_reg_pp0_iter3_tmp_19_2_5_2_reg_6694;
ap_reg_pp0_iter4_tmp_19_2_6_2_reg_6699 <= ap_reg_pp0_iter3_tmp_19_2_6_2_reg_6699;
ap_reg_pp0_iter4_tmp_19_2_7_2_reg_6704 <= ap_reg_pp0_iter3_tmp_19_2_7_2_reg_6704;
ap_reg_pp0_iter4_tmp_19_2_8_2_reg_6709 <= ap_reg_pp0_iter3_tmp_19_2_8_2_reg_6709;
ap_reg_pp0_iter4_tmp_19_2_9_2_reg_6714 <= ap_reg_pp0_iter3_tmp_19_2_9_2_reg_6714;
ap_reg_pp0_iter4_tmp_19_3_0_2_reg_6734 <= ap_reg_pp0_iter3_tmp_19_3_0_2_reg_6734;
ap_reg_pp0_iter4_tmp_19_3_10_2_reg_6784 <= ap_reg_pp0_iter3_tmp_19_3_10_2_reg_6784;
ap_reg_pp0_iter4_tmp_19_3_11_2_reg_6789 <= ap_reg_pp0_iter3_tmp_19_3_11_2_reg_6789;
ap_reg_pp0_iter4_tmp_19_3_12_2_reg_6794 <= ap_reg_pp0_iter3_tmp_19_3_12_2_reg_6794;
ap_reg_pp0_iter4_tmp_19_3_1_2_reg_6739 <= ap_reg_pp0_iter3_tmp_19_3_1_2_reg_6739;
ap_reg_pp0_iter4_tmp_19_3_2_2_reg_6744 <= ap_reg_pp0_iter3_tmp_19_3_2_2_reg_6744;
ap_reg_pp0_iter4_tmp_19_3_3_2_reg_6749 <= ap_reg_pp0_iter3_tmp_19_3_3_2_reg_6749;
ap_reg_pp0_iter4_tmp_19_3_4_2_reg_6754 <= ap_reg_pp0_iter3_tmp_19_3_4_2_reg_6754;
ap_reg_pp0_iter4_tmp_19_3_5_2_reg_6759 <= ap_reg_pp0_iter3_tmp_19_3_5_2_reg_6759;
ap_reg_pp0_iter4_tmp_19_3_6_2_reg_6764 <= ap_reg_pp0_iter3_tmp_19_3_6_2_reg_6764;
ap_reg_pp0_iter4_tmp_19_3_7_2_reg_6769 <= ap_reg_pp0_iter3_tmp_19_3_7_2_reg_6769;
ap_reg_pp0_iter4_tmp_19_3_8_2_reg_6774 <= ap_reg_pp0_iter3_tmp_19_3_8_2_reg_6774;
ap_reg_pp0_iter4_tmp_19_3_9_2_reg_6779 <= ap_reg_pp0_iter3_tmp_19_3_9_2_reg_6779;
ap_reg_pp0_iter4_tmp_19_4_0_2_reg_6799 <= ap_reg_pp0_iter3_tmp_19_4_0_2_reg_6799;
ap_reg_pp0_iter4_tmp_19_4_10_2_reg_6849 <= ap_reg_pp0_iter3_tmp_19_4_10_2_reg_6849;
ap_reg_pp0_iter4_tmp_19_4_11_2_reg_6854 <= ap_reg_pp0_iter3_tmp_19_4_11_2_reg_6854;
ap_reg_pp0_iter4_tmp_19_4_12_2_reg_6859 <= ap_reg_pp0_iter3_tmp_19_4_12_2_reg_6859;
ap_reg_pp0_iter4_tmp_19_4_1_2_reg_6804 <= ap_reg_pp0_iter3_tmp_19_4_1_2_reg_6804;
ap_reg_pp0_iter4_tmp_19_4_2_2_reg_6809 <= ap_reg_pp0_iter3_tmp_19_4_2_2_reg_6809;
ap_reg_pp0_iter4_tmp_19_4_3_2_reg_6814 <= ap_reg_pp0_iter3_tmp_19_4_3_2_reg_6814;
ap_reg_pp0_iter4_tmp_19_4_4_2_reg_6819 <= ap_reg_pp0_iter3_tmp_19_4_4_2_reg_6819;
ap_reg_pp0_iter4_tmp_19_4_5_2_reg_6824 <= ap_reg_pp0_iter3_tmp_19_4_5_2_reg_6824;
ap_reg_pp0_iter4_tmp_19_4_6_2_reg_6829 <= ap_reg_pp0_iter3_tmp_19_4_6_2_reg_6829;
ap_reg_pp0_iter4_tmp_19_4_7_2_reg_6834 <= ap_reg_pp0_iter3_tmp_19_4_7_2_reg_6834;
ap_reg_pp0_iter4_tmp_19_4_8_2_reg_6839 <= ap_reg_pp0_iter3_tmp_19_4_8_2_reg_6839;
ap_reg_pp0_iter4_tmp_19_4_9_2_reg_6844 <= ap_reg_pp0_iter3_tmp_19_4_9_2_reg_6844;
ap_reg_pp0_iter5_bufo_addr_6_reg_4579(7 downto 3) <= ap_reg_pp0_iter4_bufo_addr_6_reg_4579(7 downto 3);
ap_reg_pp0_iter5_bufo_addr_7_reg_4584(7 downto 3) <= ap_reg_pp0_iter4_bufo_addr_7_reg_4584(7 downto 3);
ap_reg_pp0_iter5_tmp_19_4_0_2_reg_6799 <= ap_reg_pp0_iter4_tmp_19_4_0_2_reg_6799;
ap_reg_pp0_iter5_tmp_19_4_10_2_reg_6849 <= ap_reg_pp0_iter4_tmp_19_4_10_2_reg_6849;
ap_reg_pp0_iter5_tmp_19_4_11_2_reg_6854 <= ap_reg_pp0_iter4_tmp_19_4_11_2_reg_6854;
ap_reg_pp0_iter5_tmp_19_4_12_2_reg_6859 <= ap_reg_pp0_iter4_tmp_19_4_12_2_reg_6859;
ap_reg_pp0_iter5_tmp_19_4_1_2_reg_6804 <= ap_reg_pp0_iter4_tmp_19_4_1_2_reg_6804;
ap_reg_pp0_iter5_tmp_19_4_2_2_reg_6809 <= ap_reg_pp0_iter4_tmp_19_4_2_2_reg_6809;
ap_reg_pp0_iter5_tmp_19_4_3_2_reg_6814 <= ap_reg_pp0_iter4_tmp_19_4_3_2_reg_6814;
ap_reg_pp0_iter5_tmp_19_4_4_2_reg_6819 <= ap_reg_pp0_iter4_tmp_19_4_4_2_reg_6819;
ap_reg_pp0_iter5_tmp_19_4_5_2_reg_6824 <= ap_reg_pp0_iter4_tmp_19_4_5_2_reg_6824;
ap_reg_pp0_iter5_tmp_19_4_6_2_reg_6829 <= ap_reg_pp0_iter4_tmp_19_4_6_2_reg_6829;
ap_reg_pp0_iter5_tmp_19_4_7_2_reg_6834 <= ap_reg_pp0_iter4_tmp_19_4_7_2_reg_6834;
ap_reg_pp0_iter5_tmp_19_4_8_2_reg_6839 <= ap_reg_pp0_iter4_tmp_19_4_8_2_reg_6839;
ap_reg_pp0_iter5_tmp_19_4_9_2_reg_6844 <= ap_reg_pp0_iter4_tmp_19_4_9_2_reg_6844;
ap_reg_pp0_iter6_bufo_addr_6_reg_4579(7 downto 3) <= ap_reg_pp0_iter5_bufo_addr_6_reg_4579(7 downto 3);
ap_reg_pp0_iter6_bufo_addr_7_reg_4584(7 downto 3) <= ap_reg_pp0_iter5_bufo_addr_7_reg_4584(7 downto 3);
ap_reg_pp0_iter7_bufo_addr_6_reg_4579(7 downto 3) <= ap_reg_pp0_iter6_bufo_addr_6_reg_4579(7 downto 3);
ap_reg_pp0_iter7_bufo_addr_7_reg_4584(7 downto 3) <= ap_reg_pp0_iter6_bufo_addr_7_reg_4584(7 downto 3);
ap_reg_pp0_iter8_bufo_addr_6_reg_4579(7 downto 3) <= ap_reg_pp0_iter7_bufo_addr_6_reg_4579(7 downto 3);
ap_reg_pp0_iter8_bufo_addr_7_reg_4584(7 downto 3) <= ap_reg_pp0_iter7_bufo_addr_7_reg_4584(7 downto 3);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
ap_reg_pp0_iter2_tmp_19_0_0_1_reg_4854 <= tmp_19_0_0_1_reg_4854;
ap_reg_pp0_iter2_tmp_19_0_10_1_reg_4954 <= tmp_19_0_10_1_reg_4954;
ap_reg_pp0_iter2_tmp_19_0_11_1_reg_4964 <= tmp_19_0_11_1_reg_4964;
ap_reg_pp0_iter2_tmp_19_0_12_1_reg_4974 <= tmp_19_0_12_1_reg_4974;
ap_reg_pp0_iter2_tmp_19_0_1_1_reg_4864 <= tmp_19_0_1_1_reg_4864;
ap_reg_pp0_iter2_tmp_19_0_2_1_reg_4874 <= tmp_19_0_2_1_reg_4874;
ap_reg_pp0_iter2_tmp_19_0_3_1_reg_4884 <= tmp_19_0_3_1_reg_4884;
ap_reg_pp0_iter2_tmp_19_0_4_1_reg_4894 <= tmp_19_0_4_1_reg_4894;
ap_reg_pp0_iter2_tmp_19_0_5_1_reg_4904 <= tmp_19_0_5_1_reg_4904;
ap_reg_pp0_iter2_tmp_19_0_6_1_reg_4914 <= tmp_19_0_6_1_reg_4914;
ap_reg_pp0_iter2_tmp_19_0_7_1_reg_4924 <= tmp_19_0_7_1_reg_4924;
ap_reg_pp0_iter2_tmp_19_0_8_1_reg_4934 <= tmp_19_0_8_1_reg_4934;
ap_reg_pp0_iter2_tmp_19_0_9_1_reg_4944 <= tmp_19_0_9_1_reg_4944;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
ap_reg_pp0_iter3_tmp_19_5_0_2_reg_6864 <= tmp_19_5_0_2_reg_6864;
ap_reg_pp0_iter3_tmp_19_5_10_2_reg_6914 <= tmp_19_5_10_2_reg_6914;
ap_reg_pp0_iter3_tmp_19_5_11_2_reg_6919 <= tmp_19_5_11_2_reg_6919;
ap_reg_pp0_iter3_tmp_19_5_12_2_reg_6924 <= tmp_19_5_12_2_reg_6924;
ap_reg_pp0_iter3_tmp_19_5_1_2_reg_6869 <= tmp_19_5_1_2_reg_6869;
ap_reg_pp0_iter3_tmp_19_5_2_2_reg_6874 <= tmp_19_5_2_2_reg_6874;
ap_reg_pp0_iter3_tmp_19_5_3_2_reg_6879 <= tmp_19_5_3_2_reg_6879;
ap_reg_pp0_iter3_tmp_19_5_4_2_reg_6884 <= tmp_19_5_4_2_reg_6884;
ap_reg_pp0_iter3_tmp_19_5_5_2_reg_6889 <= tmp_19_5_5_2_reg_6889;
ap_reg_pp0_iter3_tmp_19_5_6_2_reg_6894 <= tmp_19_5_6_2_reg_6894;
ap_reg_pp0_iter3_tmp_19_5_7_2_reg_6899 <= tmp_19_5_7_2_reg_6899;
ap_reg_pp0_iter3_tmp_19_5_8_2_reg_6904 <= tmp_19_5_8_2_reg_6904;
ap_reg_pp0_iter3_tmp_19_5_9_2_reg_6909 <= tmp_19_5_9_2_reg_6909;
ap_reg_pp0_iter3_tmp_19_6_0_2_reg_6929 <= tmp_19_6_0_2_reg_6929;
ap_reg_pp0_iter3_tmp_19_6_10_2_reg_6979 <= tmp_19_6_10_2_reg_6979;
ap_reg_pp0_iter3_tmp_19_6_11_2_reg_6984 <= tmp_19_6_11_2_reg_6984;
ap_reg_pp0_iter3_tmp_19_6_12_2_reg_6989 <= tmp_19_6_12_2_reg_6989;
ap_reg_pp0_iter3_tmp_19_6_1_2_reg_6934 <= tmp_19_6_1_2_reg_6934;
ap_reg_pp0_iter3_tmp_19_6_2_2_reg_6939 <= tmp_19_6_2_2_reg_6939;
ap_reg_pp0_iter3_tmp_19_6_3_2_reg_6944 <= tmp_19_6_3_2_reg_6944;
ap_reg_pp0_iter3_tmp_19_6_4_2_reg_6949 <= tmp_19_6_4_2_reg_6949;
ap_reg_pp0_iter3_tmp_19_6_5_2_reg_6954 <= tmp_19_6_5_2_reg_6954;
ap_reg_pp0_iter3_tmp_19_6_6_2_reg_6959 <= tmp_19_6_6_2_reg_6959;
ap_reg_pp0_iter3_tmp_19_6_7_2_reg_6964 <= tmp_19_6_7_2_reg_6964;
ap_reg_pp0_iter3_tmp_19_6_8_2_reg_6969 <= tmp_19_6_8_2_reg_6969;
ap_reg_pp0_iter3_tmp_19_6_9_2_reg_6974 <= tmp_19_6_9_2_reg_6974;
ap_reg_pp0_iter3_tmp_19_7_0_2_reg_6994 <= tmp_19_7_0_2_reg_6994;
ap_reg_pp0_iter3_tmp_19_7_10_2_reg_7044 <= tmp_19_7_10_2_reg_7044;
ap_reg_pp0_iter3_tmp_19_7_11_2_reg_7049 <= tmp_19_7_11_2_reg_7049;
ap_reg_pp0_iter3_tmp_19_7_12_2_reg_7054 <= tmp_19_7_12_2_reg_7054;
ap_reg_pp0_iter3_tmp_19_7_1_2_reg_6999 <= tmp_19_7_1_2_reg_6999;
ap_reg_pp0_iter3_tmp_19_7_2_2_reg_7004 <= tmp_19_7_2_2_reg_7004;
ap_reg_pp0_iter3_tmp_19_7_3_2_reg_7009 <= tmp_19_7_3_2_reg_7009;
ap_reg_pp0_iter3_tmp_19_7_4_2_reg_7014 <= tmp_19_7_4_2_reg_7014;
ap_reg_pp0_iter3_tmp_19_7_5_2_reg_7019 <= tmp_19_7_5_2_reg_7019;
ap_reg_pp0_iter3_tmp_19_7_6_2_reg_7024 <= tmp_19_7_6_2_reg_7024;
ap_reg_pp0_iter3_tmp_19_7_7_2_reg_7029 <= tmp_19_7_7_2_reg_7029;
ap_reg_pp0_iter3_tmp_19_7_8_2_reg_7034 <= tmp_19_7_8_2_reg_7034;
ap_reg_pp0_iter3_tmp_19_7_9_2_reg_7039 <= tmp_19_7_9_2_reg_7039;
ap_reg_pp0_iter4_tmp_19_5_0_2_reg_6864 <= ap_reg_pp0_iter3_tmp_19_5_0_2_reg_6864;
ap_reg_pp0_iter4_tmp_19_5_10_2_reg_6914 <= ap_reg_pp0_iter3_tmp_19_5_10_2_reg_6914;
ap_reg_pp0_iter4_tmp_19_5_11_2_reg_6919 <= ap_reg_pp0_iter3_tmp_19_5_11_2_reg_6919;
ap_reg_pp0_iter4_tmp_19_5_12_2_reg_6924 <= ap_reg_pp0_iter3_tmp_19_5_12_2_reg_6924;
ap_reg_pp0_iter4_tmp_19_5_1_2_reg_6869 <= ap_reg_pp0_iter3_tmp_19_5_1_2_reg_6869;
ap_reg_pp0_iter4_tmp_19_5_2_2_reg_6874 <= ap_reg_pp0_iter3_tmp_19_5_2_2_reg_6874;
ap_reg_pp0_iter4_tmp_19_5_3_2_reg_6879 <= ap_reg_pp0_iter3_tmp_19_5_3_2_reg_6879;
ap_reg_pp0_iter4_tmp_19_5_4_2_reg_6884 <= ap_reg_pp0_iter3_tmp_19_5_4_2_reg_6884;
ap_reg_pp0_iter4_tmp_19_5_5_2_reg_6889 <= ap_reg_pp0_iter3_tmp_19_5_5_2_reg_6889;
ap_reg_pp0_iter4_tmp_19_5_6_2_reg_6894 <= ap_reg_pp0_iter3_tmp_19_5_6_2_reg_6894;
ap_reg_pp0_iter4_tmp_19_5_7_2_reg_6899 <= ap_reg_pp0_iter3_tmp_19_5_7_2_reg_6899;
ap_reg_pp0_iter4_tmp_19_5_8_2_reg_6904 <= ap_reg_pp0_iter3_tmp_19_5_8_2_reg_6904;
ap_reg_pp0_iter4_tmp_19_5_9_2_reg_6909 <= ap_reg_pp0_iter3_tmp_19_5_9_2_reg_6909;
ap_reg_pp0_iter4_tmp_19_6_0_2_reg_6929 <= ap_reg_pp0_iter3_tmp_19_6_0_2_reg_6929;
ap_reg_pp0_iter4_tmp_19_6_10_2_reg_6979 <= ap_reg_pp0_iter3_tmp_19_6_10_2_reg_6979;
ap_reg_pp0_iter4_tmp_19_6_11_2_reg_6984 <= ap_reg_pp0_iter3_tmp_19_6_11_2_reg_6984;
ap_reg_pp0_iter4_tmp_19_6_12_2_reg_6989 <= ap_reg_pp0_iter3_tmp_19_6_12_2_reg_6989;
ap_reg_pp0_iter4_tmp_19_6_1_2_reg_6934 <= ap_reg_pp0_iter3_tmp_19_6_1_2_reg_6934;
ap_reg_pp0_iter4_tmp_19_6_2_2_reg_6939 <= ap_reg_pp0_iter3_tmp_19_6_2_2_reg_6939;
ap_reg_pp0_iter4_tmp_19_6_3_2_reg_6944 <= ap_reg_pp0_iter3_tmp_19_6_3_2_reg_6944;
ap_reg_pp0_iter4_tmp_19_6_4_2_reg_6949 <= ap_reg_pp0_iter3_tmp_19_6_4_2_reg_6949;
ap_reg_pp0_iter4_tmp_19_6_5_2_reg_6954 <= ap_reg_pp0_iter3_tmp_19_6_5_2_reg_6954;
ap_reg_pp0_iter4_tmp_19_6_6_2_reg_6959 <= ap_reg_pp0_iter3_tmp_19_6_6_2_reg_6959;
ap_reg_pp0_iter4_tmp_19_6_7_2_reg_6964 <= ap_reg_pp0_iter3_tmp_19_6_7_2_reg_6964;
ap_reg_pp0_iter4_tmp_19_6_8_2_reg_6969 <= ap_reg_pp0_iter3_tmp_19_6_8_2_reg_6969;
ap_reg_pp0_iter4_tmp_19_6_9_2_reg_6974 <= ap_reg_pp0_iter3_tmp_19_6_9_2_reg_6974;
ap_reg_pp0_iter4_tmp_19_7_0_2_reg_6994 <= ap_reg_pp0_iter3_tmp_19_7_0_2_reg_6994;
ap_reg_pp0_iter4_tmp_19_7_10_2_reg_7044 <= ap_reg_pp0_iter3_tmp_19_7_10_2_reg_7044;
ap_reg_pp0_iter4_tmp_19_7_11_2_reg_7049 <= ap_reg_pp0_iter3_tmp_19_7_11_2_reg_7049;
ap_reg_pp0_iter4_tmp_19_7_12_2_reg_7054 <= ap_reg_pp0_iter3_tmp_19_7_12_2_reg_7054;
ap_reg_pp0_iter4_tmp_19_7_1_2_reg_6999 <= ap_reg_pp0_iter3_tmp_19_7_1_2_reg_6999;
ap_reg_pp0_iter4_tmp_19_7_2_2_reg_7004 <= ap_reg_pp0_iter3_tmp_19_7_2_2_reg_7004;
ap_reg_pp0_iter4_tmp_19_7_3_2_reg_7009 <= ap_reg_pp0_iter3_tmp_19_7_3_2_reg_7009;
ap_reg_pp0_iter4_tmp_19_7_4_2_reg_7014 <= ap_reg_pp0_iter3_tmp_19_7_4_2_reg_7014;
ap_reg_pp0_iter4_tmp_19_7_5_2_reg_7019 <= ap_reg_pp0_iter3_tmp_19_7_5_2_reg_7019;
ap_reg_pp0_iter4_tmp_19_7_6_2_reg_7024 <= ap_reg_pp0_iter3_tmp_19_7_6_2_reg_7024;
ap_reg_pp0_iter4_tmp_19_7_7_2_reg_7029 <= ap_reg_pp0_iter3_tmp_19_7_7_2_reg_7029;
ap_reg_pp0_iter4_tmp_19_7_8_2_reg_7034 <= ap_reg_pp0_iter3_tmp_19_7_8_2_reg_7034;
ap_reg_pp0_iter4_tmp_19_7_9_2_reg_7039 <= ap_reg_pp0_iter3_tmp_19_7_9_2_reg_7039;
ap_reg_pp0_iter5_tmp_19_5_0_2_reg_6864 <= ap_reg_pp0_iter4_tmp_19_5_0_2_reg_6864;
ap_reg_pp0_iter5_tmp_19_5_10_2_reg_6914 <= ap_reg_pp0_iter4_tmp_19_5_10_2_reg_6914;
ap_reg_pp0_iter5_tmp_19_5_11_2_reg_6919 <= ap_reg_pp0_iter4_tmp_19_5_11_2_reg_6919;
ap_reg_pp0_iter5_tmp_19_5_12_2_reg_6924 <= ap_reg_pp0_iter4_tmp_19_5_12_2_reg_6924;
ap_reg_pp0_iter5_tmp_19_5_1_2_reg_6869 <= ap_reg_pp0_iter4_tmp_19_5_1_2_reg_6869;
ap_reg_pp0_iter5_tmp_19_5_2_2_reg_6874 <= ap_reg_pp0_iter4_tmp_19_5_2_2_reg_6874;
ap_reg_pp0_iter5_tmp_19_5_3_2_reg_6879 <= ap_reg_pp0_iter4_tmp_19_5_3_2_reg_6879;
ap_reg_pp0_iter5_tmp_19_5_4_2_reg_6884 <= ap_reg_pp0_iter4_tmp_19_5_4_2_reg_6884;
ap_reg_pp0_iter5_tmp_19_5_5_2_reg_6889 <= ap_reg_pp0_iter4_tmp_19_5_5_2_reg_6889;
ap_reg_pp0_iter5_tmp_19_5_6_2_reg_6894 <= ap_reg_pp0_iter4_tmp_19_5_6_2_reg_6894;
ap_reg_pp0_iter5_tmp_19_5_7_2_reg_6899 <= ap_reg_pp0_iter4_tmp_19_5_7_2_reg_6899;
ap_reg_pp0_iter5_tmp_19_5_8_2_reg_6904 <= ap_reg_pp0_iter4_tmp_19_5_8_2_reg_6904;
ap_reg_pp0_iter5_tmp_19_5_9_2_reg_6909 <= ap_reg_pp0_iter4_tmp_19_5_9_2_reg_6909;
ap_reg_pp0_iter5_tmp_19_6_0_2_reg_6929 <= ap_reg_pp0_iter4_tmp_19_6_0_2_reg_6929;
ap_reg_pp0_iter5_tmp_19_6_10_2_reg_6979 <= ap_reg_pp0_iter4_tmp_19_6_10_2_reg_6979;
ap_reg_pp0_iter5_tmp_19_6_11_2_reg_6984 <= ap_reg_pp0_iter4_tmp_19_6_11_2_reg_6984;
ap_reg_pp0_iter5_tmp_19_6_12_2_reg_6989 <= ap_reg_pp0_iter4_tmp_19_6_12_2_reg_6989;
ap_reg_pp0_iter5_tmp_19_6_1_2_reg_6934 <= ap_reg_pp0_iter4_tmp_19_6_1_2_reg_6934;
ap_reg_pp0_iter5_tmp_19_6_2_2_reg_6939 <= ap_reg_pp0_iter4_tmp_19_6_2_2_reg_6939;
ap_reg_pp0_iter5_tmp_19_6_3_2_reg_6944 <= ap_reg_pp0_iter4_tmp_19_6_3_2_reg_6944;
ap_reg_pp0_iter5_tmp_19_6_4_2_reg_6949 <= ap_reg_pp0_iter4_tmp_19_6_4_2_reg_6949;
ap_reg_pp0_iter5_tmp_19_6_5_2_reg_6954 <= ap_reg_pp0_iter4_tmp_19_6_5_2_reg_6954;
ap_reg_pp0_iter5_tmp_19_6_6_2_reg_6959 <= ap_reg_pp0_iter4_tmp_19_6_6_2_reg_6959;
ap_reg_pp0_iter5_tmp_19_6_7_2_reg_6964 <= ap_reg_pp0_iter4_tmp_19_6_7_2_reg_6964;
ap_reg_pp0_iter5_tmp_19_6_8_2_reg_6969 <= ap_reg_pp0_iter4_tmp_19_6_8_2_reg_6969;
ap_reg_pp0_iter5_tmp_19_6_9_2_reg_6974 <= ap_reg_pp0_iter4_tmp_19_6_9_2_reg_6974;
ap_reg_pp0_iter5_tmp_19_7_0_2_reg_6994 <= ap_reg_pp0_iter4_tmp_19_7_0_2_reg_6994;
ap_reg_pp0_iter5_tmp_19_7_10_2_reg_7044 <= ap_reg_pp0_iter4_tmp_19_7_10_2_reg_7044;
ap_reg_pp0_iter5_tmp_19_7_11_2_reg_7049 <= ap_reg_pp0_iter4_tmp_19_7_11_2_reg_7049;
ap_reg_pp0_iter5_tmp_19_7_12_2_reg_7054 <= ap_reg_pp0_iter4_tmp_19_7_12_2_reg_7054;
ap_reg_pp0_iter5_tmp_19_7_1_2_reg_6999 <= ap_reg_pp0_iter4_tmp_19_7_1_2_reg_6999;
ap_reg_pp0_iter5_tmp_19_7_2_2_reg_7004 <= ap_reg_pp0_iter4_tmp_19_7_2_2_reg_7004;
ap_reg_pp0_iter5_tmp_19_7_3_2_reg_7009 <= ap_reg_pp0_iter4_tmp_19_7_3_2_reg_7009;
ap_reg_pp0_iter5_tmp_19_7_4_2_reg_7014 <= ap_reg_pp0_iter4_tmp_19_7_4_2_reg_7014;
ap_reg_pp0_iter5_tmp_19_7_5_2_reg_7019 <= ap_reg_pp0_iter4_tmp_19_7_5_2_reg_7019;
ap_reg_pp0_iter5_tmp_19_7_6_2_reg_7024 <= ap_reg_pp0_iter4_tmp_19_7_6_2_reg_7024;
ap_reg_pp0_iter5_tmp_19_7_7_2_reg_7029 <= ap_reg_pp0_iter4_tmp_19_7_7_2_reg_7029;
ap_reg_pp0_iter5_tmp_19_7_8_2_reg_7034 <= ap_reg_pp0_iter4_tmp_19_7_8_2_reg_7034;
ap_reg_pp0_iter5_tmp_19_7_9_2_reg_7039 <= ap_reg_pp0_iter4_tmp_19_7_9_2_reg_7039;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_0_load_1_reg_3931 <= bufi_0_Dout_B;
bufi_0_load_reg_3693 <= bufi_0_Dout_A;
bufi_1_load_1_reg_3948 <= bufi_1_Dout_B;
bufi_1_load_reg_3718 <= bufi_1_Dout_A;
bufi_2_load_1_reg_3965 <= bufi_2_Dout_B;
bufi_2_load_reg_3735 <= bufi_2_Dout_A;
bufw_0_load_1_reg_3710 <= bufw_0_Dout_B;
bufw_0_load_reg_3686 <= bufw_0_Dout_A;
bufw_10_load_1_reg_3894 <= bufw_10_Dout_B;
bufw_10_load_reg_3887 <= bufw_10_Dout_A;
bufw_11_load_1_reg_3909 <= bufw_11_Dout_B;
bufw_11_load_reg_3902 <= bufw_11_Dout_A;
bufw_12_load_1_reg_3924 <= bufw_12_Dout_B;
bufw_12_load_reg_3917 <= bufw_12_Dout_A;
bufw_1_load_1_reg_3759 <= bufw_1_Dout_B;
bufw_1_load_reg_3752 <= bufw_1_Dout_A;
bufw_2_load_1_reg_3774 <= bufw_2_Dout_B;
bufw_2_load_reg_3767 <= bufw_2_Dout_A;
bufw_3_load_1_reg_3789 <= bufw_3_Dout_B;
bufw_3_load_reg_3782 <= bufw_3_Dout_A;
bufw_4_load_1_reg_3804 <= bufw_4_Dout_B;
bufw_4_load_reg_3797 <= bufw_4_Dout_A;
bufw_5_load_1_reg_3819 <= bufw_5_Dout_B;
bufw_5_load_reg_3812 <= bufw_5_Dout_A;
bufw_6_load_1_reg_3834 <= bufw_6_Dout_B;
bufw_6_load_reg_3827 <= bufw_6_Dout_A;
bufw_7_load_1_reg_3849 <= bufw_7_Dout_B;
bufw_7_load_reg_3842 <= bufw_7_Dout_A;
bufw_8_load_1_reg_3864 <= bufw_8_Dout_B;
bufw_8_load_reg_3857 <= bufw_8_Dout_A;
bufw_9_load_1_reg_3879 <= bufw_9_Dout_B;
bufw_9_load_reg_3872 <= bufw_9_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufi_0_load_2_reg_4103 <= bufi_0_Dout_A;
bufi_0_load_3_reg_4154 <= bufi_0_Dout_B;
bufi_1_load_2_reg_4120 <= bufi_1_Dout_A;
bufi_1_load_3_reg_4171 <= bufi_1_Dout_B;
bufi_2_load_2_reg_4137 <= bufi_2_Dout_A;
bufi_2_load_3_reg_4188 <= bufi_2_Dout_B;
bufw_0_load_2_reg_4012 <= bufw_0_Dout_A;
bufw_10_load_2_reg_4082 <= bufw_10_Dout_A;
bufw_11_load_2_reg_4089 <= bufw_11_Dout_A;
bufw_12_load_2_reg_4096 <= bufw_12_Dout_A;
bufw_1_load_2_reg_4019 <= bufw_1_Dout_A;
bufw_2_load_2_reg_4026 <= bufw_2_Dout_A;
bufw_3_load_2_reg_4033 <= bufw_3_Dout_A;
bufw_4_load_2_reg_4040 <= bufw_4_Dout_A;
bufw_5_load_2_reg_4047 <= bufw_5_Dout_A;
bufw_6_load_2_reg_4054 <= bufw_6_Dout_A;
bufw_7_load_2_reg_4061 <= bufw_7_Dout_A;
bufw_8_load_2_reg_4068 <= bufw_8_Dout_A;
bufw_9_load_2_reg_4075 <= bufw_9_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
bufi_0_load_4_reg_4205 <= bufi_0_Dout_A;
bufi_0_load_5_reg_4256 <= bufi_0_Dout_B;
bufi_1_load_4_reg_4222 <= bufi_1_Dout_A;
bufi_1_load_5_reg_4273 <= bufi_1_Dout_B;
bufi_2_load_4_reg_4239 <= bufi_2_Dout_A;
bufi_2_load_5_reg_4290 <= bufi_2_Dout_B;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
bufi_0_load_6_reg_4327 <= bufi_0_Dout_A;
bufi_0_load_7_reg_4378 <= bufi_0_Dout_B;
bufi_1_load_6_reg_4344 <= bufi_1_Dout_A;
bufi_1_load_7_reg_4395 <= bufi_1_Dout_B;
bufi_2_load_6_reg_4361 <= bufi_2_Dout_A;
bufi_2_load_7_reg_4412 <= bufi_2_Dout_B;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
bufo_addr_1_reg_4322(7 downto 3) <= tmp_336_fu_2040_p3(8 - 1 downto 0)(7 downto 3);
bufo_addr_reg_4317(7 downto 3) <= tmp_334_fu_2029_p1(8 - 1 downto 0)(7 downto 3);
tmp_333_reg_4307(7 downto 3) <= tmp_333_fu_2022_p3(7 downto 3);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
bufo_addr_2_reg_4429(7 downto 3) <= tmp_338_fu_2054_p3(8 - 1 downto 0)(7 downto 3);
bufo_addr_3_reg_4434(7 downto 3) <= tmp_340_fu_2068_p3(8 - 1 downto 0)(7 downto 3);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
bufo_addr_4_reg_4439(7 downto 3) <= tmp_342_fu_2082_p3(8 - 1 downto 0)(7 downto 3);
bufo_addr_5_reg_4444(7 downto 3) <= tmp_344_fu_2096_p3(8 - 1 downto 0)(7 downto 3);
tmp_350_reg_4449 <= tmp_350_fu_2105_p1;
tmp_352_reg_4514 <= tmp_352_fu_2109_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufo_addr_6_reg_4579(7 downto 3) <= tmp_346_fu_2118_p3(8 - 1 downto 0)(7 downto 3);
bufo_addr_7_reg_4584(7 downto 3) <= tmp_348_fu_2132_p3(8 - 1 downto 0)(7 downto 3);
tmp_353_reg_4589 <= tmp_353_fu_2141_p1;
tmp_354_reg_4654 <= tmp_354_fu_2145_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten1_fu_1541_p2 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
exitcond_flatten_reg_3190 <= exitcond_flatten_fu_1559_p2;
i_1_reg_3185 <= i_1_fu_1553_p2;
indvar_flatten_op_reg_3211 <= indvar_flatten_op_fu_1571_p2;
tmp_5_reg_3206 <= tmp_5_fu_1565_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
indvar_flatten_next1_reg_3180 <= indvar_flatten_next1_fu_1547_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
indvar_flatten_next_reg_3252 <= indvar_flatten_next_fu_1613_p3;
tmp_1_mid2_v_reg_3225 <= tmp_1_mid2_v_fu_1584_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
j_1_reg_3264 <= j_1_fu_1642_p2;
tmp_1_reg_3257 <= tmp_1_fu_1633_p2;
tmp_s_reg_3270 <= tmp_s_fu_1647_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
j_mid_reg_3216 <= j_mid_fu_1577_p3;
row_b_mid2_reg_3245 <= row_b_mid2_fu_1605_p3;
tmp_7_mid_reg_3233 <= tmp_7_mid_fu_1595_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
row_b_1_reg_3276 <= row_b_1_fu_1652_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
tmp_102_reg_4609 <= grp_fu_1285_p1(159 downto 128);
tmp_105_reg_4614 <= grp_fu_1295_p1(191 downto 160);
tmp_108_reg_4619 <= grp_fu_1305_p1(223 downto 192);
tmp_111_reg_4624 <= grp_fu_1315_p1(255 downto 224);
tmp_114_reg_4629 <= grp_fu_1325_p1(287 downto 256);
tmp_117_reg_4634 <= grp_fu_1335_p1(319 downto 288);
tmp_120_reg_4639 <= grp_fu_1345_p1(351 downto 320);
tmp_123_reg_4644 <= grp_fu_1355_p1(383 downto 352);
tmp_126_reg_4649 <= grp_fu_1365_p1(415 downto 384);
tmp_133_reg_4659 <= grp_fu_1375_p1(63 downto 32);
tmp_136_reg_4664 <= grp_fu_1385_p1(95 downto 64);
tmp_139_reg_4669 <= grp_fu_1395_p1(127 downto 96);
tmp_142_reg_4674 <= grp_fu_1405_p1(159 downto 128);
tmp_145_reg_4679 <= grp_fu_1415_p1(191 downto 160);
tmp_148_reg_4684 <= grp_fu_1425_p1(223 downto 192);
tmp_151_reg_4689 <= grp_fu_1435_p1(255 downto 224);
tmp_154_reg_4694 <= grp_fu_1445_p1(287 downto 256);
tmp_157_reg_4699 <= grp_fu_1455_p1(319 downto 288);
tmp_160_reg_4704 <= grp_fu_1465_p1(351 downto 320);
tmp_163_reg_4709 <= grp_fu_1475_p1(383 downto 352);
tmp_166_reg_4714 <= grp_fu_1485_p1(415 downto 384);
tmp_93_reg_4594 <= grp_fu_1255_p1(63 downto 32);
tmp_96_reg_4599 <= grp_fu_1265_p1(95 downto 64);
tmp_99_reg_4604 <= grp_fu_1275_p1(127 downto 96);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (tmp_7_mid_reg_3233 = ap_const_lv1_1) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
tmp_12_1_mid1_reg_3294 <= tmp_12_1_mid1_fu_1667_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (tmp_7_mid_reg_3233 = ap_const_lv1_1) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
tmp_12_2_mid1_reg_3331 <= tmp_12_2_mid1_fu_1748_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (tmp_7_mid_reg_3233 = ap_const_lv1_1) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
tmp_12_4_mid1_reg_3481 <= tmp_12_4_mid1_fu_1840_p2;
tmp_12_5_mid1_reg_3486 <= tmp_12_5_mid1_fu_1846_p2;
tmp_12_6_mid1_reg_3491 <= tmp_12_6_mid1_fu_1852_p2;
tmp_12_7_mid1_reg_3496 <= tmp_12_7_mid1_fu_1858_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
tmp_130_reg_3336 <= tmp_130_fu_1753_p2;
tmp_170_reg_3341 <= tmp_170_fu_1758_p2;
tmp_3_reg_3311 <= tmp_3_fu_1706_p2;
tmp_5_mid2_cast2_reg_3316(2 downto 0) <= tmp_5_mid2_cast2_fu_1721_p1(2 downto 0);
tmp_6_reg_3321 <= tmp_6_fu_1727_p2;
tmp_8_reg_3326 <= tmp_8_fu_1732_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
tmp_13_reg_4454 <= grp_fu_1255_p1(63 downto 32);
tmp_16_reg_4459 <= grp_fu_1265_p1(95 downto 64);
tmp_19_reg_4464 <= grp_fu_1275_p1(127 downto 96);
tmp_22_reg_4469 <= grp_fu_1285_p1(159 downto 128);
tmp_25_reg_4474 <= grp_fu_1295_p1(191 downto 160);
tmp_28_reg_4479 <= grp_fu_1305_p1(223 downto 192);
tmp_31_reg_4484 <= grp_fu_1315_p1(255 downto 224);
tmp_34_reg_4489 <= grp_fu_1325_p1(287 downto 256);
tmp_37_reg_4494 <= grp_fu_1335_p1(319 downto 288);
tmp_40_reg_4499 <= grp_fu_1345_p1(351 downto 320);
tmp_43_reg_4504 <= grp_fu_1355_p1(383 downto 352);
tmp_46_reg_4509 <= grp_fu_1365_p1(415 downto 384);
tmp_53_reg_4519 <= grp_fu_1375_p1(63 downto 32);
tmp_56_reg_4524 <= grp_fu_1385_p1(95 downto 64);
tmp_59_reg_4529 <= grp_fu_1395_p1(127 downto 96);
tmp_62_reg_4534 <= grp_fu_1405_p1(159 downto 128);
tmp_65_reg_4539 <= grp_fu_1415_p1(191 downto 160);
tmp_68_reg_4544 <= grp_fu_1425_p1(223 downto 192);
tmp_71_reg_4549 <= grp_fu_1435_p1(255 downto 224);
tmp_74_reg_4554 <= grp_fu_1445_p1(287 downto 256);
tmp_77_reg_4559 <= grp_fu_1455_p1(319 downto 288);
tmp_80_reg_4564 <= grp_fu_1465_p1(351 downto 320);
tmp_83_reg_4569 <= grp_fu_1475_p1(383 downto 352);
tmp_86_reg_4574 <= grp_fu_1485_p1(415 downto 384);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
tmp_173_reg_4724 <= grp_fu_1255_p1(63 downto 32);
tmp_176_reg_4729 <= grp_fu_1265_p1(95 downto 64);
tmp_179_reg_4734 <= grp_fu_1275_p1(127 downto 96);
tmp_182_reg_4739 <= grp_fu_1285_p1(159 downto 128);
tmp_185_reg_4744 <= grp_fu_1295_p1(191 downto 160);
tmp_188_reg_4749 <= grp_fu_1305_p1(223 downto 192);
tmp_191_reg_4754 <= grp_fu_1315_p1(255 downto 224);
tmp_194_reg_4759 <= grp_fu_1325_p1(287 downto 256);
tmp_197_reg_4764 <= grp_fu_1335_p1(319 downto 288);
tmp_200_reg_4769 <= grp_fu_1345_p1(351 downto 320);
tmp_203_reg_4774 <= grp_fu_1355_p1(383 downto 352);
tmp_206_reg_4779 <= grp_fu_1365_p1(415 downto 384);
tmp_213_reg_4789 <= grp_fu_1375_p1(63 downto 32);
tmp_216_reg_4794 <= grp_fu_1385_p1(95 downto 64);
tmp_219_reg_4799 <= grp_fu_1395_p1(127 downto 96);
tmp_222_reg_4804 <= grp_fu_1405_p1(159 downto 128);
tmp_225_reg_4809 <= grp_fu_1415_p1(191 downto 160);
tmp_228_reg_4814 <= grp_fu_1425_p1(223 downto 192);
tmp_231_reg_4819 <= grp_fu_1435_p1(255 downto 224);
tmp_234_reg_4824 <= grp_fu_1445_p1(287 downto 256);
tmp_237_reg_4829 <= grp_fu_1455_p1(319 downto 288);
tmp_240_reg_4834 <= grp_fu_1465_p1(351 downto 320);
tmp_243_reg_4839 <= grp_fu_1475_p1(383 downto 352);
tmp_246_reg_4844 <= grp_fu_1485_p1(415 downto 384);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
tmp_19_0_0_1_reg_4854 <= grp_fu_1103_p2;
tmp_19_0_10_1_reg_4954 <= grp_fu_1183_p2;
tmp_19_0_10_reg_4959 <= grp_fu_1187_p2;
tmp_19_0_11_1_reg_4964 <= grp_fu_1191_p2;
tmp_19_0_11_reg_4969 <= grp_fu_1195_p2;
tmp_19_0_12_1_reg_4974 <= grp_fu_1199_p2;
tmp_19_0_1_1_reg_4864 <= grp_fu_1111_p2;
tmp_19_0_1_reg_4859 <= grp_fu_1107_p2;
tmp_19_0_2_1_reg_4874 <= grp_fu_1119_p2;
tmp_19_0_2_reg_4869 <= grp_fu_1115_p2;
tmp_19_0_3_1_reg_4884 <= grp_fu_1127_p2;
tmp_19_0_3_reg_4879 <= grp_fu_1123_p2;
tmp_19_0_4_1_reg_4894 <= grp_fu_1135_p2;
tmp_19_0_4_reg_4889 <= grp_fu_1131_p2;
tmp_19_0_5_1_reg_4904 <= grp_fu_1143_p2;
tmp_19_0_5_reg_4899 <= grp_fu_1139_p2;
tmp_19_0_6_1_reg_4914 <= grp_fu_1151_p2;
tmp_19_0_6_reg_4909 <= grp_fu_1147_p2;
tmp_19_0_7_1_reg_4924 <= grp_fu_1159_p2;
tmp_19_0_7_reg_4919 <= grp_fu_1155_p2;
tmp_19_0_8_1_reg_4934 <= grp_fu_1167_p2;
tmp_19_0_8_reg_4929 <= grp_fu_1163_p2;
tmp_19_0_9_1_reg_4944 <= grp_fu_1175_p2;
tmp_19_0_9_reg_4939 <= grp_fu_1171_p2;
tmp_19_0_s_reg_4949 <= grp_fu_1179_p2;
tmp_19_1_10_reg_5034 <= grp_fu_1247_p2;
tmp_19_1_11_reg_5039 <= grp_fu_1251_p2;
tmp_19_1_1_reg_4984 <= grp_fu_1207_p2;
tmp_19_1_2_reg_4989 <= grp_fu_1211_p2;
tmp_19_1_3_reg_4994 <= grp_fu_1215_p2;
tmp_19_1_4_reg_4999 <= grp_fu_1219_p2;
tmp_19_1_5_reg_5004 <= grp_fu_1223_p2;
tmp_19_1_6_reg_5009 <= grp_fu_1227_p2;
tmp_19_1_7_reg_5014 <= grp_fu_1231_p2;
tmp_19_1_8_reg_5019 <= grp_fu_1235_p2;
tmp_19_1_9_reg_5024 <= grp_fu_1239_p2;
tmp_19_1_reg_4979 <= grp_fu_1203_p2;
tmp_19_1_s_reg_5029 <= grp_fu_1243_p2;
tmp_253_reg_5049 <= grp_fu_1255_p1(63 downto 32);
tmp_256_reg_5054 <= grp_fu_1265_p1(95 downto 64);
tmp_259_reg_5059 <= grp_fu_1275_p1(127 downto 96);
tmp_262_reg_5064 <= grp_fu_1285_p1(159 downto 128);
tmp_265_reg_5069 <= grp_fu_1295_p1(191 downto 160);
tmp_268_reg_5074 <= grp_fu_1305_p1(223 downto 192);
tmp_271_reg_5079 <= grp_fu_1315_p1(255 downto 224);
tmp_274_reg_5084 <= grp_fu_1325_p1(287 downto 256);
tmp_277_reg_5089 <= grp_fu_1335_p1(319 downto 288);
tmp_280_reg_5094 <= grp_fu_1345_p1(351 downto 320);
tmp_283_reg_5099 <= grp_fu_1355_p1(383 downto 352);
tmp_286_reg_5104 <= grp_fu_1365_p1(415 downto 384);
tmp_293_reg_5114 <= grp_fu_1375_p1(63 downto 32);
tmp_296_reg_5119 <= grp_fu_1385_p1(95 downto 64);
tmp_299_reg_5124 <= grp_fu_1395_p1(127 downto 96);
tmp_302_reg_5129 <= grp_fu_1405_p1(159 downto 128);
tmp_305_reg_5134 <= grp_fu_1415_p1(191 downto 160);
tmp_308_reg_5139 <= grp_fu_1425_p1(223 downto 192);
tmp_311_reg_5144 <= grp_fu_1435_p1(255 downto 224);
tmp_314_reg_5149 <= grp_fu_1445_p1(287 downto 256);
tmp_317_reg_5154 <= grp_fu_1455_p1(319 downto 288);
tmp_320_reg_5159 <= grp_fu_1465_p1(351 downto 320);
tmp_323_reg_5164 <= grp_fu_1475_p1(383 downto 352);
tmp_326_reg_5169 <= grp_fu_1485_p1(415 downto 384);
tmp_349_reg_4849 <= grp_fu_1099_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
tmp_19_0_0_2_reg_6474 <= grp_fu_1099_p2;
tmp_19_0_10_2_reg_6524 <= grp_fu_1139_p2;
tmp_19_0_11_2_reg_6529 <= grp_fu_1143_p2;
tmp_19_0_12_2_reg_6534 <= grp_fu_1147_p2;
tmp_19_0_1_2_reg_6479 <= grp_fu_1103_p2;
tmp_19_0_2_2_reg_6484 <= grp_fu_1107_p2;
tmp_19_0_3_2_reg_6489 <= grp_fu_1111_p2;
tmp_19_0_4_2_reg_6494 <= grp_fu_1115_p2;
tmp_19_0_5_2_reg_6499 <= grp_fu_1119_p2;
tmp_19_0_6_2_reg_6504 <= grp_fu_1123_p2;
tmp_19_0_7_2_reg_6509 <= grp_fu_1127_p2;
tmp_19_0_8_2_reg_6514 <= grp_fu_1131_p2;
tmp_19_0_9_2_reg_6519 <= grp_fu_1135_p2;
tmp_19_1_0_2_reg_6539 <= grp_fu_1151_p2;
tmp_19_1_10_2_reg_6589 <= grp_fu_1191_p2;
tmp_19_1_11_2_reg_6594 <= grp_fu_1195_p2;
tmp_19_1_12_2_reg_6599 <= grp_fu_1199_p2;
tmp_19_1_1_2_reg_6544 <= grp_fu_1155_p2;
tmp_19_1_2_2_reg_6549 <= grp_fu_1159_p2;
tmp_19_1_3_2_reg_6554 <= grp_fu_1163_p2;
tmp_19_1_4_2_reg_6559 <= grp_fu_1167_p2;
tmp_19_1_5_2_reg_6564 <= grp_fu_1171_p2;
tmp_19_1_6_2_reg_6569 <= grp_fu_1175_p2;
tmp_19_1_7_2_reg_6574 <= grp_fu_1179_p2;
tmp_19_1_8_2_reg_6579 <= grp_fu_1183_p2;
tmp_19_1_9_2_reg_6584 <= grp_fu_1187_p2;
tmp_19_7_0_1_reg_6604 <= grp_fu_1203_p2;
tmp_19_7_10_1_reg_6654 <= grp_fu_1243_p2;
tmp_19_7_11_1_reg_6659 <= grp_fu_1247_p2;
tmp_19_7_12_1_reg_6664 <= grp_fu_1251_p2;
tmp_19_7_1_1_reg_6609 <= grp_fu_1207_p2;
tmp_19_7_2_1_reg_6614 <= grp_fu_1211_p2;
tmp_19_7_3_1_reg_6619 <= grp_fu_1215_p2;
tmp_19_7_4_1_reg_6624 <= grp_fu_1219_p2;
tmp_19_7_5_1_reg_6629 <= grp_fu_1223_p2;
tmp_19_7_6_1_reg_6634 <= grp_fu_1227_p2;
tmp_19_7_7_1_reg_6639 <= grp_fu_1231_p2;
tmp_19_7_8_1_reg_6644 <= grp_fu_1235_p2;
tmp_19_7_9_1_reg_6649 <= grp_fu_1239_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
tmp_19_1_0_1_reg_5244 <= grp_fu_1099_p2;
tmp_19_1_10_1_reg_5344 <= grp_fu_1139_p2;
tmp_19_1_11_1_reg_5354 <= grp_fu_1143_p2;
tmp_19_1_12_1_reg_5364 <= grp_fu_1147_p2;
tmp_19_1_1_1_reg_5254 <= grp_fu_1103_p2;
tmp_19_1_2_1_reg_5264 <= grp_fu_1107_p2;
tmp_19_1_3_1_reg_5274 <= grp_fu_1111_p2;
tmp_19_1_4_1_reg_5284 <= grp_fu_1115_p2;
tmp_19_1_5_1_reg_5294 <= grp_fu_1119_p2;
tmp_19_1_6_1_reg_5304 <= grp_fu_1123_p2;
tmp_19_1_7_1_reg_5314 <= grp_fu_1127_p2;
tmp_19_1_8_1_reg_5324 <= grp_fu_1131_p2;
tmp_19_1_9_1_reg_5334 <= grp_fu_1135_p2;
tmp_19_2_10_reg_5424 <= grp_fu_1195_p2;
tmp_19_2_11_reg_5429 <= grp_fu_1199_p2;
tmp_19_2_1_reg_5374 <= grp_fu_1155_p2;
tmp_19_2_2_reg_5379 <= grp_fu_1159_p2;
tmp_19_2_3_reg_5384 <= grp_fu_1163_p2;
tmp_19_2_4_reg_5389 <= grp_fu_1167_p2;
tmp_19_2_5_reg_5394 <= grp_fu_1171_p2;
tmp_19_2_6_reg_5399 <= grp_fu_1175_p2;
tmp_19_2_7_reg_5404 <= grp_fu_1179_p2;
tmp_19_2_8_reg_5409 <= grp_fu_1183_p2;
tmp_19_2_9_reg_5414 <= grp_fu_1187_p2;
tmp_19_2_reg_5369 <= grp_fu_1151_p2;
tmp_19_2_s_reg_5419 <= grp_fu_1191_p2;
tmp_19_3_10_reg_5489 <= grp_fu_1247_p2;
tmp_19_3_11_reg_5494 <= grp_fu_1251_p2;
tmp_19_3_1_reg_5439 <= grp_fu_1207_p2;
tmp_19_3_2_reg_5444 <= grp_fu_1211_p2;
tmp_19_3_3_reg_5449 <= grp_fu_1215_p2;
tmp_19_3_4_reg_5454 <= grp_fu_1219_p2;
tmp_19_3_5_reg_5459 <= grp_fu_1223_p2;
tmp_19_3_6_reg_5464 <= grp_fu_1227_p2;
tmp_19_3_7_reg_5469 <= grp_fu_1231_p2;
tmp_19_3_8_reg_5474 <= grp_fu_1235_p2;
tmp_19_3_9_reg_5479 <= grp_fu_1239_p2;
tmp_19_3_reg_5434 <= grp_fu_1203_p2;
tmp_19_3_s_reg_5484 <= grp_fu_1243_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
tmp_19_2_0_1_reg_5504 <= grp_fu_1099_p2;
tmp_19_2_10_1_reg_5604 <= grp_fu_1139_p2;
tmp_19_2_11_1_reg_5614 <= grp_fu_1143_p2;
tmp_19_2_12_1_reg_5624 <= grp_fu_1147_p2;
tmp_19_2_1_1_reg_5514 <= grp_fu_1103_p2;
tmp_19_2_2_1_reg_5524 <= grp_fu_1107_p2;
tmp_19_2_3_1_reg_5534 <= grp_fu_1111_p2;
tmp_19_2_4_1_reg_5544 <= grp_fu_1115_p2;
tmp_19_2_5_1_reg_5554 <= grp_fu_1119_p2;
tmp_19_2_6_1_reg_5564 <= grp_fu_1123_p2;
tmp_19_2_7_1_reg_5574 <= grp_fu_1127_p2;
tmp_19_2_8_1_reg_5584 <= grp_fu_1131_p2;
tmp_19_2_9_1_reg_5594 <= grp_fu_1135_p2;
tmp_19_4_10_reg_5749 <= grp_fu_1195_p2;
tmp_19_4_11_reg_5754 <= grp_fu_1199_p2;
tmp_19_4_1_reg_5699 <= grp_fu_1155_p2;
tmp_19_4_2_reg_5704 <= grp_fu_1159_p2;
tmp_19_4_3_reg_5709 <= grp_fu_1163_p2;
tmp_19_4_4_reg_5714 <= grp_fu_1167_p2;
tmp_19_4_5_reg_5719 <= grp_fu_1171_p2;
tmp_19_4_6_reg_5724 <= grp_fu_1175_p2;
tmp_19_4_7_reg_5729 <= grp_fu_1179_p2;
tmp_19_4_8_reg_5734 <= grp_fu_1183_p2;
tmp_19_4_9_reg_5739 <= grp_fu_1187_p2;
tmp_19_4_reg_5694 <= grp_fu_1151_p2;
tmp_19_4_s_reg_5744 <= grp_fu_1191_p2;
tmp_19_5_10_reg_5814 <= grp_fu_1247_p2;
tmp_19_5_11_reg_5819 <= grp_fu_1251_p2;
tmp_19_5_1_reg_5764 <= grp_fu_1207_p2;
tmp_19_5_2_reg_5769 <= grp_fu_1211_p2;
tmp_19_5_3_reg_5774 <= grp_fu_1215_p2;
tmp_19_5_4_reg_5779 <= grp_fu_1219_p2;
tmp_19_5_5_reg_5784 <= grp_fu_1223_p2;
tmp_19_5_6_reg_5789 <= grp_fu_1227_p2;
tmp_19_5_7_reg_5794 <= grp_fu_1231_p2;
tmp_19_5_8_reg_5799 <= grp_fu_1235_p2;
tmp_19_5_9_reg_5804 <= grp_fu_1239_p2;
tmp_19_5_reg_5759 <= grp_fu_1203_p2;
tmp_19_5_s_reg_5809 <= grp_fu_1243_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
tmp_19_2_0_2_reg_6669 <= grp_fu_1099_p2;
tmp_19_2_10_2_reg_6719 <= grp_fu_1139_p2;
tmp_19_2_11_2_reg_6724 <= grp_fu_1143_p2;
tmp_19_2_12_2_reg_6729 <= grp_fu_1147_p2;
tmp_19_2_1_2_reg_6674 <= grp_fu_1103_p2;
tmp_19_2_2_2_reg_6679 <= grp_fu_1107_p2;
tmp_19_2_3_2_reg_6684 <= grp_fu_1111_p2;
tmp_19_2_4_2_reg_6689 <= grp_fu_1115_p2;
tmp_19_2_5_2_reg_6694 <= grp_fu_1119_p2;
tmp_19_2_6_2_reg_6699 <= grp_fu_1123_p2;
tmp_19_2_7_2_reg_6704 <= grp_fu_1127_p2;
tmp_19_2_8_2_reg_6709 <= grp_fu_1131_p2;
tmp_19_2_9_2_reg_6714 <= grp_fu_1135_p2;
tmp_19_3_0_2_reg_6734 <= grp_fu_1151_p2;
tmp_19_3_10_2_reg_6784 <= grp_fu_1191_p2;
tmp_19_3_11_2_reg_6789 <= grp_fu_1195_p2;
tmp_19_3_12_2_reg_6794 <= grp_fu_1199_p2;
tmp_19_3_1_2_reg_6739 <= grp_fu_1155_p2;
tmp_19_3_2_2_reg_6744 <= grp_fu_1159_p2;
tmp_19_3_3_2_reg_6749 <= grp_fu_1163_p2;
tmp_19_3_4_2_reg_6754 <= grp_fu_1167_p2;
tmp_19_3_5_2_reg_6759 <= grp_fu_1171_p2;
tmp_19_3_6_2_reg_6764 <= grp_fu_1175_p2;
tmp_19_3_7_2_reg_6769 <= grp_fu_1179_p2;
tmp_19_3_8_2_reg_6774 <= grp_fu_1183_p2;
tmp_19_3_9_2_reg_6779 <= grp_fu_1187_p2;
tmp_19_4_0_2_reg_6799 <= grp_fu_1203_p2;
tmp_19_4_10_2_reg_6849 <= grp_fu_1243_p2;
tmp_19_4_11_2_reg_6854 <= grp_fu_1247_p2;
tmp_19_4_12_2_reg_6859 <= grp_fu_1251_p2;
tmp_19_4_1_2_reg_6804 <= grp_fu_1207_p2;
tmp_19_4_2_2_reg_6809 <= grp_fu_1211_p2;
tmp_19_4_3_2_reg_6814 <= grp_fu_1215_p2;
tmp_19_4_4_2_reg_6819 <= grp_fu_1219_p2;
tmp_19_4_5_2_reg_6824 <= grp_fu_1223_p2;
tmp_19_4_6_2_reg_6829 <= grp_fu_1227_p2;
tmp_19_4_7_2_reg_6834 <= grp_fu_1231_p2;
tmp_19_4_8_2_reg_6839 <= grp_fu_1235_p2;
tmp_19_4_9_2_reg_6844 <= grp_fu_1239_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
tmp_19_3_0_1_reg_5824 <= grp_fu_1099_p2;
tmp_19_3_10_1_reg_5874 <= grp_fu_1139_p2;
tmp_19_3_11_1_reg_5879 <= grp_fu_1143_p2;
tmp_19_3_12_1_reg_5884 <= grp_fu_1147_p2;
tmp_19_3_1_1_reg_5829 <= grp_fu_1103_p2;
tmp_19_3_2_1_reg_5834 <= grp_fu_1107_p2;
tmp_19_3_3_1_reg_5839 <= grp_fu_1111_p2;
tmp_19_3_4_1_reg_5844 <= grp_fu_1115_p2;
tmp_19_3_5_1_reg_5849 <= grp_fu_1119_p2;
tmp_19_3_6_1_reg_5854 <= grp_fu_1123_p2;
tmp_19_3_7_1_reg_5859 <= grp_fu_1127_p2;
tmp_19_3_8_1_reg_5864 <= grp_fu_1131_p2;
tmp_19_3_9_1_reg_5869 <= grp_fu_1135_p2;
tmp_19_6_10_reg_6074 <= grp_fu_1195_p2;
tmp_19_6_11_reg_6079 <= grp_fu_1199_p2;
tmp_19_6_1_reg_6024 <= grp_fu_1155_p2;
tmp_19_6_2_reg_6029 <= grp_fu_1159_p2;
tmp_19_6_3_reg_6034 <= grp_fu_1163_p2;
tmp_19_6_4_reg_6039 <= grp_fu_1167_p2;
tmp_19_6_5_reg_6044 <= grp_fu_1171_p2;
tmp_19_6_6_reg_6049 <= grp_fu_1175_p2;
tmp_19_6_7_reg_6054 <= grp_fu_1179_p2;
tmp_19_6_8_reg_6059 <= grp_fu_1183_p2;
tmp_19_6_9_reg_6064 <= grp_fu_1187_p2;
tmp_19_6_reg_6019 <= grp_fu_1151_p2;
tmp_19_6_s_reg_6069 <= grp_fu_1191_p2;
tmp_19_7_10_reg_6139 <= grp_fu_1247_p2;
tmp_19_7_11_reg_6144 <= grp_fu_1251_p2;
tmp_19_7_1_reg_6089 <= grp_fu_1207_p2;
tmp_19_7_2_reg_6094 <= grp_fu_1211_p2;
tmp_19_7_3_reg_6099 <= grp_fu_1215_p2;
tmp_19_7_4_reg_6104 <= grp_fu_1219_p2;
tmp_19_7_5_reg_6109 <= grp_fu_1223_p2;
tmp_19_7_6_reg_6114 <= grp_fu_1227_p2;
tmp_19_7_7_reg_6119 <= grp_fu_1231_p2;
tmp_19_7_8_reg_6124 <= grp_fu_1235_p2;
tmp_19_7_9_reg_6129 <= grp_fu_1239_p2;
tmp_19_7_reg_6084 <= grp_fu_1203_p2;
tmp_19_7_s_reg_6134 <= grp_fu_1243_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
tmp_19_4_0_1_reg_6149 <= grp_fu_1099_p2;
tmp_19_4_10_1_reg_6199 <= grp_fu_1139_p2;
tmp_19_4_11_1_reg_6204 <= grp_fu_1143_p2;
tmp_19_4_12_1_reg_6209 <= grp_fu_1147_p2;
tmp_19_4_1_1_reg_6154 <= grp_fu_1103_p2;
tmp_19_4_2_1_reg_6159 <= grp_fu_1107_p2;
tmp_19_4_3_1_reg_6164 <= grp_fu_1111_p2;
tmp_19_4_4_1_reg_6169 <= grp_fu_1115_p2;
tmp_19_4_5_1_reg_6174 <= grp_fu_1119_p2;
tmp_19_4_6_1_reg_6179 <= grp_fu_1123_p2;
tmp_19_4_7_1_reg_6184 <= grp_fu_1127_p2;
tmp_19_4_8_1_reg_6189 <= grp_fu_1131_p2;
tmp_19_4_9_1_reg_6194 <= grp_fu_1135_p2;
tmp_19_5_0_1_reg_6214 <= grp_fu_1151_p2;
tmp_19_5_10_1_reg_6264 <= grp_fu_1191_p2;
tmp_19_5_11_1_reg_6269 <= grp_fu_1195_p2;
tmp_19_5_12_1_reg_6274 <= grp_fu_1199_p2;
tmp_19_5_1_1_reg_6219 <= grp_fu_1155_p2;
tmp_19_5_2_1_reg_6224 <= grp_fu_1159_p2;
tmp_19_5_3_1_reg_6229 <= grp_fu_1163_p2;
tmp_19_5_4_1_reg_6234 <= grp_fu_1167_p2;
tmp_19_5_5_1_reg_6239 <= grp_fu_1171_p2;
tmp_19_5_6_1_reg_6244 <= grp_fu_1175_p2;
tmp_19_5_7_1_reg_6249 <= grp_fu_1179_p2;
tmp_19_5_8_1_reg_6254 <= grp_fu_1183_p2;
tmp_19_5_9_1_reg_6259 <= grp_fu_1187_p2;
tmp_19_6_0_1_reg_6284 <= grp_fu_1203_p2;
tmp_19_6_10_1_reg_6384 <= grp_fu_1243_p2;
tmp_19_6_11_1_reg_6394 <= grp_fu_1247_p2;
tmp_19_6_12_1_reg_6404 <= grp_fu_1251_p2;
tmp_19_6_1_1_reg_6294 <= grp_fu_1207_p2;
tmp_19_6_2_1_reg_6304 <= grp_fu_1211_p2;
tmp_19_6_3_1_reg_6314 <= grp_fu_1215_p2;
tmp_19_6_4_1_reg_6324 <= grp_fu_1219_p2;
tmp_19_6_5_1_reg_6334 <= grp_fu_1223_p2;
tmp_19_6_6_1_reg_6344 <= grp_fu_1227_p2;
tmp_19_6_7_1_reg_6354 <= grp_fu_1231_p2;
tmp_19_6_8_1_reg_6364 <= grp_fu_1235_p2;
tmp_19_6_9_1_reg_6374 <= grp_fu_1239_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
tmp_19_5_0_2_reg_6864 <= grp_fu_1099_p2;
tmp_19_5_10_2_reg_6914 <= grp_fu_1139_p2;
tmp_19_5_11_2_reg_6919 <= grp_fu_1143_p2;
tmp_19_5_12_2_reg_6924 <= grp_fu_1147_p2;
tmp_19_5_1_2_reg_6869 <= grp_fu_1103_p2;
tmp_19_5_2_2_reg_6874 <= grp_fu_1107_p2;
tmp_19_5_3_2_reg_6879 <= grp_fu_1111_p2;
tmp_19_5_4_2_reg_6884 <= grp_fu_1115_p2;
tmp_19_5_5_2_reg_6889 <= grp_fu_1119_p2;
tmp_19_5_6_2_reg_6894 <= grp_fu_1123_p2;
tmp_19_5_7_2_reg_6899 <= grp_fu_1127_p2;
tmp_19_5_8_2_reg_6904 <= grp_fu_1131_p2;
tmp_19_5_9_2_reg_6909 <= grp_fu_1135_p2;
tmp_19_6_0_2_reg_6929 <= grp_fu_1151_p2;
tmp_19_6_10_2_reg_6979 <= grp_fu_1191_p2;
tmp_19_6_11_2_reg_6984 <= grp_fu_1195_p2;
tmp_19_6_12_2_reg_6989 <= grp_fu_1199_p2;
tmp_19_6_1_2_reg_6934 <= grp_fu_1155_p2;
tmp_19_6_2_2_reg_6939 <= grp_fu_1159_p2;
tmp_19_6_3_2_reg_6944 <= grp_fu_1163_p2;
tmp_19_6_4_2_reg_6949 <= grp_fu_1167_p2;
tmp_19_6_5_2_reg_6954 <= grp_fu_1171_p2;
tmp_19_6_6_2_reg_6959 <= grp_fu_1175_p2;
tmp_19_6_7_2_reg_6964 <= grp_fu_1179_p2;
tmp_19_6_8_2_reg_6969 <= grp_fu_1183_p2;
tmp_19_6_9_2_reg_6974 <= grp_fu_1187_p2;
tmp_19_7_0_2_reg_6994 <= grp_fu_1203_p2;
tmp_19_7_10_2_reg_7044 <= grp_fu_1243_p2;
tmp_19_7_11_2_reg_7049 <= grp_fu_1247_p2;
tmp_19_7_12_2_reg_7054 <= grp_fu_1251_p2;
tmp_19_7_1_2_reg_6999 <= grp_fu_1207_p2;
tmp_19_7_2_2_reg_7004 <= grp_fu_1211_p2;
tmp_19_7_3_2_reg_7009 <= grp_fu_1215_p2;
tmp_19_7_4_2_reg_7014 <= grp_fu_1219_p2;
tmp_19_7_5_2_reg_7019 <= grp_fu_1223_p2;
tmp_19_7_6_2_reg_7024 <= grp_fu_1227_p2;
tmp_19_7_7_2_reg_7029 <= grp_fu_1231_p2;
tmp_19_7_8_2_reg_7034 <= grp_fu_1235_p2;
tmp_19_7_9_2_reg_7039 <= grp_fu_1239_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
tmp_20_0_0_1_reg_7579 <= grp_fu_943_p2;
tmp_20_0_10_1_reg_7629 <= grp_fu_983_p2;
tmp_20_0_11_1_reg_7634 <= grp_fu_987_p2;
tmp_20_0_12_1_reg_7639 <= grp_fu_991_p2;
tmp_20_0_1_1_reg_7584 <= grp_fu_947_p2;
tmp_20_0_2_1_reg_7589 <= grp_fu_951_p2;
tmp_20_0_3_1_reg_7594 <= grp_fu_955_p2;
tmp_20_0_4_1_reg_7599 <= grp_fu_959_p2;
tmp_20_0_5_1_reg_7604 <= grp_fu_963_p2;
tmp_20_0_6_1_reg_7609 <= grp_fu_967_p2;
tmp_20_0_7_1_reg_7614 <= grp_fu_971_p2;
tmp_20_0_8_1_reg_7619 <= grp_fu_975_p2;
tmp_20_0_9_1_reg_7624 <= grp_fu_979_p2;
tmp_20_1_0_1_reg_7644 <= grp_fu_995_p2;
tmp_20_1_10_1_reg_7694 <= grp_fu_1035_p2;
tmp_20_1_11_1_reg_7699 <= grp_fu_1039_p2;
tmp_20_1_12_1_reg_7704 <= grp_fu_1043_p2;
tmp_20_1_1_1_reg_7649 <= grp_fu_999_p2;
tmp_20_1_2_1_reg_7654 <= grp_fu_1003_p2;
tmp_20_1_3_1_reg_7659 <= grp_fu_1007_p2;
tmp_20_1_4_1_reg_7664 <= grp_fu_1011_p2;
tmp_20_1_5_1_reg_7669 <= grp_fu_1015_p2;
tmp_20_1_6_1_reg_7674 <= grp_fu_1019_p2;
tmp_20_1_7_1_reg_7679 <= grp_fu_1023_p2;
tmp_20_1_8_1_reg_7684 <= grp_fu_1027_p2;
tmp_20_1_9_1_reg_7689 <= grp_fu_1031_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
tmp_20_0_0_2_reg_8099 <= grp_fu_943_p2;
tmp_20_0_10_2_reg_8149 <= grp_fu_983_p2;
tmp_20_0_11_2_reg_8154 <= grp_fu_987_p2;
tmp_20_0_12_2_reg_8159 <= grp_fu_991_p2;
tmp_20_0_1_2_reg_8104 <= grp_fu_947_p2;
tmp_20_0_2_2_reg_8109 <= grp_fu_951_p2;
tmp_20_0_3_2_reg_8114 <= grp_fu_955_p2;
tmp_20_0_4_2_reg_8119 <= grp_fu_959_p2;
tmp_20_0_5_2_reg_8124 <= grp_fu_963_p2;
tmp_20_0_6_2_reg_8129 <= grp_fu_967_p2;
tmp_20_0_7_2_reg_8134 <= grp_fu_971_p2;
tmp_20_0_8_2_reg_8139 <= grp_fu_975_p2;
tmp_20_0_9_2_reg_8144 <= grp_fu_979_p2;
tmp_20_1_0_2_reg_8164 <= grp_fu_995_p2;
tmp_20_1_10_2_reg_8214 <= grp_fu_1035_p2;
tmp_20_1_11_2_reg_8219 <= grp_fu_1039_p2;
tmp_20_1_12_2_reg_8224 <= grp_fu_1043_p2;
tmp_20_1_1_2_reg_8169 <= grp_fu_999_p2;
tmp_20_1_2_2_reg_8174 <= grp_fu_1003_p2;
tmp_20_1_3_2_reg_8179 <= grp_fu_1007_p2;
tmp_20_1_4_2_reg_8184 <= grp_fu_1011_p2;
tmp_20_1_5_2_reg_8189 <= grp_fu_1015_p2;
tmp_20_1_6_2_reg_8194 <= grp_fu_1019_p2;
tmp_20_1_7_2_reg_8199 <= grp_fu_1023_p2;
tmp_20_1_8_2_reg_8204 <= grp_fu_1027_p2;
tmp_20_1_9_2_reg_8209 <= grp_fu_1031_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter3_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
tmp_20_0_10_reg_7114 <= grp_fu_987_p2;
tmp_20_0_11_reg_7119 <= grp_fu_991_p2;
tmp_20_0_1_reg_7064 <= grp_fu_947_p2;
tmp_20_0_2_reg_7069 <= grp_fu_951_p2;
tmp_20_0_3_reg_7074 <= grp_fu_955_p2;
tmp_20_0_4_reg_7079 <= grp_fu_959_p2;
tmp_20_0_5_reg_7084 <= grp_fu_963_p2;
tmp_20_0_6_reg_7089 <= grp_fu_967_p2;
tmp_20_0_7_reg_7094 <= grp_fu_971_p2;
tmp_20_0_8_reg_7099 <= grp_fu_975_p2;
tmp_20_0_9_reg_7104 <= grp_fu_979_p2;
tmp_20_0_s_reg_7109 <= grp_fu_983_p2;
tmp_20_1_10_reg_7179 <= grp_fu_1039_p2;
tmp_20_1_11_reg_7184 <= grp_fu_1043_p2;
tmp_20_1_1_reg_7129 <= grp_fu_999_p2;
tmp_20_1_2_reg_7134 <= grp_fu_1003_p2;
tmp_20_1_3_reg_7139 <= grp_fu_1007_p2;
tmp_20_1_4_reg_7144 <= grp_fu_1011_p2;
tmp_20_1_5_reg_7149 <= grp_fu_1015_p2;
tmp_20_1_6_reg_7154 <= grp_fu_1019_p2;
tmp_20_1_7_reg_7159 <= grp_fu_1023_p2;
tmp_20_1_8_reg_7164 <= grp_fu_1027_p2;
tmp_20_1_9_reg_7169 <= grp_fu_1031_p2;
tmp_20_1_reg_7124 <= grp_fu_995_p2;
tmp_20_1_s_reg_7174 <= grp_fu_1035_p2;
tmp_351_reg_7059 <= grp_fu_943_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
tmp_20_2_0_1_reg_7709 <= grp_fu_943_p2;
tmp_20_2_10_1_reg_7759 <= grp_fu_983_p2;
tmp_20_2_11_1_reg_7764 <= grp_fu_987_p2;
tmp_20_2_12_1_reg_7769 <= grp_fu_991_p2;
tmp_20_2_1_1_reg_7714 <= grp_fu_947_p2;
tmp_20_2_2_1_reg_7719 <= grp_fu_951_p2;
tmp_20_2_3_1_reg_7724 <= grp_fu_955_p2;
tmp_20_2_4_1_reg_7729 <= grp_fu_959_p2;
tmp_20_2_5_1_reg_7734 <= grp_fu_963_p2;
tmp_20_2_6_1_reg_7739 <= grp_fu_967_p2;
tmp_20_2_7_1_reg_7744 <= grp_fu_971_p2;
tmp_20_2_8_1_reg_7749 <= grp_fu_975_p2;
tmp_20_2_9_1_reg_7754 <= grp_fu_979_p2;
tmp_20_3_0_1_reg_7774 <= grp_fu_995_p2;
tmp_20_3_10_1_reg_7824 <= grp_fu_1035_p2;
tmp_20_3_11_1_reg_7829 <= grp_fu_1039_p2;
tmp_20_3_12_1_reg_7834 <= grp_fu_1043_p2;
tmp_20_3_1_1_reg_7779 <= grp_fu_999_p2;
tmp_20_3_2_1_reg_7784 <= grp_fu_1003_p2;
tmp_20_3_3_1_reg_7789 <= grp_fu_1007_p2;
tmp_20_3_4_1_reg_7794 <= grp_fu_1011_p2;
tmp_20_3_5_1_reg_7799 <= grp_fu_1015_p2;
tmp_20_3_6_1_reg_7804 <= grp_fu_1019_p2;
tmp_20_3_7_1_reg_7809 <= grp_fu_1023_p2;
tmp_20_3_8_1_reg_7814 <= grp_fu_1027_p2;
tmp_20_3_9_1_reg_7819 <= grp_fu_1031_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
tmp_20_2_0_2_reg_8229 <= grp_fu_943_p2;
tmp_20_2_10_2_reg_8279 <= grp_fu_983_p2;
tmp_20_2_11_2_reg_8284 <= grp_fu_987_p2;
tmp_20_2_12_2_reg_8289 <= grp_fu_991_p2;
tmp_20_2_1_2_reg_8234 <= grp_fu_947_p2;
tmp_20_2_2_2_reg_8239 <= grp_fu_951_p2;
tmp_20_2_3_2_reg_8244 <= grp_fu_955_p2;
tmp_20_2_4_2_reg_8249 <= grp_fu_959_p2;
tmp_20_2_5_2_reg_8254 <= grp_fu_963_p2;
tmp_20_2_6_2_reg_8259 <= grp_fu_967_p2;
tmp_20_2_7_2_reg_8264 <= grp_fu_971_p2;
tmp_20_2_8_2_reg_8269 <= grp_fu_975_p2;
tmp_20_2_9_2_reg_8274 <= grp_fu_979_p2;
tmp_20_3_0_2_reg_8294 <= grp_fu_995_p2;
tmp_20_3_10_2_reg_8344 <= grp_fu_1035_p2;
tmp_20_3_11_2_reg_8349 <= grp_fu_1039_p2;
tmp_20_3_12_2_reg_8354 <= grp_fu_1043_p2;
tmp_20_3_1_2_reg_8299 <= grp_fu_999_p2;
tmp_20_3_2_2_reg_8304 <= grp_fu_1003_p2;
tmp_20_3_3_2_reg_8309 <= grp_fu_1007_p2;
tmp_20_3_4_2_reg_8314 <= grp_fu_1011_p2;
tmp_20_3_5_2_reg_8319 <= grp_fu_1015_p2;
tmp_20_3_6_2_reg_8324 <= grp_fu_1019_p2;
tmp_20_3_7_2_reg_8329 <= grp_fu_1023_p2;
tmp_20_3_8_2_reg_8334 <= grp_fu_1027_p2;
tmp_20_3_9_2_reg_8339 <= grp_fu_1031_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter3_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
tmp_20_2_10_reg_7244 <= grp_fu_987_p2;
tmp_20_2_11_reg_7249 <= grp_fu_991_p2;
tmp_20_2_1_reg_7194 <= grp_fu_947_p2;
tmp_20_2_2_reg_7199 <= grp_fu_951_p2;
tmp_20_2_3_reg_7204 <= grp_fu_955_p2;
tmp_20_2_4_reg_7209 <= grp_fu_959_p2;
tmp_20_2_5_reg_7214 <= grp_fu_963_p2;
tmp_20_2_6_reg_7219 <= grp_fu_967_p2;
tmp_20_2_7_reg_7224 <= grp_fu_971_p2;
tmp_20_2_8_reg_7229 <= grp_fu_975_p2;
tmp_20_2_9_reg_7234 <= grp_fu_979_p2;
tmp_20_2_reg_7189 <= grp_fu_943_p2;
tmp_20_2_s_reg_7239 <= grp_fu_983_p2;
tmp_20_3_10_reg_7309 <= grp_fu_1039_p2;
tmp_20_3_11_reg_7314 <= grp_fu_1043_p2;
tmp_20_3_1_reg_7259 <= grp_fu_999_p2;
tmp_20_3_2_reg_7264 <= grp_fu_1003_p2;
tmp_20_3_3_reg_7269 <= grp_fu_1007_p2;
tmp_20_3_4_reg_7274 <= grp_fu_1011_p2;
tmp_20_3_5_reg_7279 <= grp_fu_1015_p2;
tmp_20_3_6_reg_7284 <= grp_fu_1019_p2;
tmp_20_3_7_reg_7289 <= grp_fu_1023_p2;
tmp_20_3_8_reg_7294 <= grp_fu_1027_p2;
tmp_20_3_9_reg_7299 <= grp_fu_1031_p2;
tmp_20_3_reg_7254 <= grp_fu_995_p2;
tmp_20_3_s_reg_7304 <= grp_fu_1035_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
tmp_20_4_0_1_reg_7839 <= grp_fu_1047_p2;
tmp_20_4_10_1_reg_7889 <= grp_fu_1087_p2;
tmp_20_4_11_1_reg_7894 <= grp_fu_1091_p2;
tmp_20_4_12_1_reg_7899 <= grp_fu_1095_p2;
tmp_20_4_1_1_reg_7844 <= grp_fu_1051_p2;
tmp_20_4_2_1_reg_7849 <= grp_fu_1055_p2;
tmp_20_4_3_1_reg_7854 <= grp_fu_1059_p2;
tmp_20_4_4_1_reg_7859 <= grp_fu_1063_p2;
tmp_20_4_5_1_reg_7864 <= grp_fu_1067_p2;
tmp_20_4_6_1_reg_7869 <= grp_fu_1071_p2;
tmp_20_4_7_1_reg_7874 <= grp_fu_1075_p2;
tmp_20_4_8_1_reg_7879 <= grp_fu_1079_p2;
tmp_20_4_9_1_reg_7884 <= grp_fu_1083_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
tmp_20_4_0_2_reg_8359 <= grp_fu_1047_p2;
tmp_20_4_10_2_reg_8409 <= grp_fu_1087_p2;
tmp_20_4_11_2_reg_8414 <= grp_fu_1091_p2;
tmp_20_4_12_2_reg_8419 <= grp_fu_1095_p2;
tmp_20_4_1_2_reg_8364 <= grp_fu_1051_p2;
tmp_20_4_2_2_reg_8369 <= grp_fu_1055_p2;
tmp_20_4_3_2_reg_8374 <= grp_fu_1059_p2;
tmp_20_4_4_2_reg_8379 <= grp_fu_1063_p2;
tmp_20_4_5_2_reg_8384 <= grp_fu_1067_p2;
tmp_20_4_6_2_reg_8389 <= grp_fu_1071_p2;
tmp_20_4_7_2_reg_8394 <= grp_fu_1075_p2;
tmp_20_4_8_2_reg_8399 <= grp_fu_1079_p2;
tmp_20_4_9_2_reg_8404 <= grp_fu_1083_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter3_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
tmp_20_4_10_reg_7374 <= grp_fu_987_p2;
tmp_20_4_11_reg_7379 <= grp_fu_991_p2;
tmp_20_4_1_reg_7324 <= grp_fu_947_p2;
tmp_20_4_2_reg_7329 <= grp_fu_951_p2;
tmp_20_4_3_reg_7334 <= grp_fu_955_p2;
tmp_20_4_4_reg_7339 <= grp_fu_959_p2;
tmp_20_4_5_reg_7344 <= grp_fu_963_p2;
tmp_20_4_6_reg_7349 <= grp_fu_967_p2;
tmp_20_4_7_reg_7354 <= grp_fu_971_p2;
tmp_20_4_8_reg_7359 <= grp_fu_975_p2;
tmp_20_4_9_reg_7364 <= grp_fu_979_p2;
tmp_20_4_reg_7319 <= grp_fu_943_p2;
tmp_20_4_s_reg_7369 <= grp_fu_983_p2;
tmp_20_5_10_reg_7439 <= grp_fu_1039_p2;
tmp_20_5_11_reg_7444 <= grp_fu_1043_p2;
tmp_20_5_1_reg_7389 <= grp_fu_999_p2;
tmp_20_5_2_reg_7394 <= grp_fu_1003_p2;
tmp_20_5_3_reg_7399 <= grp_fu_1007_p2;
tmp_20_5_4_reg_7404 <= grp_fu_1011_p2;
tmp_20_5_5_reg_7409 <= grp_fu_1015_p2;
tmp_20_5_6_reg_7414 <= grp_fu_1019_p2;
tmp_20_5_7_reg_7419 <= grp_fu_1023_p2;
tmp_20_5_8_reg_7424 <= grp_fu_1027_p2;
tmp_20_5_9_reg_7429 <= grp_fu_1031_p2;
tmp_20_5_reg_7384 <= grp_fu_995_p2;
tmp_20_5_s_reg_7434 <= grp_fu_1035_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
tmp_20_5_0_1_reg_7904 <= grp_fu_1047_p2;
tmp_20_5_10_1_reg_7954 <= grp_fu_1087_p2;
tmp_20_5_11_1_reg_7959 <= grp_fu_1091_p2;
tmp_20_5_12_1_reg_7964 <= grp_fu_1095_p2;
tmp_20_5_1_1_reg_7909 <= grp_fu_1051_p2;
tmp_20_5_2_1_reg_7914 <= grp_fu_1055_p2;
tmp_20_5_3_1_reg_7919 <= grp_fu_1059_p2;
tmp_20_5_4_1_reg_7924 <= grp_fu_1063_p2;
tmp_20_5_5_1_reg_7929 <= grp_fu_1067_p2;
tmp_20_5_6_1_reg_7934 <= grp_fu_1071_p2;
tmp_20_5_7_1_reg_7939 <= grp_fu_1075_p2;
tmp_20_5_8_1_reg_7944 <= grp_fu_1079_p2;
tmp_20_5_9_1_reg_7949 <= grp_fu_1083_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
tmp_20_5_0_2_reg_8424 <= grp_fu_1047_p2;
tmp_20_5_10_2_reg_8474 <= grp_fu_1087_p2;
tmp_20_5_11_2_reg_8479 <= grp_fu_1091_p2;
tmp_20_5_12_2_reg_8484 <= grp_fu_1095_p2;
tmp_20_5_1_2_reg_8429 <= grp_fu_1051_p2;
tmp_20_5_2_2_reg_8434 <= grp_fu_1055_p2;
tmp_20_5_3_2_reg_8439 <= grp_fu_1059_p2;
tmp_20_5_4_2_reg_8444 <= grp_fu_1063_p2;
tmp_20_5_5_2_reg_8449 <= grp_fu_1067_p2;
tmp_20_5_6_2_reg_8454 <= grp_fu_1071_p2;
tmp_20_5_7_2_reg_8459 <= grp_fu_1075_p2;
tmp_20_5_8_2_reg_8464 <= grp_fu_1079_p2;
tmp_20_5_9_2_reg_8469 <= grp_fu_1083_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
tmp_20_6_0_1_reg_7969 <= grp_fu_1047_p2;
tmp_20_6_10_1_reg_8019 <= grp_fu_1087_p2;
tmp_20_6_11_1_reg_8024 <= grp_fu_1091_p2;
tmp_20_6_12_1_reg_8029 <= grp_fu_1095_p2;
tmp_20_6_1_1_reg_7974 <= grp_fu_1051_p2;
tmp_20_6_2_1_reg_7979 <= grp_fu_1055_p2;
tmp_20_6_3_1_reg_7984 <= grp_fu_1059_p2;
tmp_20_6_4_1_reg_7989 <= grp_fu_1063_p2;
tmp_20_6_5_1_reg_7994 <= grp_fu_1067_p2;
tmp_20_6_6_1_reg_7999 <= grp_fu_1071_p2;
tmp_20_6_7_1_reg_8004 <= grp_fu_1075_p2;
tmp_20_6_8_1_reg_8009 <= grp_fu_1079_p2;
tmp_20_6_9_1_reg_8014 <= grp_fu_1083_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter8_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8))) then
tmp_20_6_0_2_reg_8489 <= grp_fu_1047_p2;
tmp_20_6_10_2_reg_8539 <= grp_fu_1087_p2;
tmp_20_6_11_2_reg_8544 <= grp_fu_1091_p2;
tmp_20_6_12_2_reg_8549 <= grp_fu_1095_p2;
tmp_20_6_1_2_reg_8494 <= grp_fu_1051_p2;
tmp_20_6_2_2_reg_8499 <= grp_fu_1055_p2;
tmp_20_6_3_2_reg_8504 <= grp_fu_1059_p2;
tmp_20_6_4_2_reg_8509 <= grp_fu_1063_p2;
tmp_20_6_5_2_reg_8514 <= grp_fu_1067_p2;
tmp_20_6_6_2_reg_8519 <= grp_fu_1071_p2;
tmp_20_6_7_2_reg_8524 <= grp_fu_1075_p2;
tmp_20_6_8_2_reg_8529 <= grp_fu_1079_p2;
tmp_20_6_9_2_reg_8534 <= grp_fu_1083_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter3_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
tmp_20_6_10_reg_7504 <= grp_fu_987_p2;
tmp_20_6_11_reg_7509 <= grp_fu_991_p2;
tmp_20_6_1_reg_7454 <= grp_fu_947_p2;
tmp_20_6_2_reg_7459 <= grp_fu_951_p2;
tmp_20_6_3_reg_7464 <= grp_fu_955_p2;
tmp_20_6_4_reg_7469 <= grp_fu_959_p2;
tmp_20_6_5_reg_7474 <= grp_fu_963_p2;
tmp_20_6_6_reg_7479 <= grp_fu_967_p2;
tmp_20_6_7_reg_7484 <= grp_fu_971_p2;
tmp_20_6_8_reg_7489 <= grp_fu_975_p2;
tmp_20_6_9_reg_7494 <= grp_fu_979_p2;
tmp_20_6_reg_7449 <= grp_fu_943_p2;
tmp_20_6_s_reg_7499 <= grp_fu_983_p2;
tmp_20_7_10_reg_7569 <= grp_fu_1039_p2;
tmp_20_7_11_reg_7574 <= grp_fu_1043_p2;
tmp_20_7_1_reg_7519 <= grp_fu_999_p2;
tmp_20_7_2_reg_7524 <= grp_fu_1003_p2;
tmp_20_7_3_reg_7529 <= grp_fu_1007_p2;
tmp_20_7_4_reg_7534 <= grp_fu_1011_p2;
tmp_20_7_5_reg_7539 <= grp_fu_1015_p2;
tmp_20_7_6_reg_7544 <= grp_fu_1019_p2;
tmp_20_7_7_reg_7549 <= grp_fu_1023_p2;
tmp_20_7_8_reg_7554 <= grp_fu_1027_p2;
tmp_20_7_9_reg_7559 <= grp_fu_1031_p2;
tmp_20_7_reg_7514 <= grp_fu_995_p2;
tmp_20_7_s_reg_7564 <= grp_fu_1035_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
tmp_20_7_0_1_reg_8034 <= grp_fu_1047_p2;
tmp_20_7_10_1_reg_8084 <= grp_fu_1087_p2;
tmp_20_7_11_1_reg_8089 <= grp_fu_1091_p2;
tmp_20_7_12_1_reg_8094 <= grp_fu_1095_p2;
tmp_20_7_1_1_reg_8039 <= grp_fu_1051_p2;
tmp_20_7_2_1_reg_8044 <= grp_fu_1055_p2;
tmp_20_7_3_1_reg_8049 <= grp_fu_1059_p2;
tmp_20_7_4_1_reg_8054 <= grp_fu_1063_p2;
tmp_20_7_5_1_reg_8059 <= grp_fu_1067_p2;
tmp_20_7_6_1_reg_8064 <= grp_fu_1071_p2;
tmp_20_7_7_1_reg_8069 <= grp_fu_1075_p2;
tmp_20_7_8_1_reg_8074 <= grp_fu_1079_p2;
tmp_20_7_9_1_reg_8079 <= grp_fu_1083_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter8_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8))) then
tmp_20_7_0_2_reg_8554 <= grp_fu_1047_p2;
tmp_20_7_10_2_reg_8604 <= grp_fu_1087_p2;
tmp_20_7_11_2_reg_8609 <= grp_fu_1091_p2;
tmp_20_7_12_2_reg_8614 <= grp_fu_1095_p2;
tmp_20_7_1_2_reg_8559 <= grp_fu_1051_p2;
tmp_20_7_2_2_reg_8564 <= grp_fu_1055_p2;
tmp_20_7_3_2_reg_8569 <= grp_fu_1059_p2;
tmp_20_7_4_2_reg_8574 <= grp_fu_1063_p2;
tmp_20_7_5_2_reg_8579 <= grp_fu_1067_p2;
tmp_20_7_6_2_reg_8584 <= grp_fu_1071_p2;
tmp_20_7_7_2_reg_8589 <= grp_fu_1075_p2;
tmp_20_7_8_2_reg_8594 <= grp_fu_1079_p2;
tmp_20_7_9_2_reg_8599 <= grp_fu_1083_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
tmp_210_reg_3511 <= tmp_210_fu_1876_p2;
tmp_250_reg_3516 <= tmp_250_fu_1881_p2;
tmp_7_reg_3356 <= tmp_7_fu_1807_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
tmp_290_reg_3616 <= tmp_290_fu_1978_p2;
tmp_330_reg_3621 <= tmp_330_fu_1983_p2;
tmp_331_reg_3626 <= tmp_331_fu_1988_p2;
tmp_332_reg_3631 <= tmp_332_fu_1993_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
tmp_2_reg_3281 <= tmp_2_fu_1657_p2;
tmp_90_reg_3299(9 downto 2) <= tmp_90_fu_1694_p2(9 downto 2);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
tmp_355_reg_4719 <= tmp_355_fu_2149_p1;
tmp_356_reg_4784 <= tmp_356_fu_2153_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
tmp_357_reg_5044 <= tmp_357_fu_2157_p1;
tmp_358_reg_5109 <= tmp_358_fu_2161_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
tmp_5_mid2_reg_3286 <= tmp_5_mid2_fu_1662_p3;
end if;
end if;
end process;
tmp_90_reg_3299(1 downto 0) <= "00";
tmp_5_mid2_cast2_reg_3316(6 downto 3) <= "0000";
tmp_333_reg_4307(2 downto 0) <= "000";
bufo_addr_reg_4317(2 downto 0) <= "000";
ap_reg_pp0_iter2_bufo_addr_reg_4317(2 downto 0) <= "000";
ap_reg_pp0_iter3_bufo_addr_reg_4317(2 downto 0) <= "000";
ap_reg_pp0_iter4_bufo_addr_reg_4317(2 downto 0) <= "000";
ap_reg_pp0_iter5_bufo_addr_reg_4317(2 downto 0) <= "000";
ap_reg_pp0_iter6_bufo_addr_reg_4317(2 downto 0) <= "000";
ap_reg_pp0_iter7_bufo_addr_reg_4317(2 downto 0) <= "000";
bufo_addr_1_reg_4322(2 downto 0) <= "001";
ap_reg_pp0_iter2_bufo_addr_1_reg_4322(2 downto 0) <= "001";
ap_reg_pp0_iter3_bufo_addr_1_reg_4322(2 downto 0) <= "001";
ap_reg_pp0_iter4_bufo_addr_1_reg_4322(2 downto 0) <= "001";
ap_reg_pp0_iter5_bufo_addr_1_reg_4322(2 downto 0) <= "001";
ap_reg_pp0_iter6_bufo_addr_1_reg_4322(2 downto 0) <= "001";
ap_reg_pp0_iter7_bufo_addr_1_reg_4322(2 downto 0) <= "001";
bufo_addr_2_reg_4429(2 downto 0) <= "010";
ap_reg_pp0_iter2_bufo_addr_2_reg_4429(2 downto 0) <= "010";
ap_reg_pp0_iter3_bufo_addr_2_reg_4429(2 downto 0) <= "010";
ap_reg_pp0_iter4_bufo_addr_2_reg_4429(2 downto 0) <= "010";
ap_reg_pp0_iter5_bufo_addr_2_reg_4429(2 downto 0) <= "010";
ap_reg_pp0_iter6_bufo_addr_2_reg_4429(2 downto 0) <= "010";
ap_reg_pp0_iter7_bufo_addr_2_reg_4429(2 downto 0) <= "010";
bufo_addr_3_reg_4434(2 downto 0) <= "011";
ap_reg_pp0_iter2_bufo_addr_3_reg_4434(2 downto 0) <= "011";
ap_reg_pp0_iter3_bufo_addr_3_reg_4434(2 downto 0) <= "011";
ap_reg_pp0_iter4_bufo_addr_3_reg_4434(2 downto 0) <= "011";
ap_reg_pp0_iter5_bufo_addr_3_reg_4434(2 downto 0) <= "011";
ap_reg_pp0_iter6_bufo_addr_3_reg_4434(2 downto 0) <= "011";
ap_reg_pp0_iter7_bufo_addr_3_reg_4434(2 downto 0) <= "011";
bufo_addr_4_reg_4439(2 downto 0) <= "100";
ap_reg_pp0_iter2_bufo_addr_4_reg_4439(2 downto 0) <= "100";
ap_reg_pp0_iter3_bufo_addr_4_reg_4439(2 downto 0) <= "100";
ap_reg_pp0_iter4_bufo_addr_4_reg_4439(2 downto 0) <= "100";
ap_reg_pp0_iter5_bufo_addr_4_reg_4439(2 downto 0) <= "100";
ap_reg_pp0_iter6_bufo_addr_4_reg_4439(2 downto 0) <= "100";
ap_reg_pp0_iter7_bufo_addr_4_reg_4439(2 downto 0) <= "100";
bufo_addr_5_reg_4444(2 downto 0) <= "101";
ap_reg_pp0_iter2_bufo_addr_5_reg_4444(2 downto 0) <= "101";
ap_reg_pp0_iter3_bufo_addr_5_reg_4444(2 downto 0) <= "101";
ap_reg_pp0_iter4_bufo_addr_5_reg_4444(2 downto 0) <= "101";
ap_reg_pp0_iter5_bufo_addr_5_reg_4444(2 downto 0) <= "101";
ap_reg_pp0_iter6_bufo_addr_5_reg_4444(2 downto 0) <= "101";
ap_reg_pp0_iter7_bufo_addr_5_reg_4444(2 downto 0) <= "101";
bufo_addr_6_reg_4579(2 downto 0) <= "110";
ap_reg_pp0_iter2_bufo_addr_6_reg_4579(2 downto 0) <= "110";
ap_reg_pp0_iter3_bufo_addr_6_reg_4579(2 downto 0) <= "110";
ap_reg_pp0_iter4_bufo_addr_6_reg_4579(2 downto 0) <= "110";
ap_reg_pp0_iter5_bufo_addr_6_reg_4579(2 downto 0) <= "110";
ap_reg_pp0_iter6_bufo_addr_6_reg_4579(2 downto 0) <= "110";
ap_reg_pp0_iter7_bufo_addr_6_reg_4579(2 downto 0) <= "110";
ap_reg_pp0_iter8_bufo_addr_6_reg_4579(2 downto 0) <= "110";
bufo_addr_7_reg_4584(2 downto 0) <= "111";
ap_reg_pp0_iter2_bufo_addr_7_reg_4584(2 downto 0) <= "111";
ap_reg_pp0_iter3_bufo_addr_7_reg_4584(2 downto 0) <= "111";
ap_reg_pp0_iter4_bufo_addr_7_reg_4584(2 downto 0) <= "111";
ap_reg_pp0_iter5_bufo_addr_7_reg_4584(2 downto 0) <= "111";
ap_reg_pp0_iter6_bufo_addr_7_reg_4584(2 downto 0) <= "111";
ap_reg_pp0_iter7_bufo_addr_7_reg_4584(2 downto 0) <= "111";
ap_reg_pp0_iter8_bufo_addr_7_reg_4584(2 downto 0) <= "111";
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, exitcond_flatten1_fu_1541_p2, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_subdone, ap_block_pp0_stage7_subdone, ap_block_pp0_stage1_subdone, ap_enable_reg_pp0_iter9, ap_block_pp0_stage2_subdone, ap_block_pp0_stage3_subdone, ap_block_pp0_stage4_subdone, ap_block_pp0_stage5_subdone, ap_block_pp0_stage6_subdone)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_pp0_stage0 =>
if ((not(((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (exitcond_flatten1_fu_1541_p2 = ap_const_lv1_1) and (ap_block_pp0_stage0_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) and (ap_block_pp0_stage0_subdone = ap_const_boolean_0))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
elsif (((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (exitcond_flatten1_fu_1541_p2 = ap_const_lv1_1) and (ap_block_pp0_stage0_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
ap_NS_fsm <= ap_ST_fsm_state76;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage1 =>
if ((not(((ap_block_pp0_stage1_subdone = ap_const_boolean_0) and (ap_enable_reg_pp0_iter8 = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) and (ap_block_pp0_stage1_subdone = ap_const_boolean_0))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
elsif (((ap_block_pp0_stage1_subdone = ap_const_boolean_0) and (ap_enable_reg_pp0_iter8 = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
ap_NS_fsm <= ap_ST_fsm_state76;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
end if;
when ap_ST_fsm_pp0_stage2 =>
if ((ap_block_pp0_stage2_subdone = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
end if;
when ap_ST_fsm_pp0_stage3 =>
if ((ap_block_pp0_stage3_subdone = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
end if;
when ap_ST_fsm_pp0_stage4 =>
if ((ap_block_pp0_stage4_subdone = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
end if;
when ap_ST_fsm_pp0_stage5 =>
if ((ap_block_pp0_stage5_subdone = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
end if;
when ap_ST_fsm_pp0_stage6 =>
if ((ap_block_pp0_stage6_subdone = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
end if;
when ap_ST_fsm_pp0_stage7 =>
if ((ap_block_pp0_stage7_subdone = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
end if;
when ap_ST_fsm_state76 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXXXXXXXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(1);
ap_CS_fsm_pp0_stage1 <= ap_CS_fsm(2);
ap_CS_fsm_pp0_stage2 <= ap_CS_fsm(3);
ap_CS_fsm_pp0_stage3 <= ap_CS_fsm(4);
ap_CS_fsm_pp0_stage4 <= ap_CS_fsm(5);
ap_CS_fsm_pp0_stage5 <= ap_CS_fsm(6);
ap_CS_fsm_pp0_stage6 <= ap_CS_fsm(7);
ap_CS_fsm_pp0_stage7 <= ap_CS_fsm(8);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state76 <= ap_CS_fsm(9);
ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state10_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage1_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state12_pp0_stage2_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state13_pp0_stage3_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state14_pp0_stage4_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state15_pp0_stage5_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state16_pp0_stage6_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state17_pp0_stage7_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state18_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state19_pp0_stage1_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state20_pp0_stage2_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state21_pp0_stage3_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state22_pp0_stage4_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state23_pp0_stage5_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state24_pp0_stage6_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state25_pp0_stage7_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state26_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state27_pp0_stage1_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state28_pp0_stage2_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state29_pp0_stage3_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state2_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state30_pp0_stage4_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state31_pp0_stage5_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state32_pp0_stage6_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state33_pp0_stage7_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state34_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state35_pp0_stage1_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state36_pp0_stage2_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state37_pp0_stage3_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state38_pp0_stage4_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state39_pp0_stage5_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state3_pp0_stage1_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state40_pp0_stage6_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state41_pp0_stage7_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state42_pp0_stage0_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state43_pp0_stage1_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state44_pp0_stage2_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state45_pp0_stage3_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state46_pp0_stage4_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state47_pp0_stage5_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state48_pp0_stage6_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state49_pp0_stage7_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage2_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state50_pp0_stage0_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state51_pp0_stage1_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state52_pp0_stage2_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state53_pp0_stage3_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state54_pp0_stage4_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state55_pp0_stage5_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state56_pp0_stage6_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state57_pp0_stage7_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state58_pp0_stage0_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state59_pp0_stage1_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage3_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state60_pp0_stage2_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state61_pp0_stage3_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state62_pp0_stage4_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state63_pp0_stage5_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state64_pp0_stage6_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state65_pp0_stage7_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state66_pp0_stage0_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state67_pp0_stage1_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state68_pp0_stage2_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state69_pp0_stage3_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage4_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state70_pp0_stage4_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state71_pp0_stage5_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state72_pp0_stage6_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state73_pp0_stage7_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state74_pp0_stage0_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state75_pp0_stage1_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage5_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage6_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage7_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_condition_pp0_exit_iter0_state2_assign_proc : process(exitcond_flatten1_fu_1541_p2)
begin
if ((exitcond_flatten1_fu_1541_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_CS_fsm_state76)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state76)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter9) and (ap_const_logic_0 = ap_enable_reg_pp0_iter8) and (ap_const_logic_0 = ap_enable_reg_pp0_iter7) and (ap_const_logic_0 = ap_enable_reg_pp0_iter6) and (ap_const_logic_0 = ap_enable_reg_pp0_iter5) and (ap_const_logic_0 = ap_enable_reg_pp0_iter4) and (ap_const_logic_0 = ap_enable_reg_pp0_iter3) and (ap_const_logic_0 = ap_enable_reg_pp0_iter2))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_phi_mux_i_phi_fu_900_p4_assign_proc : process(i_reg_896, ap_CS_fsm_pp0_stage0, exitcond_flatten1_reg_3176, tmp_1_mid2_v_reg_3225, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_phi_mux_i_phi_fu_900_p4 <= tmp_1_mid2_v_reg_3225;
else
ap_phi_mux_i_phi_fu_900_p4 <= i_reg_896;
end if;
end process;
ap_phi_mux_indvar_flatten1_phi_fu_889_p4_assign_proc : process(indvar_flatten1_reg_885, ap_CS_fsm_pp0_stage0, exitcond_flatten1_reg_3176, indvar_flatten_next1_reg_3180, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_phi_mux_indvar_flatten1_phi_fu_889_p4 <= indvar_flatten_next1_reg_3180;
else
ap_phi_mux_indvar_flatten1_phi_fu_889_p4 <= indvar_flatten1_reg_885;
end if;
end process;
ap_phi_mux_indvar_flatten_phi_fu_912_p4_assign_proc : process(indvar_flatten_reg_908, ap_CS_fsm_pp0_stage0, exitcond_flatten1_reg_3176, indvar_flatten_next_reg_3252, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_phi_mux_indvar_flatten_phi_fu_912_p4 <= indvar_flatten_next_reg_3252;
else
ap_phi_mux_indvar_flatten_phi_fu_912_p4 <= indvar_flatten_reg_908;
end if;
end process;
ap_phi_mux_j_phi_fu_923_p4_assign_proc : process(j_reg_919, ap_CS_fsm_pp0_stage0, exitcond_flatten1_reg_3176, tmp_5_mid2_reg_3286, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_phi_mux_j_phi_fu_923_p4 <= tmp_5_mid2_reg_3286;
else
ap_phi_mux_j_phi_fu_923_p4 <= j_reg_919;
end if;
end process;
ap_phi_mux_row_b_phi_fu_935_p4_assign_proc : process(row_b_reg_931, ap_CS_fsm_pp0_stage0, exitcond_flatten1_reg_3176, row_b_1_reg_3276, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_phi_mux_row_b_phi_fu_935_p4 <= row_b_1_reg_3276;
else
ap_phi_mux_row_b_phi_fu_935_p4 <= row_b_reg_931;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state76)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state76)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
bufi_0_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_0_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_0_Addr_A_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, tmp_334_cast_fu_1864_p1, ap_block_pp0_stage6, tmp_336_cast_fu_1966_p1, tmp_338_cast_fu_1998_p1, ap_block_pp0_stage7, tmp_340_cast_fu_2010_p1)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufi_0_Addr_A_orig <= tmp_340_cast_fu_2010_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_0_Addr_A_orig <= tmp_338_cast_fu_1998_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_0_Addr_A_orig <= tmp_336_cast_fu_1966_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_0_Addr_A_orig <= tmp_334_cast_fu_1864_p1(32 - 1 downto 0);
else
bufi_0_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_0_Addr_B <= std_logic_vector(shift_left(unsigned(bufi_0_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_0_Addr_B_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, tmp_335_cast_fu_1870_p1, ap_block_pp0_stage6, tmp_337_cast_fu_1972_p1, ap_block_pp0_stage7, tmp_339_cast_fu_2004_p1, tmp_341_cast_fu_2016_p1)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufi_0_Addr_B_orig <= tmp_341_cast_fu_2016_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_0_Addr_B_orig <= tmp_339_cast_fu_2004_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_0_Addr_B_orig <= tmp_337_cast_fu_1972_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_0_Addr_B_orig <= tmp_335_cast_fu_1870_p1(32 - 1 downto 0);
else
bufi_0_Addr_B_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_0_Clk_A <= ap_clk;
bufi_0_Clk_B <= ap_clk;
bufi_0_Din_A <= ap_const_lv32_0;
bufi_0_Din_B <= ap_const_lv32_0;
bufi_0_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_11001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufi_0_EN_A <= ap_const_logic_1;
else
bufi_0_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_0_EN_B_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_11001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufi_0_EN_B <= ap_const_logic_1;
else
bufi_0_EN_B <= ap_const_logic_0;
end if;
end process;
bufi_0_Rst_A <= ap_rst_n_inv;
bufi_0_Rst_B <= ap_rst_n_inv;
bufi_0_WEN_A <= ap_const_lv4_0;
bufi_0_WEN_B <= ap_const_lv4_0;
bufi_1_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_1_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_1_Addr_A_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, tmp_334_cast_fu_1864_p1, ap_block_pp0_stage6, tmp_336_cast_fu_1966_p1, tmp_338_cast_fu_1998_p1, ap_block_pp0_stage7, tmp_340_cast_fu_2010_p1)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufi_1_Addr_A_orig <= tmp_340_cast_fu_2010_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_1_Addr_A_orig <= tmp_338_cast_fu_1998_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_1_Addr_A_orig <= tmp_336_cast_fu_1966_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_1_Addr_A_orig <= tmp_334_cast_fu_1864_p1(32 - 1 downto 0);
else
bufi_1_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_1_Addr_B <= std_logic_vector(shift_left(unsigned(bufi_1_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_1_Addr_B_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, tmp_335_cast_fu_1870_p1, ap_block_pp0_stage6, tmp_337_cast_fu_1972_p1, ap_block_pp0_stage7, tmp_339_cast_fu_2004_p1, tmp_341_cast_fu_2016_p1)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufi_1_Addr_B_orig <= tmp_341_cast_fu_2016_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_1_Addr_B_orig <= tmp_339_cast_fu_2004_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_1_Addr_B_orig <= tmp_337_cast_fu_1972_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_1_Addr_B_orig <= tmp_335_cast_fu_1870_p1(32 - 1 downto 0);
else
bufi_1_Addr_B_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_1_Clk_A <= ap_clk;
bufi_1_Clk_B <= ap_clk;
bufi_1_Din_A <= ap_const_lv32_0;
bufi_1_Din_B <= ap_const_lv32_0;
bufi_1_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_11001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufi_1_EN_A <= ap_const_logic_1;
else
bufi_1_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_1_EN_B_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_11001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufi_1_EN_B <= ap_const_logic_1;
else
bufi_1_EN_B <= ap_const_logic_0;
end if;
end process;
bufi_1_Rst_A <= ap_rst_n_inv;
bufi_1_Rst_B <= ap_rst_n_inv;
bufi_1_WEN_A <= ap_const_lv4_0;
bufi_1_WEN_B <= ap_const_lv4_0;
bufi_2_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_2_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_2_Addr_A_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, tmp_334_cast_fu_1864_p1, ap_block_pp0_stage6, tmp_336_cast_fu_1966_p1, tmp_338_cast_fu_1998_p1, ap_block_pp0_stage7, tmp_340_cast_fu_2010_p1)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufi_2_Addr_A_orig <= tmp_340_cast_fu_2010_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_2_Addr_A_orig <= tmp_338_cast_fu_1998_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_2_Addr_A_orig <= tmp_336_cast_fu_1966_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_2_Addr_A_orig <= tmp_334_cast_fu_1864_p1(32 - 1 downto 0);
else
bufi_2_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_2_Addr_B <= std_logic_vector(shift_left(unsigned(bufi_2_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_2_Addr_B_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, tmp_335_cast_fu_1870_p1, ap_block_pp0_stage6, tmp_337_cast_fu_1972_p1, ap_block_pp0_stage7, tmp_339_cast_fu_2004_p1, tmp_341_cast_fu_2016_p1)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufi_2_Addr_B_orig <= tmp_341_cast_fu_2016_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_2_Addr_B_orig <= tmp_339_cast_fu_2004_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_2_Addr_B_orig <= tmp_337_cast_fu_1972_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_2_Addr_B_orig <= tmp_335_cast_fu_1870_p1(32 - 1 downto 0);
else
bufi_2_Addr_B_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_2_Clk_A <= ap_clk;
bufi_2_Clk_B <= ap_clk;
bufi_2_Din_A <= ap_const_lv32_0;
bufi_2_Din_B <= ap_const_lv32_0;
bufi_2_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_11001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufi_2_EN_A <= ap_const_logic_1;
else
bufi_2_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_2_EN_B_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_11001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufi_2_EN_B <= ap_const_logic_1;
else
bufi_2_EN_B <= ap_const_logic_0;
end if;
end process;
bufi_2_Rst_A <= ap_rst_n_inv;
bufi_2_Rst_B <= ap_rst_n_inv;
bufi_2_WEN_A <= ap_const_lv4_0;
bufi_2_WEN_B <= ap_const_lv4_0;
bufo_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_6(31-1 downto 0)))));
bufo_Addr_A_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter1, ap_reg_pp0_iter7_bufo_addr_reg_4317, ap_reg_pp0_iter7_bufo_addr_2_reg_4429, ap_reg_pp0_iter7_bufo_addr_4_reg_4439, ap_reg_pp0_iter8_bufo_addr_6_reg_4579, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, tmp_334_fu_2029_p1, ap_block_pp0_stage2, tmp_338_fu_2054_p3, ap_block_pp0_stage3, tmp_342_fu_2082_p3, ap_block_pp0_stage4, tmp_346_fu_2118_p3, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
bufo_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter8_bufo_addr_6_reg_4579),32));
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufo_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter7_bufo_addr_4_reg_4439),32));
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
bufo_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter7_bufo_addr_2_reg_4429),32));
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
bufo_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter7_bufo_addr_reg_4317),32));
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufo_Addr_A_orig <= tmp_346_fu_2118_p3(32 - 1 downto 0);
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
bufo_Addr_A_orig <= tmp_342_fu_2082_p3(32 - 1 downto 0);
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
bufo_Addr_A_orig <= tmp_338_fu_2054_p3(32 - 1 downto 0);
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
bufo_Addr_A_orig <= tmp_334_fu_2029_p1(32 - 1 downto 0);
else
bufo_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufo_Addr_B <= std_logic_vector(shift_left(unsigned(bufo_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_6(31-1 downto 0)))));
bufo_Addr_B_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter1, ap_reg_pp0_iter7_bufo_addr_1_reg_4322, ap_reg_pp0_iter7_bufo_addr_3_reg_4434, ap_reg_pp0_iter7_bufo_addr_5_reg_4444, ap_reg_pp0_iter8_bufo_addr_7_reg_4584, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, tmp_336_fu_2040_p3, ap_block_pp0_stage3, tmp_340_fu_2068_p3, ap_block_pp0_stage4, tmp_344_fu_2096_p3, tmp_348_fu_2132_p3, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
bufo_Addr_B_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter8_bufo_addr_7_reg_4584),32));
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufo_Addr_B_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter7_bufo_addr_5_reg_4444),32));
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
bufo_Addr_B_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter7_bufo_addr_3_reg_4434),32));
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
bufo_Addr_B_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter7_bufo_addr_1_reg_4322),32));
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufo_Addr_B_orig <= tmp_348_fu_2132_p3(32 - 1 downto 0);
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
bufo_Addr_B_orig <= tmp_344_fu_2096_p3(32 - 1 downto 0);
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
bufo_Addr_B_orig <= tmp_340_fu_2068_p3(32 - 1 downto 0);
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
bufo_Addr_B_orig <= tmp_336_fu_2040_p3(32 - 1 downto 0);
else
bufo_Addr_B_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufo_Clk_A <= ap_clk;
bufo_Clk_B <= ap_clk;
bufo_Din_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9, ap_block_pp0_stage0, ap_block_pp0_stage6, ap_block_pp0_stage7, tmp_49_fu_2620_p14, tmp_129_fu_2760_p14, tmp_209_fu_2900_p14, tmp_289_fu_3040_p14, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
bufo_Din_A <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_289_fu_3040_p14),512));
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufo_Din_A <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_209_fu_2900_p14),512));
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
bufo_Din_A <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_129_fu_2760_p14),512));
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
bufo_Din_A <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_49_fu_2620_p14),512));
else
bufo_Din_A <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufo_Din_B_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9, ap_block_pp0_stage0, ap_block_pp0_stage6, ap_block_pp0_stage7, tmp_89_fu_2690_p14, tmp_169_fu_2830_p14, tmp_249_fu_2970_p14, ap_block_pp0_stage1, tmp_329_fu_3110_p14)
begin
if (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
bufo_Din_B <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_329_fu_3110_p14),512));
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufo_Din_B <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_249_fu_2970_p14),512));
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
bufo_Din_B <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_169_fu_2830_p14),512));
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
bufo_Din_B <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_89_fu_2690_p14),512));
else
bufo_Din_B <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufo_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_11001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_11001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_11001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufo_EN_A <= ap_const_logic_1;
else
bufo_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_EN_B_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_11001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_11001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_11001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufo_EN_B <= ap_const_logic_1;
else
bufo_EN_B <= ap_const_logic_0;
end if;
end process;
bufo_Rst_A <= ap_rst_n_inv;
bufo_Rst_B <= ap_rst_n_inv;
bufo_WEN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_reg_pp0_iter7_exitcond_flatten1_reg_3176, ap_reg_pp0_iter9_exitcond_flatten1_reg_3176, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter9_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9)) or ((ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufo_WEN_A <= ap_const_lv64_FFFFFFFFFFFFFFFF;
else
bufo_WEN_A <= ap_const_lv64_0;
end if;
end process;
bufo_WEN_B_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_reg_pp0_iter7_exitcond_flatten1_reg_3176, ap_reg_pp0_iter9_exitcond_flatten1_reg_3176, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter9_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9)) or ((ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufo_WEN_B <= ap_const_lv64_FFFFFFFFFFFFFFFF;
else
bufo_WEN_B <= ap_const_lv64_0;
end if;
end process;
bufw_0_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_0_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_0_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_0_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_0_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_0_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_0_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_0_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_0_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_0_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_0_Clk_A <= ap_clk;
bufw_0_Clk_B <= ap_clk;
bufw_0_Din_A <= ap_const_lv32_0;
bufw_0_Din_B <= ap_const_lv32_0;
bufw_0_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_0_EN_A <= ap_const_logic_1;
else
bufw_0_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_0_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_0_EN_B <= ap_const_logic_1;
else
bufw_0_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_0_Rst_A <= ap_rst_n_inv;
bufw_0_Rst_B <= ap_rst_n_inv;
bufw_0_WEN_A <= ap_const_lv4_0;
bufw_0_WEN_B <= ap_const_lv4_0;
bufw_10_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_10_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_10_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_10_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_10_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_10_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_10_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_10_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_10_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_10_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_10_Clk_A <= ap_clk;
bufw_10_Clk_B <= ap_clk;
bufw_10_Din_A <= ap_const_lv32_0;
bufw_10_Din_B <= ap_const_lv32_0;
bufw_10_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_10_EN_A <= ap_const_logic_1;
else
bufw_10_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_10_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_10_EN_B <= ap_const_logic_1;
else
bufw_10_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_10_Rst_A <= ap_rst_n_inv;
bufw_10_Rst_B <= ap_rst_n_inv;
bufw_10_WEN_A <= ap_const_lv4_0;
bufw_10_WEN_B <= ap_const_lv4_0;
bufw_11_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_11_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_11_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_11_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_11_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_11_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_11_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_11_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_11_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_11_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_11_Clk_A <= ap_clk;
bufw_11_Clk_B <= ap_clk;
bufw_11_Din_A <= ap_const_lv32_0;
bufw_11_Din_B <= ap_const_lv32_0;
bufw_11_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_11_EN_A <= ap_const_logic_1;
else
bufw_11_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_11_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_11_EN_B <= ap_const_logic_1;
else
bufw_11_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_11_Rst_A <= ap_rst_n_inv;
bufw_11_Rst_B <= ap_rst_n_inv;
bufw_11_WEN_A <= ap_const_lv4_0;
bufw_11_WEN_B <= ap_const_lv4_0;
bufw_12_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_12_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_12_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_12_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_12_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_12_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_12_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_12_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_12_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_12_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_12_Clk_A <= ap_clk;
bufw_12_Clk_B <= ap_clk;
bufw_12_Din_A <= ap_const_lv32_0;
bufw_12_Din_B <= ap_const_lv32_0;
bufw_12_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_12_EN_A <= ap_const_logic_1;
else
bufw_12_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_12_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_12_EN_B <= ap_const_logic_1;
else
bufw_12_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_12_Rst_A <= ap_rst_n_inv;
bufw_12_Rst_B <= ap_rst_n_inv;
bufw_12_WEN_A <= ap_const_lv4_0;
bufw_12_WEN_B <= ap_const_lv4_0;
bufw_1_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_1_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_1_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_1_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_1_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_1_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_1_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_1_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_1_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_1_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_1_Clk_A <= ap_clk;
bufw_1_Clk_B <= ap_clk;
bufw_1_Din_A <= ap_const_lv32_0;
bufw_1_Din_B <= ap_const_lv32_0;
bufw_1_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_1_EN_A <= ap_const_logic_1;
else
bufw_1_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_1_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_1_EN_B <= ap_const_logic_1;
else
bufw_1_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_1_Rst_A <= ap_rst_n_inv;
bufw_1_Rst_B <= ap_rst_n_inv;
bufw_1_WEN_A <= ap_const_lv4_0;
bufw_1_WEN_B <= ap_const_lv4_0;
bufw_2_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_2_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_2_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_2_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_2_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_2_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_2_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_2_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_2_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_2_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_2_Clk_A <= ap_clk;
bufw_2_Clk_B <= ap_clk;
bufw_2_Din_A <= ap_const_lv32_0;
bufw_2_Din_B <= ap_const_lv32_0;
bufw_2_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_2_EN_A <= ap_const_logic_1;
else
bufw_2_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_2_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_2_EN_B <= ap_const_logic_1;
else
bufw_2_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_2_Rst_A <= ap_rst_n_inv;
bufw_2_Rst_B <= ap_rst_n_inv;
bufw_2_WEN_A <= ap_const_lv4_0;
bufw_2_WEN_B <= ap_const_lv4_0;
bufw_3_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_3_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_3_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_3_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_3_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_3_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_3_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_3_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_3_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_3_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_3_Clk_A <= ap_clk;
bufw_3_Clk_B <= ap_clk;
bufw_3_Din_A <= ap_const_lv32_0;
bufw_3_Din_B <= ap_const_lv32_0;
bufw_3_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_3_EN_A <= ap_const_logic_1;
else
bufw_3_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_3_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_3_EN_B <= ap_const_logic_1;
else
bufw_3_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_3_Rst_A <= ap_rst_n_inv;
bufw_3_Rst_B <= ap_rst_n_inv;
bufw_3_WEN_A <= ap_const_lv4_0;
bufw_3_WEN_B <= ap_const_lv4_0;
bufw_4_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_4_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_4_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_4_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_4_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_4_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_4_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_4_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_4_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_4_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_4_Clk_A <= ap_clk;
bufw_4_Clk_B <= ap_clk;
bufw_4_Din_A <= ap_const_lv32_0;
bufw_4_Din_B <= ap_const_lv32_0;
bufw_4_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_4_EN_A <= ap_const_logic_1;
else
bufw_4_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_4_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_4_EN_B <= ap_const_logic_1;
else
bufw_4_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_4_Rst_A <= ap_rst_n_inv;
bufw_4_Rst_B <= ap_rst_n_inv;
bufw_4_WEN_A <= ap_const_lv4_0;
bufw_4_WEN_B <= ap_const_lv4_0;
bufw_5_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_5_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_5_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_5_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_5_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_5_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_5_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_5_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_5_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_5_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_5_Clk_A <= ap_clk;
bufw_5_Clk_B <= ap_clk;
bufw_5_Din_A <= ap_const_lv32_0;
bufw_5_Din_B <= ap_const_lv32_0;
bufw_5_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_5_EN_A <= ap_const_logic_1;
else
bufw_5_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_5_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_5_EN_B <= ap_const_logic_1;
else
bufw_5_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_5_Rst_A <= ap_rst_n_inv;
bufw_5_Rst_B <= ap_rst_n_inv;
bufw_5_WEN_A <= ap_const_lv4_0;
bufw_5_WEN_B <= ap_const_lv4_0;
bufw_6_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_6_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_6_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_6_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_6_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_6_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_6_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_6_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_6_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_6_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_6_Clk_A <= ap_clk;
bufw_6_Clk_B <= ap_clk;
bufw_6_Din_A <= ap_const_lv32_0;
bufw_6_Din_B <= ap_const_lv32_0;
bufw_6_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_6_EN_A <= ap_const_logic_1;
else
bufw_6_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_6_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_6_EN_B <= ap_const_logic_1;
else
bufw_6_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_6_Rst_A <= ap_rst_n_inv;
bufw_6_Rst_B <= ap_rst_n_inv;
bufw_6_WEN_A <= ap_const_lv4_0;
bufw_6_WEN_B <= ap_const_lv4_0;
bufw_7_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_7_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_7_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_7_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_7_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_7_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_7_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_7_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_7_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_7_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_7_Clk_A <= ap_clk;
bufw_7_Clk_B <= ap_clk;
bufw_7_Din_A <= ap_const_lv32_0;
bufw_7_Din_B <= ap_const_lv32_0;
bufw_7_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_7_EN_A <= ap_const_logic_1;
else
bufw_7_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_7_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_7_EN_B <= ap_const_logic_1;
else
bufw_7_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_7_Rst_A <= ap_rst_n_inv;
bufw_7_Rst_B <= ap_rst_n_inv;
bufw_7_WEN_A <= ap_const_lv4_0;
bufw_7_WEN_B <= ap_const_lv4_0;
bufw_8_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_8_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_8_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_8_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_8_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_8_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_8_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_8_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_8_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_8_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_8_Clk_A <= ap_clk;
bufw_8_Clk_B <= ap_clk;
bufw_8_Din_A <= ap_const_lv32_0;
bufw_8_Din_B <= ap_const_lv32_0;
bufw_8_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_8_EN_A <= ap_const_logic_1;
else
bufw_8_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_8_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_8_EN_B <= ap_const_logic_1;
else
bufw_8_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_8_Rst_A <= ap_rst_n_inv;
bufw_8_Rst_B <= ap_rst_n_inv;
bufw_8_WEN_A <= ap_const_lv4_0;
bufw_8_WEN_B <= ap_const_lv4_0;
bufw_9_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_9_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_9_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_9_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_9_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_9_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_9_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_9_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_9_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_9_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_9_Clk_A <= ap_clk;
bufw_9_Clk_B <= ap_clk;
bufw_9_Din_A <= ap_const_lv32_0;
bufw_9_Din_B <= ap_const_lv32_0;
bufw_9_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_9_EN_A <= ap_const_logic_1;
else
bufw_9_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_9_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_9_EN_B <= ap_const_logic_1;
else
bufw_9_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_9_Rst_A <= ap_rst_n_inv;
bufw_9_Rst_B <= ap_rst_n_inv;
bufw_9_WEN_A <= ap_const_lv4_0;
bufw_9_WEN_B <= ap_const_lv4_0;
exitcond_flatten1_fu_1541_p2 <= "1" when (ap_phi_mux_indvar_flatten1_phi_fu_889_p4 = ap_const_lv10_2A3) else "0";
exitcond_flatten_fu_1559_p2 <= "1" when (ap_phi_mux_indvar_flatten_phi_fu_912_p4 = ap_const_lv8_87) else "0";
grp_fu_1003_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_57_fu_2225_p1, tmp_137_fu_2329_p1, tmp_217_fu_2433_p1, tmp_297_fu_2537_p1, ap_enable_reg_pp0_iter3, tmp_20_1_2_reg_7134, tmp_20_3_2_reg_7264, ap_enable_reg_pp0_iter5, tmp_20_1_2_1_reg_7654, tmp_20_3_2_1_reg_7784, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1003_p0 <= tmp_20_3_2_1_reg_7784;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1003_p0 <= tmp_20_1_2_1_reg_7654;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1003_p0 <= tmp_20_3_2_reg_7264;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1003_p0 <= tmp_20_1_2_reg_7134;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1003_p0 <= tmp_297_fu_2537_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1003_p0 <= tmp_217_fu_2433_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1003_p0 <= tmp_137_fu_2329_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1003_p0 <= tmp_57_fu_2225_p1;
else
grp_fu_1003_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1003_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_2_reg_4989, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_2_1_reg_5264, tmp_19_3_2_reg_5444, tmp_19_5_2_reg_5769, ap_reg_pp0_iter3_tmp_19_3_2_1_reg_5834, tmp_19_7_2_reg_6094, ap_reg_pp0_iter4_tmp_19_1_2_2_reg_6549, ap_reg_pp0_iter4_tmp_19_3_2_2_reg_6744, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1003_p1 <= ap_reg_pp0_iter4_tmp_19_3_2_2_reg_6744;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1003_p1 <= ap_reg_pp0_iter4_tmp_19_1_2_2_reg_6549;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1003_p1 <= ap_reg_pp0_iter3_tmp_19_3_2_1_reg_5834;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1003_p1 <= ap_reg_pp0_iter3_tmp_19_1_2_1_reg_5264;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1003_p1 <= tmp_19_7_2_reg_6094;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1003_p1 <= tmp_19_5_2_reg_5769;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1003_p1 <= tmp_19_3_2_reg_5444;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1003_p1 <= tmp_19_1_2_reg_4989;
else
grp_fu_1003_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1007_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_60_fu_2229_p1, tmp_140_fu_2333_p1, tmp_220_fu_2437_p1, tmp_300_fu_2541_p1, ap_enable_reg_pp0_iter3, tmp_20_1_3_reg_7139, tmp_20_3_3_reg_7269, ap_enable_reg_pp0_iter5, tmp_20_1_3_1_reg_7659, tmp_20_3_3_1_reg_7789, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1007_p0 <= tmp_20_3_3_1_reg_7789;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1007_p0 <= tmp_20_1_3_1_reg_7659;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1007_p0 <= tmp_20_3_3_reg_7269;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1007_p0 <= tmp_20_1_3_reg_7139;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1007_p0 <= tmp_300_fu_2541_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1007_p0 <= tmp_220_fu_2437_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1007_p0 <= tmp_140_fu_2333_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1007_p0 <= tmp_60_fu_2229_p1;
else
grp_fu_1007_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1007_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_3_reg_4994, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_3_1_reg_5274, tmp_19_3_3_reg_5449, tmp_19_5_3_reg_5774, ap_reg_pp0_iter3_tmp_19_3_3_1_reg_5839, tmp_19_7_3_reg_6099, ap_reg_pp0_iter4_tmp_19_1_3_2_reg_6554, ap_reg_pp0_iter4_tmp_19_3_3_2_reg_6749, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1007_p1 <= ap_reg_pp0_iter4_tmp_19_3_3_2_reg_6749;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1007_p1 <= ap_reg_pp0_iter4_tmp_19_1_3_2_reg_6554;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1007_p1 <= ap_reg_pp0_iter3_tmp_19_3_3_1_reg_5839;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1007_p1 <= ap_reg_pp0_iter3_tmp_19_1_3_1_reg_5274;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1007_p1 <= tmp_19_7_3_reg_6099;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1007_p1 <= tmp_19_5_3_reg_5774;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1007_p1 <= tmp_19_3_3_reg_5449;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1007_p1 <= tmp_19_1_3_reg_4994;
else
grp_fu_1007_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1011_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_63_fu_2233_p1, tmp_143_fu_2337_p1, tmp_223_fu_2441_p1, tmp_303_fu_2545_p1, ap_enable_reg_pp0_iter3, tmp_20_1_4_reg_7144, tmp_20_3_4_reg_7274, ap_enable_reg_pp0_iter5, tmp_20_1_4_1_reg_7664, tmp_20_3_4_1_reg_7794, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1011_p0 <= tmp_20_3_4_1_reg_7794;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1011_p0 <= tmp_20_1_4_1_reg_7664;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1011_p0 <= tmp_20_3_4_reg_7274;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1011_p0 <= tmp_20_1_4_reg_7144;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1011_p0 <= tmp_303_fu_2545_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1011_p0 <= tmp_223_fu_2441_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1011_p0 <= tmp_143_fu_2337_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1011_p0 <= tmp_63_fu_2233_p1;
else
grp_fu_1011_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1011_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_4_reg_4999, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_4_1_reg_5284, tmp_19_3_4_reg_5454, tmp_19_5_4_reg_5779, ap_reg_pp0_iter3_tmp_19_3_4_1_reg_5844, tmp_19_7_4_reg_6104, ap_reg_pp0_iter4_tmp_19_1_4_2_reg_6559, ap_reg_pp0_iter4_tmp_19_3_4_2_reg_6754, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1011_p1 <= ap_reg_pp0_iter4_tmp_19_3_4_2_reg_6754;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1011_p1 <= ap_reg_pp0_iter4_tmp_19_1_4_2_reg_6559;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1011_p1 <= ap_reg_pp0_iter3_tmp_19_3_4_1_reg_5844;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1011_p1 <= ap_reg_pp0_iter3_tmp_19_1_4_1_reg_5284;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1011_p1 <= tmp_19_7_4_reg_6104;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1011_p1 <= tmp_19_5_4_reg_5779;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1011_p1 <= tmp_19_3_4_reg_5454;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1011_p1 <= tmp_19_1_4_reg_4999;
else
grp_fu_1011_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1015_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_66_fu_2237_p1, tmp_146_fu_2341_p1, tmp_226_fu_2445_p1, tmp_306_fu_2549_p1, ap_enable_reg_pp0_iter3, tmp_20_1_5_reg_7149, tmp_20_3_5_reg_7279, ap_enable_reg_pp0_iter5, tmp_20_1_5_1_reg_7669, tmp_20_3_5_1_reg_7799, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1015_p0 <= tmp_20_3_5_1_reg_7799;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1015_p0 <= tmp_20_1_5_1_reg_7669;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1015_p0 <= tmp_20_3_5_reg_7279;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1015_p0 <= tmp_20_1_5_reg_7149;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1015_p0 <= tmp_306_fu_2549_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1015_p0 <= tmp_226_fu_2445_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1015_p0 <= tmp_146_fu_2341_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1015_p0 <= tmp_66_fu_2237_p1;
else
grp_fu_1015_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1015_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_5_reg_5004, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_5_1_reg_5294, tmp_19_3_5_reg_5459, tmp_19_5_5_reg_5784, ap_reg_pp0_iter3_tmp_19_3_5_1_reg_5849, tmp_19_7_5_reg_6109, ap_reg_pp0_iter4_tmp_19_1_5_2_reg_6564, ap_reg_pp0_iter4_tmp_19_3_5_2_reg_6759, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1015_p1 <= ap_reg_pp0_iter4_tmp_19_3_5_2_reg_6759;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1015_p1 <= ap_reg_pp0_iter4_tmp_19_1_5_2_reg_6564;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1015_p1 <= ap_reg_pp0_iter3_tmp_19_3_5_1_reg_5849;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1015_p1 <= ap_reg_pp0_iter3_tmp_19_1_5_1_reg_5294;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1015_p1 <= tmp_19_7_5_reg_6109;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1015_p1 <= tmp_19_5_5_reg_5784;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1015_p1 <= tmp_19_3_5_reg_5459;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1015_p1 <= tmp_19_1_5_reg_5004;
else
grp_fu_1015_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1019_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_69_fu_2241_p1, tmp_149_fu_2345_p1, tmp_229_fu_2449_p1, tmp_309_fu_2553_p1, ap_enable_reg_pp0_iter3, tmp_20_1_6_reg_7154, tmp_20_3_6_reg_7284, ap_enable_reg_pp0_iter5, tmp_20_1_6_1_reg_7674, tmp_20_3_6_1_reg_7804, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1019_p0 <= tmp_20_3_6_1_reg_7804;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1019_p0 <= tmp_20_1_6_1_reg_7674;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1019_p0 <= tmp_20_3_6_reg_7284;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1019_p0 <= tmp_20_1_6_reg_7154;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1019_p0 <= tmp_309_fu_2553_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1019_p0 <= tmp_229_fu_2449_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1019_p0 <= tmp_149_fu_2345_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1019_p0 <= tmp_69_fu_2241_p1;
else
grp_fu_1019_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1019_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_6_reg_5009, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_6_1_reg_5304, tmp_19_3_6_reg_5464, tmp_19_5_6_reg_5789, ap_reg_pp0_iter3_tmp_19_3_6_1_reg_5854, tmp_19_7_6_reg_6114, ap_reg_pp0_iter4_tmp_19_1_6_2_reg_6569, ap_reg_pp0_iter4_tmp_19_3_6_2_reg_6764, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1019_p1 <= ap_reg_pp0_iter4_tmp_19_3_6_2_reg_6764;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1019_p1 <= ap_reg_pp0_iter4_tmp_19_1_6_2_reg_6569;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1019_p1 <= ap_reg_pp0_iter3_tmp_19_3_6_1_reg_5854;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1019_p1 <= ap_reg_pp0_iter3_tmp_19_1_6_1_reg_5304;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1019_p1 <= tmp_19_7_6_reg_6114;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1019_p1 <= tmp_19_5_6_reg_5789;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1019_p1 <= tmp_19_3_6_reg_5464;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1019_p1 <= tmp_19_1_6_reg_5009;
else
grp_fu_1019_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1023_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_72_fu_2245_p1, tmp_152_fu_2349_p1, tmp_232_fu_2453_p1, tmp_312_fu_2557_p1, ap_enable_reg_pp0_iter3, tmp_20_1_7_reg_7159, tmp_20_3_7_reg_7289, ap_enable_reg_pp0_iter5, tmp_20_1_7_1_reg_7679, tmp_20_3_7_1_reg_7809, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1023_p0 <= tmp_20_3_7_1_reg_7809;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1023_p0 <= tmp_20_1_7_1_reg_7679;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1023_p0 <= tmp_20_3_7_reg_7289;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1023_p0 <= tmp_20_1_7_reg_7159;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1023_p0 <= tmp_312_fu_2557_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1023_p0 <= tmp_232_fu_2453_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1023_p0 <= tmp_152_fu_2349_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1023_p0 <= tmp_72_fu_2245_p1;
else
grp_fu_1023_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1023_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_7_reg_5014, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_7_1_reg_5314, tmp_19_3_7_reg_5469, tmp_19_5_7_reg_5794, ap_reg_pp0_iter3_tmp_19_3_7_1_reg_5859, tmp_19_7_7_reg_6119, ap_reg_pp0_iter4_tmp_19_1_7_2_reg_6574, ap_reg_pp0_iter4_tmp_19_3_7_2_reg_6769, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1023_p1 <= ap_reg_pp0_iter4_tmp_19_3_7_2_reg_6769;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1023_p1 <= ap_reg_pp0_iter4_tmp_19_1_7_2_reg_6574;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1023_p1 <= ap_reg_pp0_iter3_tmp_19_3_7_1_reg_5859;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1023_p1 <= ap_reg_pp0_iter3_tmp_19_1_7_1_reg_5314;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1023_p1 <= tmp_19_7_7_reg_6119;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1023_p1 <= tmp_19_5_7_reg_5794;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1023_p1 <= tmp_19_3_7_reg_5469;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1023_p1 <= tmp_19_1_7_reg_5014;
else
grp_fu_1023_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1027_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_75_fu_2249_p1, tmp_155_fu_2353_p1, tmp_235_fu_2457_p1, tmp_315_fu_2561_p1, ap_enable_reg_pp0_iter3, tmp_20_1_8_reg_7164, tmp_20_3_8_reg_7294, ap_enable_reg_pp0_iter5, tmp_20_1_8_1_reg_7684, tmp_20_3_8_1_reg_7814, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1027_p0 <= tmp_20_3_8_1_reg_7814;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1027_p0 <= tmp_20_1_8_1_reg_7684;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1027_p0 <= tmp_20_3_8_reg_7294;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1027_p0 <= tmp_20_1_8_reg_7164;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1027_p0 <= tmp_315_fu_2561_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1027_p0 <= tmp_235_fu_2457_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1027_p0 <= tmp_155_fu_2353_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1027_p0 <= tmp_75_fu_2249_p1;
else
grp_fu_1027_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1027_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_8_reg_5019, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_8_1_reg_5324, tmp_19_3_8_reg_5474, tmp_19_5_8_reg_5799, ap_reg_pp0_iter3_tmp_19_3_8_1_reg_5864, tmp_19_7_8_reg_6124, ap_reg_pp0_iter4_tmp_19_1_8_2_reg_6579, ap_reg_pp0_iter4_tmp_19_3_8_2_reg_6774, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1027_p1 <= ap_reg_pp0_iter4_tmp_19_3_8_2_reg_6774;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1027_p1 <= ap_reg_pp0_iter4_tmp_19_1_8_2_reg_6579;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1027_p1 <= ap_reg_pp0_iter3_tmp_19_3_8_1_reg_5864;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1027_p1 <= ap_reg_pp0_iter3_tmp_19_1_8_1_reg_5324;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1027_p1 <= tmp_19_7_8_reg_6124;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1027_p1 <= tmp_19_5_8_reg_5799;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1027_p1 <= tmp_19_3_8_reg_5474;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1027_p1 <= tmp_19_1_8_reg_5019;
else
grp_fu_1027_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1031_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_78_fu_2253_p1, tmp_158_fu_2357_p1, tmp_238_fu_2461_p1, tmp_318_fu_2565_p1, ap_enable_reg_pp0_iter3, tmp_20_1_9_reg_7169, tmp_20_3_9_reg_7299, ap_enable_reg_pp0_iter5, tmp_20_1_9_1_reg_7689, tmp_20_3_9_1_reg_7819, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1031_p0 <= tmp_20_3_9_1_reg_7819;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1031_p0 <= tmp_20_1_9_1_reg_7689;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1031_p0 <= tmp_20_3_9_reg_7299;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1031_p0 <= tmp_20_1_9_reg_7169;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1031_p0 <= tmp_318_fu_2565_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1031_p0 <= tmp_238_fu_2461_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1031_p0 <= tmp_158_fu_2357_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1031_p0 <= tmp_78_fu_2253_p1;
else
grp_fu_1031_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1031_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_9_reg_5024, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_9_1_reg_5334, tmp_19_3_9_reg_5479, tmp_19_5_9_reg_5804, ap_reg_pp0_iter3_tmp_19_3_9_1_reg_5869, tmp_19_7_9_reg_6129, ap_reg_pp0_iter4_tmp_19_1_9_2_reg_6584, ap_reg_pp0_iter4_tmp_19_3_9_2_reg_6779, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1031_p1 <= ap_reg_pp0_iter4_tmp_19_3_9_2_reg_6779;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1031_p1 <= ap_reg_pp0_iter4_tmp_19_1_9_2_reg_6584;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1031_p1 <= ap_reg_pp0_iter3_tmp_19_3_9_1_reg_5869;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1031_p1 <= ap_reg_pp0_iter3_tmp_19_1_9_1_reg_5334;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1031_p1 <= tmp_19_7_9_reg_6129;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1031_p1 <= tmp_19_5_9_reg_5804;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1031_p1 <= tmp_19_3_9_reg_5479;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1031_p1 <= tmp_19_1_9_reg_5024;
else
grp_fu_1031_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1035_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_81_fu_2257_p1, tmp_161_fu_2361_p1, tmp_241_fu_2465_p1, tmp_321_fu_2569_p1, ap_enable_reg_pp0_iter3, tmp_20_1_s_reg_7174, tmp_20_3_s_reg_7304, ap_enable_reg_pp0_iter5, tmp_20_1_10_1_reg_7694, tmp_20_3_10_1_reg_7824, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1035_p0 <= tmp_20_3_10_1_reg_7824;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1035_p0 <= tmp_20_1_10_1_reg_7694;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1035_p0 <= tmp_20_3_s_reg_7304;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1035_p0 <= tmp_20_1_s_reg_7174;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1035_p0 <= tmp_321_fu_2569_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1035_p0 <= tmp_241_fu_2465_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1035_p0 <= tmp_161_fu_2361_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1035_p0 <= tmp_81_fu_2257_p1;
else
grp_fu_1035_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1035_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_s_reg_5029, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_10_1_reg_5344, tmp_19_3_s_reg_5484, tmp_19_5_s_reg_5809, ap_reg_pp0_iter3_tmp_19_3_10_1_reg_5874, tmp_19_7_s_reg_6134, ap_reg_pp0_iter4_tmp_19_1_10_2_reg_6589, ap_reg_pp0_iter4_tmp_19_3_10_2_reg_6784, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1035_p1 <= ap_reg_pp0_iter4_tmp_19_3_10_2_reg_6784;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1035_p1 <= ap_reg_pp0_iter4_tmp_19_1_10_2_reg_6589;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1035_p1 <= ap_reg_pp0_iter3_tmp_19_3_10_1_reg_5874;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1035_p1 <= ap_reg_pp0_iter3_tmp_19_1_10_1_reg_5344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1035_p1 <= tmp_19_7_s_reg_6134;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1035_p1 <= tmp_19_5_s_reg_5809;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1035_p1 <= tmp_19_3_s_reg_5484;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1035_p1 <= tmp_19_1_s_reg_5029;
else
grp_fu_1035_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1039_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_84_fu_2261_p1, tmp_164_fu_2365_p1, tmp_244_fu_2469_p1, tmp_324_fu_2573_p1, ap_enable_reg_pp0_iter3, tmp_20_1_10_reg_7179, tmp_20_3_10_reg_7309, ap_enable_reg_pp0_iter5, tmp_20_1_11_1_reg_7699, tmp_20_3_11_1_reg_7829, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1039_p0 <= tmp_20_3_11_1_reg_7829;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1039_p0 <= tmp_20_1_11_1_reg_7699;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1039_p0 <= tmp_20_3_10_reg_7309;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1039_p0 <= tmp_20_1_10_reg_7179;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1039_p0 <= tmp_324_fu_2573_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1039_p0 <= tmp_244_fu_2469_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1039_p0 <= tmp_164_fu_2365_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1039_p0 <= tmp_84_fu_2261_p1;
else
grp_fu_1039_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1039_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_10_reg_5034, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_11_1_reg_5354, tmp_19_3_10_reg_5489, tmp_19_5_10_reg_5814, ap_reg_pp0_iter3_tmp_19_3_11_1_reg_5879, tmp_19_7_10_reg_6139, ap_reg_pp0_iter4_tmp_19_1_11_2_reg_6594, ap_reg_pp0_iter4_tmp_19_3_11_2_reg_6789, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1039_p1 <= ap_reg_pp0_iter4_tmp_19_3_11_2_reg_6789;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1039_p1 <= ap_reg_pp0_iter4_tmp_19_1_11_2_reg_6594;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1039_p1 <= ap_reg_pp0_iter3_tmp_19_3_11_1_reg_5879;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1039_p1 <= ap_reg_pp0_iter3_tmp_19_1_11_1_reg_5354;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1039_p1 <= tmp_19_7_10_reg_6139;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1039_p1 <= tmp_19_5_10_reg_5814;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1039_p1 <= tmp_19_3_10_reg_5489;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1039_p1 <= tmp_19_1_10_reg_5034;
else
grp_fu_1039_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1043_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_87_fu_2265_p1, tmp_167_fu_2369_p1, tmp_247_fu_2473_p1, tmp_327_fu_2577_p1, ap_enable_reg_pp0_iter3, tmp_20_1_11_reg_7184, tmp_20_3_11_reg_7314, ap_enable_reg_pp0_iter5, tmp_20_1_12_1_reg_7704, tmp_20_3_12_1_reg_7834, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1043_p0 <= tmp_20_3_12_1_reg_7834;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1043_p0 <= tmp_20_1_12_1_reg_7704;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1043_p0 <= tmp_20_3_11_reg_7314;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1043_p0 <= tmp_20_1_11_reg_7184;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1043_p0 <= tmp_327_fu_2577_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1043_p0 <= tmp_247_fu_2473_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1043_p0 <= tmp_167_fu_2369_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1043_p0 <= tmp_87_fu_2265_p1;
else
grp_fu_1043_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1043_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_11_reg_5039, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_12_1_reg_5364, tmp_19_3_11_reg_5494, tmp_19_5_11_reg_5819, ap_reg_pp0_iter3_tmp_19_3_12_1_reg_5884, tmp_19_7_11_reg_6144, ap_reg_pp0_iter4_tmp_19_1_12_2_reg_6599, ap_reg_pp0_iter4_tmp_19_3_12_2_reg_6794, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1043_p1 <= ap_reg_pp0_iter4_tmp_19_3_12_2_reg_6794;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1043_p1 <= ap_reg_pp0_iter4_tmp_19_1_12_2_reg_6599;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1043_p1 <= ap_reg_pp0_iter3_tmp_19_3_12_1_reg_5884;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1043_p1 <= ap_reg_pp0_iter3_tmp_19_1_12_1_reg_5364;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1043_p1 <= tmp_19_7_11_reg_6144;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1043_p1 <= tmp_19_5_11_reg_5819;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1043_p1 <= tmp_19_3_11_reg_5494;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1043_p1 <= tmp_19_1_11_reg_5039;
else
grp_fu_1043_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1047_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_reg_7319, tmp_20_5_reg_7384, tmp_20_6_reg_7449, ap_enable_reg_pp0_iter4, tmp_20_7_reg_7514, ap_enable_reg_pp0_iter5, tmp_20_4_0_1_reg_7839, tmp_20_5_0_1_reg_7904, tmp_20_6_0_1_reg_7969, tmp_20_7_0_1_reg_8034, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1047_p0 <= tmp_20_7_0_1_reg_8034;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1047_p0 <= tmp_20_6_0_1_reg_7969;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1047_p0 <= tmp_20_5_0_1_reg_7904;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1047_p0 <= tmp_20_4_0_1_reg_7839;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1047_p0 <= tmp_20_7_reg_7514;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1047_p0 <= tmp_20_6_reg_7449;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1047_p0 <= tmp_20_5_reg_7384;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1047_p0 <= tmp_20_4_reg_7319;
else
grp_fu_1047_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1047_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_0_1_reg_6149, ap_reg_pp0_iter3_tmp_19_5_0_1_reg_6214, ap_reg_pp0_iter3_tmp_19_6_0_1_reg_6284, ap_reg_pp0_iter3_tmp_19_7_0_1_reg_6604, ap_reg_pp0_iter5_tmp_19_4_0_2_reg_6799, ap_reg_pp0_iter5_tmp_19_5_0_2_reg_6864, ap_reg_pp0_iter5_tmp_19_6_0_2_reg_6929, ap_reg_pp0_iter5_tmp_19_7_0_2_reg_6994, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1047_p1 <= ap_reg_pp0_iter5_tmp_19_7_0_2_reg_6994;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1047_p1 <= ap_reg_pp0_iter5_tmp_19_6_0_2_reg_6929;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1047_p1 <= ap_reg_pp0_iter5_tmp_19_5_0_2_reg_6864;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1047_p1 <= ap_reg_pp0_iter5_tmp_19_4_0_2_reg_6799;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1047_p1 <= ap_reg_pp0_iter3_tmp_19_7_0_1_reg_6604;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1047_p1 <= ap_reg_pp0_iter3_tmp_19_6_0_1_reg_6284;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1047_p1 <= ap_reg_pp0_iter3_tmp_19_5_0_1_reg_6214;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1047_p1 <= ap_reg_pp0_iter3_tmp_19_4_0_1_reg_6149;
else
grp_fu_1047_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1051_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_1_reg_7324, tmp_20_5_1_reg_7389, ap_enable_reg_pp0_iter4, tmp_20_6_1_reg_7454, tmp_20_7_1_reg_7519, ap_enable_reg_pp0_iter5, tmp_20_4_1_1_reg_7844, tmp_20_5_1_1_reg_7909, tmp_20_6_1_1_reg_7974, ap_enable_reg_pp0_iter6, tmp_20_7_1_1_reg_8039, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1051_p0 <= tmp_20_7_1_1_reg_8039;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1051_p0 <= tmp_20_6_1_1_reg_7974;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1051_p0 <= tmp_20_5_1_1_reg_7909;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1051_p0 <= tmp_20_4_1_1_reg_7844;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1051_p0 <= tmp_20_7_1_reg_7519;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1051_p0 <= tmp_20_6_1_reg_7454;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1051_p0 <= tmp_20_5_1_reg_7389;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1051_p0 <= tmp_20_4_1_reg_7324;
else
grp_fu_1051_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1051_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_1_1_reg_6154, ap_reg_pp0_iter3_tmp_19_5_1_1_reg_6219, ap_reg_pp0_iter3_tmp_19_6_1_1_reg_6294, ap_reg_pp0_iter3_tmp_19_7_1_1_reg_6609, ap_reg_pp0_iter5_tmp_19_4_1_2_reg_6804, ap_reg_pp0_iter5_tmp_19_5_1_2_reg_6869, ap_reg_pp0_iter5_tmp_19_6_1_2_reg_6934, ap_reg_pp0_iter5_tmp_19_7_1_2_reg_6999, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1051_p1 <= ap_reg_pp0_iter5_tmp_19_7_1_2_reg_6999;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1051_p1 <= ap_reg_pp0_iter5_tmp_19_6_1_2_reg_6934;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1051_p1 <= ap_reg_pp0_iter5_tmp_19_5_1_2_reg_6869;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1051_p1 <= ap_reg_pp0_iter5_tmp_19_4_1_2_reg_6804;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1051_p1 <= ap_reg_pp0_iter3_tmp_19_7_1_1_reg_6609;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1051_p1 <= ap_reg_pp0_iter3_tmp_19_6_1_1_reg_6294;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1051_p1 <= ap_reg_pp0_iter3_tmp_19_5_1_1_reg_6219;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1051_p1 <= ap_reg_pp0_iter3_tmp_19_4_1_1_reg_6154;
else
grp_fu_1051_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1055_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_2_reg_7329, tmp_20_5_2_reg_7394, ap_enable_reg_pp0_iter4, tmp_20_6_2_reg_7459, tmp_20_7_2_reg_7524, ap_enable_reg_pp0_iter5, tmp_20_4_2_1_reg_7849, tmp_20_5_2_1_reg_7914, tmp_20_6_2_1_reg_7979, ap_enable_reg_pp0_iter6, tmp_20_7_2_1_reg_8044, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1055_p0 <= tmp_20_7_2_1_reg_8044;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1055_p0 <= tmp_20_6_2_1_reg_7979;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1055_p0 <= tmp_20_5_2_1_reg_7914;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1055_p0 <= tmp_20_4_2_1_reg_7849;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1055_p0 <= tmp_20_7_2_reg_7524;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1055_p0 <= tmp_20_6_2_reg_7459;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1055_p0 <= tmp_20_5_2_reg_7394;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1055_p0 <= tmp_20_4_2_reg_7329;
else
grp_fu_1055_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1055_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_2_1_reg_6159, ap_reg_pp0_iter3_tmp_19_5_2_1_reg_6224, ap_reg_pp0_iter3_tmp_19_6_2_1_reg_6304, ap_reg_pp0_iter3_tmp_19_7_2_1_reg_6614, ap_reg_pp0_iter5_tmp_19_4_2_2_reg_6809, ap_reg_pp0_iter5_tmp_19_5_2_2_reg_6874, ap_reg_pp0_iter5_tmp_19_6_2_2_reg_6939, ap_reg_pp0_iter5_tmp_19_7_2_2_reg_7004, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1055_p1 <= ap_reg_pp0_iter5_tmp_19_7_2_2_reg_7004;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1055_p1 <= ap_reg_pp0_iter5_tmp_19_6_2_2_reg_6939;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1055_p1 <= ap_reg_pp0_iter5_tmp_19_5_2_2_reg_6874;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1055_p1 <= ap_reg_pp0_iter5_tmp_19_4_2_2_reg_6809;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1055_p1 <= ap_reg_pp0_iter3_tmp_19_7_2_1_reg_6614;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1055_p1 <= ap_reg_pp0_iter3_tmp_19_6_2_1_reg_6304;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1055_p1 <= ap_reg_pp0_iter3_tmp_19_5_2_1_reg_6224;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1055_p1 <= ap_reg_pp0_iter3_tmp_19_4_2_1_reg_6159;
else
grp_fu_1055_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1059_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_3_reg_7334, tmp_20_5_3_reg_7399, ap_enable_reg_pp0_iter4, tmp_20_6_3_reg_7464, tmp_20_7_3_reg_7529, ap_enable_reg_pp0_iter5, tmp_20_4_3_1_reg_7854, tmp_20_5_3_1_reg_7919, tmp_20_6_3_1_reg_7984, ap_enable_reg_pp0_iter6, tmp_20_7_3_1_reg_8049, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1059_p0 <= tmp_20_7_3_1_reg_8049;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1059_p0 <= tmp_20_6_3_1_reg_7984;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1059_p0 <= tmp_20_5_3_1_reg_7919;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1059_p0 <= tmp_20_4_3_1_reg_7854;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1059_p0 <= tmp_20_7_3_reg_7529;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1059_p0 <= tmp_20_6_3_reg_7464;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1059_p0 <= tmp_20_5_3_reg_7399;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1059_p0 <= tmp_20_4_3_reg_7334;
else
grp_fu_1059_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1059_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_3_1_reg_6164, ap_reg_pp0_iter3_tmp_19_5_3_1_reg_6229, ap_reg_pp0_iter3_tmp_19_6_3_1_reg_6314, ap_reg_pp0_iter3_tmp_19_7_3_1_reg_6619, ap_reg_pp0_iter5_tmp_19_4_3_2_reg_6814, ap_reg_pp0_iter5_tmp_19_5_3_2_reg_6879, ap_reg_pp0_iter5_tmp_19_6_3_2_reg_6944, ap_reg_pp0_iter5_tmp_19_7_3_2_reg_7009, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1059_p1 <= ap_reg_pp0_iter5_tmp_19_7_3_2_reg_7009;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1059_p1 <= ap_reg_pp0_iter5_tmp_19_6_3_2_reg_6944;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1059_p1 <= ap_reg_pp0_iter5_tmp_19_5_3_2_reg_6879;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1059_p1 <= ap_reg_pp0_iter5_tmp_19_4_3_2_reg_6814;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1059_p1 <= ap_reg_pp0_iter3_tmp_19_7_3_1_reg_6619;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1059_p1 <= ap_reg_pp0_iter3_tmp_19_6_3_1_reg_6314;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1059_p1 <= ap_reg_pp0_iter3_tmp_19_5_3_1_reg_6229;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1059_p1 <= ap_reg_pp0_iter3_tmp_19_4_3_1_reg_6164;
else
grp_fu_1059_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1063_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_4_reg_7339, tmp_20_5_4_reg_7404, ap_enable_reg_pp0_iter4, tmp_20_6_4_reg_7469, tmp_20_7_4_reg_7534, ap_enable_reg_pp0_iter5, tmp_20_4_4_1_reg_7859, tmp_20_5_4_1_reg_7924, tmp_20_6_4_1_reg_7989, ap_enable_reg_pp0_iter6, tmp_20_7_4_1_reg_8054, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1063_p0 <= tmp_20_7_4_1_reg_8054;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1063_p0 <= tmp_20_6_4_1_reg_7989;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1063_p0 <= tmp_20_5_4_1_reg_7924;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1063_p0 <= tmp_20_4_4_1_reg_7859;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1063_p0 <= tmp_20_7_4_reg_7534;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1063_p0 <= tmp_20_6_4_reg_7469;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1063_p0 <= tmp_20_5_4_reg_7404;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1063_p0 <= tmp_20_4_4_reg_7339;
else
grp_fu_1063_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1063_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_4_1_reg_6169, ap_reg_pp0_iter3_tmp_19_5_4_1_reg_6234, ap_reg_pp0_iter3_tmp_19_6_4_1_reg_6324, ap_reg_pp0_iter3_tmp_19_7_4_1_reg_6624, ap_reg_pp0_iter5_tmp_19_4_4_2_reg_6819, ap_reg_pp0_iter5_tmp_19_5_4_2_reg_6884, ap_reg_pp0_iter5_tmp_19_6_4_2_reg_6949, ap_reg_pp0_iter5_tmp_19_7_4_2_reg_7014, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1063_p1 <= ap_reg_pp0_iter5_tmp_19_7_4_2_reg_7014;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1063_p1 <= ap_reg_pp0_iter5_tmp_19_6_4_2_reg_6949;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1063_p1 <= ap_reg_pp0_iter5_tmp_19_5_4_2_reg_6884;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1063_p1 <= ap_reg_pp0_iter5_tmp_19_4_4_2_reg_6819;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1063_p1 <= ap_reg_pp0_iter3_tmp_19_7_4_1_reg_6624;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1063_p1 <= ap_reg_pp0_iter3_tmp_19_6_4_1_reg_6324;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1063_p1 <= ap_reg_pp0_iter3_tmp_19_5_4_1_reg_6234;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1063_p1 <= ap_reg_pp0_iter3_tmp_19_4_4_1_reg_6169;
else
grp_fu_1063_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1067_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_5_reg_7344, tmp_20_5_5_reg_7409, ap_enable_reg_pp0_iter4, tmp_20_6_5_reg_7474, tmp_20_7_5_reg_7539, ap_enable_reg_pp0_iter5, tmp_20_4_5_1_reg_7864, tmp_20_5_5_1_reg_7929, tmp_20_6_5_1_reg_7994, ap_enable_reg_pp0_iter6, tmp_20_7_5_1_reg_8059, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1067_p0 <= tmp_20_7_5_1_reg_8059;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1067_p0 <= tmp_20_6_5_1_reg_7994;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1067_p0 <= tmp_20_5_5_1_reg_7929;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1067_p0 <= tmp_20_4_5_1_reg_7864;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1067_p0 <= tmp_20_7_5_reg_7539;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1067_p0 <= tmp_20_6_5_reg_7474;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1067_p0 <= tmp_20_5_5_reg_7409;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1067_p0 <= tmp_20_4_5_reg_7344;
else
grp_fu_1067_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1067_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_5_1_reg_6174, ap_reg_pp0_iter3_tmp_19_5_5_1_reg_6239, ap_reg_pp0_iter3_tmp_19_6_5_1_reg_6334, ap_reg_pp0_iter3_tmp_19_7_5_1_reg_6629, ap_reg_pp0_iter5_tmp_19_4_5_2_reg_6824, ap_reg_pp0_iter5_tmp_19_5_5_2_reg_6889, ap_reg_pp0_iter5_tmp_19_6_5_2_reg_6954, ap_reg_pp0_iter5_tmp_19_7_5_2_reg_7019, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1067_p1 <= ap_reg_pp0_iter5_tmp_19_7_5_2_reg_7019;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1067_p1 <= ap_reg_pp0_iter5_tmp_19_6_5_2_reg_6954;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1067_p1 <= ap_reg_pp0_iter5_tmp_19_5_5_2_reg_6889;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1067_p1 <= ap_reg_pp0_iter5_tmp_19_4_5_2_reg_6824;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1067_p1 <= ap_reg_pp0_iter3_tmp_19_7_5_1_reg_6629;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1067_p1 <= ap_reg_pp0_iter3_tmp_19_6_5_1_reg_6334;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1067_p1 <= ap_reg_pp0_iter3_tmp_19_5_5_1_reg_6239;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1067_p1 <= ap_reg_pp0_iter3_tmp_19_4_5_1_reg_6174;
else
grp_fu_1067_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1071_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_6_reg_7349, tmp_20_5_6_reg_7414, ap_enable_reg_pp0_iter4, tmp_20_6_6_reg_7479, tmp_20_7_6_reg_7544, ap_enable_reg_pp0_iter5, tmp_20_4_6_1_reg_7869, tmp_20_5_6_1_reg_7934, tmp_20_6_6_1_reg_7999, ap_enable_reg_pp0_iter6, tmp_20_7_6_1_reg_8064, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1071_p0 <= tmp_20_7_6_1_reg_8064;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1071_p0 <= tmp_20_6_6_1_reg_7999;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1071_p0 <= tmp_20_5_6_1_reg_7934;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1071_p0 <= tmp_20_4_6_1_reg_7869;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1071_p0 <= tmp_20_7_6_reg_7544;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1071_p0 <= tmp_20_6_6_reg_7479;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1071_p0 <= tmp_20_5_6_reg_7414;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1071_p0 <= tmp_20_4_6_reg_7349;
else
grp_fu_1071_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1071_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_6_1_reg_6179, ap_reg_pp0_iter3_tmp_19_5_6_1_reg_6244, ap_reg_pp0_iter3_tmp_19_6_6_1_reg_6344, ap_reg_pp0_iter3_tmp_19_7_6_1_reg_6634, ap_reg_pp0_iter5_tmp_19_4_6_2_reg_6829, ap_reg_pp0_iter5_tmp_19_5_6_2_reg_6894, ap_reg_pp0_iter5_tmp_19_6_6_2_reg_6959, ap_reg_pp0_iter5_tmp_19_7_6_2_reg_7024, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1071_p1 <= ap_reg_pp0_iter5_tmp_19_7_6_2_reg_7024;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1071_p1 <= ap_reg_pp0_iter5_tmp_19_6_6_2_reg_6959;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1071_p1 <= ap_reg_pp0_iter5_tmp_19_5_6_2_reg_6894;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1071_p1 <= ap_reg_pp0_iter5_tmp_19_4_6_2_reg_6829;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1071_p1 <= ap_reg_pp0_iter3_tmp_19_7_6_1_reg_6634;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1071_p1 <= ap_reg_pp0_iter3_tmp_19_6_6_1_reg_6344;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1071_p1 <= ap_reg_pp0_iter3_tmp_19_5_6_1_reg_6244;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1071_p1 <= ap_reg_pp0_iter3_tmp_19_4_6_1_reg_6179;
else
grp_fu_1071_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1075_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_7_reg_7354, tmp_20_5_7_reg_7419, ap_enable_reg_pp0_iter4, tmp_20_6_7_reg_7484, tmp_20_7_7_reg_7549, ap_enable_reg_pp0_iter5, tmp_20_4_7_1_reg_7874, tmp_20_5_7_1_reg_7939, tmp_20_6_7_1_reg_8004, ap_enable_reg_pp0_iter6, tmp_20_7_7_1_reg_8069, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1075_p0 <= tmp_20_7_7_1_reg_8069;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1075_p0 <= tmp_20_6_7_1_reg_8004;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1075_p0 <= tmp_20_5_7_1_reg_7939;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1075_p0 <= tmp_20_4_7_1_reg_7874;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1075_p0 <= tmp_20_7_7_reg_7549;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1075_p0 <= tmp_20_6_7_reg_7484;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1075_p0 <= tmp_20_5_7_reg_7419;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1075_p0 <= tmp_20_4_7_reg_7354;
else
grp_fu_1075_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1075_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_7_1_reg_6184, ap_reg_pp0_iter3_tmp_19_5_7_1_reg_6249, ap_reg_pp0_iter3_tmp_19_6_7_1_reg_6354, ap_reg_pp0_iter3_tmp_19_7_7_1_reg_6639, ap_reg_pp0_iter5_tmp_19_4_7_2_reg_6834, ap_reg_pp0_iter5_tmp_19_5_7_2_reg_6899, ap_reg_pp0_iter5_tmp_19_6_7_2_reg_6964, ap_reg_pp0_iter5_tmp_19_7_7_2_reg_7029, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1075_p1 <= ap_reg_pp0_iter5_tmp_19_7_7_2_reg_7029;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1075_p1 <= ap_reg_pp0_iter5_tmp_19_6_7_2_reg_6964;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1075_p1 <= ap_reg_pp0_iter5_tmp_19_5_7_2_reg_6899;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1075_p1 <= ap_reg_pp0_iter5_tmp_19_4_7_2_reg_6834;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1075_p1 <= ap_reg_pp0_iter3_tmp_19_7_7_1_reg_6639;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1075_p1 <= ap_reg_pp0_iter3_tmp_19_6_7_1_reg_6354;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1075_p1 <= ap_reg_pp0_iter3_tmp_19_5_7_1_reg_6249;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1075_p1 <= ap_reg_pp0_iter3_tmp_19_4_7_1_reg_6184;
else
grp_fu_1075_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1079_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_8_reg_7359, tmp_20_5_8_reg_7424, ap_enable_reg_pp0_iter4, tmp_20_6_8_reg_7489, tmp_20_7_8_reg_7554, ap_enable_reg_pp0_iter5, tmp_20_4_8_1_reg_7879, tmp_20_5_8_1_reg_7944, tmp_20_6_8_1_reg_8009, ap_enable_reg_pp0_iter6, tmp_20_7_8_1_reg_8074, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1079_p0 <= tmp_20_7_8_1_reg_8074;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1079_p0 <= tmp_20_6_8_1_reg_8009;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1079_p0 <= tmp_20_5_8_1_reg_7944;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1079_p0 <= tmp_20_4_8_1_reg_7879;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1079_p0 <= tmp_20_7_8_reg_7554;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1079_p0 <= tmp_20_6_8_reg_7489;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1079_p0 <= tmp_20_5_8_reg_7424;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1079_p0 <= tmp_20_4_8_reg_7359;
else
grp_fu_1079_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1079_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_8_1_reg_6189, ap_reg_pp0_iter3_tmp_19_5_8_1_reg_6254, ap_reg_pp0_iter3_tmp_19_6_8_1_reg_6364, ap_reg_pp0_iter3_tmp_19_7_8_1_reg_6644, ap_reg_pp0_iter5_tmp_19_4_8_2_reg_6839, ap_reg_pp0_iter5_tmp_19_5_8_2_reg_6904, ap_reg_pp0_iter5_tmp_19_6_8_2_reg_6969, ap_reg_pp0_iter5_tmp_19_7_8_2_reg_7034, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1079_p1 <= ap_reg_pp0_iter5_tmp_19_7_8_2_reg_7034;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1079_p1 <= ap_reg_pp0_iter5_tmp_19_6_8_2_reg_6969;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1079_p1 <= ap_reg_pp0_iter5_tmp_19_5_8_2_reg_6904;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1079_p1 <= ap_reg_pp0_iter5_tmp_19_4_8_2_reg_6839;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1079_p1 <= ap_reg_pp0_iter3_tmp_19_7_8_1_reg_6644;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1079_p1 <= ap_reg_pp0_iter3_tmp_19_6_8_1_reg_6364;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1079_p1 <= ap_reg_pp0_iter3_tmp_19_5_8_1_reg_6254;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1079_p1 <= ap_reg_pp0_iter3_tmp_19_4_8_1_reg_6189;
else
grp_fu_1079_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1083_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_9_reg_7364, tmp_20_5_9_reg_7429, ap_enable_reg_pp0_iter4, tmp_20_6_9_reg_7494, tmp_20_7_9_reg_7559, ap_enable_reg_pp0_iter5, tmp_20_4_9_1_reg_7884, tmp_20_5_9_1_reg_7949, tmp_20_6_9_1_reg_8014, ap_enable_reg_pp0_iter6, tmp_20_7_9_1_reg_8079, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1083_p0 <= tmp_20_7_9_1_reg_8079;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1083_p0 <= tmp_20_6_9_1_reg_8014;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1083_p0 <= tmp_20_5_9_1_reg_7949;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1083_p0 <= tmp_20_4_9_1_reg_7884;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1083_p0 <= tmp_20_7_9_reg_7559;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1083_p0 <= tmp_20_6_9_reg_7494;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1083_p0 <= tmp_20_5_9_reg_7429;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1083_p0 <= tmp_20_4_9_reg_7364;
else
grp_fu_1083_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1083_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_9_1_reg_6194, ap_reg_pp0_iter3_tmp_19_5_9_1_reg_6259, ap_reg_pp0_iter3_tmp_19_6_9_1_reg_6374, ap_reg_pp0_iter3_tmp_19_7_9_1_reg_6649, ap_reg_pp0_iter5_tmp_19_4_9_2_reg_6844, ap_reg_pp0_iter5_tmp_19_5_9_2_reg_6909, ap_reg_pp0_iter5_tmp_19_6_9_2_reg_6974, ap_reg_pp0_iter5_tmp_19_7_9_2_reg_7039, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1083_p1 <= ap_reg_pp0_iter5_tmp_19_7_9_2_reg_7039;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1083_p1 <= ap_reg_pp0_iter5_tmp_19_6_9_2_reg_6974;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1083_p1 <= ap_reg_pp0_iter5_tmp_19_5_9_2_reg_6909;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1083_p1 <= ap_reg_pp0_iter5_tmp_19_4_9_2_reg_6844;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1083_p1 <= ap_reg_pp0_iter3_tmp_19_7_9_1_reg_6649;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1083_p1 <= ap_reg_pp0_iter3_tmp_19_6_9_1_reg_6374;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1083_p1 <= ap_reg_pp0_iter3_tmp_19_5_9_1_reg_6259;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1083_p1 <= ap_reg_pp0_iter3_tmp_19_4_9_1_reg_6194;
else
grp_fu_1083_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1087_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_s_reg_7369, tmp_20_5_s_reg_7434, ap_enable_reg_pp0_iter4, tmp_20_6_s_reg_7499, tmp_20_7_s_reg_7564, ap_enable_reg_pp0_iter5, tmp_20_4_10_1_reg_7889, tmp_20_5_10_1_reg_7954, tmp_20_6_10_1_reg_8019, ap_enable_reg_pp0_iter6, tmp_20_7_10_1_reg_8084, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1087_p0 <= tmp_20_7_10_1_reg_8084;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1087_p0 <= tmp_20_6_10_1_reg_8019;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1087_p0 <= tmp_20_5_10_1_reg_7954;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1087_p0 <= tmp_20_4_10_1_reg_7889;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1087_p0 <= tmp_20_7_s_reg_7564;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1087_p0 <= tmp_20_6_s_reg_7499;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1087_p0 <= tmp_20_5_s_reg_7434;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1087_p0 <= tmp_20_4_s_reg_7369;
else
grp_fu_1087_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1087_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_10_1_reg_6199, ap_reg_pp0_iter3_tmp_19_5_10_1_reg_6264, ap_reg_pp0_iter3_tmp_19_6_10_1_reg_6384, ap_reg_pp0_iter3_tmp_19_7_10_1_reg_6654, ap_reg_pp0_iter5_tmp_19_4_10_2_reg_6849, ap_reg_pp0_iter5_tmp_19_5_10_2_reg_6914, ap_reg_pp0_iter5_tmp_19_6_10_2_reg_6979, ap_reg_pp0_iter5_tmp_19_7_10_2_reg_7044, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1087_p1 <= ap_reg_pp0_iter5_tmp_19_7_10_2_reg_7044;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1087_p1 <= ap_reg_pp0_iter5_tmp_19_6_10_2_reg_6979;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1087_p1 <= ap_reg_pp0_iter5_tmp_19_5_10_2_reg_6914;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1087_p1 <= ap_reg_pp0_iter5_tmp_19_4_10_2_reg_6849;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1087_p1 <= ap_reg_pp0_iter3_tmp_19_7_10_1_reg_6654;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1087_p1 <= ap_reg_pp0_iter3_tmp_19_6_10_1_reg_6384;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1087_p1 <= ap_reg_pp0_iter3_tmp_19_5_10_1_reg_6264;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1087_p1 <= ap_reg_pp0_iter3_tmp_19_4_10_1_reg_6199;
else
grp_fu_1087_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1091_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_10_reg_7374, tmp_20_5_10_reg_7439, ap_enable_reg_pp0_iter4, tmp_20_6_10_reg_7504, tmp_20_7_10_reg_7569, ap_enable_reg_pp0_iter5, tmp_20_4_11_1_reg_7894, tmp_20_5_11_1_reg_7959, tmp_20_6_11_1_reg_8024, ap_enable_reg_pp0_iter6, tmp_20_7_11_1_reg_8089, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1091_p0 <= tmp_20_7_11_1_reg_8089;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1091_p0 <= tmp_20_6_11_1_reg_8024;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1091_p0 <= tmp_20_5_11_1_reg_7959;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1091_p0 <= tmp_20_4_11_1_reg_7894;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1091_p0 <= tmp_20_7_10_reg_7569;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1091_p0 <= tmp_20_6_10_reg_7504;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1091_p0 <= tmp_20_5_10_reg_7439;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1091_p0 <= tmp_20_4_10_reg_7374;
else
grp_fu_1091_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1091_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_11_1_reg_6204, ap_reg_pp0_iter3_tmp_19_5_11_1_reg_6269, ap_reg_pp0_iter3_tmp_19_6_11_1_reg_6394, ap_reg_pp0_iter3_tmp_19_7_11_1_reg_6659, ap_reg_pp0_iter5_tmp_19_4_11_2_reg_6854, ap_reg_pp0_iter5_tmp_19_5_11_2_reg_6919, ap_reg_pp0_iter5_tmp_19_6_11_2_reg_6984, ap_reg_pp0_iter5_tmp_19_7_11_2_reg_7049, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1091_p1 <= ap_reg_pp0_iter5_tmp_19_7_11_2_reg_7049;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1091_p1 <= ap_reg_pp0_iter5_tmp_19_6_11_2_reg_6984;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1091_p1 <= ap_reg_pp0_iter5_tmp_19_5_11_2_reg_6919;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1091_p1 <= ap_reg_pp0_iter5_tmp_19_4_11_2_reg_6854;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1091_p1 <= ap_reg_pp0_iter3_tmp_19_7_11_1_reg_6659;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1091_p1 <= ap_reg_pp0_iter3_tmp_19_6_11_1_reg_6394;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1091_p1 <= ap_reg_pp0_iter3_tmp_19_5_11_1_reg_6269;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1091_p1 <= ap_reg_pp0_iter3_tmp_19_4_11_1_reg_6204;
else
grp_fu_1091_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1095_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_11_reg_7379, tmp_20_5_11_reg_7444, ap_enable_reg_pp0_iter4, tmp_20_6_11_reg_7509, tmp_20_7_11_reg_7574, ap_enable_reg_pp0_iter5, tmp_20_4_12_1_reg_7899, tmp_20_5_12_1_reg_7964, tmp_20_6_12_1_reg_8029, ap_enable_reg_pp0_iter6, tmp_20_7_12_1_reg_8094, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1095_p0 <= tmp_20_7_12_1_reg_8094;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1095_p0 <= tmp_20_6_12_1_reg_8029;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1095_p0 <= tmp_20_5_12_1_reg_7964;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1095_p0 <= tmp_20_4_12_1_reg_7899;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1095_p0 <= tmp_20_7_11_reg_7574;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1095_p0 <= tmp_20_6_11_reg_7509;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1095_p0 <= tmp_20_5_11_reg_7444;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1095_p0 <= tmp_20_4_11_reg_7379;
else
grp_fu_1095_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1095_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_12_1_reg_6209, ap_reg_pp0_iter3_tmp_19_5_12_1_reg_6274, ap_reg_pp0_iter3_tmp_19_6_12_1_reg_6404, ap_reg_pp0_iter3_tmp_19_7_12_1_reg_6664, ap_reg_pp0_iter5_tmp_19_4_12_2_reg_6859, ap_reg_pp0_iter5_tmp_19_5_12_2_reg_6924, ap_reg_pp0_iter5_tmp_19_6_12_2_reg_6989, ap_reg_pp0_iter5_tmp_19_7_12_2_reg_7054, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1095_p1 <= ap_reg_pp0_iter5_tmp_19_7_12_2_reg_7054;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1095_p1 <= ap_reg_pp0_iter5_tmp_19_6_12_2_reg_6989;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1095_p1 <= ap_reg_pp0_iter5_tmp_19_5_12_2_reg_6924;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1095_p1 <= ap_reg_pp0_iter5_tmp_19_4_12_2_reg_6859;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1095_p1 <= ap_reg_pp0_iter3_tmp_19_7_12_1_reg_6664;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1095_p1 <= ap_reg_pp0_iter3_tmp_19_6_12_1_reg_6404;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1095_p1 <= ap_reg_pp0_iter3_tmp_19_5_12_1_reg_6274;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1095_p1 <= ap_reg_pp0_iter3_tmp_19_4_12_1_reg_6209;
else
grp_fu_1095_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1099_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_0_load_reg_3686, bufw_0_load_1_reg_3710, bufw_0_load_2_reg_4012, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1099_p0 <= bufw_0_load_2_reg_4012;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1099_p0 <= bufw_0_load_1_reg_3710;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1099_p0 <= bufw_0_load_reg_3686;
else
grp_fu_1099_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1099_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1099_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1099_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1099_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1099_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1099_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1099_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1099_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1099_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1099_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1099_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1103_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_0_load_1_reg_3710, bufw_1_load_1_reg_3759, ap_enable_reg_pp0_iter1, bufw_1_load_2_reg_4019, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1103_p0 <= bufw_1_load_2_reg_4019;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1103_p0 <= bufw_1_load_1_reg_3759;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1103_p0 <= bufw_0_load_1_reg_3710;
else
grp_fu_1103_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1103_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1103_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1103_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1103_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1103_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1103_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1103_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1103_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1103_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1103_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1103_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1107_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_1_load_reg_3752, bufw_2_load_1_reg_3774, ap_enable_reg_pp0_iter1, bufw_2_load_2_reg_4026, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1107_p0 <= bufw_2_load_2_reg_4026;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1107_p0 <= bufw_2_load_1_reg_3774;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1107_p0 <= bufw_1_load_reg_3752;
else
grp_fu_1107_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1107_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1107_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1107_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1107_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1107_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1107_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1107_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1107_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1107_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1107_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1107_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1111_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_1_load_1_reg_3759, bufw_3_load_1_reg_3789, ap_enable_reg_pp0_iter1, bufw_3_load_2_reg_4033, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1111_p0 <= bufw_3_load_2_reg_4033;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1111_p0 <= bufw_3_load_1_reg_3789;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1111_p0 <= bufw_1_load_1_reg_3759;
else
grp_fu_1111_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1111_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1111_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1111_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1111_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1111_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1111_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1111_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1111_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1111_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1111_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1111_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1115_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_2_load_reg_3767, bufw_4_load_1_reg_3804, ap_enable_reg_pp0_iter1, bufw_4_load_2_reg_4040, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1115_p0 <= bufw_4_load_2_reg_4040;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1115_p0 <= bufw_4_load_1_reg_3804;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1115_p0 <= bufw_2_load_reg_3767;
else
grp_fu_1115_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1115_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1115_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1115_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1115_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1115_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1115_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1115_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1115_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1115_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1115_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1115_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1119_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_2_load_1_reg_3774, bufw_5_load_1_reg_3819, ap_enable_reg_pp0_iter1, bufw_5_load_2_reg_4047, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1119_p0 <= bufw_5_load_2_reg_4047;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1119_p0 <= bufw_5_load_1_reg_3819;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1119_p0 <= bufw_2_load_1_reg_3774;
else
grp_fu_1119_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1119_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1119_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1119_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1119_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1119_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1119_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1119_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1119_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1119_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1119_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1119_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1123_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_3_load_reg_3782, bufw_6_load_1_reg_3834, ap_enable_reg_pp0_iter1, bufw_6_load_2_reg_4054, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1123_p0 <= bufw_6_load_2_reg_4054;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1123_p0 <= bufw_6_load_1_reg_3834;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1123_p0 <= bufw_3_load_reg_3782;
else
grp_fu_1123_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1123_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1123_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1123_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1123_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1123_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1123_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1123_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1123_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1123_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1123_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1123_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1127_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_3_load_1_reg_3789, bufw_7_load_1_reg_3849, ap_enable_reg_pp0_iter1, bufw_7_load_2_reg_4061, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1127_p0 <= bufw_7_load_2_reg_4061;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1127_p0 <= bufw_7_load_1_reg_3849;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1127_p0 <= bufw_3_load_1_reg_3789;
else
grp_fu_1127_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1127_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1127_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1127_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1127_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1127_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1127_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1127_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1127_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1127_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1127_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1127_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1131_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_4_load_reg_3797, bufw_8_load_1_reg_3864, ap_enable_reg_pp0_iter1, bufw_8_load_2_reg_4068, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1131_p0 <= bufw_8_load_2_reg_4068;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1131_p0 <= bufw_8_load_1_reg_3864;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1131_p0 <= bufw_4_load_reg_3797;
else
grp_fu_1131_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1131_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1131_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1131_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1131_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1131_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1131_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1131_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1131_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1131_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1131_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1131_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1135_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_4_load_1_reg_3804, bufw_9_load_1_reg_3879, ap_enable_reg_pp0_iter1, bufw_9_load_2_reg_4075, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1135_p0 <= bufw_9_load_2_reg_4075;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1135_p0 <= bufw_9_load_1_reg_3879;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1135_p0 <= bufw_4_load_1_reg_3804;
else
grp_fu_1135_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1135_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1135_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1135_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1135_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1135_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1135_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1135_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1135_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1135_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1135_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1135_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1139_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_5_load_reg_3812, bufw_10_load_1_reg_3894, ap_enable_reg_pp0_iter1, bufw_10_load_2_reg_4082, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1139_p0 <= bufw_10_load_2_reg_4082;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1139_p0 <= bufw_10_load_1_reg_3894;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1139_p0 <= bufw_5_load_reg_3812;
else
grp_fu_1139_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1139_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1139_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1139_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1139_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1139_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1139_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1139_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1139_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1139_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1139_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1139_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1143_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_5_load_1_reg_3819, bufw_11_load_1_reg_3909, ap_enable_reg_pp0_iter1, bufw_11_load_2_reg_4089, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1143_p0 <= bufw_11_load_2_reg_4089;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1143_p0 <= bufw_11_load_1_reg_3909;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1143_p0 <= bufw_5_load_1_reg_3819;
else
grp_fu_1143_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1143_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1143_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1143_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1143_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1143_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1143_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1143_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1143_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1143_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1143_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1143_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1147_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_6_load_reg_3827, bufw_12_load_1_reg_3924, ap_enable_reg_pp0_iter1, bufw_12_load_2_reg_4096, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1147_p0 <= bufw_12_load_2_reg_4096;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1147_p0 <= bufw_12_load_1_reg_3924;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1147_p0 <= bufw_6_load_reg_3827;
else
grp_fu_1147_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1147_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1147_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1147_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1147_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1147_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1147_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1147_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1147_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1147_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1147_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1147_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1151_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_0_load_reg_3686, bufw_0_load_1_reg_3710, bufw_6_load_1_reg_3834, bufw_0_load_2_reg_4012, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1151_p0 <= bufw_0_load_2_reg_4012;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1151_p0 <= bufw_0_load_1_reg_3710;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1151_p0 <= bufw_0_load_reg_3686;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1151_p0 <= bufw_6_load_1_reg_3834;
else
grp_fu_1151_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1151_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1151_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1151_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1151_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1151_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1151_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1151_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1151_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1151_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1151_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1151_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1155_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_1_load_reg_3752, bufw_1_load_1_reg_3759, bufw_7_load_reg_3842, ap_enable_reg_pp0_iter1, bufw_1_load_2_reg_4019, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1155_p0 <= bufw_1_load_2_reg_4019;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1155_p0 <= bufw_1_load_1_reg_3759;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1155_p0 <= bufw_1_load_reg_3752;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1155_p0 <= bufw_7_load_reg_3842;
else
grp_fu_1155_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1155_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1155_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1155_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1155_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1155_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1155_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1155_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1155_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1155_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1155_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1155_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1159_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_2_load_reg_3767, bufw_2_load_1_reg_3774, bufw_7_load_1_reg_3849, ap_enable_reg_pp0_iter1, bufw_2_load_2_reg_4026, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1159_p0 <= bufw_2_load_2_reg_4026;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1159_p0 <= bufw_2_load_1_reg_3774;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1159_p0 <= bufw_2_load_reg_3767;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1159_p0 <= bufw_7_load_1_reg_3849;
else
grp_fu_1159_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1159_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1159_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1159_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1159_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1159_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1159_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1159_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1159_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1159_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1159_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1159_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1163_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_3_load_reg_3782, bufw_3_load_1_reg_3789, bufw_8_load_reg_3857, ap_enable_reg_pp0_iter1, bufw_3_load_2_reg_4033, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1163_p0 <= bufw_3_load_2_reg_4033;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1163_p0 <= bufw_3_load_1_reg_3789;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1163_p0 <= bufw_3_load_reg_3782;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1163_p0 <= bufw_8_load_reg_3857;
else
grp_fu_1163_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1163_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1163_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1163_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1163_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1163_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1163_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1163_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1163_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1163_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1163_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1163_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1167_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_4_load_reg_3797, bufw_4_load_1_reg_3804, bufw_8_load_1_reg_3864, ap_enable_reg_pp0_iter1, bufw_4_load_2_reg_4040, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1167_p0 <= bufw_4_load_2_reg_4040;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1167_p0 <= bufw_4_load_1_reg_3804;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1167_p0 <= bufw_4_load_reg_3797;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1167_p0 <= bufw_8_load_1_reg_3864;
else
grp_fu_1167_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1167_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1167_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1167_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1167_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1167_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1167_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1167_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1167_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1167_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1167_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1167_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1171_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_5_load_reg_3812, bufw_5_load_1_reg_3819, bufw_9_load_reg_3872, ap_enable_reg_pp0_iter1, bufw_5_load_2_reg_4047, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1171_p0 <= bufw_5_load_2_reg_4047;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1171_p0 <= bufw_5_load_1_reg_3819;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1171_p0 <= bufw_5_load_reg_3812;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1171_p0 <= bufw_9_load_reg_3872;
else
grp_fu_1171_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1171_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1171_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1171_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1171_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1171_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1171_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1171_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1171_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1171_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1171_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1171_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1175_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_6_load_reg_3827, bufw_6_load_1_reg_3834, bufw_9_load_1_reg_3879, ap_enable_reg_pp0_iter1, bufw_6_load_2_reg_4054, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1175_p0 <= bufw_6_load_2_reg_4054;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1175_p0 <= bufw_6_load_1_reg_3834;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1175_p0 <= bufw_6_load_reg_3827;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1175_p0 <= bufw_9_load_1_reg_3879;
else
grp_fu_1175_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1175_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1175_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1175_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1175_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1175_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1175_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1175_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1175_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1175_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1175_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1175_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1179_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_7_load_reg_3842, bufw_7_load_1_reg_3849, bufw_10_load_reg_3887, ap_enable_reg_pp0_iter1, bufw_7_load_2_reg_4061, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1179_p0 <= bufw_7_load_2_reg_4061;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1179_p0 <= bufw_7_load_1_reg_3849;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1179_p0 <= bufw_7_load_reg_3842;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1179_p0 <= bufw_10_load_reg_3887;
else
grp_fu_1179_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1179_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1179_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1179_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1179_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1179_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1179_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1179_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1179_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1179_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1179_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1179_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1183_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_8_load_reg_3857, bufw_8_load_1_reg_3864, bufw_10_load_1_reg_3894, ap_enable_reg_pp0_iter1, bufw_8_load_2_reg_4068, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1183_p0 <= bufw_8_load_2_reg_4068;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1183_p0 <= bufw_8_load_1_reg_3864;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1183_p0 <= bufw_8_load_reg_3857;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1183_p0 <= bufw_10_load_1_reg_3894;
else
grp_fu_1183_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1183_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1183_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1183_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1183_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1183_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1183_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1183_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1183_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1183_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1183_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1183_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1187_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_9_load_reg_3872, bufw_9_load_1_reg_3879, bufw_11_load_reg_3902, ap_enable_reg_pp0_iter1, bufw_9_load_2_reg_4075, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1187_p0 <= bufw_9_load_2_reg_4075;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1187_p0 <= bufw_9_load_1_reg_3879;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1187_p0 <= bufw_9_load_reg_3872;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1187_p0 <= bufw_11_load_reg_3902;
else
grp_fu_1187_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1187_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1187_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1187_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1187_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1187_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1187_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1187_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1187_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1187_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1187_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1187_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1191_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_10_load_reg_3887, bufw_10_load_1_reg_3894, bufw_11_load_1_reg_3909, ap_enable_reg_pp0_iter1, bufw_10_load_2_reg_4082, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1191_p0 <= bufw_10_load_2_reg_4082;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1191_p0 <= bufw_10_load_1_reg_3894;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1191_p0 <= bufw_10_load_reg_3887;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1191_p0 <= bufw_11_load_1_reg_3909;
else
grp_fu_1191_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1191_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1191_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1191_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1191_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1191_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1191_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1191_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1191_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1191_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1191_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1191_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1195_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_11_load_reg_3902, bufw_11_load_1_reg_3909, bufw_12_load_reg_3917, ap_enable_reg_pp0_iter1, bufw_11_load_2_reg_4089, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1195_p0 <= bufw_11_load_2_reg_4089;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1195_p0 <= bufw_11_load_1_reg_3909;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1195_p0 <= bufw_11_load_reg_3902;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1195_p0 <= bufw_12_load_reg_3917;
else
grp_fu_1195_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1195_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1195_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1195_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1195_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1195_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1195_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1195_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1195_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1195_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1195_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1195_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1199_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_12_load_reg_3917, bufw_12_load_1_reg_3924, ap_enable_reg_pp0_iter1, bufw_12_load_2_reg_4096, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1199_p0 <= bufw_12_load_2_reg_4096;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1199_p0 <= bufw_12_load_reg_3917;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1199_p0 <= bufw_12_load_1_reg_3924;
else
grp_fu_1199_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1199_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1199_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1199_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1199_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1199_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1199_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1199_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1199_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1199_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1199_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1199_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1203_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_0_load_reg_3686, bufw_0_load_1_reg_3710, bufw_0_load_2_reg_4012, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1203_p0 <= bufw_0_load_2_reg_4012;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1203_p0 <= bufw_0_load_1_reg_3710;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1203_p0 <= bufw_0_load_reg_3686;
else
grp_fu_1203_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1203_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1203_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1203_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1203_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1203_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1203_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1203_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1203_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1203_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1203_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1203_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1207_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_1_load_reg_3752, bufw_1_load_1_reg_3759, ap_enable_reg_pp0_iter1, bufw_1_load_2_reg_4019, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1207_p0 <= bufw_1_load_2_reg_4019;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1207_p0 <= bufw_1_load_1_reg_3759;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1207_p0 <= bufw_1_load_reg_3752;
else
grp_fu_1207_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1207_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1207_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1207_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1207_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1207_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1207_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1207_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1207_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1207_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1207_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1207_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1211_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_2_load_reg_3767, bufw_2_load_1_reg_3774, ap_enable_reg_pp0_iter1, bufw_2_load_2_reg_4026, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1211_p0 <= bufw_2_load_2_reg_4026;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1211_p0 <= bufw_2_load_1_reg_3774;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1211_p0 <= bufw_2_load_reg_3767;
else
grp_fu_1211_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1211_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1211_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1211_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1211_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1211_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1211_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1211_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1211_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1211_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1211_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1211_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1215_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_3_load_reg_3782, bufw_3_load_1_reg_3789, ap_enable_reg_pp0_iter1, bufw_3_load_2_reg_4033, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1215_p0 <= bufw_3_load_2_reg_4033;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1215_p0 <= bufw_3_load_1_reg_3789;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1215_p0 <= bufw_3_load_reg_3782;
else
grp_fu_1215_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1215_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1215_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1215_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1215_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1215_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1215_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1215_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1215_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1215_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1215_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1215_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1219_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_4_load_reg_3797, bufw_4_load_1_reg_3804, ap_enable_reg_pp0_iter1, bufw_4_load_2_reg_4040, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1219_p0 <= bufw_4_load_2_reg_4040;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1219_p0 <= bufw_4_load_1_reg_3804;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1219_p0 <= bufw_4_load_reg_3797;
else
grp_fu_1219_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1219_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1219_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1219_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1219_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1219_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1219_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1219_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1219_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1219_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1219_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1219_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1223_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_5_load_reg_3812, bufw_5_load_1_reg_3819, ap_enable_reg_pp0_iter1, bufw_5_load_2_reg_4047, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1223_p0 <= bufw_5_load_2_reg_4047;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1223_p0 <= bufw_5_load_1_reg_3819;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1223_p0 <= bufw_5_load_reg_3812;
else
grp_fu_1223_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1223_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1223_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1223_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1223_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1223_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1223_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1223_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1223_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1223_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1223_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1223_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1227_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_6_load_reg_3827, bufw_6_load_1_reg_3834, ap_enable_reg_pp0_iter1, bufw_6_load_2_reg_4054, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1227_p0 <= bufw_6_load_2_reg_4054;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1227_p0 <= bufw_6_load_1_reg_3834;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1227_p0 <= bufw_6_load_reg_3827;
else
grp_fu_1227_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1227_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1227_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1227_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1227_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1227_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1227_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1227_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1227_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1227_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1227_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1227_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1231_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_7_load_reg_3842, bufw_7_load_1_reg_3849, ap_enable_reg_pp0_iter1, bufw_7_load_2_reg_4061, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1231_p0 <= bufw_7_load_2_reg_4061;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1231_p0 <= bufw_7_load_1_reg_3849;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1231_p0 <= bufw_7_load_reg_3842;
else
grp_fu_1231_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1231_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1231_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1231_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1231_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1231_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1231_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1231_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1231_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1231_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1231_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1231_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1235_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_8_load_reg_3857, bufw_8_load_1_reg_3864, ap_enable_reg_pp0_iter1, bufw_8_load_2_reg_4068, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1235_p0 <= bufw_8_load_2_reg_4068;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1235_p0 <= bufw_8_load_1_reg_3864;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1235_p0 <= bufw_8_load_reg_3857;
else
grp_fu_1235_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1235_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1235_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1235_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1235_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1235_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1235_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1235_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1235_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1235_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1235_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1235_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1239_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_9_load_reg_3872, bufw_9_load_1_reg_3879, ap_enable_reg_pp0_iter1, bufw_9_load_2_reg_4075, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1239_p0 <= bufw_9_load_2_reg_4075;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1239_p0 <= bufw_9_load_1_reg_3879;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1239_p0 <= bufw_9_load_reg_3872;
else
grp_fu_1239_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1239_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1239_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1239_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1239_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1239_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1239_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1239_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1239_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1239_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1239_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1239_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1243_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_10_load_reg_3887, bufw_10_load_1_reg_3894, ap_enable_reg_pp0_iter1, bufw_10_load_2_reg_4082, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1243_p0 <= bufw_10_load_2_reg_4082;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1243_p0 <= bufw_10_load_1_reg_3894;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1243_p0 <= bufw_10_load_reg_3887;
else
grp_fu_1243_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1243_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1243_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1243_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1243_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1243_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1243_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1243_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1243_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1243_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1243_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1243_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1247_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_11_load_reg_3902, bufw_11_load_1_reg_3909, ap_enable_reg_pp0_iter1, bufw_11_load_2_reg_4089, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1247_p0 <= bufw_11_load_2_reg_4089;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1247_p0 <= bufw_11_load_1_reg_3909;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1247_p0 <= bufw_11_load_reg_3902;
else
grp_fu_1247_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1247_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1247_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1247_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1247_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1247_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1247_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1247_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1247_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1247_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1247_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1247_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1251_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_12_load_reg_3917, bufw_12_load_1_reg_3924, ap_enable_reg_pp0_iter1, bufw_12_load_2_reg_4096, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1251_p0 <= bufw_12_load_2_reg_4096;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1251_p0 <= bufw_12_load_1_reg_3924;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1251_p0 <= bufw_12_load_reg_3917;
else
grp_fu_1251_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1251_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1251_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1251_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1251_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1251_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1251_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1251_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1251_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1251_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1251_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1251_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1255_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1265_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1275_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1285_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1295_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1305_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1315_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1325_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1335_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1345_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1355_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1365_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1375_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1385_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1395_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1405_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1415_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1425_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1435_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1445_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1455_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1465_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1475_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1485_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_943_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_11_fu_2165_p1, ap_enable_reg_pp0_iter2, tmp_91_fu_2269_p1, tmp_171_fu_2373_p1, tmp_251_fu_2477_p1, tmp_351_reg_7059, ap_enable_reg_pp0_iter3, tmp_20_2_reg_7189, tmp_20_0_0_1_reg_7579, ap_enable_reg_pp0_iter5, tmp_20_2_0_1_reg_7709, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_943_p0 <= tmp_20_2_0_1_reg_7709;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_943_p0 <= tmp_20_0_0_1_reg_7579;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_943_p0 <= tmp_20_2_reg_7189;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_943_p0 <= tmp_351_reg_7059;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_943_p0 <= tmp_251_fu_2477_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_943_p0 <= tmp_171_fu_2373_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_943_p0 <= tmp_91_fu_2269_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_943_p0 <= tmp_11_fu_2165_p1;
else
grp_fu_943_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_943_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_349_reg_4849, ap_reg_pp0_iter2_tmp_19_0_0_1_reg_4854, ap_enable_reg_pp0_iter2, tmp_19_2_reg_5369, ap_reg_pp0_iter3_tmp_19_2_0_1_reg_5504, tmp_19_4_reg_5694, tmp_19_6_reg_6019, ap_reg_pp0_iter4_tmp_19_0_0_2_reg_6474, ap_reg_pp0_iter4_tmp_19_2_0_2_reg_6669, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_943_p1 <= ap_reg_pp0_iter4_tmp_19_2_0_2_reg_6669;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_943_p1 <= ap_reg_pp0_iter4_tmp_19_0_0_2_reg_6474;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_943_p1 <= ap_reg_pp0_iter3_tmp_19_2_0_1_reg_5504;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_943_p1 <= ap_reg_pp0_iter2_tmp_19_0_0_1_reg_4854;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_943_p1 <= tmp_19_6_reg_6019;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_943_p1 <= tmp_19_4_reg_5694;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_943_p1 <= tmp_19_2_reg_5369;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_943_p1 <= tmp_349_reg_4849;
else
grp_fu_943_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_947_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_14_fu_2169_p1, ap_enable_reg_pp0_iter2, tmp_94_fu_2273_p1, tmp_174_fu_2377_p1, tmp_254_fu_2481_p1, ap_enable_reg_pp0_iter3, tmp_20_0_1_reg_7064, tmp_20_2_1_reg_7194, ap_enable_reg_pp0_iter5, tmp_20_0_1_1_reg_7584, tmp_20_2_1_1_reg_7714, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_947_p0 <= tmp_20_2_1_1_reg_7714;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_947_p0 <= tmp_20_0_1_1_reg_7584;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_947_p0 <= tmp_20_2_1_reg_7194;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_947_p0 <= tmp_20_0_1_reg_7064;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_947_p0 <= tmp_254_fu_2481_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_947_p0 <= tmp_174_fu_2377_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_947_p0 <= tmp_94_fu_2273_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_947_p0 <= tmp_14_fu_2169_p1;
else
grp_fu_947_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_947_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_1_reg_4859, ap_reg_pp0_iter2_tmp_19_0_1_1_reg_4864, ap_enable_reg_pp0_iter2, tmp_19_2_1_reg_5374, ap_reg_pp0_iter3_tmp_19_2_1_1_reg_5514, tmp_19_4_1_reg_5699, tmp_19_6_1_reg_6024, ap_reg_pp0_iter4_tmp_19_0_1_2_reg_6479, ap_reg_pp0_iter4_tmp_19_2_1_2_reg_6674, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_947_p1 <= ap_reg_pp0_iter4_tmp_19_2_1_2_reg_6674;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_947_p1 <= ap_reg_pp0_iter4_tmp_19_0_1_2_reg_6479;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_947_p1 <= ap_reg_pp0_iter3_tmp_19_2_1_1_reg_5514;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_947_p1 <= ap_reg_pp0_iter2_tmp_19_0_1_1_reg_4864;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_947_p1 <= tmp_19_6_1_reg_6024;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_947_p1 <= tmp_19_4_1_reg_5699;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_947_p1 <= tmp_19_2_1_reg_5374;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_947_p1 <= tmp_19_0_1_reg_4859;
else
grp_fu_947_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_951_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_17_fu_2173_p1, ap_enable_reg_pp0_iter2, tmp_97_fu_2277_p1, tmp_177_fu_2381_p1, tmp_257_fu_2485_p1, ap_enable_reg_pp0_iter3, tmp_20_0_2_reg_7069, tmp_20_2_2_reg_7199, ap_enable_reg_pp0_iter5, tmp_20_0_2_1_reg_7589, tmp_20_2_2_1_reg_7719, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_951_p0 <= tmp_20_2_2_1_reg_7719;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_951_p0 <= tmp_20_0_2_1_reg_7589;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_951_p0 <= tmp_20_2_2_reg_7199;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_951_p0 <= tmp_20_0_2_reg_7069;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_951_p0 <= tmp_257_fu_2485_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_951_p0 <= tmp_177_fu_2381_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_951_p0 <= tmp_97_fu_2277_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_951_p0 <= tmp_17_fu_2173_p1;
else
grp_fu_951_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_951_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_2_reg_4869, ap_reg_pp0_iter2_tmp_19_0_2_1_reg_4874, ap_enable_reg_pp0_iter2, tmp_19_2_2_reg_5379, ap_reg_pp0_iter3_tmp_19_2_2_1_reg_5524, tmp_19_4_2_reg_5704, tmp_19_6_2_reg_6029, ap_reg_pp0_iter4_tmp_19_0_2_2_reg_6484, ap_reg_pp0_iter4_tmp_19_2_2_2_reg_6679, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_951_p1 <= ap_reg_pp0_iter4_tmp_19_2_2_2_reg_6679;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_951_p1 <= ap_reg_pp0_iter4_tmp_19_0_2_2_reg_6484;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_951_p1 <= ap_reg_pp0_iter3_tmp_19_2_2_1_reg_5524;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_951_p1 <= ap_reg_pp0_iter2_tmp_19_0_2_1_reg_4874;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_951_p1 <= tmp_19_6_2_reg_6029;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_951_p1 <= tmp_19_4_2_reg_5704;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_951_p1 <= tmp_19_2_2_reg_5379;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_951_p1 <= tmp_19_0_2_reg_4869;
else
grp_fu_951_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_955_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_fu_2177_p1, ap_enable_reg_pp0_iter2, tmp_100_fu_2281_p1, tmp_180_fu_2385_p1, tmp_260_fu_2489_p1, ap_enable_reg_pp0_iter3, tmp_20_0_3_reg_7074, tmp_20_2_3_reg_7204, ap_enable_reg_pp0_iter5, tmp_20_0_3_1_reg_7594, tmp_20_2_3_1_reg_7724, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_955_p0 <= tmp_20_2_3_1_reg_7724;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_955_p0 <= tmp_20_0_3_1_reg_7594;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_955_p0 <= tmp_20_2_3_reg_7204;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_955_p0 <= tmp_20_0_3_reg_7074;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_955_p0 <= tmp_260_fu_2489_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_955_p0 <= tmp_180_fu_2385_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_955_p0 <= tmp_100_fu_2281_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_955_p0 <= tmp_20_fu_2177_p1;
else
grp_fu_955_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_955_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_3_reg_4879, ap_reg_pp0_iter2_tmp_19_0_3_1_reg_4884, ap_enable_reg_pp0_iter2, tmp_19_2_3_reg_5384, ap_reg_pp0_iter3_tmp_19_2_3_1_reg_5534, tmp_19_4_3_reg_5709, tmp_19_6_3_reg_6034, ap_reg_pp0_iter4_tmp_19_0_3_2_reg_6489, ap_reg_pp0_iter4_tmp_19_2_3_2_reg_6684, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_955_p1 <= ap_reg_pp0_iter4_tmp_19_2_3_2_reg_6684;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_955_p1 <= ap_reg_pp0_iter4_tmp_19_0_3_2_reg_6489;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_955_p1 <= ap_reg_pp0_iter3_tmp_19_2_3_1_reg_5534;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_955_p1 <= ap_reg_pp0_iter2_tmp_19_0_3_1_reg_4884;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_955_p1 <= tmp_19_6_3_reg_6034;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_955_p1 <= tmp_19_4_3_reg_5709;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_955_p1 <= tmp_19_2_3_reg_5384;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_955_p1 <= tmp_19_0_3_reg_4879;
else
grp_fu_955_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_959_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_23_fu_2181_p1, ap_enable_reg_pp0_iter2, tmp_103_fu_2285_p1, tmp_183_fu_2389_p1, tmp_263_fu_2493_p1, ap_enable_reg_pp0_iter3, tmp_20_0_4_reg_7079, tmp_20_2_4_reg_7209, ap_enable_reg_pp0_iter5, tmp_20_0_4_1_reg_7599, tmp_20_2_4_1_reg_7729, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_959_p0 <= tmp_20_2_4_1_reg_7729;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_959_p0 <= tmp_20_0_4_1_reg_7599;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_959_p0 <= tmp_20_2_4_reg_7209;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_959_p0 <= tmp_20_0_4_reg_7079;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_959_p0 <= tmp_263_fu_2493_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_959_p0 <= tmp_183_fu_2389_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_959_p0 <= tmp_103_fu_2285_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_959_p0 <= tmp_23_fu_2181_p1;
else
grp_fu_959_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_959_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_4_reg_4889, ap_reg_pp0_iter2_tmp_19_0_4_1_reg_4894, ap_enable_reg_pp0_iter2, tmp_19_2_4_reg_5389, ap_reg_pp0_iter3_tmp_19_2_4_1_reg_5544, tmp_19_4_4_reg_5714, tmp_19_6_4_reg_6039, ap_reg_pp0_iter4_tmp_19_0_4_2_reg_6494, ap_reg_pp0_iter4_tmp_19_2_4_2_reg_6689, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_959_p1 <= ap_reg_pp0_iter4_tmp_19_2_4_2_reg_6689;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_959_p1 <= ap_reg_pp0_iter4_tmp_19_0_4_2_reg_6494;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_959_p1 <= ap_reg_pp0_iter3_tmp_19_2_4_1_reg_5544;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_959_p1 <= ap_reg_pp0_iter2_tmp_19_0_4_1_reg_4894;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_959_p1 <= tmp_19_6_4_reg_6039;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_959_p1 <= tmp_19_4_4_reg_5714;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_959_p1 <= tmp_19_2_4_reg_5389;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_959_p1 <= tmp_19_0_4_reg_4889;
else
grp_fu_959_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_963_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_26_fu_2185_p1, ap_enable_reg_pp0_iter2, tmp_106_fu_2289_p1, tmp_186_fu_2393_p1, tmp_266_fu_2497_p1, ap_enable_reg_pp0_iter3, tmp_20_0_5_reg_7084, tmp_20_2_5_reg_7214, ap_enable_reg_pp0_iter5, tmp_20_0_5_1_reg_7604, tmp_20_2_5_1_reg_7734, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_963_p0 <= tmp_20_2_5_1_reg_7734;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_963_p0 <= tmp_20_0_5_1_reg_7604;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_963_p0 <= tmp_20_2_5_reg_7214;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_963_p0 <= tmp_20_0_5_reg_7084;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_963_p0 <= tmp_266_fu_2497_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_963_p0 <= tmp_186_fu_2393_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_963_p0 <= tmp_106_fu_2289_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_963_p0 <= tmp_26_fu_2185_p1;
else
grp_fu_963_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_963_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_5_reg_4899, ap_reg_pp0_iter2_tmp_19_0_5_1_reg_4904, ap_enable_reg_pp0_iter2, tmp_19_2_5_reg_5394, ap_reg_pp0_iter3_tmp_19_2_5_1_reg_5554, tmp_19_4_5_reg_5719, tmp_19_6_5_reg_6044, ap_reg_pp0_iter4_tmp_19_0_5_2_reg_6499, ap_reg_pp0_iter4_tmp_19_2_5_2_reg_6694, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_963_p1 <= ap_reg_pp0_iter4_tmp_19_2_5_2_reg_6694;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_963_p1 <= ap_reg_pp0_iter4_tmp_19_0_5_2_reg_6499;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_963_p1 <= ap_reg_pp0_iter3_tmp_19_2_5_1_reg_5554;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_963_p1 <= ap_reg_pp0_iter2_tmp_19_0_5_1_reg_4904;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_963_p1 <= tmp_19_6_5_reg_6044;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_963_p1 <= tmp_19_4_5_reg_5719;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_963_p1 <= tmp_19_2_5_reg_5394;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_963_p1 <= tmp_19_0_5_reg_4899;
else
grp_fu_963_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_967_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_29_fu_2189_p1, ap_enable_reg_pp0_iter2, tmp_109_fu_2293_p1, tmp_189_fu_2397_p1, tmp_269_fu_2501_p1, ap_enable_reg_pp0_iter3, tmp_20_0_6_reg_7089, tmp_20_2_6_reg_7219, ap_enable_reg_pp0_iter5, tmp_20_0_6_1_reg_7609, tmp_20_2_6_1_reg_7739, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_967_p0 <= tmp_20_2_6_1_reg_7739;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_967_p0 <= tmp_20_0_6_1_reg_7609;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_967_p0 <= tmp_20_2_6_reg_7219;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_967_p0 <= tmp_20_0_6_reg_7089;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_967_p0 <= tmp_269_fu_2501_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_967_p0 <= tmp_189_fu_2397_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_967_p0 <= tmp_109_fu_2293_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_967_p0 <= tmp_29_fu_2189_p1;
else
grp_fu_967_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_967_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_6_reg_4909, ap_reg_pp0_iter2_tmp_19_0_6_1_reg_4914, ap_enable_reg_pp0_iter2, tmp_19_2_6_reg_5399, ap_reg_pp0_iter3_tmp_19_2_6_1_reg_5564, tmp_19_4_6_reg_5724, tmp_19_6_6_reg_6049, ap_reg_pp0_iter4_tmp_19_0_6_2_reg_6504, ap_reg_pp0_iter4_tmp_19_2_6_2_reg_6699, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_967_p1 <= ap_reg_pp0_iter4_tmp_19_2_6_2_reg_6699;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_967_p1 <= ap_reg_pp0_iter4_tmp_19_0_6_2_reg_6504;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_967_p1 <= ap_reg_pp0_iter3_tmp_19_2_6_1_reg_5564;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_967_p1 <= ap_reg_pp0_iter2_tmp_19_0_6_1_reg_4914;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_967_p1 <= tmp_19_6_6_reg_6049;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_967_p1 <= tmp_19_4_6_reg_5724;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_967_p1 <= tmp_19_2_6_reg_5399;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_967_p1 <= tmp_19_0_6_reg_4909;
else
grp_fu_967_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_971_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_32_fu_2193_p1, ap_enable_reg_pp0_iter2, tmp_112_fu_2297_p1, tmp_192_fu_2401_p1, tmp_272_fu_2505_p1, ap_enable_reg_pp0_iter3, tmp_20_0_7_reg_7094, tmp_20_2_7_reg_7224, ap_enable_reg_pp0_iter5, tmp_20_0_7_1_reg_7614, tmp_20_2_7_1_reg_7744, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_971_p0 <= tmp_20_2_7_1_reg_7744;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_971_p0 <= tmp_20_0_7_1_reg_7614;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_971_p0 <= tmp_20_2_7_reg_7224;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_971_p0 <= tmp_20_0_7_reg_7094;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_971_p0 <= tmp_272_fu_2505_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_971_p0 <= tmp_192_fu_2401_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_971_p0 <= tmp_112_fu_2297_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_971_p0 <= tmp_32_fu_2193_p1;
else
grp_fu_971_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_971_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_7_reg_4919, ap_reg_pp0_iter2_tmp_19_0_7_1_reg_4924, ap_enable_reg_pp0_iter2, tmp_19_2_7_reg_5404, ap_reg_pp0_iter3_tmp_19_2_7_1_reg_5574, tmp_19_4_7_reg_5729, tmp_19_6_7_reg_6054, ap_reg_pp0_iter4_tmp_19_0_7_2_reg_6509, ap_reg_pp0_iter4_tmp_19_2_7_2_reg_6704, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_971_p1 <= ap_reg_pp0_iter4_tmp_19_2_7_2_reg_6704;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_971_p1 <= ap_reg_pp0_iter4_tmp_19_0_7_2_reg_6509;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_971_p1 <= ap_reg_pp0_iter3_tmp_19_2_7_1_reg_5574;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_971_p1 <= ap_reg_pp0_iter2_tmp_19_0_7_1_reg_4924;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_971_p1 <= tmp_19_6_7_reg_6054;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_971_p1 <= tmp_19_4_7_reg_5729;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_971_p1 <= tmp_19_2_7_reg_5404;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_971_p1 <= tmp_19_0_7_reg_4919;
else
grp_fu_971_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_975_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_35_fu_2197_p1, ap_enable_reg_pp0_iter2, tmp_115_fu_2301_p1, tmp_195_fu_2405_p1, tmp_275_fu_2509_p1, ap_enable_reg_pp0_iter3, tmp_20_0_8_reg_7099, tmp_20_2_8_reg_7229, ap_enable_reg_pp0_iter5, tmp_20_0_8_1_reg_7619, tmp_20_2_8_1_reg_7749, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_975_p0 <= tmp_20_2_8_1_reg_7749;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_975_p0 <= tmp_20_0_8_1_reg_7619;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_975_p0 <= tmp_20_2_8_reg_7229;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_975_p0 <= tmp_20_0_8_reg_7099;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_975_p0 <= tmp_275_fu_2509_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_975_p0 <= tmp_195_fu_2405_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_975_p0 <= tmp_115_fu_2301_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_975_p0 <= tmp_35_fu_2197_p1;
else
grp_fu_975_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_975_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_8_reg_4929, ap_reg_pp0_iter2_tmp_19_0_8_1_reg_4934, ap_enable_reg_pp0_iter2, tmp_19_2_8_reg_5409, ap_reg_pp0_iter3_tmp_19_2_8_1_reg_5584, tmp_19_4_8_reg_5734, tmp_19_6_8_reg_6059, ap_reg_pp0_iter4_tmp_19_0_8_2_reg_6514, ap_reg_pp0_iter4_tmp_19_2_8_2_reg_6709, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_975_p1 <= ap_reg_pp0_iter4_tmp_19_2_8_2_reg_6709;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_975_p1 <= ap_reg_pp0_iter4_tmp_19_0_8_2_reg_6514;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_975_p1 <= ap_reg_pp0_iter3_tmp_19_2_8_1_reg_5584;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_975_p1 <= ap_reg_pp0_iter2_tmp_19_0_8_1_reg_4934;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_975_p1 <= tmp_19_6_8_reg_6059;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_975_p1 <= tmp_19_4_8_reg_5734;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_975_p1 <= tmp_19_2_8_reg_5409;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_975_p1 <= tmp_19_0_8_reg_4929;
else
grp_fu_975_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_979_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_38_fu_2201_p1, ap_enable_reg_pp0_iter2, tmp_118_fu_2305_p1, tmp_198_fu_2409_p1, tmp_278_fu_2513_p1, ap_enable_reg_pp0_iter3, tmp_20_0_9_reg_7104, tmp_20_2_9_reg_7234, ap_enable_reg_pp0_iter5, tmp_20_0_9_1_reg_7624, tmp_20_2_9_1_reg_7754, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_979_p0 <= tmp_20_2_9_1_reg_7754;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_979_p0 <= tmp_20_0_9_1_reg_7624;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_979_p0 <= tmp_20_2_9_reg_7234;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_979_p0 <= tmp_20_0_9_reg_7104;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_979_p0 <= tmp_278_fu_2513_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_979_p0 <= tmp_198_fu_2409_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_979_p0 <= tmp_118_fu_2305_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_979_p0 <= tmp_38_fu_2201_p1;
else
grp_fu_979_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_979_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_9_reg_4939, ap_reg_pp0_iter2_tmp_19_0_9_1_reg_4944, ap_enable_reg_pp0_iter2, tmp_19_2_9_reg_5414, ap_reg_pp0_iter3_tmp_19_2_9_1_reg_5594, tmp_19_4_9_reg_5739, tmp_19_6_9_reg_6064, ap_reg_pp0_iter4_tmp_19_0_9_2_reg_6519, ap_reg_pp0_iter4_tmp_19_2_9_2_reg_6714, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_979_p1 <= ap_reg_pp0_iter4_tmp_19_2_9_2_reg_6714;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_979_p1 <= ap_reg_pp0_iter4_tmp_19_0_9_2_reg_6519;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_979_p1 <= ap_reg_pp0_iter3_tmp_19_2_9_1_reg_5594;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_979_p1 <= ap_reg_pp0_iter2_tmp_19_0_9_1_reg_4944;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_979_p1 <= tmp_19_6_9_reg_6064;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_979_p1 <= tmp_19_4_9_reg_5739;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_979_p1 <= tmp_19_2_9_reg_5414;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_979_p1 <= tmp_19_0_9_reg_4939;
else
grp_fu_979_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_983_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_41_fu_2205_p1, ap_enable_reg_pp0_iter2, tmp_121_fu_2309_p1, tmp_201_fu_2413_p1, tmp_281_fu_2517_p1, ap_enable_reg_pp0_iter3, tmp_20_0_s_reg_7109, tmp_20_2_s_reg_7239, ap_enable_reg_pp0_iter5, tmp_20_0_10_1_reg_7629, tmp_20_2_10_1_reg_7759, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_983_p0 <= tmp_20_2_10_1_reg_7759;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_983_p0 <= tmp_20_0_10_1_reg_7629;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_983_p0 <= tmp_20_2_s_reg_7239;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_983_p0 <= tmp_20_0_s_reg_7109;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_983_p0 <= tmp_281_fu_2517_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_983_p0 <= tmp_201_fu_2413_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_983_p0 <= tmp_121_fu_2309_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_983_p0 <= tmp_41_fu_2205_p1;
else
grp_fu_983_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_983_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_s_reg_4949, ap_reg_pp0_iter2_tmp_19_0_10_1_reg_4954, ap_enable_reg_pp0_iter2, tmp_19_2_s_reg_5419, ap_reg_pp0_iter3_tmp_19_2_10_1_reg_5604, tmp_19_4_s_reg_5744, tmp_19_6_s_reg_6069, ap_reg_pp0_iter4_tmp_19_0_10_2_reg_6524, ap_reg_pp0_iter4_tmp_19_2_10_2_reg_6719, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_983_p1 <= ap_reg_pp0_iter4_tmp_19_2_10_2_reg_6719;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_983_p1 <= ap_reg_pp0_iter4_tmp_19_0_10_2_reg_6524;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_983_p1 <= ap_reg_pp0_iter3_tmp_19_2_10_1_reg_5604;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_983_p1 <= ap_reg_pp0_iter2_tmp_19_0_10_1_reg_4954;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_983_p1 <= tmp_19_6_s_reg_6069;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_983_p1 <= tmp_19_4_s_reg_5744;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_983_p1 <= tmp_19_2_s_reg_5419;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_983_p1 <= tmp_19_0_s_reg_4949;
else
grp_fu_983_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_987_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_44_fu_2209_p1, ap_enable_reg_pp0_iter2, tmp_124_fu_2313_p1, tmp_204_fu_2417_p1, tmp_284_fu_2521_p1, ap_enable_reg_pp0_iter3, tmp_20_0_10_reg_7114, tmp_20_2_10_reg_7244, ap_enable_reg_pp0_iter5, tmp_20_0_11_1_reg_7634, tmp_20_2_11_1_reg_7764, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_987_p0 <= tmp_20_2_11_1_reg_7764;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_987_p0 <= tmp_20_0_11_1_reg_7634;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_987_p0 <= tmp_20_2_10_reg_7244;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_987_p0 <= tmp_20_0_10_reg_7114;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_987_p0 <= tmp_284_fu_2521_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_987_p0 <= tmp_204_fu_2417_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_987_p0 <= tmp_124_fu_2313_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_987_p0 <= tmp_44_fu_2209_p1;
else
grp_fu_987_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_987_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_10_reg_4959, ap_reg_pp0_iter2_tmp_19_0_11_1_reg_4964, ap_enable_reg_pp0_iter2, tmp_19_2_10_reg_5424, ap_reg_pp0_iter3_tmp_19_2_11_1_reg_5614, tmp_19_4_10_reg_5749, tmp_19_6_10_reg_6074, ap_reg_pp0_iter4_tmp_19_0_11_2_reg_6529, ap_reg_pp0_iter4_tmp_19_2_11_2_reg_6724, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_987_p1 <= ap_reg_pp0_iter4_tmp_19_2_11_2_reg_6724;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_987_p1 <= ap_reg_pp0_iter4_tmp_19_0_11_2_reg_6529;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_987_p1 <= ap_reg_pp0_iter3_tmp_19_2_11_1_reg_5614;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_987_p1 <= ap_reg_pp0_iter2_tmp_19_0_11_1_reg_4964;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_987_p1 <= tmp_19_6_10_reg_6074;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_987_p1 <= tmp_19_4_10_reg_5749;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_987_p1 <= tmp_19_2_10_reg_5424;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_987_p1 <= tmp_19_0_10_reg_4959;
else
grp_fu_987_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_991_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_47_fu_2213_p1, ap_enable_reg_pp0_iter2, tmp_127_fu_2317_p1, tmp_207_fu_2421_p1, tmp_287_fu_2525_p1, ap_enable_reg_pp0_iter3, tmp_20_0_11_reg_7119, tmp_20_2_11_reg_7249, ap_enable_reg_pp0_iter5, tmp_20_0_12_1_reg_7639, tmp_20_2_12_1_reg_7769, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_991_p0 <= tmp_20_2_12_1_reg_7769;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_991_p0 <= tmp_20_0_12_1_reg_7639;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_991_p0 <= tmp_20_2_11_reg_7249;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_991_p0 <= tmp_20_0_11_reg_7119;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_991_p0 <= tmp_287_fu_2525_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_991_p0 <= tmp_207_fu_2421_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_991_p0 <= tmp_127_fu_2317_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_991_p0 <= tmp_47_fu_2213_p1;
else
grp_fu_991_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_991_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_11_reg_4969, ap_reg_pp0_iter2_tmp_19_0_12_1_reg_4974, ap_enable_reg_pp0_iter2, tmp_19_2_11_reg_5429, ap_reg_pp0_iter3_tmp_19_2_12_1_reg_5624, tmp_19_4_11_reg_5754, tmp_19_6_11_reg_6079, ap_reg_pp0_iter4_tmp_19_0_12_2_reg_6534, ap_reg_pp0_iter4_tmp_19_2_12_2_reg_6729, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_991_p1 <= ap_reg_pp0_iter4_tmp_19_2_12_2_reg_6729;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_991_p1 <= ap_reg_pp0_iter4_tmp_19_0_12_2_reg_6534;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_991_p1 <= ap_reg_pp0_iter3_tmp_19_2_12_1_reg_5624;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_991_p1 <= ap_reg_pp0_iter2_tmp_19_0_12_1_reg_4974;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_991_p1 <= tmp_19_6_11_reg_6079;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_991_p1 <= tmp_19_4_11_reg_5754;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_991_p1 <= tmp_19_2_11_reg_5429;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_991_p1 <= tmp_19_0_11_reg_4969;
else
grp_fu_991_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_995_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_51_fu_2217_p1, ap_enable_reg_pp0_iter2, tmp_131_fu_2321_p1, tmp_211_fu_2425_p1, tmp_291_fu_2529_p1, ap_enable_reg_pp0_iter3, tmp_20_1_reg_7124, tmp_20_3_reg_7254, ap_enable_reg_pp0_iter5, tmp_20_1_0_1_reg_7644, tmp_20_3_0_1_reg_7774, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_995_p0 <= tmp_20_3_0_1_reg_7774;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_995_p0 <= tmp_20_1_0_1_reg_7644;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_995_p0 <= tmp_20_3_reg_7254;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_995_p0 <= tmp_20_1_reg_7124;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_995_p0 <= tmp_291_fu_2529_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_995_p0 <= tmp_211_fu_2425_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_995_p0 <= tmp_131_fu_2321_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_995_p0 <= tmp_51_fu_2217_p1;
else
grp_fu_995_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_995_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_reg_4979, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_0_1_reg_5244, tmp_19_3_reg_5434, tmp_19_5_reg_5759, ap_reg_pp0_iter3_tmp_19_3_0_1_reg_5824, tmp_19_7_reg_6084, ap_reg_pp0_iter4_tmp_19_1_0_2_reg_6539, ap_reg_pp0_iter4_tmp_19_3_0_2_reg_6734, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_995_p1 <= ap_reg_pp0_iter4_tmp_19_3_0_2_reg_6734;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_995_p1 <= ap_reg_pp0_iter4_tmp_19_1_0_2_reg_6539;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_995_p1 <= ap_reg_pp0_iter3_tmp_19_3_0_1_reg_5824;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_995_p1 <= ap_reg_pp0_iter3_tmp_19_1_0_1_reg_5244;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_995_p1 <= tmp_19_7_reg_6084;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_995_p1 <= tmp_19_5_reg_5759;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_995_p1 <= tmp_19_3_reg_5434;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_995_p1 <= tmp_19_1_reg_4979;
else
grp_fu_995_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_999_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_54_fu_2221_p1, tmp_134_fu_2325_p1, tmp_214_fu_2429_p1, tmp_294_fu_2533_p1, ap_enable_reg_pp0_iter3, tmp_20_1_1_reg_7129, tmp_20_3_1_reg_7259, ap_enable_reg_pp0_iter5, tmp_20_1_1_1_reg_7649, tmp_20_3_1_1_reg_7779, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_999_p0 <= tmp_20_3_1_1_reg_7779;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_999_p0 <= tmp_20_1_1_1_reg_7649;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_999_p0 <= tmp_20_3_1_reg_7259;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_999_p0 <= tmp_20_1_1_reg_7129;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_999_p0 <= tmp_294_fu_2533_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_999_p0 <= tmp_214_fu_2429_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_999_p0 <= tmp_134_fu_2325_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_999_p0 <= tmp_54_fu_2221_p1;
else
grp_fu_999_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_999_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_1_reg_4984, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_1_1_reg_5254, tmp_19_3_1_reg_5439, tmp_19_5_1_reg_5764, ap_reg_pp0_iter3_tmp_19_3_1_1_reg_5829, tmp_19_7_1_reg_6089, ap_reg_pp0_iter4_tmp_19_1_1_2_reg_6544, ap_reg_pp0_iter4_tmp_19_3_1_2_reg_6739, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_999_p1 <= ap_reg_pp0_iter4_tmp_19_3_1_2_reg_6739;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_999_p1 <= ap_reg_pp0_iter4_tmp_19_1_1_2_reg_6544;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_999_p1 <= ap_reg_pp0_iter3_tmp_19_3_1_1_reg_5829;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_999_p1 <= ap_reg_pp0_iter3_tmp_19_1_1_1_reg_5254;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_999_p1 <= tmp_19_7_1_reg_6089;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_999_p1 <= tmp_19_5_1_reg_5764;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_999_p1 <= tmp_19_3_1_reg_5439;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_999_p1 <= tmp_19_1_1_reg_4984;
else
grp_fu_999_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
i_1_fu_1553_p2 <= std_logic_vector(unsigned(ap_const_lv3_1) + unsigned(ap_phi_mux_i_phi_fu_900_p4));
indvar_flatten_next1_fu_1547_p2 <= std_logic_vector(unsigned(ap_phi_mux_indvar_flatten1_phi_fu_889_p4) + unsigned(ap_const_lv10_1));
indvar_flatten_next_fu_1613_p3 <=
ap_const_lv8_1 when (exitcond_flatten_reg_3190(0) = '1') else
indvar_flatten_op_reg_3211;
indvar_flatten_op_fu_1571_p2 <= std_logic_vector(unsigned(ap_const_lv8_1) + unsigned(ap_phi_mux_indvar_flatten_phi_fu_912_p4));
j_1_fu_1642_p2 <= std_logic_vector(unsigned(ap_const_lv3_1) + unsigned(j_mid_reg_3216));
j_mid_fu_1577_p3 <=
ap_const_lv3_0 when (exitcond_flatten_reg_3190(0) = '1') else
j_reg_919;
not_exitcond_flatten_fu_1590_p2 <= (exitcond_flatten_reg_3190 xor ap_const_lv1_1);
p_shl1_cast_fu_1690_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_50_fu_1683_p3),10));
p_shl2_cast_fu_1629_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_fu_1622_p3),6));
p_shl_cast_fu_1679_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_fu_1672_p3),10));
row_b_1_fu_1652_p2 <= std_logic_vector(unsigned(ap_const_lv5_1) + unsigned(row_b_mid2_reg_3245));
row_b_mid2_fu_1605_p3 <=
ap_const_lv5_0 when (tmp_4_fu_1600_p2(0) = '1') else
row_b_reg_931;
tmp_100_fu_2281_p1 <= tmp_99_reg_4604;
tmp_101_fu_2730_p1 <= tmp_20_2_3_2_reg_8244;
tmp_103_fu_2285_p1 <= tmp_102_reg_4609;
tmp_104_fu_2733_p1 <= tmp_20_2_4_2_reg_8249;
tmp_106_fu_2289_p1 <= tmp_105_reg_4614;
tmp_107_fu_2736_p1 <= tmp_20_2_5_2_reg_8254;
tmp_109_fu_2293_p1 <= tmp_108_reg_4619;
tmp_10_fu_1672_p3 <= (tmp_s_reg_3270 & ap_const_lv4_0);
tmp_110_fu_2739_p1 <= tmp_20_2_6_2_reg_8259;
tmp_112_fu_2297_p1 <= tmp_111_reg_4624;
tmp_113_fu_2742_p1 <= tmp_20_2_7_2_reg_8264;
tmp_115_fu_2301_p1 <= tmp_114_reg_4629;
tmp_116_fu_2745_p1 <= tmp_20_2_8_2_reg_8269;
tmp_118_fu_2305_p1 <= tmp_117_reg_4634;
tmp_119_fu_2748_p1 <= tmp_20_2_9_2_reg_8274;
tmp_11_fu_2165_p1 <= tmp_350_reg_4449;
tmp_121_fu_2309_p1 <= tmp_120_reg_4639;
tmp_122_fu_2751_p1 <= tmp_20_2_10_2_reg_8279;
tmp_124_fu_2313_p1 <= tmp_123_reg_4644;
tmp_125_fu_2754_p1 <= tmp_20_2_11_2_reg_8284;
tmp_127_fu_2317_p1 <= tmp_126_reg_4649;
tmp_128_fu_2757_p1 <= tmp_20_2_12_2_reg_8289;
tmp_129_fu_2760_p14 <= ((((((((((((tmp_128_fu_2757_p1 & tmp_125_fu_2754_p1) & tmp_122_fu_2751_p1) & tmp_119_fu_2748_p1) & tmp_116_fu_2745_p1) & tmp_113_fu_2742_p1) & tmp_110_fu_2739_p1) & tmp_107_fu_2736_p1) & tmp_104_fu_2733_p1) & tmp_101_fu_2730_p1) & tmp_98_fu_2727_p1) & tmp_95_fu_2724_p1) & tmp_92_fu_2721_p1);
tmp_12_1_fu_1499_p2 <= std_logic_vector(unsigned(ap_phi_mux_j_phi_fu_923_p4) + unsigned(ap_const_lv3_1));
tmp_12_1_mid1_fu_1667_p2 <= std_logic_vector(unsigned(ap_const_lv3_2) + unsigned(j_mid_reg_3216));
tmp_12_2_fu_1505_p2 <= std_logic_vector(unsigned(ap_phi_mux_j_phi_fu_923_p4) + unsigned(ap_const_lv3_2));
tmp_12_2_mid1_fu_1748_p2 <= std_logic_vector(unsigned(ap_const_lv3_3) + unsigned(j_mid_reg_3216));
tmp_12_3_fu_1511_p2 <= std_logic_vector(unsigned(ap_phi_mux_j_phi_fu_923_p4) + unsigned(ap_const_lv3_3));
tmp_12_3_mid1_fu_1824_p2 <= (j_mid_reg_3216 xor ap_const_lv3_4);
tmp_12_4_fu_1517_p2 <= std_logic_vector(unsigned(tmp_6_cast2_fu_1495_p1) + unsigned(ap_const_lv4_4));
tmp_12_4_mid1_fu_1840_p2 <= std_logic_vector(unsigned(ap_const_lv4_4) + unsigned(tmp_6_cast2_mid1_fu_1811_p1));
tmp_12_5_fu_1523_p2 <= std_logic_vector(unsigned(tmp_6_cast2_fu_1495_p1) + unsigned(ap_const_lv4_5));
tmp_12_5_mid1_fu_1846_p2 <= std_logic_vector(unsigned(ap_const_lv4_5) + unsigned(tmp_6_cast2_mid1_fu_1811_p1));
tmp_12_6_fu_1529_p2 <= std_logic_vector(unsigned(tmp_6_cast2_fu_1495_p1) + unsigned(ap_const_lv4_6));
tmp_12_6_mid1_fu_1852_p2 <= std_logic_vector(unsigned(ap_const_lv4_6) + unsigned(tmp_6_cast2_mid1_fu_1811_p1));
tmp_12_7_fu_1535_p2 <= std_logic_vector(unsigned(tmp_6_cast2_fu_1495_p1) + unsigned(ap_const_lv4_7));
tmp_12_7_mid1_fu_1858_p2 <= std_logic_vector(unsigned(ap_const_lv4_7) + unsigned(tmp_6_cast2_mid1_fu_1811_p1));
tmp_12_fu_2581_p1 <= tmp_20_0_0_2_reg_8099;
tmp_130_fu_1753_p2 <= std_logic_vector(unsigned(tmp_90_reg_3299) + unsigned(tmp_5_mid2_cast1_fu_1718_p1));
tmp_131_fu_2321_p1 <= tmp_354_reg_4654;
tmp_132_fu_2791_p1 <= tmp_20_3_0_2_reg_8294;
tmp_134_fu_2325_p1 <= tmp_133_reg_4659;
tmp_135_fu_2794_p1 <= tmp_20_3_1_2_reg_8299;
tmp_137_fu_2329_p1 <= tmp_136_reg_4664;
tmp_138_fu_2797_p1 <= tmp_20_3_2_2_reg_8304;
tmp_13_1_mid2_cast_fu_1744_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_1_mid2_fu_1738_p3),10));
tmp_13_1_mid2_fu_1738_p3 <=
tmp_12_1_mid1_reg_3294 when (tmp_7_mid_reg_3233(0) = '1') else
tmp_13_1_mid_fu_1712_p3;
tmp_13_1_mid_fu_1712_p3 <=
ap_const_lv3_1 when (exitcond_flatten_reg_3190(0) = '1') else
tmp_12_1_reg_3141;
tmp_13_2_mid2_cast_fu_1820_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_2_mid2_fu_1814_p3),10));
tmp_13_2_mid2_fu_1814_p3 <=
tmp_12_2_mid1_reg_3331 when (tmp_7_mid_reg_3233(0) = '1') else
tmp_13_2_mid_fu_1763_p3;
tmp_13_2_mid_fu_1763_p3 <=
ap_const_lv3_2 when (exitcond_flatten_reg_3190(0) = '1') else
tmp_12_2_reg_3146;
tmp_13_3_mid2_cast_fu_1836_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_3_mid2_fu_1829_p3),10));
tmp_13_3_mid2_fu_1829_p3 <=
tmp_12_3_mid1_fu_1824_p2 when (tmp_7_mid_reg_3233(0) = '1') else
tmp_13_3_mid_fu_1769_p3;
tmp_13_3_mid_fu_1769_p3 <=
ap_const_lv3_3 when (exitcond_flatten_reg_3190(0) = '1') else
tmp_12_3_reg_3151;
tmp_13_4_mid2_cast_fu_1932_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_4_mid2_fu_1926_p3),10));
tmp_13_4_mid2_fu_1926_p3 <=
tmp_12_4_mid1_reg_3481 when (tmp_7_mid_reg_3233(0) = '1') else
tmp_13_4_mid_fu_1886_p3;
tmp_13_4_mid_fu_1886_p3 <=
ap_const_lv4_4 when (exitcond_flatten_reg_3190(0) = '1') else
tmp_12_4_reg_3156;
tmp_13_5_mid2_cast_fu_1942_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_5_mid2_fu_1936_p3),10));
tmp_13_5_mid2_fu_1936_p3 <=
tmp_12_5_mid1_reg_3486 when (tmp_7_mid_reg_3233(0) = '1') else
tmp_13_5_mid_fu_1892_p3;
tmp_13_5_mid_fu_1892_p3 <=
ap_const_lv4_5 when (exitcond_flatten_reg_3190(0) = '1') else
tmp_12_5_reg_3161;
tmp_13_6_mid2_cast_fu_1952_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_6_mid2_fu_1946_p3),10));
tmp_13_6_mid2_fu_1946_p3 <=
tmp_12_6_mid1_reg_3491 when (tmp_7_mid_reg_3233(0) = '1') else
tmp_13_6_mid_fu_1898_p3;
tmp_13_6_mid_fu_1898_p3 <=
ap_const_lv4_6 when (exitcond_flatten_reg_3190(0) = '1') else
tmp_12_6_reg_3166;
tmp_13_7_mid2_cast_fu_1962_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_7_mid2_fu_1956_p3),10));
tmp_13_7_mid2_fu_1956_p3 <=
tmp_12_7_mid1_reg_3496 when (tmp_7_mid_reg_3233(0) = '1') else
tmp_13_7_mid_fu_1904_p3;
tmp_13_7_mid_fu_1904_p3 <=
ap_const_lv4_7 when (exitcond_flatten_reg_3190(0) = '1') else
tmp_12_7_reg_3171;
tmp_140_fu_2333_p1 <= tmp_139_reg_4669;
tmp_141_fu_2800_p1 <= tmp_20_3_3_2_reg_8309;
tmp_143_fu_2337_p1 <= tmp_142_reg_4674;
tmp_144_fu_2803_p1 <= tmp_20_3_4_2_reg_8314;
tmp_146_fu_2341_p1 <= tmp_145_reg_4679;
tmp_147_fu_2806_p1 <= tmp_20_3_5_2_reg_8319;
tmp_149_fu_2345_p1 <= tmp_148_reg_4684;
tmp_14_fu_2169_p1 <= tmp_13_reg_4454;
tmp_150_fu_2809_p1 <= tmp_20_3_6_2_reg_8324;
tmp_152_fu_2349_p1 <= tmp_151_reg_4689;
tmp_153_fu_2812_p1 <= tmp_20_3_7_2_reg_8329;
tmp_155_fu_2353_p1 <= tmp_154_reg_4694;
tmp_156_fu_2815_p1 <= tmp_20_3_8_2_reg_8334;
tmp_158_fu_2357_p1 <= tmp_157_reg_4699;
tmp_159_fu_2818_p1 <= tmp_20_3_9_2_reg_8339;
tmp_15_fu_2584_p1 <= tmp_20_0_1_2_reg_8104;
tmp_161_fu_2361_p1 <= tmp_160_reg_4704;
tmp_162_fu_2821_p1 <= tmp_20_3_10_2_reg_8344;
tmp_164_fu_2365_p1 <= tmp_163_reg_4709;
tmp_165_fu_2824_p1 <= tmp_20_3_11_2_reg_8349;
tmp_167_fu_2369_p1 <= tmp_166_reg_4714;
tmp_168_fu_2827_p1 <= tmp_20_3_12_2_reg_8354;
tmp_169_fu_2830_p14 <= ((((((((((((tmp_168_fu_2827_p1 & tmp_165_fu_2824_p1) & tmp_162_fu_2821_p1) & tmp_159_fu_2818_p1) & tmp_156_fu_2815_p1) & tmp_153_fu_2812_p1) & tmp_150_fu_2809_p1) & tmp_147_fu_2806_p1) & tmp_144_fu_2803_p1) & tmp_141_fu_2800_p1) & tmp_138_fu_2797_p1) & tmp_135_fu_2794_p1) & tmp_132_fu_2791_p1);
tmp_170_fu_1758_p2 <= std_logic_vector(unsigned(tmp_90_reg_3299) + unsigned(tmp_13_1_mid2_cast_fu_1744_p1));
tmp_171_fu_2373_p1 <= tmp_355_reg_4719;
tmp_172_fu_2861_p1 <= tmp_20_4_0_2_reg_8359;
tmp_174_fu_2377_p1 <= tmp_173_reg_4724;
tmp_175_fu_2864_p1 <= tmp_20_4_1_2_reg_8364;
tmp_177_fu_2381_p1 <= tmp_176_reg_4729;
tmp_178_fu_2867_p1 <= tmp_20_4_2_2_reg_8369;
tmp_17_fu_2173_p1 <= tmp_16_reg_4459;
tmp_180_fu_2385_p1 <= tmp_179_reg_4734;
tmp_181_fu_2870_p1 <= tmp_20_4_3_2_reg_8374;
tmp_183_fu_2389_p1 <= tmp_182_reg_4739;
tmp_184_fu_2873_p1 <= tmp_20_4_4_2_reg_8379;
tmp_186_fu_2393_p1 <= tmp_185_reg_4744;
tmp_187_fu_2876_p1 <= tmp_20_4_5_2_reg_8384;
tmp_189_fu_2397_p1 <= tmp_188_reg_4749;
tmp_18_fu_2587_p1 <= tmp_20_0_2_2_reg_8109;
tmp_190_fu_2879_p1 <= tmp_20_4_6_2_reg_8389;
tmp_192_fu_2401_p1 <= tmp_191_reg_4754;
tmp_193_fu_2882_p1 <= tmp_20_4_7_2_reg_8394;
tmp_195_fu_2405_p1 <= tmp_194_reg_4759;
tmp_196_fu_2885_p1 <= tmp_20_4_8_2_reg_8399;
tmp_198_fu_2409_p1 <= tmp_197_reg_4764;
tmp_199_fu_2888_p1 <= tmp_20_4_9_2_reg_8404;
tmp_1_cast_fu_1700_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_1_reg_3257),7));
tmp_1_fu_1633_p2 <= std_logic_vector(unsigned(tmp_1_mid2_cast_fu_1619_p1) + unsigned(p_shl2_cast_fu_1629_p1));
tmp_1_mid2_cast_fu_1619_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_1_mid2_v_reg_3225),6));
tmp_1_mid2_v_fu_1584_p3 <=
i_1_reg_3185 when (exitcond_flatten_reg_3190(0) = '1') else
i_reg_896;
tmp_201_fu_2413_p1 <= tmp_200_reg_4769;
tmp_202_fu_2891_p1 <= tmp_20_4_10_2_reg_8409;
tmp_204_fu_2417_p1 <= tmp_203_reg_4774;
tmp_205_fu_2894_p1 <= tmp_20_4_11_2_reg_8414;
tmp_207_fu_2421_p1 <= tmp_206_reg_4779;
tmp_208_fu_2897_p1 <= tmp_20_4_12_2_reg_8419;
tmp_209_fu_2900_p14 <= ((((((((((((tmp_208_fu_2897_p1 & tmp_205_fu_2894_p1) & tmp_202_fu_2891_p1) & tmp_199_fu_2888_p1) & tmp_196_fu_2885_p1) & tmp_193_fu_2882_p1) & tmp_190_fu_2879_p1) & tmp_187_fu_2876_p1) & tmp_184_fu_2873_p1) & tmp_181_fu_2870_p1) & tmp_178_fu_2867_p1) & tmp_175_fu_2864_p1) & tmp_172_fu_2861_p1);
tmp_20_fu_2177_p1 <= tmp_19_reg_4464;
tmp_210_fu_1876_p2 <= std_logic_vector(unsigned(tmp_90_reg_3299) + unsigned(tmp_13_2_mid2_cast_fu_1820_p1));
tmp_211_fu_2425_p1 <= tmp_356_reg_4784;
tmp_212_fu_2931_p1 <= tmp_20_5_0_2_reg_8424;
tmp_214_fu_2429_p1 <= tmp_213_reg_4789;
tmp_215_fu_2934_p1 <= tmp_20_5_1_2_reg_8429;
tmp_217_fu_2433_p1 <= tmp_216_reg_4794;
tmp_218_fu_2937_p1 <= tmp_20_5_2_2_reg_8434;
tmp_21_fu_2590_p1 <= tmp_20_0_3_2_reg_8114;
tmp_220_fu_2437_p1 <= tmp_219_reg_4799;
tmp_221_fu_2940_p1 <= tmp_20_5_3_2_reg_8439;
tmp_223_fu_2441_p1 <= tmp_222_reg_4804;
tmp_224_fu_2943_p1 <= tmp_20_5_4_2_reg_8444;
tmp_226_fu_2445_p1 <= tmp_225_reg_4809;
tmp_227_fu_2946_p1 <= tmp_20_5_5_2_reg_8449;
tmp_229_fu_2449_p1 <= tmp_228_reg_4814;
tmp_230_fu_2949_p1 <= tmp_20_5_6_2_reg_8454;
tmp_232_fu_2453_p1 <= tmp_231_reg_4819;
tmp_233_fu_2952_p1 <= tmp_20_5_7_2_reg_8459;
tmp_235_fu_2457_p1 <= tmp_234_reg_4824;
tmp_236_fu_2955_p1 <= tmp_20_5_8_2_reg_8464;
tmp_238_fu_2461_p1 <= tmp_237_reg_4829;
tmp_239_fu_2958_p1 <= tmp_20_5_9_2_reg_8469;
tmp_23_fu_2181_p1 <= tmp_22_reg_4469;
tmp_241_fu_2465_p1 <= tmp_240_reg_4834;
tmp_242_fu_2961_p1 <= tmp_20_5_10_2_reg_8474;
tmp_244_fu_2469_p1 <= tmp_243_reg_4839;
tmp_245_fu_2964_p1 <= tmp_20_5_11_2_reg_8479;
tmp_247_fu_2473_p1 <= tmp_246_reg_4844;
tmp_248_fu_2967_p1 <= tmp_20_5_12_2_reg_8484;
tmp_249_fu_2970_p14 <= ((((((((((((tmp_248_fu_2967_p1 & tmp_245_fu_2964_p1) & tmp_242_fu_2961_p1) & tmp_239_fu_2958_p1) & tmp_236_fu_2955_p1) & tmp_233_fu_2952_p1) & tmp_230_fu_2949_p1) & tmp_227_fu_2946_p1) & tmp_224_fu_2943_p1) & tmp_221_fu_2940_p1) & tmp_218_fu_2937_p1) & tmp_215_fu_2934_p1) & tmp_212_fu_2931_p1);
tmp_24_fu_2593_p1 <= tmp_20_0_4_2_reg_8119;
tmp_250_fu_1881_p2 <= std_logic_vector(unsigned(tmp_90_reg_3299) + unsigned(tmp_13_3_mid2_cast_fu_1836_p1));
tmp_251_fu_2477_p1 <= tmp_357_reg_5044;
tmp_252_fu_3001_p1 <= tmp_20_6_0_2_reg_8489;
tmp_254_fu_2481_p1 <= tmp_253_reg_5049;
tmp_255_fu_3004_p1 <= tmp_20_6_1_2_reg_8494;
tmp_257_fu_2485_p1 <= tmp_256_reg_5054;
tmp_258_fu_3007_p1 <= tmp_20_6_2_2_reg_8499;
tmp_260_fu_2489_p1 <= tmp_259_reg_5059;
tmp_261_fu_3010_p1 <= tmp_20_6_3_2_reg_8504;
tmp_263_fu_2493_p1 <= tmp_262_reg_5064;
tmp_264_fu_3013_p1 <= tmp_20_6_4_2_reg_8509;
tmp_266_fu_2497_p1 <= tmp_265_reg_5069;
tmp_267_fu_3016_p1 <= tmp_20_6_5_2_reg_8514;
tmp_269_fu_2501_p1 <= tmp_268_reg_5074;
tmp_26_fu_2185_p1 <= tmp_25_reg_4474;
tmp_270_fu_3019_p1 <= tmp_20_6_6_2_reg_8519;
tmp_272_fu_2505_p1 <= tmp_271_reg_5079;
tmp_273_fu_3022_p1 <= tmp_20_6_7_2_reg_8524;
tmp_275_fu_2509_p1 <= tmp_274_reg_5084;
tmp_276_fu_3025_p1 <= tmp_20_6_8_2_reg_8529;
tmp_278_fu_2513_p1 <= tmp_277_reg_5089;
tmp_279_fu_3028_p1 <= tmp_20_6_9_2_reg_8534;
tmp_27_fu_2596_p1 <= tmp_20_0_5_2_reg_8124;
tmp_281_fu_2517_p1 <= tmp_280_reg_5094;
tmp_282_fu_3031_p1 <= tmp_20_6_10_2_reg_8539;
tmp_284_fu_2521_p1 <= tmp_283_reg_5099;
tmp_285_fu_3034_p1 <= tmp_20_6_11_2_reg_8544;
tmp_287_fu_2525_p1 <= tmp_286_reg_5104;
tmp_288_fu_3037_p1 <= tmp_20_6_12_2_reg_8549;
tmp_289_fu_3040_p14 <= ((((((((((((tmp_288_fu_3037_p1 & tmp_285_fu_3034_p1) & tmp_282_fu_3031_p1) & tmp_279_fu_3028_p1) & tmp_276_fu_3025_p1) & tmp_273_fu_3022_p1) & tmp_270_fu_3019_p1) & tmp_267_fu_3016_p1) & tmp_264_fu_3013_p1) & tmp_261_fu_3010_p1) & tmp_258_fu_3007_p1) & tmp_255_fu_3004_p1) & tmp_252_fu_3001_p1);
tmp_290_fu_1978_p2 <= std_logic_vector(unsigned(tmp_90_reg_3299) + unsigned(tmp_13_4_mid2_cast_fu_1932_p1));
tmp_291_fu_2529_p1 <= tmp_358_reg_5109;
tmp_292_fu_3071_p1 <= tmp_20_7_0_2_reg_8554;
tmp_294_fu_2533_p1 <= tmp_293_reg_5114;
tmp_295_fu_3074_p1 <= tmp_20_7_1_2_reg_8559;
tmp_297_fu_2537_p1 <= tmp_296_reg_5119;
tmp_298_fu_3077_p1 <= tmp_20_7_2_2_reg_8564;
tmp_29_fu_2189_p1 <= tmp_28_reg_4479;
tmp_2_cast_fu_1703_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_2_reg_3281),7));
tmp_2_cast_mid2_fu_1639_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_1_mid2_v_reg_3225),5));
tmp_2_fu_1657_p2 <= std_logic_vector(unsigned(ap_const_lv6_19) + unsigned(tmp_1_reg_3257));
tmp_300_fu_2541_p1 <= tmp_299_reg_5124;
tmp_301_fu_3080_p1 <= tmp_20_7_3_2_reg_8569;
tmp_303_fu_2545_p1 <= tmp_302_reg_5129;
tmp_304_fu_3083_p1 <= tmp_20_7_4_2_reg_8574;
tmp_306_fu_2549_p1 <= tmp_305_reg_5134;
tmp_307_fu_3086_p1 <= tmp_20_7_5_2_reg_8579;
tmp_309_fu_2553_p1 <= tmp_308_reg_5139;
tmp_30_fu_2599_p1 <= tmp_20_0_6_2_reg_8129;
tmp_310_fu_3089_p1 <= tmp_20_7_6_2_reg_8584;
tmp_312_fu_2557_p1 <= tmp_311_reg_5144;
tmp_313_fu_3092_p1 <= tmp_20_7_7_2_reg_8589;
tmp_315_fu_2561_p1 <= tmp_314_reg_5149;
tmp_316_fu_3095_p1 <= tmp_20_7_8_2_reg_8594;
tmp_318_fu_2565_p1 <= tmp_317_reg_5154;
tmp_319_fu_3098_p1 <= tmp_20_7_9_2_reg_8599;
tmp_321_fu_2569_p1 <= tmp_320_reg_5159;
tmp_322_fu_3101_p1 <= tmp_20_7_10_2_reg_8604;
tmp_324_fu_2573_p1 <= tmp_323_reg_5164;
tmp_325_fu_3104_p1 <= tmp_20_7_11_2_reg_8609;
tmp_327_fu_2577_p1 <= tmp_326_reg_5169;
tmp_328_fu_3107_p1 <= tmp_20_7_12_2_reg_8614;
tmp_329_fu_3110_p14 <= ((((((((((((tmp_328_fu_3107_p1 & tmp_325_fu_3104_p1) & tmp_322_fu_3101_p1) & tmp_319_fu_3098_p1) & tmp_316_fu_3095_p1) & tmp_313_fu_3092_p1) & tmp_310_fu_3089_p1) & tmp_307_fu_3086_p1) & tmp_304_fu_3083_p1) & tmp_301_fu_3080_p1) & tmp_298_fu_3077_p1) & tmp_295_fu_3074_p1) & tmp_292_fu_3071_p1);
tmp_32_fu_2193_p1 <= tmp_31_reg_4484;
tmp_330_cast_fu_1910_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_reg_3356),64));
tmp_330_fu_1983_p2 <= std_logic_vector(unsigned(tmp_90_reg_3299) + unsigned(tmp_13_5_mid2_cast_fu_1942_p1));
tmp_331_fu_1988_p2 <= std_logic_vector(unsigned(tmp_90_reg_3299) + unsigned(tmp_13_6_mid2_cast_fu_1952_p1));
tmp_332_fu_1993_p2 <= std_logic_vector(unsigned(tmp_90_reg_3299) + unsigned(tmp_13_7_mid2_cast_fu_1962_p1));
tmp_333_fu_2022_p3 <= (ap_reg_pp0_iter1_row_b_mid2_reg_3245 & ap_const_lv3_0);
tmp_334_cast_fu_1864_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_130_reg_3336),64));
tmp_334_fu_2029_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_333_fu_2022_p3),64));
tmp_335_cast_fu_1870_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_170_reg_3341),64));
tmp_335_fu_2034_p2 <= (tmp_333_fu_2022_p3 or ap_const_lv8_1);
tmp_336_cast_fu_1966_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_210_reg_3511),64));
tmp_336_fu_2040_p3 <= (ap_const_lv56_0 & tmp_335_fu_2034_p2);
tmp_337_cast_fu_1972_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_250_reg_3516),64));
tmp_337_fu_2049_p2 <= (tmp_333_reg_4307 or ap_const_lv8_2);
tmp_338_cast_fu_1998_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_290_reg_3616),64));
tmp_338_fu_2054_p3 <= (ap_const_lv56_0 & tmp_337_fu_2049_p2);
tmp_339_cast_fu_2004_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_330_reg_3621),64));
tmp_339_fu_2063_p2 <= (tmp_333_reg_4307 or ap_const_lv8_3);
tmp_33_fu_2602_p1 <= tmp_20_0_7_2_reg_8134;
tmp_340_cast_fu_2010_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_331_reg_3626),64));
tmp_340_fu_2068_p3 <= (ap_const_lv56_0 & tmp_339_fu_2063_p2);
tmp_341_cast_fu_2016_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_332_reg_3631),64));
tmp_341_fu_2077_p2 <= (tmp_333_reg_4307 or ap_const_lv8_4);
tmp_342_fu_2082_p3 <= (ap_const_lv56_0 & tmp_341_fu_2077_p2);
tmp_343_fu_2091_p2 <= (tmp_333_reg_4307 or ap_const_lv8_5);
tmp_344_fu_2096_p3 <= (ap_const_lv56_0 & tmp_343_fu_2091_p2);
tmp_345_fu_2113_p2 <= (tmp_333_reg_4307 or ap_const_lv8_6);
tmp_346_fu_2118_p3 <= (ap_const_lv56_0 & tmp_345_fu_2113_p2);
tmp_347_fu_2127_p2 <= (tmp_333_reg_4307 or ap_const_lv8_7);
tmp_348_fu_2132_p3 <= (ap_const_lv56_0 & tmp_347_fu_2127_p2);
tmp_350_fu_2105_p0 <= bufo_Dout_A(416 - 1 downto 0);
tmp_350_fu_2105_p1 <= tmp_350_fu_2105_p0(32 - 1 downto 0);
tmp_352_fu_2109_p0 <= bufo_Dout_B(416 - 1 downto 0);
tmp_352_fu_2109_p1 <= tmp_352_fu_2109_p0(32 - 1 downto 0);
tmp_353_fu_2141_p0 <= bufo_Dout_A(416 - 1 downto 0);
tmp_353_fu_2141_p1 <= tmp_353_fu_2141_p0(32 - 1 downto 0);
tmp_354_fu_2145_p0 <= bufo_Dout_B(416 - 1 downto 0);
tmp_354_fu_2145_p1 <= tmp_354_fu_2145_p0(32 - 1 downto 0);
tmp_355_fu_2149_p0 <= bufo_Dout_A(416 - 1 downto 0);
tmp_355_fu_2149_p1 <= tmp_355_fu_2149_p0(32 - 1 downto 0);
tmp_356_fu_2153_p0 <= bufo_Dout_B(416 - 1 downto 0);
tmp_356_fu_2153_p1 <= tmp_356_fu_2153_p0(32 - 1 downto 0);
tmp_357_fu_2157_p0 <= bufo_Dout_A(416 - 1 downto 0);
tmp_357_fu_2157_p1 <= tmp_357_fu_2157_p0(32 - 1 downto 0);
tmp_358_fu_2161_p0 <= bufo_Dout_B(416 - 1 downto 0);
tmp_358_fu_2161_p1 <= tmp_358_fu_2161_p0(32 - 1 downto 0);
tmp_35_fu_2197_p1 <= tmp_34_reg_4489;
tmp_36_fu_2605_p1 <= tmp_20_0_8_2_reg_8139;
tmp_38_fu_2201_p1 <= tmp_37_reg_4494;
tmp_39_fu_2608_p1 <= tmp_20_0_9_2_reg_8144;
tmp_3_fu_1706_p2 <= std_logic_vector(unsigned(ap_const_lv7_32) + unsigned(tmp_1_cast_fu_1700_p1));
tmp_41_fu_2205_p1 <= tmp_40_reg_4499;
tmp_42_fu_2611_p1 <= tmp_20_0_10_2_reg_8149;
tmp_44_fu_2209_p1 <= tmp_43_reg_4504;
tmp_45_fu_2614_p1 <= tmp_20_0_11_2_reg_8154;
tmp_47_fu_2213_p1 <= tmp_46_reg_4509;
tmp_48_fu_2617_p1 <= tmp_20_0_12_2_reg_8159;
tmp_49_fu_2620_p14 <= ((((((((((((tmp_48_fu_2617_p1 & tmp_45_fu_2614_p1) & tmp_42_fu_2611_p1) & tmp_39_fu_2608_p1) & tmp_36_fu_2605_p1) & tmp_33_fu_2602_p1) & tmp_30_fu_2599_p1) & tmp_27_fu_2596_p1) & tmp_24_fu_2593_p1) & tmp_21_fu_2590_p1) & tmp_18_fu_2587_p1) & tmp_15_fu_2584_p1) & tmp_12_fu_2581_p1);
tmp_4_fu_1600_p2 <= (tmp_7_mid_fu_1595_p2 or exitcond_flatten_reg_3190);
tmp_50_fu_1683_p3 <= (tmp_s_reg_3270 & ap_const_lv2_0);
tmp_51_fu_2217_p1 <= tmp_352_reg_4514;
tmp_52_fu_2651_p1 <= tmp_20_1_0_2_reg_8164;
tmp_54_fu_2221_p1 <= tmp_53_reg_4519;
tmp_55_fu_2654_p1 <= tmp_20_1_1_2_reg_8169;
tmp_57_fu_2225_p1 <= tmp_56_reg_4524;
tmp_58_fu_2657_p1 <= tmp_20_1_2_2_reg_8174;
tmp_5_fu_1565_p2 <= "1" when (ap_phi_mux_row_b_phi_fu_935_p4 = ap_const_lv5_1B) else "0";
tmp_5_mid2_cast1_fu_1718_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_mid2_reg_3286),10));
tmp_5_mid2_cast2_fu_1721_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_mid2_reg_3286),7));
tmp_5_mid2_cast_fu_1724_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_mid2_reg_3286),6));
tmp_5_mid2_fu_1662_p3 <=
j_1_reg_3264 when (tmp_7_mid_reg_3233(0) = '1') else
j_mid_reg_3216;
tmp_60_fu_2229_p1 <= tmp_59_reg_4529;
tmp_61_fu_2660_p1 <= tmp_20_1_3_2_reg_8179;
tmp_63_fu_2233_p1 <= tmp_62_reg_4534;
tmp_64_fu_2663_p1 <= tmp_20_1_4_2_reg_8184;
tmp_66_fu_2237_p1 <= tmp_65_reg_4539;
tmp_67_fu_2666_p1 <= tmp_20_1_5_2_reg_8189;
tmp_69_fu_2241_p1 <= tmp_68_reg_4544;
tmp_6_cast2_fu_1495_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_phi_mux_j_phi_fu_923_p4),4));
tmp_6_cast2_mid1_fu_1811_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_1_reg_3264),4));
tmp_6_cast_fu_1775_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_6_reg_3321),64));
tmp_6_fu_1727_p2 <= std_logic_vector(unsigned(tmp_1_reg_3257) + unsigned(tmp_5_mid2_cast_fu_1724_p1));
tmp_70_fu_2669_p1 <= tmp_20_1_6_2_reg_8194;
tmp_72_fu_2245_p1 <= tmp_71_reg_4549;
tmp_73_fu_2672_p1 <= tmp_20_1_7_2_reg_8199;
tmp_75_fu_2249_p1 <= tmp_74_reg_4554;
tmp_76_fu_2675_p1 <= tmp_20_1_8_2_reg_8204;
tmp_78_fu_2253_p1 <= tmp_77_reg_4559;
tmp_79_fu_2678_p1 <= tmp_20_1_9_2_reg_8209;
tmp_7_fu_1807_p2 <= std_logic_vector(unsigned(tmp_3_reg_3311) + unsigned(tmp_5_mid2_cast2_reg_3316));
tmp_7_mid_fu_1595_p2 <= (tmp_5_reg_3206 and not_exitcond_flatten_fu_1590_p2);
tmp_81_fu_2257_p1 <= tmp_80_reg_4564;
tmp_82_fu_2681_p1 <= tmp_20_1_10_2_reg_8214;
tmp_84_fu_2261_p1 <= tmp_83_reg_4569;
tmp_85_fu_2684_p1 <= tmp_20_1_11_2_reg_8219;
tmp_87_fu_2265_p1 <= tmp_86_reg_4574;
tmp_88_fu_2687_p1 <= tmp_20_1_12_2_reg_8224;
tmp_89_fu_2690_p14 <= ((((((((((((tmp_88_fu_2687_p1 & tmp_85_fu_2684_p1) & tmp_82_fu_2681_p1) & tmp_79_fu_2678_p1) & tmp_76_fu_2675_p1) & tmp_73_fu_2672_p1) & tmp_70_fu_2669_p1) & tmp_67_fu_2666_p1) & tmp_64_fu_2663_p1) & tmp_61_fu_2660_p1) & tmp_58_fu_2657_p1) & tmp_55_fu_2654_p1) & tmp_52_fu_2651_p1);
tmp_8_cast_fu_1791_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_8_reg_3326),64));
tmp_8_fu_1732_p2 <= std_logic_vector(unsigned(tmp_2_cast_fu_1703_p1) + unsigned(tmp_5_mid2_cast2_fu_1721_p1));
tmp_90_fu_1694_p2 <= std_logic_vector(unsigned(p_shl_cast_fu_1679_p1) - unsigned(p_shl1_cast_fu_1690_p1));
tmp_91_fu_2269_p1 <= tmp_353_reg_4589;
tmp_92_fu_2721_p1 <= tmp_20_2_0_2_reg_8229;
tmp_94_fu_2273_p1 <= tmp_93_reg_4594;
tmp_95_fu_2724_p1 <= tmp_20_2_1_2_reg_8234;
tmp_97_fu_2277_p1 <= tmp_96_reg_4599;
tmp_98_fu_2727_p1 <= tmp_20_2_2_2_reg_8239;
tmp_fu_1622_p3 <= (tmp_1_mid2_v_reg_3225 & ap_const_lv2_0);
tmp_s_fu_1647_p2 <= std_logic_vector(unsigned(tmp_2_cast_mid2_fu_1639_p1) + unsigned(row_b_mid2_reg_3245));
end behav;
|
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2007.
--Squarer, solo logica combinacional,
--optimizado para el polinomio de reduccion que se este empleando,
-- funciona solo si el máximo grado del polinomio de reduccion D más 2 es menor a m.
-- Se trata básicamente de un multiplicador de digito combinacional. El tamaño del digito es D+2;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-----------------------------------------------------------------------------------
entity squarer_113 is
generic(
NUM_BITS : positive := 113 --113 163, 233, 277, 283, 409, 571 -- Orden del campo finito
);
port(
-- clk : in std_logic;
-- en : in std_logic;
A_x : in std_logic_vector(NUM_BITS-1 downto 0);-- 2
A2_x : out std_logic_vector(NUM_BITS-1 downto 0)-- A2_x = (A_x) mod Fx
);
end;
---------------------------------------------------------------------------------------------------
architecture behave of squarer_113 is
begin
A2_x(112) <= A_x(56) xor A_x(108);
A2_x(111) <= A_x(112);
A2_x(110) <= A_x(55) xor A_x(107);
A2_x(109) <= A_x(111);
A2_x(108) <= A_x(54) xor A_x(106);
A2_x(107) <= A_x(110);
A2_x(106) <= A_x(53) xor A_x(105);
A2_x(105) <= A_x(109);
A2_x(104) <= A_x(52) xor A_x(104);
A2_x(103) <= A_x(108);
A2_x(102) <= A_x(51) xor A_x(103);
A2_x(101) <= A_x(107);
A2_x(100) <= A_x(50) xor A_x(102);
A2_x(99) <= A_x(106);
A2_x(98) <= A_x(49) xor A_x(101);
A2_x(97) <= A_x(105);
A2_x(96) <= A_x(48) xor A_x(100);
A2_x(95) <= A_x(104);
A2_x(94) <= A_x(47) xor A_x(99);
A2_x(93) <= A_x(103);
A2_x(92) <= A_x(46) xor A_x(98);
A2_x(91) <= A_x(102);
A2_x(90) <= A_x(45) xor A_x(97);
A2_x(89) <= A_x(101);
A2_x(88) <= A_x(44) xor A_x(96);
A2_x(87) <= A_x(100);
A2_x(86) <= A_x(43) xor A_x(95);
A2_x(85) <= A_x(99);
A2_x(84) <= A_x(42) xor A_x(94);
A2_x(83) <= A_x(98);
A2_x(82) <= A_x(41) xor A_x(93);
A2_x(81) <= A_x(97);
A2_x(80) <= A_x(40) xor A_x(92);
A2_x(79) <= A_x(96);
A2_x(78) <= A_x(39) xor A_x(91);
A2_x(77) <= A_x(95);
A2_x(76) <= A_x(38) xor A_x(90);
A2_x(75) <= A_x(94);
A2_x(74) <= A_x(37) xor A_x(89);
A2_x(73) <= A_x(93);
A2_x(72) <= A_x(36) xor A_x(88);
A2_x(71) <= A_x(92);
A2_x(70) <= A_x(35) xor A_x(87);
A2_x(69) <= A_x(91);
A2_x(68) <= A_x(34) xor A_x(86);
A2_x(67) <= A_x(90);
A2_x(66) <= A_x(33) xor A_x(85);
A2_x(65) <= A_x(89);
A2_x(64) <= A_x(32) xor A_x(84);
A2_x(63) <= A_x(88);
A2_x(62) <= A_x(31) xor A_x(83);
A2_x(61) <= A_x(87);
A2_x(60) <= A_x(30) xor A_x(82);
A2_x(59) <= A_x(86);
A2_x(58) <= A_x(29) xor A_x(81);
A2_x(57) <= A_x(85);
A2_x(56) <= A_x(28) xor A_x(80);
A2_x(55) <= A_x(84);
A2_x(54) <= A_x(27) xor A_x(79);
A2_x(53) <= A_x(83);
A2_x(52) <= A_x(26) xor A_x(78);
A2_x(51) <= A_x(82);
A2_x(50) <= A_x(25) xor A_x(77);
A2_x(49) <= A_x(81);
A2_x(48) <= A_x(24) xor A_x(76);
A2_x(47) <= A_x(80);
A2_x(46) <= A_x(23) xor A_x(75);
A2_x(45) <= A_x(79);
A2_x(44) <= A_x(22) xor A_x(74);
A2_x(43) <= A_x(78);
A2_x(42) <= A_x(21) xor A_x(73);
A2_x(41) <= A_x(77);
A2_x(40) <= A_x(20) xor A_x(72);
A2_x(39) <= A_x(76);
A2_x(38) <= A_x(19) xor A_x(71);
A2_x(37) <= A_x(75);
A2_x(36) <= A_x(18) xor A_x(70);
A2_x(35) <= A_x(74);
A2_x(34) <= A_x(17) xor A_x(69);
A2_x(33) <= A_x(73);
A2_x(32) <= A_x(16) xor A_x(68);
A2_x(31) <= A_x(72);
A2_x(30) <= A_x(15) xor A_x(67);
A2_x(29) <= A_x(71);
A2_x(28) <= A_x(14) xor A_x(66);
A2_x(27) <= A_x(70);
A2_x(26) <= A_x(13) xor A_x(65);
A2_x(25) <= A_x(69);
A2_x(24) <= A_x(12) xor A_x(64);
A2_x(23) <= A_x(68);
A2_x(22) <= A_x(11) xor A_x(63);
A2_x(21) <= A_x(67);
A2_x(20) <= A_x(10) xor A_x(62);
A2_x(19) <= A_x(66);
A2_x(18) <= A_x(9) xor A_x(61);
A2_x(17) <= A_x(65);
A2_x(16) <= A_x(8) xor A_x(60) xor A_x(112);
A2_x(15) <= A_x(64);
A2_x(14) <= A_x(7) xor A_x(59) xor A_x(111);
A2_x(13) <= A_x(63);
A2_x(12) <= A_x(6) xor A_x(58) xor A_x(110);
A2_x(11) <= A_x(62);
A2_x(10) <= A_x(5) xor A_x(57) xor A_x(109);
A2_x(9) <= A_x(61);
A2_x(8) <= A_x(4);
A2_x(7) <= A_x(60) xor A_x(112);
A2_x(6) <= A_x(3);
A2_x(5) <= A_x(59) xor A_x(111);
A2_x(4) <= A_x(2);
A2_x(3) <= A_x(58) xor A_x(110);
A2_x(2) <= A_x(1);
A2_x(1) <= A_x(57) xor A_x(109);
A2_x(0) <= A_x(0);
end behave; |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
use gaisler.grusb.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
wdogn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART2 tx data
rxd2 : in std_logic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_logic; -- bus ready
bexcn : in std_logic; -- bus exception
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
eth_macclk : in std_logic;
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
emdintn : in std_logic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic_vector(0 to CFG_CAN_NUM-1);
can_rxd : in std_logic_vector(0 to CFG_CAN_NUM-1);
-- can_stb : out std_logic_vector(0 to CFG_CAN_NUM-1)
spw_clk : in std_logic;
spw_rxdp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxdn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdn : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsn : out std_logic_vector(0 to CFG_SPW_NUM-1);
usb_clkout : in std_logic;
usb_d : inout std_logic_vector(7 downto 0);
usb_nxt : in std_logic;
usb_stp : out std_logic;
usb_dir : in std_logic;
usb_resetn : out std_ulogic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl : std_logic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal spwi : grspw_in_type_vector(0 to CFG_SPW_NUM-1);
signal spwo : grspw_out_type_vector(0 to CFG_SPW_NUM-1);
signal spw_clkl : std_logic;
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
signal stati : ahbstat_in_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal ethclk, egtx_clk_fb : std_logic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal wdog : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, elock, ulock : std_ulogic;
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal lclk, pci_lclk : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal tck, tms, tdi, tdo : std_logic;
signal usbi : grusb_in_vector(0 downto 0);
signal usbo : grusb_out_vector(0 downto 0);
signal uclk : std_ulogic := '0';
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN + CFG_PCI + CFG_GRUSBHC +
CFG_GRUSBDC;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
constant OEPOL : integer := padoen_polarity(padtech);
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep : boolean;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN,
CFG_INVCLK, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK, BOARD_FREQ)
port map (lclk, pci_lclk, clkm, open, open, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1)
port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn, rstraw);
clklock <= cgo.clklock and elock and ulock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+
CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+
CFG_GRUSBHC*(CFG_GRUSBHC_EHC+CFG_GRUSBHC_UHC)+
CFG_GRUSBDC*CFG_GRUSBDC_AIFACE+
CFG_GRUSB_DCL,
nahbs => 8+CFG_GRUSBHC*CFG_GRUSBHC_UHC+CFG_GRUSBDC)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
cpu : for i in 0 to CFG_NCPU-1 generate
nosh : if CFG_GRFPUSH = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.edac <= gpioo.val(2); memi.bwidth <= gpioo.val(1 downto 0);
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, oepol => OEPOL,
sdbits => 32 + 32*CFG_MCTRL_SD64, pageburst => CFG_MCTRL_PAGE)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
data_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (data, memo.data, memo.vbdrive, memi.data);
brdyn_pad : inpad generic map (tech => padtech) port map (brdyn, memi.brdyn);
bexcn_pad : inpad generic map (tech => padtech) port map (bexcn, memi.bexcn);
memi.writen <= '1'; memi.wrn <= "1111";
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);
sd_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (sd(31 downto 0), memo.sddata(31 downto 0),
memo.svbdrive(31 downto 0), memi.sd(31 downto 0));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadvv generic map (tech => padtech, width => 32)
port map (sd(63 downto 32), memo.data(31 downto 0),
memo.svbdrive(63 downto 32), memi.sd(63 downto 32));
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width => 8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
nosd0 : if (CFG_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- No PROM/SRAM controller
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, vcc);
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, vcc(1 downto 0));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 6, paddr => 6, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(6), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(6) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
-- apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
wdog <= gpto.wdogn when OEPOL = 0 else gpto.wdog;
wdogn_pad : odpad generic map (tech => padtech, oepol => OEPOL) port map (wdogn, wdog);
end generate;
-- notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 9, paddr => 9, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(9), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati.cerror(0) <= memo.ce;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp : if CFG_PCI /= 0 generate
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
pci0 : pci_target generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
device_id => CFG_PCIDID, vendor_id => CFG_PCIVID, nsync => 2)
port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG));
end generate;
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#,
ioaddr => 16#400#, nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4),
ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech, dmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#)
port map ( rstn, clkm, pciclk, pcii, apbi, apbo(8));
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 8, paddr => 8,
apb_en => CFG_PCI_ARBAPB)
port map ( clk => pciclk, rst_n => pcii.rst,
req_n => pci_arb_req_n, frame_n => pcii.frame,
gnt_n => pci_arb_gnt_n, pclk => clkm,
prst_n => rstn, apbi => apbi, apbo => apbo(10)
);
pgnt_pad : outpadv generic map (tech => padtech, width => 4)
port map (pci_arb_gnt, pci_arb_gnt_n);
preq_pad : inpadv generic map (tech => padtech, width => 4)
port map (pci_arb_req, pci_arb_req_n);
end generate;
pcipads0 : pcipads generic map (padtech => padtech, host => 0) -- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
end generate;
-- nop1 : if CFG_PCI <= 1 generate apbo(4) <= apb_none; end generate;
-- nop2 : if CFG_PCI <= 2 generate apbo(5) <= apb_none; end generate;
-- nop3 : if CFG_PCI <= 1 generate ahbso(4) <= ahbs_none; end generate;
-- notrc : if CFG_PCITBUFEN = 0 generate apbo(8) <= apb_none; end generate;
-- noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 7, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1)
port map(
rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(14), ethi => ethi, etho => etho);
greth1g: if CFG_GRETH1G = 1 generate
eth_macclk_pad : clkpad
generic map (tech => padtech, arch => 3, hf => 1)
port map (eth_macclk, egtx_clk, cgo.clklock, elock);
end generate greth1g;
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (erxd, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
emdintn_pad : inpad generic map (tech => padtech)
port map (emdintn, ethi.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (etxd, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
-- emdis_pad : outpad generic map (tech => padtech)
-- port map (emddis, vcc(0));
-- eepwrdwn_pad : outpad generic map (tech => padtech)
-- port map (epwrdwn, gnd(0));
-- esleep_pad : outpad generic map (tech => padtech)
-- port map (esleep, gnd(0));
-- epause_pad : outpad generic map (tech => padtech)
-- port map (epause, gnd(0));
-- ereset_pad : outpad generic map (tech => padtech)
-- port map (ereset, gnd(0));
ethi.gtx_clk <= egtx_clk;
end generate;
noeth: if CFG_GRETH = 0 or CFG_GRETH1G = 0 generate
elock <= '1';
end generate noeth;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
can_pads : for i in 0 to CFG_CAN_NUM-1 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd(i), can_ltx(i));
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd(i), can_lrx(i));
end generate;
end generate;
-- can_stb <= '0'; -- no standby
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
-- ocram : if CFG_AHBRAMEN = 1 generate
-- ahbram0 : ftahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
-- tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pindex => 6,
-- paddr => 6, edacen => CFG_AHBRAEDAC, autoscrub => CFG_AHBRASCRU,
-- errcnten => CFG_AHBRAECNT, cntbits => CFG_AHBRAEBIT)
-- port map ( rstn, clkm, ahbsi, ahbso(7), apbi, apbo(6), open);
-- end generate;
--
-- nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
spw_clk_pad : clkpad generic map (tech => padtech) port map (spw_clk, spw_clkl);
-- spw_clkl <= pciclk;
spw_rxtxclk <= spw_clkl;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0';
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => memtech,
hindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+i,
pindex => 10+i,
paddr => 10+i, pirq => 10+i,
sysfreq => CPU_FREQ, nsync => 1, rmap => CFG_SPW_RMAP,
rmapcrc => CFG_SPW_RMAPCRC, fifosize1 => CFG_SPW_AHBFIFO,
fifosize2 => CFG_SPW_RXFIFO, rxclkbuftype => 1,
rmapbufs => CFG_SPW_RMAPBUF,ft => CFG_SPW_FT, ports => 1,
dmachan => CFG_SPW_DMACHAN,
netlist => CFG_SPW_NETLIST, spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT, output_type => CFG_SPW_OUTPUT,
rxtx_sameclk => CFG_SPW_RTSAME)
port map(rstn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+i),
apbi, apbo(10+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '0';
spwi(i).clkdiv10 <= conv_std_logic_vector(CPU_FREQ/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxdp(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxsp(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txdp(i), spw_txdn(i), spwo(i).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txsp(i), spw_txsn(i), spwo(i).s(0), gnd(0));
end generate;
end generate;
nospw : if CFG_SPW_EN = 0 generate
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxdp(0), spw_rxdn(0), spwi(0).d(0));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxsp(0), spw_rxsn(0), spwi(0).s(0));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txdp(0), spw_txdn(0), spwi(0).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txsp(0), spw_txsn(0), spwi(0).s(0), gnd(0));
end generate;
-------------------------------------------------------------------------------
-- USB ------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Note that more than one USB component can not be instantiated at the same
-- time (board has only one USB transceiver), therefore they share AHB
-- master/slave indexes
-----------------------------------------------------------------------------
-- Shared pads
-----------------------------------------------------------------------------
usbpads: if (CFG_GRUSBHC + CFG_GRUSBDC + CFG_GRUSB_DCL) /= 0 generate
-- Incoming 60 MHz clock from transceiver, arch 3 = through BUFGDLL or
-- similiar.
usb_clkout_pad : clkpad
generic map (tech => padtech, arch => 3)
port map (usb_clkout, uclk, cgo.clklock, ulock);
usb_d_pad: iopadv
generic map(tech => padtech, width => 8)
port map (usb_d, usbo(0).dataout(7 downto 0), usbo(0).oen,
usbi(0).datain(7 downto 0));
usb_nxt_pad : inpad generic map (tech => padtech)
port map (usb_nxt, usbi(0).nxt);
usb_dir_pad : inpad generic map (tech => padtech)
port map (usb_dir, usbi(0).dir);
usb_resetn_pad : outpad generic map (tech => padtech)
port map (usb_resetn, usbo(0).reset);
usb_stp_pad : outpad generic map (tech => padtech)
port map (usb_stp, usbo(0).stp);
end generate usbpads;
nousb: if (CFG_GRUSBHC + CFG_GRUSBDC + CFG_GRUSB_DCL) = 0 generate
ulock <= '1';
end generate nousb;
-----------------------------------------------------------------------------
-- USB 2.0 Host Controller
-----------------------------------------------------------------------------
usbhc0: if CFG_GRUSBHC = 1 generate
usbhc0 : grusbhc
generic map (
ehchindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM,
ehcpindex => 13, ehcpaddr => 13, ehcpirq => 13, ehcpmask => 16#fff#,
uhchindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+1,
uhchsindex => 8, uhchaddr => 16#A00#, uhchmask => 16#fff#, uhchirq => 9, tech => fabtech,
memtech => memtech, ehcgen => CFG_GRUSBHC_EHC, uhcgen => CFG_GRUSBHC_UHC,
endian_conv => CFG_GRUSBHC_ENDIAN, be_regs => CFG_GRUSBHC_BEREGS,
be_desc => CFG_GRUSBHC_BEDESC, uhcblo => CFG_GRUSBHC_BLO,
bwrd => CFG_GRUSBHC_BWRD, vbusconf => CFG_GRUSBHC_VBUSCONF)
port map (
clkm,uclk,rstn,apbi,apbo(13),ahbmi,ahbsi,
ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM),
ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+1
downto
CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+1),
ahbso(8 downto 8),
usbo,usbi);
end generate usbhc0;
-----------------------------------------------------------------------------
-- USB 2.0 Device Controller
-----------------------------------------------------------------------------
usbdc0: if CFG_GRUSBDC = 1 generate
usbdc0: grusbdc
generic map(
hsindex => 8, hirq => 6, haddr => 16#004#, hmask => 16#FFC#,
hmindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM,
aiface => CFG_GRUSBDC_AIFACE, uiface => 1,
nepi => CFG_GRUSBDC_NEPI, nepo => CFG_GRUSBDC_NEPO,
i0 => CFG_GRUSBDC_I0, i1 => CFG_GRUSBDC_I1,
i2 => CFG_GRUSBDC_I2, i3 => CFG_GRUSBDC_I3,
i4 => CFG_GRUSBDC_I4, i5 => CFG_GRUSBDC_I5,
i6 => CFG_GRUSBDC_I6, i7 => CFG_GRUSBDC_I7,
i8 => CFG_GRUSBDC_I8, i9 => CFG_GRUSBDC_I9,
i10 => CFG_GRUSBDC_I10, i11 => CFG_GRUSBDC_I11,
i12 => CFG_GRUSBDC_I12, i13 => CFG_GRUSBDC_I13,
i14 => CFG_GRUSBDC_I14, i15 => CFG_GRUSBDC_I15,
o0 => CFG_GRUSBDC_O0, o1 => CFG_GRUSBDC_O1,
o2 => CFG_GRUSBDC_O2, o3 => CFG_GRUSBDC_O3,
o4 => CFG_GRUSBDC_O4, o5 => CFG_GRUSBDC_O5,
o6 => CFG_GRUSBDC_O6, o7 => CFG_GRUSBDC_O7,
o8 => CFG_GRUSBDC_O8, o9 => CFG_GRUSBDC_O9,
o10 => CFG_GRUSBDC_O10, o11 => CFG_GRUSBDC_O11,
o12 => CFG_GRUSBDC_O12, o13 => CFG_GRUSBDC_O13,
o14 => CFG_GRUSBDC_O14, o15 => CFG_GRUSBDC_O15,
memtech => memtech, keepclk => 1)
port map(
uclk => uclk,
usbi => usbi(0),
usbo => usbo(0),
hclk => clkm,
hrst => rstn,
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM),
ahbsi => ahbsi,
ahbso => ahbso(8)
);
end generate usbdc0;
-----------------------------------------------------------------------------
-- USB DCL
-----------------------------------------------------------------------------
usb_dcl0: if CFG_GRUSB_DCL = 1 generate
usb_dcl0: grusb_dcl
generic map (
hindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM,
memtech => memtech, keepclk => 1, uiface => 1)
port map (
uclk, usbi(0), usbo(0), clkm, rstn, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM));
end generate usb_dcl0;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+log2x(CFG_PCI)-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 GR-PCI-XC5LX50 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity comm_fpga_fx2 is
port(
clk_in : in std_logic; -- 48MHz clock from FX2LP
reset_in : in std_logic; -- synchronous active-high reset input
reset_out : out std_logic; -- synchronous active-high reset output
-- FX2LP interface ---------------------------------------------------------------------------
fx2FifoSel_out : out std_logic; -- select FIFO: '0' for EP2OUT, '1' for EP6IN
fx2Data_io : inout std_logic_vector(7 downto 0); -- 8-bit data to/from FX2LP
-- When EP2OUT selected:
fx2Read_out : out std_logic; -- asserted (active-low) when reading from FX2LP
fx2GotData_in : in std_logic; -- asserted (active-high) when FX2LP has data for us
-- When EP6IN selected:
fx2Write_out : out std_logic; -- asserted (active-low) when writing to FX2LP
fx2GotRoom_in : in std_logic; -- asserted (active-high) when FX2LP has room for more data from us
fx2PktEnd_out : out std_logic; -- asserted (active-low) when a host read needs to be committed early
-- Channel read/write interface --------------------------------------------------------------
chanAddr_out : out std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
h2fData_out : out std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
h2fValid_out : out std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData_out"
h2fReady_in : in std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
f2hData_in : in std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
f2hValid_in : in std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
f2hReady_out : out std_logic -- '1' means "on the next clock rising edge, put your next byte of data on f2hData_in"
);
end entity;
architecture rtl of comm_fpga_fx2 is
-- The read/write nomenclature here refers to the FPGA reading and writing the FX2LP FIFOs, and is therefore
-- of the opposite sense to the host's read and write. So host reads are fulfilled in the S_WRITE state, and
-- vice-versa. Apologies for the confusion.
type StateType is (
S_RESET, -- wait for gotData_in to go low when FX2LP enables FIFO mode
S_IDLE, -- wait for requst from host & register chanAddr & isWrite
S_GET_COUNT0, -- register most significant byte of message length
S_GET_COUNT1, -- register least significant byte of message length
S_BEGIN_WRITE, -- switch direction of FX2LP data bus
S_WRITE, -- write data to FX2LP EP6IN FIFO, one byte at a time
S_END_WRITE_ALIGNED, -- end an aligned write (do not assert fx2PktEnd_out)
S_END_WRITE_NONALIGNED, -- end a nonaligned write (assert fx2PktEnd_out)
S_READ -- read data from FX2LP EP2OUT FIFO, one byte at a time
);
constant FIFO_READ : std_logic_vector(1 downto 0) := "10"; -- assert fx2Read_out (active-low)
constant FIFO_WRITE : std_logic_vector(1 downto 0) := "01"; -- assert fx2Write_out (active-low)
constant FIFO_NOP : std_logic_vector(1 downto 0) := "11"; -- assert nothing
constant OUT_FIFO : std_logic := '0'; -- EP2OUT
constant IN_FIFO : std_logic := '1'; -- EP6IN
signal state, state_next : StateType := S_RESET;
signal fifoOp : std_logic_vector(1 downto 0) := "ZZ";
signal count, count_next : unsigned(16 downto 0) := (others => '0'); -- read/write count
signal chanAddr, chanAddr_next : std_logic_vector(6 downto 0) := (others => '0'); -- channel being accessed (0-127)
signal isWrite, isWrite_next : std_logic := '0'; -- is this FX2LP FIFO access a write or a read?
signal isAligned, isAligned_next : std_logic := '0'; -- is this FX2LP FIFO write block-aligned?
signal dataOut : std_logic_vector(7 downto 0); -- data to be driven on fx2Data_io
signal driveBus : std_logic := '0'; -- whether or not to drive fx2Data_io
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
state <= S_RESET;
count <= (others => '0');
chanAddr <= (others => '0');
isWrite <= '0';
isAligned <= '0';
else
state <= state_next;
count <= count_next;
chanAddr <= chanAddr_next;
isWrite <= isWrite_next;
isAligned <= isAligned_next;
end if;
end if;
end process;
-- Next state logic
process(
state, fx2Data_io, fx2GotData_in, fx2GotRoom_in, count, isAligned, isWrite, chanAddr,
f2hData_in, f2hValid_in, h2fReady_in)
begin
state_next <= state;
count_next <= count;
chanAddr_next <= chanAddr;
isWrite_next <= isWrite; -- is the FPGA writing to the FX2LP?
isAligned_next <= isAligned; -- does this FIFO write end on a block (512-byte) boundary?
dataOut <= (others => '0');
driveBus <= '0'; -- don't drive fx2Data_io by default
fifoOp <= FIFO_READ; -- read the FX2LP FIFO by default
fx2PktEnd_out <= '1'; -- inactive: FPGA does not commit a short packet.
f2hReady_out <= '0';
h2fValid_out <= '0';
reset_out <= '0';
case state is
when S_GET_COUNT0 =>
fx2FifoSel_out <= OUT_FIFO; -- Reading from FX2LP
if ( fx2GotData_in = '1' ) then
-- The count high word high byte will be available on the next clock edge.
count_next(15 downto 8) <= unsigned(fx2Data_io);
state_next <= S_GET_COUNT1;
end if;
when S_GET_COUNT1 =>
fx2FifoSel_out <= OUT_FIFO; -- Reading from FX2LP
if ( fx2GotData_in = '1' ) then
-- The count high word low byte will be available on the next clock edge.
count_next(7 downto 0) <= unsigned(fx2Data_io);
if ( count(15 downto 8) = x"00" and fx2Data_io = x"00" ) then
count_next(16) <= '1';
else
count_next(16) <= '0';
end if;
if ( isWrite = '1' ) then
state_next <= S_BEGIN_WRITE;
else
state_next <= S_READ;
end if;
end if;
when S_BEGIN_WRITE =>
fx2FifoSel_out <= IN_FIFO; -- Writing to FX2LP
fifoOp <= FIFO_NOP;
if ( count(8 downto 0) = "000000000" ) then
isAligned_next <= '1';
else
isAligned_next <= '0';
end if;
state_next <= S_WRITE;
when S_WRITE =>
fx2FifoSel_out <= IN_FIFO; -- Writing to FX2LP
if ( fx2GotRoom_in = '1' ) then
f2hReady_out <= '1';
end if;
if ( fx2GotRoom_in = '1' and f2hValid_in = '1' ) then
fifoOp <= FIFO_WRITE;
dataOut <= f2hData_in;
driveBus <= '1';
count_next <= count - 1;
if ( count = 1 ) then
if ( isAligned = '1' ) then
state_next <= S_END_WRITE_ALIGNED; -- don't assert fx2PktEnd
else
state_next <= S_END_WRITE_NONALIGNED; -- assert fx2PktEnd to commit small packet
end if;
end if;
else
fifoOp <= FIFO_NOP;
end if;
when S_END_WRITE_ALIGNED =>
fx2FifoSel_out <= IN_FIFO; -- Writing to FX2LP
fifoOp <= FIFO_NOP;
state_next <= S_IDLE;
when S_END_WRITE_NONALIGNED =>
fx2FifoSel_out <= IN_FIFO; -- Writing to FX2LP
fifoOp <= FIFO_NOP;
fx2PktEnd_out <= '0'; -- Active: FPGA commits the packet early.
state_next <= S_IDLE;
when S_READ =>
fx2FifoSel_out <= OUT_FIFO; -- Reading from FX2LP
if ( fx2GotData_in = '1' and h2fReady_in = '1') then
-- A data byte will be available on the next clock edge
h2fValid_out <= '1';
count_next <= count - 1;
if ( count = 1 ) then
state_next <= S_IDLE;
end if;
else
fifoOp <= FIFO_NOP;
end if;
-- S_RESET - tri-state everything
when S_RESET =>
reset_out <= '1';
driveBus <= '0';
fifoOp <= "ZZ";
fx2FifoSel_out <= 'Z';
fx2PktEnd_out <= 'Z';
if ( fx2GotData_in = '0' ) then
state_next <= S_IDLE;
end if;
-- S_IDLE and others
when others =>
fx2FifoSel_out <= OUT_FIFO; -- Reading from FX2LP
if ( fx2GotData_in = '1' ) then
-- The read/write flag and a seven-bit channel address will be available on the
-- next clock edge.
chanAddr_next <= fx2Data_io(6 downto 0);
isWrite_next <= fx2Data_io(7);
state_next <= S_GET_COUNT0;
end if;
end case;
end process;
-- Drive stateless signals
fx2Read_out <= fifoOp(0);
fx2Write_out <= fifoOp(1);
chanAddr_out <= chanAddr;
h2fData_out <= fx2Data_io;
fx2Data_io <= dataOut when driveBus = '1' else (others => 'Z');
end architecture;
|
-------------------------------------------------------------------------------
--
-- File: tb_TestTop.vhd
-- Author: Tudor Gherman, Robert Bocos
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Top level test bench. This test bench does not extensively test all modules
-- of the ZmodScopeController. Such tests are carried out at component level.
-- A simulation model is provided for the ADC SPI interface to test
-- configuration registers read/write commands.
-- A command queue is loaded into an external FIFO to exercise the IP's SPI
-- indirect access port.
-- A ramp signal is used as stimulus for the data bus. The calibrated samples
-- output by the IP are compared against the expected values in order to test
-- the calibration functionality.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.PkgZmodDigitizer.all;
library UNISIM;
use UNISIM.VComponents.all;
entity tb_TestTop is
Generic (
-- Parameter identifying the Zmod:
-- 6 -> Zmod Scope 1410 - 125 (AD9648)
kZmodID : integer range 6 to 6 := 6;
-- Sampling Clock Period of type "time" in ns
kADC_SamplingClkPeriod : time := 8.138ns;
-- ADC Clock divider ratio (Register 0x0B of AD96xx and AD92xx)
kADC_ClkDiv : integer range 1 to 1 := 1;
-- ADC dynamic/static calibration
kExtCalibEn : boolean := true;
-- Enable/Disable SPI Inirect Access Port
kExtCmdInterfaceEn : boolean := true;
-- Channel1 high gain multiplicative (gain) compensation coefficient parameter
kCh1HgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101010111000";
-- Channel1 high gain additive (offset) compensation coefficient parameter
kCh1HgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111011000";
-- Channel2 high gain multiplicative (gain) compensation coefficient parameter
kCh2HgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101010111000";
-- Channel2 high gain additive (offset) compensation coefficient parameter
kCh2HgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111011000";
-- Clock Generator I2C config address (0x67, 0x68(Default), 0x69)
kCDCEI2C_Addr : std_logic_vector(7 downto 0) := x"CE";
--Parameter to shorten the Clock generator configuration time over I2C
kCDCE_SimulationConfig : boolean := true;
-- Clock Generator I2C shortened configuration number of commands to send over I2C for simulation
kCDCE_SimulationCmdTotal : integer range 0 to kCDCE_RegNrZeroBased := 2;
-- Parameter identifying the CDCE output frequency with SECREF(XTAL) as reference frequency:
-- 0 -> 122.88MHz
-- 1 -> 30MHz
-- 2 -> 40MHz
-- 3 -> 50MHz
-- 4 -> 60MHz
-- 5 -> 80MHz
-- 6 -> 100MHz
-- 7 -> 120MHz
kCDCEFreqSel : integer range 0 to CDCE_I2C_Cmds'length := 0
);
end tb_TestTop;
architecture Behavioral of tb_TestTop is
constant kNumClockCycles : integer := 5000000;
-- ADC number of bits.
constant kADC_Width : integer := SelADC_Width(kZmodID);
signal SysClk100: std_logic := '1';
signal ADC_SamplingClk: std_logic := '1';
signal CDCE_InClk: std_logic := '1';
signal DcoClkOut : std_logic := '1';
signal aRst_n, aRst: std_logic;
signal sInitDoneADC: std_logic;
signal sConfigError: std_logic;
signal doDataAxisTvalid: STD_LOGIC;
signal doDataAxisTready: STD_LOGIC;
signal doDataAxisTdata: STD_LOGIC_VECTOR(31 DOWNTO 0);
signal doExtCh1HgMultCoef: std_logic_vector (17 downto 0);
signal doExtCh1HgAddCoef: std_logic_vector (17 downto 0);
signal doExtCh2HgAddCoef: std_logic_vector (17 downto 0);
signal doExtCh2HgMultCoef: std_logic_vector (17 downto 0);
signal sTestMode: std_logic;
signal doSyncIn: std_logic_vector(kADC_ClkDiv-1 downto 0);
signal sCmdTxAxisTvalid: STD_LOGIC;
signal sCmdTxAxisTready: STD_LOGIC;
signal sCmdTxAxisTdata: STD_LOGIC_VECTOR(31 DOWNTO 0);
signal sCmdRxAxisTvalid: STD_LOGIC;
signal sCmdRxAxisTready: STD_LOGIC;
signal sCmdRxAxisTdata: STD_LOGIC_VECTOR(31 DOWNTO 0);
signal ZmodAdcClkIn_p: std_logic;
signal ZmodAdcClkIn_n: std_logic;
signal aZmodSync: std_logic;
signal ZmodDcoClk, ZmodDcoClkDly: std_logic := '1';
signal diZmodADC_Data: std_logic_vector(kADC_Width-1 downto 0);
signal sZmodADC_SDIO: std_logic;
signal sZmodADC_CS: std_logic;
signal sZmodADC_Sclk: std_logic;
signal s_scl_i : std_logic;
signal s_scl_o : std_logic;
signal s_scl_t : std_logic;
signal s_sda_i : std_logic;
signal s_sda_o : std_logic;
signal s_sda_t : std_logic;
signal t_scl_io : std_logic;
signal t_sda_io : std_logic;
signal e_scl_i : std_logic;
signal e_scl_o : std_logic;
signal e_scl_t : std_logic;
signal e_sda_i : std_logic;
signal e_sda_o : std_logic;
signal e_sda_t : std_logic;
signal sZmodDcoPLL_Lock : std_logic;
signal aCG_PLL_Lock : std_logic := '1';
signal sInitDoneClockGen : std_logic;
signal sPLL_LockClockGen : std_logic;
signal REFSEL : std_logic;
signal HW_SW_CTRL : std_logic;
signal PDN : std_logic;
signal diZmodADC_DataCnt : unsigned(kADC_Width-1 downto 0);
signal diDataGenCntEn, diDataGenRst_n : std_logic;
signal doChA_DataPathTest, doChB_DataPathTest : std_logic_vector (kADC_Width-1 downto 0);
signal doChannel1_Test, doChannel2_Test : std_logic_vector(kADC_Width-1 downto 0);
signal doCh1OutInt, doCh2OutInt : integer;
signal doCh1TestInt, doCh2TestInt : integer;
signal doCh1Diff, doCh2Diff : integer;
signal aEnOverflowTest : std_logic;
signal sEnableAcquisition : std_logic;
constant kSysClkPeriod : time := 10ns; -- System Clock Period
--constant kADC_SamplingClkPeriod : time := 8.138ns;
constant kInitDoneLatency : time := kSysClkPeriod;
-- 2 stages SyncAsync module latency for crossings in SysClk100 domain
constant kSyncAsyncSysLatency: time := kSysClkPeriod*2;
-- Handshake data module latency when crossing from SysClk100 to ADC_samplingClk domain.
constant kHandshakeSys2ADC_Latency: time := kSysClkPeriod+4*kADC_SamplingClkPeriod;
-- The latency with which cDataAxisTvalid is de-asserted after a relay state modification
-- is requested.
-- The sInitDoneRelay signal is pushed through a HandshakeData
-- synchronization module and it will take 1 extra ADC_samplingClk cycle for the
-- FIFO reset to be generated.
-- The ADC_Calibration module adds a latency of extra 3 ADC_SamplingClk cycles
-- The valid signal should be de-asserted in HandshakeDataLatency +
-- + 3 ADC_SamplingClk cycles + 1 ADC_SamplingClk cycle (wait for valid de-assert after FIFO reset).
constant kAxisValidLatency : time := kHandshakeSys2ADC_Latency + 4*kADC_SamplingClkPeriod;
-- Synchronization FIFO depth
constant kSyncFIFO_Depth : integer := 16;
-- Time required for sDataOverflow to assert after cDataAxisTready is de-asserted:
-- If the FIFO is empty and rd_en is de-asserted it will take kSyncFIFO_Depth write clock cycles
-- to fill the FIFO. 1 extra clock cycle will be required by the FIFO to assert the overflow
-- signal, 1 clock cycle will be added by the ProcDataOverflow synchronous process and a maximum
-- time interval equal to kSyncAsyncSysClkLatency is added to pass the dDataOverflow into the
-- SysClk100 domain. This assessment is based on the presumption that the FIFO wr_en signal is
-- asserted for longer that the FIFO latency before the rd_en signal is de-asserted.
constant kOverflowLatency: time := kSyncAsyncSysLatency + kSyncFIFO_Depth * kADC_SamplingClkPeriod + 2 * kADC_SamplingClkPeriod;
-- Calibration constants used to test the dynamic calibration behavior
constant kCh1HgMultCoefDynamic : std_logic_vector (17 downto 0) := "010001101000010001";
constant kCh1HgAddCoefDynamic : std_logic_vector (17 downto 0) := "111111101110111000";
constant kCh2HgMultCoefDynamic : std_logic_vector (17 downto 0) := "010001011010101111";
constant kCh2HgAddCoefDynamic : std_logic_vector (17 downto 0) := "000000001000000111";
-- Adding padding (i.e. 2 bits on the most significant positions) to the static
-- calibration constants.
-- The padding is necessary only to be able to enter hexadecimal calibration constants
-- from the GUI.
-- Channel1 high gain multiplicative (gain) compensation coefficient parameter
constant kCh1HgMultCoefStaticPad : std_logic_vector(19 downto 0) :=
"00"&kCh1HgMultCoefStatic;
-- Channel1 high gain additive (offset) compensation coefficient parameter
constant kCh1HgAddCoefStaticPad : std_logic_vector(19 downto 0) :=
"00"&kCh1HgAddCoefStatic;
-- Channel2 high gain multiplicative (gain) compensation coefficient parameter
constant kCh2HgMultCoefStaticPad : std_logic_vector(19 downto 0) :=
"00"&kCh2HgMultCoefStatic;
-- Channel2 high gain additive (offset) compensation coefficient parameter
constant kCh2HgAddCoefStaticPad : std_logic_vector(19 downto 0) :=
"00"&kCh2HgAddCoefStatic;
constant kSamplingPeriod : integer := integer(DCO_ClockPeriod(kCDCEFreqSel));
constant kSamplingPeriodReal : real := (real(kSamplingPeriod)*0.001);
begin
------------------------------------------------------------------------------------------
--Top level component instantiation
------------------------------------------------------------------------------------------
InstZmodDigitizer_Cotroller: entity work.ZmodDigitizerController
Generic Map(
kZmodID => kZmodID,
kADC_ClkDiv => kADC_ClkDiv,
kADC_Width => kADC_Width,
kExtCalibEn => kExtCalibEn,
kExtCmdInterfaceEn => kExtCmdInterfaceEn,
kCh1HgMultCoefStatic => kCh1HgMultCoefStaticPad,
kCh1HgAddCoefStatic => kCh1HgAddCoefStaticPad,
kCh2HgMultCoefStatic => kCh2HgMultCoefStaticPad,
kCh2HgAddCoefStatic => kCh2HgAddCoefStaticPad,
kCGI2C_Addr => kCDCEI2C_Addr,
kCG_SimulationConfig => kCDCE_SimulationConfig,
kCG_SimulationCmdTotal => kCDCE_SimulationCmdTotal,
kCDCEFreqSel => kCDCEFreqSel
)
Port Map(
SysClk100 => SysClk100,
ClockGenPriRefClk => CDCE_InClk,
aRst_n => aRst_n,
sInitDoneADC => sInitDoneADC,
sConfigError => sConfigError,
sEnableAcquisition => sEnableAcquisition,
doDataAxisTvalid => doDataAxisTvalid,
doDataAxisTready => doDataAxisTready,
doDataAxisTdata => doDataAxisTdata,
doExtCh1HgMultCoef => doExtCh1HgMultCoef,
doExtCh1HgAddCoef => doExtCh1HgAddCoef,
doExtCh2HgMultCoef => doExtCh2HgMultCoef,
doExtCh2HgAddCoef => doExtCh2HgAddCoef,
sTestMode => sTestMode,
sCmdTxAxisTvalid => sCmdTxAxisTvalid,
sCmdTxAxisTready => sCmdTxAxisTready,
sCmdTxAxisTdata => sCmdTxAxisTdata,
sCmdRxAxisTvalid => sCmdRxAxisTvalid,
sCmdRxAxisTready => sCmdRxAxisTready,
sCmdRxAxisTdata => sCmdRxAxisTdata,
CG_InputClk_p => ZmodAdcClkIn_p,
CG_InputClk_n => ZmodAdcClkIn_n,
aZmodSync => aZmodSync,
DcoClkIn => ZmodDcoClk,
ZmodDcoClkOut => DcoClkOut,
sZmodDcoPLL_Lock => sZmodDcoPLL_Lock,
diZmodADC_Data => diZmodADC_Data,
sZmodADC_SDIO => sZmodADC_SDIO,
sZmodADC_CS => sZmodADC_CS,
sZmodADC_Sclk => sZmodADC_Sclk,
aCG_PLL_Lock => aCG_PLL_Lock,
sInitDoneClockGen => sInitDoneClockGen,
sPLL_LockClockGen => sPLL_LockClockGen,
aREFSEL => REFSEL,
aHW_SW_CTRL => HW_SW_CTRL,
sPDNout_n => PDN,
----------------------------------------------------------------------------------
-- IIC bus signals
----------------------------------------------------------------------------------
s_scl_i => s_scl_i, -- IIC Serial Clock Input from 3-state buffer (required)
s_scl_o => s_scl_o, -- IIC Serial Clock Output to 3-state buffer (required)
s_scl_t => s_scl_t, -- IIC Serial Clock Output Enable to 3-state buffer (required)
s_sda_i => s_sda_i, -- IIC Serial Data Input from 3-state buffer (required)
s_sda_o => s_sda_o, -- IIC Serial Data Output to 3-state buffer (required)
s_sda_t => s_sda_t -- IIC Serial Data Output Enable to 3-state buffer (required)
);
CDCE_IIC_scl_iobuf: component IOBUF
port map (
I => s_scl_o,
IO => t_scl_io,
O => s_scl_i,
T => s_scl_t
);
CDCE_IIC_sda_iobuf: component IOBUF
port map (
I => s_sda_o,
IO => t_sda_io,
O => s_sda_i,
T => s_sda_t
);
TWISlave_IIC_scl_iobuf: component IOBUF
port map (
I => e_scl_o,
IO => t_scl_io,
O => e_scl_i,
T => e_scl_t
);
TWISlave_IIC_sda_iobuf: component IOBUF
port map (
I => e_sda_o,
IO => t_sda_io,
O => e_sda_i,
T => e_sda_t
);
SlaveController: entity work.ClockGen_I2C_DataCheck
generic map (
kSampleClkFreqInMHz => 100,
kSlaveAddress => kCDCEI2C_Addr(7 downto 1),
kFreqSel => kCDCEFreqSel
)
port map (
SampleClk => SysClk100,
SRST => aRst,
-- two-wire interface
aSDA_I => e_sda_i,
aSDA_O => e_sda_o,
aSDA_T => e_sda_t,
aSCL_I => e_scl_i,
aSCL_O => e_scl_o,
aSCL_T => e_scl_t
);
--Emulate Pull-Up in Simulation
t_scl_io <= 'H';
t_sda_io <= 'H';
------------------------------------------------------------------------------------------
-- SPI test related modules instantiation
------------------------------------------------------------------------------------------
InstAD96xx_92xx: entity work.AD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kDataWidth => kSPI_DataWidth,
kCommandWidth => kSPI_CommandWidth
)
Port Map(
SysClk100 => SysClk100,
asRst_n => aRst_n,
InsertError => '0',
sSPI_Clk => sZmodADC_Sclk,
sSDIO => sZmodADC_SDIO,
sCS => sZmodADC_CS
);
TestCmdFIFO: entity work.SPI_IAP_TestModule
Generic Map(
kZmodID => kZmodID
)
Port Map(
SysClk100 => SysClk100,
asRst_n => aRst_n,
sInitDoneADC => sInitDoneADC,
sCmdTxAxisTvalid => sCmdTxAxisTvalid,
sCmdTxAxisTready => sCmdTxAxisTready,
sCmdTxAxisTdata => sCmdTxAxisTdata,
sCmdRxAxisTvalid => sCmdRxAxisTvalid,
sCmdRxAxisTready => sCmdRxAxisTready,
sCmdRxAxisTdata => sCmdRxAxisTdata
);
------------------------------------------------------------------------------------------
-- Data path & calibration test related modules instantiation
------------------------------------------------------------------------------------------
InstDataPathDlyCh1 : entity work.DataPathLatency
Generic Map (
kNumFIFO_Stages => 0,
kDataWidth => kADC_Width
)
Port Map(
ZmodDcoClk => DcoClkOut,
ZmodDcoClkDly => ZmodDcoClkDly,
doDataIn => diZmodADC_Data,
doChA_DataOut => doChA_DataPathTest,
doChB_DataOut => doChB_DataPathTest);
InstCalibDataRefCh1 : entity work.CalibDataReference
Generic Map (
kWidth => kADC_Width,
kExtCalibEn => kExtCalibEn,
kLgMultCoefStatic => (others => '0'),
kLgAddCoefStatic => (others => '0'),
kHgMultCoefStatic => kCh1HgMultCoefStatic,
kHgAddCoefStatic => kCh1HgAddCoefStatic,
kInvert => true,
kLatency => 2,
kTestLatency => 1
)
Port Map(
SamplingClk => DcoClkOut,
cTestMode => sTestMode, -- sTestMode is constant in the current test bench
cChIn => doChA_DataPathTest,
cChOut => doChannel1_Test,
cExtLgMultCoef => (others => '0'),
cExtLgAddCoef => (others => '0'),
cExtHgMultCoef => doExtCh1HgMultCoef,
cExtHgAddCoef => doExtCh1HgAddCoef,
cGainState => '1' --Force High Gain
);
InstCalibDataRefCh2 : entity work.CalibDataReference
Generic Map (
kWidth => kADC_Width,
kExtCalibEn => kExtCalibEn,
kLgMultCoefStatic => (others => '0'),
kLgAddCoefStatic => (others => '0'),
kHgMultCoefStatic => kCh2HgMultCoefStatic,
kHgAddCoefStatic => kCh2HgAddCoefStatic,
kInvert => false,
kLatency => 2,
kTestLatency => 1
)
Port Map(
SamplingClk => DcoClkOut,
cTestMode => sTestMode, -- sTestMode is constant in the current test bench
cChIn => doChB_DataPathTest,
cChOut => doChannel2_Test,
cExtLgMultCoef => (others => '0'),
cExtLgAddCoef => (others => '0'),
cExtHgMultCoef => doExtCh2HgMultCoef,
cExtHgAddCoef => doExtCh2HgAddCoef,
cGainState => '1' --Force High Gain
);
doCh1OutInt <= to_integer(signed(doDataAxisTdata(31 downto 32-kADC_Width)));
doCh2OutInt <= to_integer(signed(doDataAxisTdata(15 downto 16-kADC_Width)));
doCh1TestInt <= to_integer(signed(doChannel1_Test));
doCh2TestInt <= to_integer(signed(doChannel2_Test));
doCh1Diff <= doCh1OutInt - doCh1TestInt;
doCh2Diff <= doCh2OutInt - doCh2TestInt;
------------------------------------------------------------------------------------------
-- Clock generation
------------------------------------------------------------------------------------------
ProcSystmClock: process
begin
for i in 0 to kNumClockCycles loop
wait for kSysClkPeriod/2;
SysClk100 <= not SysClk100;
wait for kSysClkPeriod/2;
SysClk100 <= not SysClk100;
end loop;
wait;
end process;
ProcSamplingClk: process
begin
for i in 0 to kNumClockCycles loop
wait for kADC_SamplingClkPeriod/2;
ADC_SamplingClk <= not ADC_SamplingClk;
wait for kADC_SamplingClkPeriod/2;
ADC_SamplingClk <= not ADC_SamplingClk;
end loop;
wait;
end process;
ProcCDCE_InClk: process
begin
for i in 0 to (kNumClockCycles*kADC_ClkDiv) loop
wait for kADC_SamplingClkPeriod/(2*kADC_ClkDiv);
CDCE_InClk <= not CDCE_InClk;
wait for kADC_SamplingClkPeriod/(2*kADC_ClkDiv);
CDCE_InClk <= not CDCE_InClk;
end loop;
wait;
end process;
ProcDcoClk: process
begin
wait for kTdcoMax;
for i in 0 to kNumClockCycles loop
wait for kADC_SamplingClkPeriod/2;
ZmodDcoClk <= not ZmodDcoClk;
wait for kADC_SamplingClkPeriod/2;
ZmodDcoClk <= not ZmodDcoClk;
end loop;
wait;
end process;
ZmodDcoClkDly <= ZmodDcoClk after
(IDDR_ClockPhase(kSamplingPeriodReal)/360.0)*kADC_SamplingClkPeriod;
------------------------------------------------------------------------------------------
-- Stimuli generation
------------------------------------------------------------------------------------------
-- A ramp signal is used as stimuli for the ADC data bus
ProcDataGen: process (ZmodDcoClk)
begin
if ((aRst_n = '0') or (diDataGenRst_n = '0')) then
diZmodADC_DataCnt <= (others => '0');
elsif (rising_edge(ZmodDcoClk) or falling_edge(ZmodDcoClk)) then
if (diDataGenCntEn = '1') then
diZmodADC_DataCnt <= diZmodADC_DataCnt + 1;
end if;
end if;
end process;
diZmodADC_Data <= std_logic_vector(diZmodADC_DataCnt);
aRst <= not aRst_n;
-- Stimuli generated in the SysClk100 domain
ProcSysClkDomainStimuli: process
begin
-- Assert reset for 10 clock cycles (this covers the minimum
-- hold time for the reset signal)
aRst_n <= '0';
aEnOverflowTest <= '0';
sEnableAcquisition <= '0';
sTestMode <= '0';
wait for 10 * kSysClkPeriod;
wait until falling_edge(SysClk100);
aRst_n <= '1';
sEnableAcquisition <= '1';
-- Process 2 * 2^14 samples to make sure all possible inputs are tested after calibration.
wait for (2**kADC_Width) * kADC_SamplingClkPeriod;
wait until doDataAxisTvalid = '1';
wait;
end process;
-- ZmodDcoClk domain stimuli. The counter used to generate the
-- ADC data bus stimuli is free running for this test bench.
ProcDcoDomainStimuli: process
begin
diDataGenRst_n <= '1';
diDataGenCntEn <= '1';
wait;
end process;
-- DcoClkOut domain stimuli.
ProcDcoClkOutDomainStimuli: process
begin
doSyncIn(0) <= '1';
if (kADC_ClkDiv > 1) then
doSyncIn(kADC_ClkDiv-1 downto 1) <= (others => '0');
end if;
doExtCh1HgMultCoef <= kCh1HgMultCoefDynamic;
doExtCh1HgAddCoef <= kCh1HgAddCoefDynamic;
doExtCh2HgMultCoef <= kCh2HgMultCoefDynamic;
doExtCh2HgAddCoef <= kCh2HgAddCoefDynamic;
wait until sInitDoneADC = '1';
doDataAxisTready <= '1';
wait;
end process;
-- Compare the calibrated data samples against the expected values.
ProcCh1CheckCalibData: process
begin
wait until sInitDoneADC = '1';
wait until doCh1TestInt'event or doCh1OutInt'event;
-- doCh1Diff is generated on the rising edge of DcoClkOut
-- and checked on the negative edge of DcoClkOut.
wait until falling_edge(DcoClkOut);
if ((doDataAxisTvalid = '1') and (aEnOverflowTest = '0')) then
assert (abs(doCh1Diff) < 2)
report "Calibration error: mismatch between expected data and actual data" & LF & HT & HT &
"Expected: " & integer'image(to_integer(signed(doChannel1_Test))) & LF & HT & HT &
"Actual: " & integer'image(doCh1OutInt) & LF & HT & HT &
"Difference: " & integer'image(doCh1Diff)
severity ERROR;
end if;
end process;
ProcCh2CheckCalibData: process
begin
wait until sInitDoneADC = '1';
wait until doCh2TestInt'event or doCh2OutInt'event;
-- doCh2Diff is generated on the rising edge of DcoClkOut
-- and checked on the negative edge of DcoClkOut.
wait until falling_edge(DcoClkOut);
if ((doDataAxisTvalid = '1') and (aEnOverflowTest = '0')) then
assert (abs(doCh2Diff) < 2)
report "Calibration error: mismatch between expected data and actual data" & LF & HT & HT &
"Expected: " & integer'image(to_integer(signed(doChannel2_Test))) & LF & HT & HT &
"Actual: " & integer'image(doCh2OutInt) & LF & HT & HT &
"Difference: " & integer'image(doCh2Diff)
severity ERROR;
end if;
end process;
ProcCheckADC_Init: process
begin
wait until sInitDoneClockGen = '1';
-- Wait for the reset signal to be de-asserted
wait until rising_edge(aRst_n);
-- Check if the sInitDoneADC signal is asserted and sConfigError is de-asserted
-- after the configuration timeout period (determined empirically)
wait for kCount5ms * kSysClkPeriod;
assert (sInitDoneADC = '1')
report "sInitDoneADC signal not asserted when expected" & LF & HT & HT
severity ERROR;
assert (sConfigError = '0')
report "sConfigError signal not de-asserted when expected" & LF & HT & HT
severity ERROR;
end process;
end Behavioral; |
-------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v8_3_1.vhd
--
-- Description:
-- This file is the VHDL behvarial model for the
-- Block Memory Generator Core.
--
-------------------------------------------------------------------------------
-- Author: Xilinx
--
-- History: January 11, 2006: Initial revision
-- June 11, 2007 : Added independent register stages for
-- Port A and Port B (IP1_Jm/v2.5)
-- August 28, 2007 : Added mux pipeline stages feature (IP2_Jm/v2.6)
-- April 07, 2009 : Added support for Spartan-6 and Virtex-6
-- features, including the following:
-- (i) error injection, detection and/or correction
-- (ii) reset priority
-- (iii) special reset behavior
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
ENTITY blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END ENTITY blk_mem_axi_regs_fwd_v8_3;
ARCHITECTURE axi_regs_fwd_arch OF blk_mem_axi_regs_fwd_v8_3 IS
SIGNAL STORAGE_DATA : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_READY_I : STD_LOGIC := '0';
SIGNAL M_VALID_I : STD_LOGIC := '0';
SIGNAL ARESET_D : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');-- Reset delay register
BEGIN
--assign local signal to its output signal
S_READY <= S_READY_I;
M_VALID <= M_VALID_I;
PROCESS(ACLK)
BEGIN
IF(ACLK'event AND ACLK = '1') THEN
ARESET_D <= ARESET_D(0) & ARESET;
END IF;
END PROCESS;
--Save payload data whenever we have a transaction on the slave side
PROCESS(ACLK, ARESET)
BEGIN
IF (ARESET = '1') THEN
STORAGE_DATA <= (OTHERS => '0');
ELSIF(ACLK'event AND ACLK = '1') THEN
IF(S_VALID = '1' AND S_READY_I = '1') THEN
STORAGE_DATA <= S_PAYLOAD_DATA;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= STORAGE_DATA;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
PROCESS(ACLK,ARESET)
BEGIN
IF (ARESET_D /= "00") THEN
M_VALID_I <= '0';
ELSIF(ACLK'event AND ACLK = '1') THEN
IF (S_VALID = '1') THEN
--Always set M_VALID_I when slave side is valid
M_VALID_I <= '1';
ELSIF (M_READY = '1') THEN
--Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= '0';
END IF;
END IF;
END PROCESS;
--Slave Ready is either when Master side drives M_READY or we have space in our storage data
S_READY_I <= (M_READY OR (NOT M_VALID_I)) AND NOT(OR_REDUCE(ARESET_D));
END axi_regs_fwd_arch;
-------------------------------------------------------------------------------
-- Description:
-- This is the behavioral model of write_wrapper for the
-- Block Memory Generator Core.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_axi_write_wrapper_beh IS
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END blk_mem_axi_write_wrapper_beh;
ARCHITECTURE axi_write_wrap_arch OF blk_mem_axi_write_wrapper_beh IS
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_AXI_WDATA_WIDTH=8,0,
if_then_else((C_AXI_WDATA_WIDTH=16),1,
if_then_else((C_AXI_WDATA_WIDTH=32),2,
if_then_else((C_AXI_WDATA_WIDTH=64),3,
if_then_else((C_AXI_WDATA_WIDTH=128),4,
if_then_else((C_AXI_WDATA_WIDTH=256),5,0))))));
SIGNAL bvalid_c : std_logic := '0';
SIGNAL bready_timeout_c : std_logic := '0';
SIGNAL bvalid_rd_cnt_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_r : std_logic := '0';
SIGNAL bvalid_count_r : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL awaddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
C_AXI_AWADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL bvalid_wr_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_rd_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_last_c : std_logic := '0';
SIGNAL addr_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL aw_ready_r : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL awlen_cntr_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1');
SIGNAL awlen_int : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL awburst_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes : integer := 0;
SIGNAL wrap_boundary : integer := 0;
SIGNAL wrap_base_addr : integer := 0;
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
-- Array to store BIDs
TYPE id_array IS ARRAY (3 DOWNTO 0) OF std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
SIGNAL axi_bid_array : id_array := (others => (others => '0'));
COMPONENT write_netlist
GENERIC(
C_AXI_TYPE : integer
);
PORT(
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
S_AXI_AWVALID : IN std_logic;
aw_ready_r : OUT std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN std_logic;
S_AXI_WR_EN : OUT std_logic;
w_last_c : IN std_logic;
bready_timeout_c : IN std_logic;
addr_en_c : OUT std_logic;
incr_addr_c : OUT std_logic;
bvalid_c : OUT std_logic
);
END COMPONENT write_netlist;
BEGIN
---------------------------------------
--AXI WRITE FSM COMPONENT INSTANTIATION
---------------------------------------
axi_wr_fsm : write_netlist
GENERIC MAP (
C_AXI_TYPE => C_AXI_TYPE
)
PORT MAP (
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
S_AXI_AWVALID => S_AXI_AWVALID,
aw_ready_r => aw_ready_r,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BVALID => OPEN,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_WR_EN => S_AXI_WR_EN,
w_last_c => w_last_c,
bready_timeout_c => bready_timeout_c,
addr_en_c => addr_en_c,
incr_addr_c => incr_addr_c,
bvalid_c => bvalid_c
);
--Wrap Address boundary calculation
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWSIZE,"000"));
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(awlen_int)+1);
wrap_base_addr <= (conv_integer(awaddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary <= wrap_base_addr+total_bytes;
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awaddr_reg <= (OTHERS => '0');
num_of_bytes_r <= 0;
awburst_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awaddr_reg <= S_AXI_AWADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWBURST,"01");
ELSIF (incr_addr_c = '1') THEN
IF (awburst_int = "10") THEN
IF(conv_integer(awaddr_reg) = (wrap_boundary-num_of_bytes_r)) THEN
awaddr_reg <= conv_std_logic_vector(wrap_base_addr,C_AXI_AWADDR_WIDTH);
ELSE
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
ELSIF (awburst_int = "01" OR awburst_int = "11") THEN
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
S_AXI_AWADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
awaddr_reg(C_AXI_AWADDR_WIDTH-1 DOWNTO C_RANGE),awaddr_reg);
---------------------------------------------------------------------------
-- AXI wlast generation
---------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awlen_cntr_r <= (OTHERS => '1');
awlen_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awlen_int <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
awlen_cntr_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
ELSIF (dec_alen_c = '1') THEN
awlen_cntr_r <= awlen_cntr_r - ONE AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
w_last_c <= '1' WHEN (awlen_cntr_r = "00000000" AND S_AXI_WVALID = '1') ELSE '0';
dec_alen_c <= (incr_addr_c OR w_last_c);
---------------------------------------------------------------------------
-- Generation of bvalid counter for outstanding transactions
---------------------------------------------------------------------------
P_b_valid_os_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_count_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- bvalid_count_r generation
IF (bvalid_c = '1' AND bvalid_r = '1' AND S_AXI_BREADY = '1') THEN
bvalid_count_r <= bvalid_count_r AFTER FLOP_DELAY;
ELSIF (bvalid_c = '1') THEN
bvalid_count_r <= bvalid_count_r + "01" AFTER FLOP_DELAY;
ELSIF (bvalid_r = '1' AND S_AXI_BREADY = '1' AND bvalid_count_r /= "0") THEN
bvalid_count_r <= bvalid_count_r - "01" AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_os_r ;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is used
---------------------------------------------------------------------------
gaxi_bvalid_id_r:IF (C_HAS_AXI_ID = 1) GENERATE
SIGNAL bvalid_d1_c : std_logic := '0';
BEGIN
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
bvalid_d1_c <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
--external bvalid signal generation
IF (bvalid_d1_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_id_r;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is not used
---------------------------------------------------------------------------
gaxi_bvalid_noid_r:IF (C_HAS_AXI_ID = 0) GENERATE
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
--external bvalid signal generation
IF (bvalid_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_noid_r;
---------------------------------------------------------------------------
-- Generation of Bready timeout
---------------------------------------------------------------------------
P_brdy_tout_c: PROCESS (bvalid_count_r)
BEGIN
-- bready_timeout_c generation
IF(conv_integer(bvalid_count_r) = C_AXI_OS_WR-1) THEN
bready_timeout_c <= '1';
ELSE
bready_timeout_c <= '0';
END IF;
END PROCESS P_brdy_tout_c;
---------------------------------------------------------------------------
-- Generation of BID
---------------------------------------------------------------------------
gaxi_bid_gen:IF (C_HAS_AXI_ID = 1) GENERATE
P_bid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
bvalid_wr_cnt_r <= (OTHERS => '0');
bvalid_rd_cnt_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- STORE AWID IN AN ARRAY
IF(bvalid_c = '1') THEN
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + "01";
END IF;
-- GENERATE BID FROM AWID ARRAY
bvalid_rd_cnt_r <= bvalid_rd_cnt_c AFTER FLOP_DELAY;
S_AXI_BID <= axi_bid_array(conv_integer(bvalid_rd_cnt_c));
END IF;
END PROCESS P_bid_gen;
bvalid_rd_cnt_c <= bvalid_rd_cnt_r + "01" WHEN (bvalid_r = '1' AND S_AXI_BREADY = '1') ELSE bvalid_rd_cnt_r;
---------------------------------------------------------------------------
-- Storing AWID for generation of BID
---------------------------------------------------------------------------
P_awid_reg:PROCESS (S_ACLK)
BEGIN
IF (S_ACLK'event AND S_ACLK='1') THEN
IF(aw_ready_r = '1' AND S_AXI_AWVALID = '1') THEN
axi_bid_array(conv_integer(bvalid_wr_cnt_r)) <= S_AXI_AWID;
END IF;
END IF;
END PROCESS P_awid_reg;
END GENERATE gaxi_bid_gen;
S_AXI_BVALID <= bvalid_r;
S_AXI_AWREADY <= aw_ready_r;
END axi_write_wrap_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity write_netlist is
GENERIC(
C_AXI_TYPE : integer
);
port (
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_AWVALID : in STD_LOGIC := '0';
S_AXI_WVALID : in STD_LOGIC := '0';
S_AXI_BREADY : in STD_LOGIC := '0';
w_last_c : in STD_LOGIC := '0';
bready_timeout_c : in STD_LOGIC := '0';
aw_ready_r : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_WR_EN : out STD_LOGIC;
addr_en_c : out STD_LOGIC;
incr_addr_c : out STD_LOGIC;
bvalid_c : out STD_LOGIC
);
end write_netlist;
architecture STRUCTURE of write_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
BEGIN
---------------------------------------------------------------------------
-- AXI LITE
---------------------------------------------------------------------------
gbeh_axi_lite_sm: IF (C_AXI_TYPE = 0 ) GENERATE
signal w_ready_r_7 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSignal_bvalid_c : STD_LOGIC;
signal NlwRenamedSignal_incr_addr_c : STD_LOGIC;
signal present_state_FSM_FFd3_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal present_state_FSM_FFd1_15 : STD_LOGIC;
signal present_state_FSM_FFd4_16 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd4_In1_21 : STD_LOGIC;
signal Mmux_aw_ready_c : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
S_AXI_WREADY <= w_ready_r_7;
S_AXI_BVALID <= NlwRenamedSignal_incr_addr_c;
S_AXI_WR_EN <= NlwRenamedSignal_bvalid_c;
incr_addr_c <= NlwRenamedSignal_incr_addr_c;
bvalid_c <= NlwRenamedSignal_bvalid_c;
NlwRenamedSignal_incr_addr_c <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_7
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_16
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_13
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_15
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000055554440"
)
port map (
I0 => S_AXI_WVALID,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => '0',
O => present_state_FSM_FFd3_In
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"0000000088880800"
)
port map (
I0 => S_AXI_AWVALID,
I1 => S_AXI_WVALID,
I2 => bready_timeout_c,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => present_state_FSM_FFd2_In
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAA2000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_WVALID,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => addr_en_c
);
Mmux_w_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"F5F07570F5F05500"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => w_ready_c
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd3_13,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd1_15,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_14,
I2 => present_state_FSM_FFd3_13,
I3 => '0',
I4 => '0',
I5 => '0',
O => NlwRenamedSignal_bvalid_c
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"2F0F27072F0F2200"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => present_state_FSM_FFd4_In1_21
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_In1_21,
I3 => '0',
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_aw_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"7535753575305500"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => S_AXI_WVALID,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => present_state_FSM_FFd2_14,
O => Mmux_aw_ready_c(0)
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => Mmux_aw_ready_c(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => aw_ready_c
);
END GENERATE gbeh_axi_lite_sm;
---------------------------------------------------------------------------
-- AXI FULL
---------------------------------------------------------------------------
gbeh_axi_full_sm: IF (C_AXI_TYPE = 1 ) GENERATE
signal w_ready_r_8 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSig_OI_bvalid_c : STD_LOGIC;
signal present_state_FSM_FFd1_16 : STD_LOGIC;
signal present_state_FSM_FFd4_17 : STD_LOGIC;
signal present_state_FSM_FFd3_18 : STD_LOGIC;
signal present_state_FSM_FFd2_19 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd2_In1_24 : STD_LOGIC;
signal present_state_FSM_FFd4_In1_25 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal N4 : STD_LOGIC;
begin
S_AXI_WREADY <= w_ready_r_8;
bvalid_c <= NlwRenamedSig_OI_bvalid_c;
S_AXI_BVALID <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_8
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_17
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_18
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_19
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_16
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000000005540"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd4_17,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd3_In
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"BF3FBB33AF0FAA00"
)
port map (
I0 => S_AXI_BREADY,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd1_16,
I4 => present_state_FSM_FFd4_17,
I5 => NlwRenamedSig_OI_bvalid_c,
O => aw_ready_c
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"AAAAAAAA20000000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_19,
I3 => S_AXI_WVALID,
I4 => w_last_c,
I5 => present_state_FSM_FFd4_17,
O => addr_en_c
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_19,
I2 => present_state_FSM_FFd3_18,
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_WR_EN
);
Mmux_incr_addr_c_0_1 : STATE_LOGIC
generic map(
INIT => X"0000000000002220"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => incr_addr_c
);
Mmux_aw_ready_c_0_11 : STATE_LOGIC
generic map(
INIT => X"0000000000008880"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => NlwRenamedSig_OI_bvalid_c
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"000000000000D5C0"
)
port map (
I0 => w_last_c,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd4_17,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd2_In1_24
);
present_state_FSM_FFd2_In2 : STATE_LOGIC
generic map(
INIT => X"FFFFAAAA08AAAAAA"
)
port map (
I0 => present_state_FSM_FFd2_19,
I1 => S_AXI_AWVALID,
I2 => bready_timeout_c,
I3 => w_last_c,
I4 => S_AXI_WVALID,
I5 => present_state_FSM_FFd2_In1_24,
O => present_state_FSM_FFd2_In
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"00C0004000C00000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => w_last_c,
I2 => S_AXI_WVALID,
I3 => bready_timeout_c,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => present_state_FSM_FFd4_In1_25
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88F8"
)
port map (
I0 => present_state_FSM_FFd1_16,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_17,
I3 => S_AXI_AWVALID,
I4 => present_state_FSM_FFd4_In1_25,
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_w_ready_c_0_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => w_last_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_w_ready_c_0_Q : STATE_LOGIC
generic map(
INIT => X"FABAFABAFAAAF000"
)
port map (
I0 => N2,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd4_17,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => w_ready_c
);
Mmux_aw_ready_c_0_11_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => bready_timeout_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => w_last_c,
I1 => N4,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => present_state_FSM_FFd1_16,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
END GENERATE gbeh_axi_full_sm;
end STRUCTURE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--AXI Behavioral Model entities
ENTITY blk_mem_axi_read_wrapper_beh is
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
port (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END blk_mem_axi_read_wrapper_beh;
architecture blk_mem_axi_read_wrapper_beh_arch of blk_mem_axi_read_wrapper_beh is
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_WRITE_WIDTH_A=8,0,
if_then_else((C_WRITE_WIDTH_A=16),1,
if_then_else((C_WRITE_WIDTH_A=32),2,
if_then_else((C_WRITE_WIDTH_A=64),3,
if_then_else((C_WRITE_WIDTH_A=128),4,
if_then_else((C_WRITE_WIDTH_A=256),5,0))))));
SIGNAL ar_id_r : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
SIGNAL addr_en_c : std_logic := '0';
SIGNAL rd_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL single_trans_c : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL mux_sel_c : std_logic := '0';
SIGNAL r_last_c : std_logic := '0';
SIGNAL r_last_int_c : std_logic := '0';
SIGNAL arlen_int_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL arlen_cntr : std_logic_vector(7 DOWNTO 0) := ONE;
SIGNAL arburst_int_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL arburst_int_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL araddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),C_AXI_ARADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL total_bytes : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
SIGNAL wrap_base_addr_r : integer := 0;
SIGNAL wrap_boundary_r : integer := 0;
SIGNAL arlen_int_c : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes_c : integer := 0;
SIGNAL wrap_base_addr_c : integer := 0;
SIGNAL wrap_boundary_c : integer := 0;
SIGNAL araddr_out : std_logic_vector(C_ADDRB_WIDTH-1 downto 0) := (OTHERS => '0');
COMPONENT read_netlist
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_INCR_ADDR : OUT std_logic := '0';
S_AXI_ADDR_EN : OUT std_logic := '0';
S_AXI_SINGLE_TRANS : OUT std_logic := '0';
S_AXI_MUX_SEL : OUT std_logic := '0';
S_AXI_R_LAST : OUT std_logic := '0';
S_AXI_R_LAST_INT : IN std_logic := '0';
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT read_netlist;
BEGIN
dec_alen_c <= incr_addr_c OR r_last_int_c;
axi_read_fsm : read_netlist
GENERIC MAP(
C_AXI_TYPE => 1,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
S_AXI_INCR_ADDR => incr_addr_c,
S_AXI_ADDR_EN => addr_en_c,
S_AXI_SINGLE_TRANS => single_trans_c,
S_AXI_MUX_SEL => mux_sel_c,
S_AXI_R_LAST => r_last_c,
S_AXI_R_LAST_INT => r_last_int_c,
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN => rd_en_c
);
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(arlen_int_r)+1);
wrap_base_addr_r <= (conv_integer(araddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary_r <= wrap_base_addr_r+total_bytes;
---- combinatorial from interface
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARSIZE,"000"));
arlen_int_c <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
total_bytes_c <= conv_integer(num_of_bytes_c)*(conv_integer(arlen_int_c)+1);
wrap_base_addr_c <= (conv_integer(S_AXI_ARADDR)/if_then_else(total_bytes_c=0,1,total_bytes_c))*(total_bytes_c);
wrap_boundary_c <= wrap_base_addr_c+total_bytes_c;
arburst_int_c <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARBURST,"01");
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
araddr_reg <= (OTHERS => '0');
arburst_int_r <= (OTHERS => '0');
num_of_bytes_r <= 0;
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (incr_addr_c = '1' AND addr_en_c = '1' AND single_trans_c = '0') THEN
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
IF (arburst_int_c = "10") THEN
IF(conv_integer(S_AXI_ARADDR) = (wrap_boundary_c-num_of_bytes_c)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_c,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (arburst_int_c = "01" OR arburst_int_c = "11") THEN
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (addr_en_c = '1') THEN
araddr_reg <= S_AXI_ARADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
ELSIF (incr_addr_c = '1') THEN
IF (arburst_int_r = "10") THEN
IF(conv_integer(araddr_reg) = (wrap_boundary_r-num_of_bytes_r)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_r,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
ELSIF (arburst_int_r = "01" OR arburst_int_r = "11") THEN
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
araddr_out <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),araddr_reg(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),araddr_reg);
--------------------------------------------------------------------------
-- Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
--------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF S_ARESETN = '1' THEN
arlen_cntr <= ONE;
arlen_int_r <= (OTHERS => '0');
ELSIF S_ACLK'event AND S_ACLK = '1' THEN
IF (addr_en_c = '1' AND dec_alen_c = '1' AND single_trans_c = '0') THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= S_AXI_ARLEN - ONE AFTER FLOP_DELAY;
ELSIF addr_en_c = '1' THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
ELSIF dec_alen_c = '1' THEN
arlen_cntr <= arlen_cntr - ONE AFTER FLOP_DELAY;
ELSE
arlen_cntr <= arlen_cntr AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
r_last_int_c <= '1' WHEN (arlen_cntr = "00000000" AND S_AXI_RREADY = '1') ELSE '0' ;
--------------------------------------------------------------------------
-- AXI FULL FSM
-- Mux Selection of ARADDR
-- ARADDR is driven out from the read fsm based on the mux_sel_c
-- Based on mux_sel either ARADDR is given out or the latched ARADDR is
-- given out to BRAM
--------------------------------------------------------------------------
P_araddr_mux: PROCESS (mux_sel_c,S_AXI_ARADDR,araddr_out)
BEGIN
IF (mux_sel_c = '0') THEN
S_AXI_ARADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARADDR(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),S_AXI_ARADDR);
ELSE
S_AXI_ARADDR_OUT <= araddr_out;
END IF;
END PROCESS P_araddr_mux;
--------------------------------------------------------------------------
-- Assign output signals - AXI FULL FSM
--------------------------------------------------------------------------
S_AXI_RD_EN <= rd_en_c;
grid: IF (C_HAS_AXI_ID = 1) GENERATE
P_rid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
S_AXI_RID <= (OTHERS => '0');
ar_id_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
IF (addr_en_c = '1' AND rd_en_c = '1') THEN
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
ELSIF (addr_en_c = '1' AND rd_en_c = '0') THEN
ar_id_r <= S_AXI_ARID;
ELSIF (rd_en_c = '1') THEN
S_AXI_RID <= ar_id_r;
END IF;
END IF;
END PROCESS P_rid_gen;
END GENERATE grid;
END blk_mem_axi_read_wrapper_beh_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity read_netlist is
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_R_LAST_INT : in STD_LOGIC := '0';
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_ARVALID : in STD_LOGIC := '0';
S_AXI_RREADY : in STD_LOGIC := '0';
S_AXI_INCR_ADDR : out STD_LOGIC;
S_AXI_ADDR_EN : out STD_LOGIC;
S_AXI_SINGLE_TRANS : out STD_LOGIC;
S_AXI_MUX_SEL : out STD_LOGIC;
S_AXI_R_LAST : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RLAST : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RD_EN : out STD_LOGIC;
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end read_netlist;
architecture STRUCTURE of read_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
signal present_state_FSM_FFd1_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_r_15 : STD_LOGIC;
signal gaxi_full_sm_ar_ready_r_16 : STD_LOGIC;
signal gaxi_full_sm_r_last_r_17 : STD_LOGIC;
signal NlwRenamedSig_OI_gaxi_full_sm_r_valid_r : STD_LOGIC;
signal gaxi_full_sm_r_valid_c : STD_LOGIC;
signal S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o : STD_LOGIC;
signal gaxi_full_sm_ar_ready_c : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_c : STD_LOGIC;
signal NlwRenamedSig_OI_S_AXI_R_LAST : STD_LOGIC;
signal S_AXI_ARLEN_7_GND_8_o_equal_1_o : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal Mmux_S_AXI_R_LAST13 : STD_LOGIC;
signal N01 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal Mmux_gaxi_full_sm_ar_ready_c11 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N8 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N13 : STD_LOGIC;
begin
S_AXI_R_LAST <= NlwRenamedSig_OI_S_AXI_R_LAST;
S_AXI_ARREADY <= gaxi_full_sm_ar_ready_r_16;
S_AXI_RLAST <= gaxi_full_sm_r_last_r_17;
S_AXI_RVALID <= NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
gaxi_full_sm_outstanding_read_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_outstanding_read_c,
Q => gaxi_full_sm_outstanding_read_r_15
);
gaxi_full_sm_r_valid_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => gaxi_full_sm_r_valid_c,
Q => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r
);
gaxi_full_sm_ar_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_ar_ready_c,
Q => gaxi_full_sm_ar_ready_r_16
);
gaxi_full_sm_r_last_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => NlwRenamedSig_OI_S_AXI_R_LAST,
Q => gaxi_full_sm_r_last_r_17
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_13
);
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 : STATE_LOGIC
generic map(
INIT => X"000000000000000B"
)
port map (
I0 => S_AXI_RREADY,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o
);
Mmux_S_AXI_SINGLE_TRANS11 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_SINGLE_TRANS
);
Mmux_S_AXI_ADDR_EN11 : STATE_LOGIC
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_ADDR_EN
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"ECEE2022EEEE2022"
)
port map (
I0 => S_AXI_ARVALID,
I1 => present_state_FSM_FFd1_13,
I2 => S_AXI_RREADY,
I3 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I4 => present_state_FSM_FFd2_14,
I5 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
O => present_state_FSM_FFd2_In
);
Mmux_S_AXI_R_LAST131 : STATE_LOGIC
generic map(
INIT => X"0000000044440444"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_RREADY,
I5 => '0',
O => Mmux_S_AXI_R_LAST13
);
Mmux_S_AXI_INCR_ADDR11 : STATE_LOGIC
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => S_AXI_R_LAST_INT,
I1 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => Mmux_S_AXI_R_LAST13,
O => S_AXI_INCR_ADDR
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000FE"
)
port map (
I0 => S_AXI_ARLEN(2),
I1 => S_AXI_ARLEN(1),
I2 => S_AXI_ARLEN(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => N01
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q : STATE_LOGIC
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => S_AXI_ARLEN(7),
I1 => S_AXI_ARLEN(6),
I2 => S_AXI_ARLEN(5),
I3 => S_AXI_ARLEN(4),
I4 => S_AXI_ARLEN(3),
I5 => N01,
O => S_AXI_ARLEN_7_GND_8_o_equal_1_o
);
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_gaxi_full_sm_outstanding_read_c1 : STATE_LOGIC
generic map(
INIT => X"0020000002200200"
)
port map (
I0 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd1_13,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => N2,
O => gaxi_full_sm_outstanding_read_c
);
Mmux_gaxi_full_sm_ar_ready_c12 : STATE_LOGIC
generic map(
INIT => X"0000000000004555"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => '0',
I5 => '0',
O => Mmux_gaxi_full_sm_ar_ready_c11
);
Mmux_S_AXI_R_LAST11_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000EF"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
Mmux_S_AXI_R_LAST11 : STATE_LOGIC
generic map(
INIT => X"FCAAFC0A00AA000A"
)
port map (
I0 => S_AXI_ARVALID,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => N4,
I5 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
O => gaxi_full_sm_r_valid_c
);
S_AXI_MUX_SEL1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAAAA08"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => '0',
O => S_AXI_MUX_SEL
);
Mmux_S_AXI_RD_EN11 : STATE_LOGIC
generic map(
INIT => X"F3F3F755A2A2A200"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => gaxi_full_sm_outstanding_read_r_15,
I4 => present_state_FSM_FFd2_14,
I5 => S_AXI_ARVALID,
O => S_AXI_RD_EN
);
present_state_FSM_FFd1_In3 : beh_muxf7
port map (
I0 => N8,
I1 => N9,
S => present_state_FSM_FFd1_13,
O => present_state_FSM_FFd1_In
);
present_state_FSM_FFd1_In3_F : STATE_LOGIC
generic map(
INIT => X"000000005410F4F0"
)
port map (
I0 => S_AXI_RREADY,
I1 => present_state_FSM_FFd2_14,
I2 => S_AXI_ARVALID,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => '0',
O => N8
);
present_state_FSM_FFd1_In3_G : STATE_LOGIC
generic map(
INIT => X"0000000072FF7272"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N9
);
Mmux_gaxi_full_sm_ar_ready_c14 : beh_muxf7
port map (
I0 => N10,
I1 => N11,
S => present_state_FSM_FFd1_13,
O => gaxi_full_sm_ar_ready_c
);
Mmux_gaxi_full_sm_ar_ready_c14_F : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88A8"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => Mmux_gaxi_full_sm_ar_ready_c11,
I5 => '0',
O => N10
);
Mmux_gaxi_full_sm_ar_ready_c14_G : STATE_LOGIC
generic map(
INIT => X"000000008D008D8D"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N11
);
Mmux_S_AXI_R_LAST1 : beh_muxf7
port map (
I0 => N12,
I1 => N13,
S => present_state_FSM_FFd1_13,
O => NlwRenamedSig_OI_S_AXI_R_LAST
);
Mmux_S_AXI_R_LAST1_F : STATE_LOGIC
generic map(
INIT => X"0000000088088888"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N12
);
Mmux_S_AXI_R_LAST1_G : STATE_LOGIC
generic map(
INIT => X"00000000E400E4E4"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => S_AXI_R_LAST_INT,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N13
);
end STRUCTURE;
-------------------------------------------------------------------------------
-- Output Register Stage Entity
--
-- This module builds the output register stages of the memory. This module is
-- instantiated in the main memory module (blk_mem_gen_v8_3_1) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_output_stage IS
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_output_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6" and "virtex6l".
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
-- C_HAS_RST : Determines the presence of the RST port
-- C_RSTRAM : Determines if special reset behavior is used
-- C_RST_PRIORITY : Determines the priority between CE and SR
-- C_INIT_VAL : Initialization value
-- C_HAS_EN : Determines the presence of the EN port
-- C_HAS_REGCE : Determines the presence of the REGCE port
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
-- of the RAM primitive
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- NUM_STAGES : Determines the number of output stages
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE output_stage_behavioral OF blk_mem_gen_v8_3_1_output_stage IS
--*******************************************************
-- Functions used in the output stage ARCHITECTURE
--*******************************************************
-- Calculate num_reg_stages
FUNCTION get_num_reg_stages(NUM_STAGES: INTEGER) RETURN INTEGER IS
VARIABLE num_reg_stages : INTEGER := 0;
BEGIN
IF (NUM_STAGES = 0) THEN
num_reg_stages := 0;
ELSE
num_reg_stages := NUM_STAGES - 1;
END IF;
RETURN num_reg_stages;
END get_num_reg_stages;
-- Check if the INTEGER is zero or non-zero
FUNCTION int_to_bit(input: INTEGER) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = 0) THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END int_to_bit;
-- Constants
CONSTANT HAS_EN : STD_LOGIC := int_to_bit(C_HAS_EN);
CONSTANT HAS_REGCE : STD_LOGIC := int_to_bit(C_HAS_REGCE);
CONSTANT HAS_RST : STD_LOGIC := int_to_bit(C_HAS_RST);
CONSTANT REG_STAGES : INTEGER := get_num_reg_stages(NUM_STAGES);
-- Pipeline array
TYPE reg_data_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
TYPE reg_ecc_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC;
TYPE reg_eccaddr_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
CONSTANT REG_INIT : reg_data_array := (OTHERS => init_val);
SIGNAL out_regs : reg_data_array := REG_INIT;
SIGNAL sbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL dbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL rdaddrecc_regs: reg_eccaddr_array := (OTHERS => (OTHERS => '0'));
-- Internal signals
SIGNAL en_i : STD_LOGIC;
SIGNAL regce_i : STD_LOGIC;
SIGNAL rst_i : STD_LOGIC;
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := init_val;
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL DIN : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL RDADDRECC_IN : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ;
SIGNAL SBITERR_IN : STD_LOGIC := '0';
SIGNAL DBITERR_IN : STD_LOGIC := '0';
BEGIN
--***********************************************************************
-- Assign internal signals. This effectively wires off optional inputs.
--***********************************************************************
-- Internal enable for output registers is tied to user EN or '1' depending
-- on parameters
en_i <= EN OR (NOT HAS_EN);
-- Internal register enable for output registers is tied to user REGCE, EN
-- or '1' depending on parameters
regce_i <= (HAS_REGCE AND REGCE)
OR ((NOT HAS_REGCE) AND en_i);
-- Internal SRR is tied to user RST or '0' depending on parameters
rst_i <= RST AND HAS_RST;
--***************************************************************************
-- NUM_STAGES = 0 (No output registers. RAM only)
--***************************************************************************
zero_stages: IF (NUM_STAGES = 0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE zero_stages;
NO_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 0) GENERATE
DIN <= DIN_I;
RDADDRECC_IN <= RDADDRECC_IN_I;
SBITERR_IN <= SBITERR_IN_I;
DBITERR_IN <= DBITERR_IN_I;
END GENERATE NO_ECC_PIPE_REG;
WITH_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(ECCPIPECE = '1') THEN
DIN <= DIN_I AFTER FLOP_DELAY;
RDADDRECC_IN <= RDADDRECC_IN_I AFTER FLOP_DELAY;
SBITERR_IN <= SBITERR_IN_I AFTER FLOP_DELAY;
DBITERR_IN <= DBITERR_IN_I AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS;
END GENERATE WITH_ECC_PIPE_REG;
--***************************************************************************
-- NUM_STAGES = 1
-- (Mem Output Reg only or Mux Output Reg only)
--***************************************************************************
-- Possible valid combinations:
-- Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
-- +-----------------------------------------+
-- | C_RSTRAM_* | Reset Behavior |
-- +----------------+------------------------+
-- | 0 | Normal Behavior |
-- +----------------+------------------------+
-- | 1 | Special Behavior |
-- +----------------+------------------------+
--
-- Normal = REGCE gates reset, as in the case of all Virtex families and all
-- spartan families with the exception of S3ADSP and S6.
-- Special = EN gates reset, as in the case of S3ADSP and S6.
one_stage_norm: IF (NUM_STAGES = 1 AND
(C_RSTRAM=0 OR (C_RSTRAM=1 AND (C_XDEVICEFAMILY/="spartan3adsp" AND C_XDEVICEFAMILY/="aspartan3adsp")) OR
C_HAS_MEM_OUTPUT_REGS=0 OR C_HAS_RST=0)) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i = '1' AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
END IF;--CLK
END PROCESS;
END GENERATE one_stage_norm;
-- Special Reset Behavior for S6 and S3ADSP
one_stage_splbhv: IF (NUM_STAGES=1 AND C_RSTRAM=1 AND (C_XDEVICEFAMILY ="spartan3adsp" OR C_XDEVICEFAMILY ="aspartan3adsp"))
GENERATE
DOUT <= dout_i;
SBITERR <= '0';
DBITERR <= '0';
RDADDRECC <= (OTHERS => '0');
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (rst_i='1' AND en_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
ELSIF (regce_i='1' AND rst_i/='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE one_stage_splbhv;
--****************************************************************************
-- NUM_STAGES > 1
-- Mem Output Reg + Mux Output Reg
-- or
-- Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
-- or
-- Mux Pipeline Stages (>0) + Mux Output Reg
--****************************************************************************
multi_stage: IF (NUM_STAGES > 1) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i='1'AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
IF (en_i='1') THEN
-- Shift the data through the output stages
FOR i IN 1 TO REG_STAGES-1 LOOP
out_regs(i) <= out_regs(i-1) AFTER FLOP_DELAY;
sbiterr_regs(i) <= sbiterr_regs(i-1) AFTER FLOP_DELAY;
dbiterr_regs(i) <= dbiterr_regs(i-1) AFTER FLOP_DELAY;
rdaddrecc_regs(i) <= rdaddrecc_regs(i-1) AFTER FLOP_DELAY;
END LOOP;
out_regs(0) <= DIN;
sbiterr_regs(0) <= SBITERR_IN;
dbiterr_regs(0) <= DBITERR_IN;
rdaddrecc_regs(0) <= RDADDRECC_IN;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE multi_stage;
END output_stage_behavioral;
-------------------------------------------------------------------------------
-- SoftECC Output Register Stage Entity
-- This module builds the softecc output register stages. This module is
-- instantiated in the memory module (blk_mem_gen_v8_3_1_mem_module) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ;
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- of the RAM primitive
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE softecc_output_reg_stage_behavioral OF blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
-- Internal signals
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
--***************************************************************************
-- NO OUTPUT STAGES
--***************************************************************************
no_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE no_output_stage;
--****************************************************************************
-- WITH OUTPUT STAGE
--****************************************************************************
has_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END PROCESS;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
END GENERATE has_output_stage;
END softecc_output_reg_stage_behavioral;
--******************************************************************************
-- Main Memory module
--
-- This module is the behavioral model which implements the RAM
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
ENTITY blk_mem_gen_v8_3_1_mem_module IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_mem_module;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE mem_module_behavioral OF blk_mem_gen_v8_3_1_mem_module IS
--****************************************
-- min/max constant functions
--****************************************
-- get_max
----------
function SLV_TO_INT(SLV: in std_logic_vector
) return integer is
variable int : integer;
begin
int := 0;
for i in SLV'high downto SLV'low loop
int := int * 2;
if SLV(i) = '1' then
int := int + 1;
end if;
end loop;
return int;
end;
FUNCTION get_max(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a > b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-- get_min
----------
FUNCTION get_min(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
--***************************************************************
-- convert write_mode from STRING type for use in case statement
--***************************************************************
FUNCTION write_mode_to_vector(mode: STRING) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF (mode = "NO_CHANGE") THEN
RETURN "10";
ELSIF (mode = "READ_FIRST") THEN
RETURN "01";
ELSE
RETURN "00"; -- WRITE_FIRST
END IF;
END FUNCTION;
--***************************************************************
-- convert hex STRING to STD_LOGIC_VECTOR
--***************************************************************
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
--***************************************************************
-- locally derived constants to determine memory shape
--***************************************************************
CONSTANT MIN_WIDTH_A : INTEGER := get_min(C_WRITE_WIDTH_A, C_READ_WIDTH_A);
CONSTANT MIN_WIDTH_B : INTEGER := get_min(C_WRITE_WIDTH_B,C_READ_WIDTH_B);
CONSTANT MIN_WIDTH : INTEGER := get_min(MIN_WIDTH_A, MIN_WIDTH_B);
CONSTANT MAX_DEPTH_A : INTEGER := get_max(C_WRITE_DEPTH_A, C_READ_DEPTH_A);
CONSTANT MAX_DEPTH_B : INTEGER := get_max(C_WRITE_DEPTH_B, C_READ_DEPTH_B);
CONSTANT MAX_DEPTH : INTEGER := get_max(MAX_DEPTH_A, MAX_DEPTH_B);
TYPE int_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF std_logic_vector(C_WRITE_WIDTH_A-1 DOWNTO 0);
TYPE mem_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC_VECTOR(MIN_WIDTH-1 DOWNTO 0);
TYPE ecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
TYPE softecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
--***************************************************************
-- memory initialization function
--***************************************************************
IMPURE FUNCTION init_memory(DEFAULT_DATA :
STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
write_width_a : INTEGER;
depth : INTEGER;
width : INTEGER)
RETURN mem_array IS
VARIABLE init_return : mem_array := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(write_width_a-1 DOWNTO 0);
VARIABLE int_mem_vector : int_array:= (OTHERS => (OTHERS => '0'));
VARIABLE file_buffer : LINE;
VARIABLE i : INTEGER := 0;
VARIABLE j : INTEGER;
VARIABLE k : INTEGER;
VARIABLE ignore_line : BOOLEAN := false;
VARIABLE good_data : BOOLEAN := false;
VARIABLE char_tmp : CHARACTER;
VARIABLE index : INTEGER;
variable init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable data : std_logic_vector(255 downto 0) := (others => '0');
variable inside_init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable k_slv : std_logic_vector(31 downto 0) := (others => '0');
variable i_slv : std_logic_vector(31 downto 0) := (others => '0');
VARIABLE disp_line : line := null;
variable open_status : file_open_status;
variable input_initf_tmp : mem_array ;
variable input_initf : mem_array := (others => (others => '0'));
file int_infile : text;
variable data_line, data_line_tmp, out_data_line : line;
variable slv_width : integer;
VARIABLE d_l : LINE;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
index := 0;
FOR i IN 0 TO depth-1 LOOP
FOR j IN 0 TO width-1 LOOP
init_return(i)(j) := DEFAULT_DATA(index);
index := (index + 1) MOD C_WRITE_WIDTH_A;
END LOOP;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, file_buffer);
read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO write_width_a-1 LOOP
IF (j MOD width = 0 AND j /= 0) THEN
i := i + 1;
END IF;
init_return(i)(j MOD width) := bit_to_sl(mem_vector(j));
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
--Display output message indicating that the behavioral model is done
--initializing
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator data initialization complete." SEVERITY NOTE;
if (C_USE_BRAM_BLOCK = 1) then
--Display output message indicating that the behavioral model is being
--initialized
-- Read in the .mem file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_INIT_FILE /= "NONE") then
file_open(open_status, int_infile, C_INIT_FILE, read_mode);
while not endfile(int_infile) loop
readline(int_infile, data_line);
while (data_line /= null and data_line'length > 0) loop
if (data_line(data_line'low to data_line'low + 1) = "//") then
deallocate(data_line);
elsif ((data_line(data_line'low to data_line'low + 1) = "/*") and (data_line(data_line'high-1 to data_line'high) = "*/")) then
deallocate(data_line);
elsif (data_line(data_line'low to data_line'low + 1) = "/*") then
deallocate(data_line);
ignore_line := true;
elsif (ignore_line = true and data_line(data_line'high-1 to data_line'high) = "*/") then
deallocate(data_line);
ignore_line := false;
elsif (ignore_line = false and data_line(data_line'low) = '@') then
read(data_line, char_tmp);
hread(data_line, init_addr_slv, good_data);
i := SLV_TO_INT(init_addr_slv);
elsif (ignore_line = false) then
hread(data_line, input_initf_tmp(i), good_data);
init_return(i)(write_width_a - 1 downto 0) := input_initf_tmp(i)(write_width_a - 1 downto 0);
if (good_data = true) then
i := i + 1;
end if;
else
deallocate(data_line);
end if;
end loop;
end loop;
file_close(int_infile);
END IF;
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- memory type constants
--***************************************************************
CONSTANT MEM_TYPE_SP_RAM : INTEGER := 0;
CONSTANT MEM_TYPE_SDP_RAM : INTEGER := 1;
CONSTANT MEM_TYPE_TDP_RAM : INTEGER := 2;
CONSTANT MEM_TYPE_SP_ROM : INTEGER := 3;
CONSTANT MEM_TYPE_DP_ROM : INTEGER := 4;
--***************************************************************
-- memory configuration constant functions
--***************************************************************
--get_single_port
-----------------
FUNCTION get_single_port(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_RAM OR mem_type=MEM_TYPE_SP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_single_port;
--get_is_rom
--------------
FUNCTION get_is_rom(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_ROM OR mem_type=MEM_TYPE_DP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_is_rom;
--get_has_a_write
------------------
FUNCTION get_has_a_write(IS_ROM : INTEGER) RETURN INTEGER IS
BEGIN
IF (IS_ROM=0) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_a_write;
--get_has_b_write
------------------
FUNCTION get_has_b_write(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_TDP_RAM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_write;
--get_has_a_read
------------------
FUNCTION get_has_a_read(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SDP_RAM) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_a_read;
--get_has_b_read
------------------
FUNCTION get_has_b_read(SINGLE_PORT : INTEGER) RETURN INTEGER IS
BEGIN
IF (SINGLE_PORT=1) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_b_read;
--get_has_b_port
------------------
FUNCTION get_has_b_port(HAS_B_READ : INTEGER;
HAS_B_WRITE : INTEGER)
RETURN INTEGER IS
BEGIN
IF (HAS_B_READ=1 OR HAS_B_WRITE=1) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_port;
--get_num_output_stages
-----------------------
FUNCTION get_num_output_stages(has_mem_output_regs : INTEGER;
has_mux_output_regs : INTEGER;
mux_pipeline_stages : INTEGER)
RETURN INTEGER IS
VARIABLE actual_mux_pipeline_stages : INTEGER;
BEGIN
-- Mux pipeline stages can be non-zero only when there is a mux
-- output register.
IF (has_mux_output_regs=1) THEN
actual_mux_pipeline_stages := mux_pipeline_stages;
ELSE
actual_mux_pipeline_stages := 0;
END IF;
RETURN has_mem_output_regs+actual_mux_pipeline_stages+has_mux_output_regs;
END get_num_output_stages;
--***************************************************************************
-- Component declaration of the VARIABLE depth output register stage
--***************************************************************************
COMPONENT blk_mem_gen_v8_3_1_output_stage
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
EN : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
ECCPIPECE : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_output_stage;
COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************************************
-- locally derived constants to assist memory access
--******************************************************
CONSTANT WRITE_WIDTH_RATIO_A : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_A : INTEGER := C_READ_WIDTH_A/MIN_WIDTH;
CONSTANT WRITE_WIDTH_RATIO_B : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_B : INTEGER := C_READ_WIDTH_B/MIN_WIDTH;
--******************************************************
-- To modify the LSBs of the 'wider' data to the actual
-- address value
--******************************************************
CONSTANT WRITE_ADDR_A_DIV : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH_A;
CONSTANT READ_ADDR_A_DIV : INTEGER := C_READ_WIDTH_A/MIN_WIDTH_A;
CONSTANT WRITE_ADDR_B_DIV : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH_B;
CONSTANT READ_ADDR_B_DIV : INTEGER := C_READ_WIDTH_B/MIN_WIDTH_B;
--******************************************************
-- FUNCTION : log2roundup
--******************************************************
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
--******************************************************
-- Other constants and signals
--******************************************************
CONSTANT COLL_DELAY : TIME := 100 ps;
-- default data vector
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_DEFAULT_DATA,
C_WRITE_WIDTH_A);
CONSTANT CHKBIT_WIDTH : INTEGER := if_then_else(C_WRITE_WIDTH_A>57,8,if_then_else(C_WRITE_WIDTH_A>26,7,if_then_else(C_WRITE_WIDTH_A>11,6,if_then_else(C_WRITE_WIDTH_A>4,5,if_then_else(C_WRITE_WIDTH_A<5,4,0)))));
-- the init memory SIGNAL
SIGNAL memory_i : mem_array;
SIGNAL doublebit_error_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0);
SIGNAL current_contents_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
-- write mode constants
CONSTANT WRITE_MODE_A : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_A);
CONSTANT WRITE_MODE_B : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_B);
CONSTANT WRITE_MODES : STD_LOGIC_VECTOR(3 DOWNTO 0) :=
WRITE_MODE_A & WRITE_MODE_B;
-- reset values
CONSTANT INITA_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITA_VAL,
C_READ_WIDTH_A);
CONSTANT INITB_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITB_VAL,
C_READ_WIDTH_B);
-- memory output 'latches'
SIGNAL memory_out_a : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0) :=
INITA_VAL;
SIGNAL memory_out_b : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) :=
INITB_VAL;
SIGNAL sbiterr_in : STD_LOGIC := '0';
SIGNAL sbiterr_sdp : STD_LOGIC := '0';
SIGNAL dbiterr_in : STD_LOGIC := '0';
SIGNAL dbiterr_sdp : STD_LOGIC := '0';
SIGNAL rdaddrecc_in : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_sdp : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL doutb_i : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i : STD_LOGIC := '0';
SIGNAL dbiterr_i : STD_LOGIC := '0';
-- memory configuration constants
-----------------------------------------------
CONSTANT SINGLE_PORT : INTEGER := get_single_port(C_MEM_TYPE);
CONSTANT IS_ROM : INTEGER := get_is_rom(C_MEM_TYPE);
CONSTANT HAS_A_WRITE : INTEGER := get_has_a_write(IS_ROM);
CONSTANT HAS_B_WRITE : INTEGER := get_has_b_write(C_MEM_TYPE);
CONSTANT HAS_A_READ : INTEGER := get_has_a_read(C_MEM_TYPE);
CONSTANT HAS_B_READ : INTEGER := get_has_b_read(SINGLE_PORT);
CONSTANT HAS_B_PORT : INTEGER := get_has_b_port(HAS_B_READ, HAS_B_WRITE);
CONSTANT NUM_OUTPUT_STAGES_A : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_A,
C_MUX_PIPELINE_STAGES);
CONSTANT NUM_OUTPUT_STAGES_B : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES);
CONSTANT WEA0 : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT WEB0 : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-----------------------------------------------------------------------------
-- DEBUG CONTROL
-- DEBUG=0 : Debug output OFF
-- DEBUG=1 : Some debug info printed
-----------------------------------------------------------------------------
CONSTANT DEBUG : INTEGER := 0;
-- internal signals
-----------------------------------------------
SIGNAL ena_i : STD_LOGIC;
SIGNAL enb_i : STD_LOGIC;
SIGNAL reseta_i : STD_LOGIC;
SIGNAL resetb_i : STD_LOGIC;
SIGNAL wea_i : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL web_i : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL rea_i : STD_LOGIC;
SIGNAL reb_i : STD_LOGIC;
SIGNAL message_complete : BOOLEAN := false;
SIGNAL rsta_outp_stage : STD_LOGIC := '0';
SIGNAL rstb_outp_stage : STD_LOGIC := '0';
--*********************************************************
--FUNCTION : Collision check
--*********************************************************
FUNCTION collision_check (addr_a :
STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
iswrite_a : BOOLEAN;
addr_b :
STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
iswrite_b : BOOLEAN)
RETURN BOOLEAN IS
VARIABLE c_aw_bw : INTEGER;
VARIABLE c_aw_br : INTEGER;
VARIABLE c_ar_bw : INTEGER;
VARIABLE write_addr_a_width : INTEGER;
VARIABLE read_addr_a_width : INTEGER;
VARIABLE write_addr_b_width : INTEGER;
VARIABLE read_addr_b_width : INTEGER;
BEGIN
c_aw_bw := 0;
c_aw_br := 0;
c_ar_bw := 0;
-- Determine the effective address widths FOR each of the 4 ports
write_addr_a_width := C_ADDRA_WIDTH-log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width := C_ADDRA_WIDTH-log2roundup(READ_ADDR_A_DIV);
write_addr_b_width := C_ADDRB_WIDTH-log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width := C_ADDRB_WIDTH-log2roundup(READ_ADDR_B_DIV);
--Look FOR a write-write collision. In order FOR a write-write
--collision to exist, both ports must have a write transaction.
IF (iswrite_a AND iswrite_b) THEN
IF (write_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_a and iswrite_b
--If the B port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_a) THEN
IF (write_addr_a_width > read_addr_b_width) THEN
--read_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_b_width
--Once both are scaled to read_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
END IF; --width
END IF; --iswrite_a
--If the A port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_b) THEN
IF (read_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
ELSE
--read_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_a_width
--Once both are scaled to read_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_b
RETURN (c_aw_bw=1 OR c_aw_br=1 OR c_ar_bw=1);
END FUNCTION collision_check;
BEGIN -- Architecture
-----------------------------------------------------------------------------
-- SOFTECC and ECC SBITERR/DBITERR Outputs
-- The ECC Behavior is modeled by the behavioral models only for Virtex-6.
-- The SOFTECC Behavior is modeled by the behavioral models for Spartan-6.
-- For Virtex-5, these outputs will be tied to 0.
-----------------------------------------------------------------------------
SBITERR <= sbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_sdp WHEN (((C_FAMILY="virtex7") AND C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
-----------------------------------------------
-- This effectively wires off optional inputs
-----------------------------------------------
ena_i <= ENA WHEN (C_HAS_ENA=1) ELSE '1';
enb_i <= ENB WHEN (C_HAS_ENB=1 AND HAS_B_PORT=1) ELSE '1';
-- We are doing an "AND" operation of WEA and ENA and passing to Enbale pin of BRAM when built-in ECC is enabled,
-- what this means is that the write operation happens only when both WEA and ENA are high.
wea_i <= WEA WHEN (HAS_A_WRITE=1 AND ena_i='1') ELSE WEA0;
-- wea_i <= (OTHERS => '1') WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=1 AND ENA = '1') ELSE -- Use_ENA_pin
-- WEA WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=0) ELSE -- Always_enabled
-- WEA WHEN (HAS_A_WRITE=1 AND ena_i='1' AND C_USE_ECC = 0) ELSE
-- WEA0;
web_i <= WEB WHEN (HAS_B_WRITE=1 AND enb_i='1') ELSE WEB0;
rea_i <= ena_i WHEN (HAS_A_READ=1) ELSE '0';
reb_i <= enb_i WHEN (HAS_B_READ=1) ELSE '0';
-- these signals reset the memory latches
-- For the special reset behaviors in some of the families, the C_RSTRAM
-- attribute of the corresponding port is used to indicate if the latch is
-- reset or not.
reseta_i <= RSTA WHEN
((C_HAS_RSTA=1 AND NUM_OUTPUT_STAGES_A=0) OR
(C_HAS_RSTA=1 AND C_RSTRAM_A=1))
ELSE '0';
resetb_i <= RSTB WHEN
((C_HAS_RSTB=1 AND NUM_OUTPUT_STAGES_B=0) OR
(C_HAS_RSTB=1 AND C_RSTRAM_B=1) )
ELSE '0';
--***************************************************************************
-- This is the main PROCESS which includes the memory VARIABLE and the read
-- and write procedures. It also schedules read and write operations
--***************************************************************************
PROCESS (CLKA, CLKB,rea_i,reb_i,reseta_i,resetb_i)
-- Initialize the init memory array
------------------------------------
VARIABLE memory : mem_array := init_memory(DEFAULT_DATA,
C_WRITE_WIDTH_A,
MAX_DEPTH,
MIN_WIDTH);
-- Initialize the mem memory array
------------------------------------
VARIABLE softecc_sbiterr_arr : softecc_err_array;
VARIABLE softecc_dbiterr_arr : softecc_err_array;
VARIABLE sbiterr_arr : ecc_err_array;
VARIABLE dbiterr_arr : ecc_err_array;
CONSTANT doublebit_lsb : STD_LOGIC_VECTOR (1 DOWNTO 0):="11";
CONSTANT doublebit_msb : STD_LOGIC_VECTOR (C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 DOWNTO 0):= (OTHERS => '0');
VARIABLE doublebit_error : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0) := doublebit_msb & doublebit_lsb ;
VARIABLE current_contents_var : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
--***********************************
-- procedures to access the memory
--***********************************
-- write_a
----------
PROCEDURE write_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
inj_sbiterr : IN STD_LOGIC;
inj_dbiterr : IN STD_LOGIC) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
VARIABLE message : LINE;
VARIABLE errbit_current_contents : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
-- Block Memory Generator non-cycle-accurate message
ASSERT (message_complete) REPORT "Block Memory Generator module is using a behavioral model FOR simulation which will not precisely model memory collision behavior."
SEVERITY NOTE;
message_complete <= true;
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_A_DIV);
IF (address_i >= C_WRITE_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range FOR A Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEA = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_A + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEA_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Insert double bit errors:
IF (C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
current_contents(0) := NOT(current_contents(0));
current_contents(1) := NOT(current_contents(1));
--current_contents(0) := NOT(current_contents(30));
--current_contents(1) := NOT(current_contents(62));
END IF;
END IF;
-- Insert double bit errors:
IF (C_USE_SOFTECC=1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 downto 2) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 downto 0);
doublebit_error(0) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1);
doublebit_error(1) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-2);
current_contents := current_contents XOR doublebit_error(C_WRITE_WIDTH_A-1 DOWNTO 0);
END IF;
END IF;
IF(DEBUG=1) THEN
current_contents_var := current_contents; --for debugging current
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_A + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
-- Store address at which error is injected:
IF ((C_FAMILY = "virtex7") AND C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
sbiterr_arr(address_i) := '1';
ELSE
sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
dbiterr_arr(address_i) := '1';
ELSE
dbiterr_arr(address_i) := '0';
END IF;
END IF;
-- Store address at which softecc error is injected:
IF (C_USE_SOFTECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
softecc_sbiterr_arr(address_i) := '1';
ELSE
softecc_sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
softecc_dbiterr_arr(address_i) := '1';
ELSE
softecc_dbiterr_arr(address_i) := '0';
END IF;
END IF;
END IF;
END PROCEDURE;
-- write_b
----------
PROCEDURE write_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_B_DIV);
IF (address_i >= C_WRITE_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEB = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_B + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEB_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_B + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
END IF;
END PROCEDURE;
-- read_a
----------
PROCEDURE read_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_A_DIV);
IF (address_i >= C_READ_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for A Read"
SEVERITY WARNING;
END IF;
memory_out_a <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_A-1 LOOP
memory_out_a(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_A + i) AFTER FLOP_DELAY;
END LOOP;
END IF;
END IF;
END PROCEDURE;
-- read_b
----------
PROCEDURE read_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_B_DIV);
IF (address_i >= C_READ_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Read"
SEVERITY WARNING;
END IF;
memory_out_b <= (OTHERS => 'X') AFTER FLOP_DELAY;
sbiterr_in <= 'X' AFTER FLOP_DELAY;
dbiterr_in <= 'X' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_B-1 LOOP
memory_out_b(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_B + i) AFTER FLOP_DELAY;
END LOOP;
--assert sbiterr and dbiterr signals
IF ((C_FAMILY="virtex7") AND C_USE_ECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
--assert softecc sbiterr and dbiterr signals
ELSIF (C_USE_SOFTECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (softecc_sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (softecc_dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
END IF;
END IF;
END IF;
END PROCEDURE;
-- reset_a
----------
PROCEDURE reset_a
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
-- reset_b
----------
PROCEDURE reset_b
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
BEGIN -- begin the main PROCESS
--***************************************************************************
-- These are the main blocks which schedule read and write operations
-- Note that the reset priority feature at the latch stage is only supported
-- for Spartan-6. For other families, the default priority at the latch stage
-- is "CE"
--***************************************************************************
-- Synchronous clocks: schedule port operations with respect to both
-- write operating modes
IF (C_COMMON_CLK=1) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODES IS
WHEN "0000" => -- write_first write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "0100" => -- read_first write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "0001" => -- write_first read_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0101" => --read_first read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0010" => -- write_first no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0110" => -- read_first no_change
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1000" => -- no_change write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "1001" => -- no_change read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1010" => -- no_change no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Synchronous clocks
-- Asynchronous clocks: port operation is independent
IF (C_COMMON_CLK=0) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODE_A IS
WHEN "00" => -- write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN "01" => -- read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "10" => -- no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
IF (CLKB='1' AND CLKB'EVENT) THEN
CASE WRITE_MODE_B IS
WHEN "00" => -- write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "01" => -- read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "10" => -- no_change
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Asynchronous clocks
-- Assign the memory VARIABLE to the user_visible memory_i SIGNAL
IF(DEBUG=1) THEN
memory_i <= memory;
doublebit_error_i <= doublebit_error;
current_contents_i <= current_contents_var;
END IF;
END PROCESS;
--********************************************************************
-- Instantiate the VARIABLE depth output stage
--********************************************************************
-- Port A
rsta_outp_stage <= RSTA and not sleep;
rstb_outp_stage <= RSTB and not sleep;
reg_a : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTA,
C_RSTRAM => C_RSTRAM_A,
C_RST_PRIORITY => C_RST_PRIORITY_A,
init_val => INITA_VAL,
C_HAS_EN => C_HAS_ENA,
C_HAS_REGCE => C_HAS_REGCEA,
C_DATA_WIDTH => C_READ_WIDTH_A,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_A,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_A,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKA,
RST => rsta_outp_stage, --RSTA,
EN => ENA,
REGCE => REGCEA,
DIN_I => memory_out_a,
DOUT => DOUTA,
SBITERR_IN_I => '0',
DBITERR_IN_I => '0',
SBITERR => OPEN,
DBITERR => OPEN,
RDADDRECC_IN_I => (OTHERS => '0'),
ECCPIPECE => '0',
RDADDRECC => OPEN
);
-- Port B
reg_b : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTB,
C_RSTRAM => C_RSTRAM_B,
C_RST_PRIORITY => C_RST_PRIORITY_B,
init_val => INITB_VAL,
C_HAS_EN => C_HAS_ENB,
C_HAS_REGCE => C_HAS_REGCEB,
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_B,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKB,
RST => rstb_outp_stage,--RSTB,
EN => ENB,
REGCE => REGCEB,
DIN_I => memory_out_b,
DOUT => doutb_i,
SBITERR_IN_I => sbiterr_in,
DBITERR_IN_I => dbiterr_in,
SBITERR => sbiterr_i,
DBITERR => dbiterr_i,
RDADDRECC_IN_I => rdaddrecc_in,
ECCPIPECE => ECCPIPECE,
RDADDRECC => rdaddrecc_i
);
--********************************************************************
-- Instantiate the input / Output Register stages
--********************************************************************
output_reg_stage: blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC MAP(
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP(
CLK => CLKB,
DIN => doutb_i,
DOUT => DOUTB,
SBITERR_IN => sbiterr_i,
DBITERR_IN => dbiterr_i,
SBITERR => sbiterr_sdp,
DBITERR => dbiterr_sdp,
RDADDRECC_IN => rdaddrecc_i,
RDADDRECC => rdaddrecc_sdp
);
--*********************************
-- Synchronous collision checks
--*********************************
sync_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=1) GENERATE
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
-- collision detect
VARIABLE is_collision : BOOLEAN;
VARIABLE message : LINE;
BEGIN
IF (CLKA='1' AND CLKA'EVENT) THEN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision := false;
END IF;
-- If the write port is in READ_FIRST mode, there is no collision
IF (C_WRITE_MODE_A="READ_FIRST" AND wea_i/=WEA0 AND web_i=WEB0) THEN
is_collision := false;
END IF;
IF (C_WRITE_MODE_B="READ_FIRST" AND web_i/=WEB0 AND wea_i=WEA0) THEN
is_collision := false;
END IF;
-- Only flag if one of the accesses is a write
IF (is_collision AND (wea_i/=WEA0 OR web_i/=WEB0)) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END IF;
END PROCESS;
END GENERATE;
--*********************************
-- Asynchronous collision checks
--*********************************
async_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=0) GENERATE
SIGNAL addra_delay : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL wea_delay : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL ena_delay : STD_LOGIC;
SIGNAL addrb_delay : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
SIGNAL web_delay : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL enb_delay : STD_LOGIC;
BEGIN
-- Delay A and B addresses in order to mimic setup/hold times
PROCESS (ADDRA, wea_i, ena_i, ADDRB, web_i, enb_i)
BEGIN
addra_delay <= ADDRA AFTER COLL_DELAY;
wea_delay <= wea_i AFTER COLL_DELAY;
ena_delay <= ena_i AFTER COLL_DELAY;
addrb_delay <= ADDRB AFTER COLL_DELAY;
web_delay <= web_i AFTER COLL_DELAY;
enb_delay <= enb_i AFTER COLL_DELAY;
END PROCESS;
-- Do the checks w/rt A
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_a : BOOLEAN;
VARIABLE is_collision_delay_a : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_a := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_a := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_delay_a := collision_check(ADDRA,
wea_i/=WEA0,
addrb_delay,
web_delay/=WEB0);
ELSE
is_collision_delay_a := false;
END IF;
-- Only flag if B access is a write
IF (is_collision_a AND web_i/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_a AND web_delay/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, addrb_delay);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
-- Do the checks w/rt B
PROCESS (CLKB)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_b : BOOLEAN;
VARIABLE is_collision_delay_b : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA) /= 'X') THEN
is_collision_b := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_b := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(addra_delay) /= 'X') THEN
is_collision_delay_b := collision_check(addra_delay,
wea_delay/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_delay_b := false;
END IF;
-- Only flag if A access is a write
-- Modified condition checking (is_collision_b AND WEA0_i=/WEA0) to fix CR526228
IF (is_collision_b AND wea_i/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_b AND wea_delay/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, addra_delay);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
END GENERATE;
END mem_module_behavioral;
--******************************************************************************
-- Top module that wraps SoftECC Input register stage and the main memory module
--
-- This module is the top-level of behavioral model
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1 IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_CTRL_ECC_ALGO : STRING := "NONE";
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
--C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_SLEEP_PIN : INTEGER := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
PORT (
clka : IN STD_LOGIC := '0';
rsta : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '1';
regcea : IN STD_LOGIC := '1';
wea : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addra : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
dina : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
douta : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
clkb : IN STD_LOGIC := '0';
rstb : IN STD_LOGIC := '0';
enb : IN STD_LOGIC := '1';
regceb : IN STD_LOGIC := '1';
web : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addrb : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
dinb : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
doutb : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
injectsbiterr : IN STD_LOGIC := '0';
injectdbiterr : IN STD_LOGIC := '0';
sbiterr : OUT STD_LOGIC := '0';
dbiterr : OUT STD_LOGIC := '0';
rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : in std_logic := '0';
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic := '0';
rstb_busy : out std_logic := '0';
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
s_aclk : IN STD_LOGIC := '0';
s_aresetn : IN STD_LOGIC := '0';
-- axi full/lite slave Write (write side)
s_axi_awid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid : IN STD_LOGIC := '0';
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast : IN STD_LOGIC := '0';
s_axi_wvalid : IN STD_LOGIC := '0';
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC := '0';
-- axi full/lite slave Read (Write side)
s_axi_arid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid : IN STD_LOGIC := '0';
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_rdata : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC := '0';
-- axi full/lite sideband Signals
s_axi_injectsbiterr : IN STD_LOGIC := '0';
s_axi_injectdbiterr : IN STD_LOGIC := '0';
s_axi_sbiterr : OUT STD_LOGIC := '0';
s_axi_dbiterr : OUT STD_LOGIC := '0';
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END blk_mem_gen_v8_3_1;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE behavioral OF blk_mem_gen_v8_3_1 IS
COMPONENT blk_mem_gen_v8_3_1_mem_module
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_mem_module;
COMPONENT blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_axi_regs_fwd_v8_3;
COMPONENT blk_mem_axi_read_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT blk_mem_axi_read_wrapper_beh;
COMPONENT blk_mem_axi_write_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END COMPONENT blk_mem_axi_write_wrapper_beh;
CONSTANT FLOP_DELAY : TIME := 100 ps;
SIGNAL rsta_in : STD_LOGIC := '1';
SIGNAL ena_in : STD_LOGIC := '1';
SIGNAL regcea_in : STD_LOGIC := '1';
SIGNAL wea_in : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL addra_in : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL dina_in : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL injectsbiterr_in : STD_LOGIC := '0';
SIGNAL injectdbiterr_in : STD_LOGIC := '0';
-----------------------------------------------------------------------------
-- FUNCTION: toLowerCaseChar
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
-----------------------------------------------------------------------------
FUNCTION toLowerCaseChar(
char : character )
RETURN character IS
BEGIN
-- If char is not an upper case letter then return char
IF char<'A' OR char>'Z' THEN
RETURN char;
END IF;
-- Otherwise map char to its corresponding lower case character and
-- RETURN that
CASE char IS
WHEN 'A' => RETURN 'a';
WHEN 'B' => RETURN 'b';
WHEN 'C' => RETURN 'c';
WHEN 'D' => RETURN 'd';
WHEN 'E' => RETURN 'e';
WHEN 'F' => RETURN 'f';
WHEN 'G' => RETURN 'g';
WHEN 'H' => RETURN 'h';
WHEN 'I' => RETURN 'i';
WHEN 'J' => RETURN 'j';
WHEN 'K' => RETURN 'k';
WHEN 'L' => RETURN 'l';
WHEN 'M' => RETURN 'm';
WHEN 'N' => RETURN 'n';
WHEN 'O' => RETURN 'o';
WHEN 'P' => RETURN 'p';
WHEN 'Q' => RETURN 'q';
WHEN 'R' => RETURN 'r';
WHEN 'S' => RETURN 's';
WHEN 'T' => RETURN 't';
WHEN 'U' => RETURN 'u';
WHEN 'V' => RETURN 'v';
WHEN 'W' => RETURN 'w';
WHEN 'X' => RETURN 'x';
WHEN 'Y' => RETURN 'y';
WHEN 'Z' => RETURN 'z';
WHEN OTHERS => RETURN char;
END CASE;
END toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
FUNCTION equalIgnoreCase(
str1 : STRING;
str2 : STRING )
RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str2'left TO str1'right LOOP
IF NOT (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equalIgnoreCase;
-----------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
----------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
----------------------------------------------------------------------------
-- FUNCTION : log2roundup
----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
CONSTANT lower_limit : INTEGER := 1;
CONSTANT upper_limit : INTEGER := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
-----------------------------------------------------------------------------
-- FUNCTION : divroundup
-- Returns the ceiling value of the division
-- Data_value - the quantity to be divided, dividend
-- Divisor - the value to divide the data_value by
-----------------------------------------------------------------------------
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
SIGNAL s_axi_awaddr_out_c : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_araddr_out_c : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_wr_en_c : STD_LOGIC := '0';
SIGNAL s_axi_rd_en_c : STD_LOGIC := '0';
SIGNAL s_aresetn_a_c : STD_LOGIC := '0';
--**************************************************************************
-- AXI PARAMETERS
CONSTANT AXI_FULL_MEMORY_SLAVE : integer := if_then_else((C_AXI_SLAVE_TYPE = 0 AND C_AXI_TYPE = 1),1,0);
CONSTANT C_AXI_ADDR_WIDTH_MSB : integer := C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
CONSTANT C_AXI_ADDR_WIDTH : integer := C_AXI_ADDR_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT LOWER_BOUND_VAL : integer := if_then_else((log2roundup(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT C_AXI_ADDR_WIDTH_LSB : integer := if_then_else((AXI_FULL_MEMORY_SLAVE = 1),0,LOWER_BOUND_VAL);
CONSTANT C_AXI_OS_WR : integer := 2;
-- SAFETY LOGIC related Signals
SIGNAL RSTA_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_A : STD_LOGIC := '0';
SIGNAL RSTB_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_B : STD_LOGIC := '0';
SIGNAL ENA_dly : STD_LOGIC := '0';
SIGNAL ENA_dly_D : STD_LOGIC := '0';
SIGNAL ENB_dly : STD_LOGIC := '0';
SIGNAL ENB_dly_D : STD_LOGIC := '0';
SIGNAL RSTA_I_SAFE : STD_LOGIC := '0';
SIGNAL RSTB_I_SAFE : STD_LOGIC := '0';
SIGNAL ENA_I_SAFE : STD_LOGIC := '0';
SIGNAL ENB_I_SAFE : STD_LOGIC := '0';
SIGNAL ram_rstram_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstram_b_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_b_busy : STD_LOGIC := '0';
SIGNAL ENA_dly_reg : STD_LOGIC := '0';
SIGNAL ENB_dly_reg : STD_LOGIC := '0';
SIGNAL ENA_dly_reg_D : STD_LOGIC := '0';
SIGNAL ENB_dly_reg_D : STD_LOGIC := '0';
--**************************************************************************
BEGIN -- Architecture
--*************************************************************************
-- NO INPUT STAGE
--*************************************************************************
no_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=0) GENERATE
rsta_in <= RSTA;
ena_in <= ENA;
regcea_in <= REGCEA;
wea_in <= WEA;
addra_in <= ADDRA;
dina_in <= DINA;
injectsbiterr_in <= INJECTSBITERR;
injectdbiterr_in <= INJECTDBITERR;
END GENERATE no_input_stage;
--**************************************************************************
-- WITH INPUT STAGE
--**************************************************************************
has_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=1) GENERATE
PROCESS (CLKA)
BEGIN
IF (CLKA'EVENT AND CLKA = '1') THEN
rsta_in <= RSTA AFTER FLOP_DELAY;
ena_in <= ENA AFTER FLOP_DELAY;
regcea_in <= REGCEA AFTER FLOP_DELAY;
wea_in <= WEA AFTER FLOP_DELAY;
addra_in <= ADDRA AFTER FLOP_DELAY;
dina_in <= DINA AFTER FLOP_DELAY;
injectsbiterr_in <= INJECTSBITERR AFTER FLOP_DELAY;
injectdbiterr_in <= INJECTDBITERR AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE has_input_stage;
--**************************************************************************
-- NO SAFETY LOGIC
--**************************************************************************
NO_SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 0) GENERATE
ENA_I_SAFE <= ena_in;
ENB_I_SAFE <= ENB;
RSTA_I_SAFE <= rsta_in;
RSTB_I_SAFE <= RSTB;
END GENERATE NO_SAFETY_CKT_GEN;
--**************************************************************************
-- SAFETY LOGIC
--**************************************************************************
SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 1) GENERATE
-- RESET SAFETY LOGIC Generation
-- POR Generation
------------------------------------------------------------------------------
-- Power-ON Reset Generation
------------------------------------------------------------------------------
RST_SHFT_LOGIC_A : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
RSTA_SHFT_REG(4 DOWNTO 0) <= RSTA_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_A;
POR_RSTA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
POR_A <= RSTA_SHFT_REG(4) xor RSTA_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTA_GEN;
RST_SHFT_LOGIC_B : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
RSTB_SHFT_REG(4 DOWNTO 0) <= RSTB_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_B;
POR_RSTB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
POR_B <= RSTB_SHFT_REG(4) xor RSTB_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTB_GEN;
-----------------------------------------------------------------------------
-- Fix for the AR42571
-----------------------------------------------------------------------------
-- Reset Generation
-----------------------------------------------------------------------------
RSTA_I_SAFE <= rsta_in OR POR_A;
SPRAM_RST: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_I_SAFE <= '0';
END GENERATE SPRAM_RST;
nSPRAM_RST: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_I_SAFE <= RSTB OR POR_B;
END GENERATE nSPRAM_RST;
-----------------------------------------------------------------------------
-- RSTA/B_BUSY Generation
-----------------------------------------------------------------------------
RSTA_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
ram_rstram_a_busy <= rsta_in OR ENA_dly OR ENA_dly_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstram_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_NO_REG;
RSTA_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
ram_rstreg_a_busy <= rsta_in OR ENA_dly OR ENA_dly_reg_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstreg_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_WITH_REG;
SPRAM_RST_BUSY: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_BUSY <= '0';
END GENERATE SPRAM_RST_BUSY;
nSPRAM_RST_BUSY: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
ram_rstram_b_busy <= RSTB OR ENB_dly OR ENB_dly_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstram_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_NO_REG;
RSTB_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
ram_rstreg_b_busy <= RSTB OR ENB_dly OR ENB_dly_reg_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstreg_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_WITH_REG;
END GENERATE nSPRAM_RST_BUSY;
-----------------------------------------------------------------------------
-- ENA/ENB Generation
-----------------------------------------------------------------------------
ENA_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly <= rsta_in AFTER FLOP_DELAY;
ENA_dly_D <= ENA_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_D OR ena_in;
END GENERATE ENA_NO_REG;
ENA_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly_reg <= rsta_in AFTER FLOP_DELAY;
ENA_dly_reg_D <= ENA_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_reg_D OR ena_in;
END GENERATE ENA_WITH_REG;
SPRAM_ENB: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
ENB_I_SAFE <= '0';
END GENERATE SPRAM_ENB;
nSPRAM_ENB: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
ENB_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly <= RSTB AFTER FLOP_DELAY;
ENB_dly_D <= ENB_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_D OR ENB;
END GENERATE ENB_NO_REG;
ENB_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly_reg <= RSTB AFTER FLOP_DELAY;
ENB_dly_reg_D <= ENB_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_reg_D OR ENB;
END GENERATE ENB_WITH_REG;
END GENERATE nSPRAM_ENB;
END GENERATE SAFETY_CKT_GEN;
--**************************************************************************
-- NATIVE MEMORY MODULE INSTANCE
--**************************************************************************
native_mem_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 0) GENERATE
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,--rsta_in,
ENA => ENA_I_SAFE,--ena_in,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in,
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => RDADDRECC
);
END GENERATE native_mem_module;
--**************************************************************************
-- NATIVE MEMORY MAPPED MODULE INSTANCE
--**************************************************************************
native_mem_map_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 1) GENERATE
--**************************************************************************
-- NATIVE MEMORY MAPPED PARAMETERS
CONSTANT C_ADDRA_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_A);
CONSTANT C_ADDRB_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_B);
CONSTANT C_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
CONSTANT C_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
CONSTANT C_MEM_MAP_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_MSB;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT MEM_MAP_LOWER_BOUND_VAL_A : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT MEM_MAP_LOWER_BOUND_VAL_B : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_B,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_B,8)));
CONSTANT C_MEM_MAP_ADDRA_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_A;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_B;
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH_ACTUAL-1 DOWNTO 0) := (OTHERS => '0');
--**************************************************************************
BEGIN
RDADDRECC(C_ADDRB_WIDTH-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_MSB) <= (OTHERS => '0');
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB) <= rdaddrecc_i;
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_LSB-1 DOWNTO 0) <= (OTHERS => '0');
mem_map_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH_ACTUAL,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH_ACTUAL,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,
ENA => ENA_I_SAFE,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in(C_MEM_MAP_ADDRA_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRA_WIDTH_LSB),
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB),
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => rdaddrecc_i
);
END GENERATE native_mem_map_module;
--****************************************************************************
-- AXI MEMORY MODULE INSTANCE
--****************************************************************************
axi_mem_module: IF (C_INTERFACE_TYPE = 1) GENERATE
SIGNAL s_axi_rid_c : STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rdata_c : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rresp_c : STD_LOGIC_VECTOR(2-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rlast_c : STD_LOGIC := '0';
SIGNAL s_axi_rvalid_c : STD_LOGIC := '0';
SIGNAL s_axi_rready_c : STD_LOGIC := '0';
SIGNAL regceb_c : STD_LOGIC := '0';
BEGIN
s_aresetn_a_c <= NOT S_ARESETN;
S_AXI_BRESP <= (OTHERS => '0');
s_axi_rresp_c <= (OTHERS => '0');
no_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 0 AND C_HAS_MUX_OUTPUT_REGS_B = 0 ) GENERATE
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RLAST <= s_axi_rlast_c;
S_AXI_RVALID <= s_axi_rvalid_c;
S_AXI_RID <= s_axi_rid_c;
S_AXI_RRESP <= s_axi_rresp_c;
s_axi_rready_c <= S_AXI_RREADY;
END GENERATE no_regs;
has_regs_fwd: IF (C_HAS_MUX_OUTPUT_REGS_B = 1 OR C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
CONSTANT C_AXI_PAYLOAD : INTEGER := if_then_else((C_HAS_MUX_OUTPUT_REGS_B = 1),C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3,C_AXI_ID_WIDTH+3);
SIGNAL s_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
has_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
regceb_c <= s_axi_rvalid_c AND s_axi_rready_c;
END GENERATE has_regceb;
no_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 0) GENERATE
regceb_c <= REGCEB;
END GENERATE no_regceb;
only_core_op_regs: IF (C_HAS_MUX_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rdata_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RDATA <= m_axi_payload_c(C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_core_op_regs;
only_emb_op_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_emb_op_regs;
axi_regs_inst : blk_mem_axi_regs_fwd_v8_3
GENERIC MAP(
C_DATA_WIDTH => C_AXI_PAYLOAD
)
PORT MAP (
ACLK => S_ACLK,
ARESET => s_aresetn_a_c,
S_VALID => s_axi_rvalid_c,
S_READY => s_axi_rready_c,
S_PAYLOAD_DATA => s_axi_payload_c,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY,
M_PAYLOAD_DATA => m_axi_payload_c
);
END GENERATE has_regs_fwd;
axi_wr_fsm : blk_mem_axi_write_wrapper_beh
GENERIC MAP(
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_AXI_AWADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_WDATA_WIDTH => C_WRITE_WIDTH_A,
C_AXI_OS_WR => C_AXI_OS_WR
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Slave Write Interface
S_AXI_AWADDR => S_AXI_AWADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_AWLEN => S_AXI_AWLEN,
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BID => S_AXI_BID,
-- Signals for BRAM interface
S_AXI_AWADDR_OUT =>s_axi_awaddr_out_c,
S_AXI_WR_EN =>s_axi_wr_en_c
);
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => 1, -- For AXI, Read Enable is always C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => 1, -- For AXI C_USE_BYTE_WEA is always 1,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => 1, -- For AXI, Read Enable is always C_HAS_ENB,
C_HAS_REGCEB => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_BYTE_WEB => 1, -- For AXI C_USE_BYTE_WEB is always 1,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => 0, --For AXI, Primitive Registers A is not supported C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => 0,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
--Port A:
CLKA => S_AClk,
RSTA => s_aresetn_a_c,
ENA => s_axi_wr_en_c,
REGCEA => regcea_in,
WEA => S_AXI_WSTRB,
ADDRA => s_axi_awaddr_out_c,
DINA => S_AXI_WDATA,
DOUTA => DOUTA,
--Port B:
CLKB => S_AClk,
RSTB => s_aresetn_a_c,
ENB => s_axi_rd_en_c,
REGCEB => regceb_c,
WEB => (OTHERS => '0'),
ADDRB => s_axi_araddr_out_c,
DINB => DINB,
DOUTB => s_axi_rdata_c,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => '0',
SLEEP => '0',
RDADDRECC => RDADDRECC
);
axi_rd_sm : blk_mem_axi_read_wrapper_beh
GENERIC MAP (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_PIPELINE_STAGES => 1,
C_AXI_ARADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_AClk,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Read Side
S_AXI_ARADDR => S_AXI_ARADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARSIZE => S_AXI_ARSIZE,
S_AXI_ARBURST => S_AXI_ARBURST,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => s_axi_rlast_c,
S_AXI_RVALID => s_axi_rvalid_c,
S_AXI_RREADY => s_axi_rready_c,
S_AXI_ARID => S_AXI_ARID,
S_AXI_RID => s_axi_rid_c,
-- AXI Full/Lite Read FSM Outputs
S_AXI_ARADDR_OUT => s_axi_araddr_out_c,
S_AXI_RD_EN => s_axi_rd_en_c
);
END GENERATE axi_mem_module;
END behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_clr is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_clr;
architecture beh_ff_clr_arch of beh_ff_clr is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(CLR, C)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_clr_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_ce is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_ce;
architecture beh_ff_ce_arch of beh_ff_ce is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, CLR)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
if (CE = '1') then
q_o <= D after 100 ps;
end if;
end if;
end process;
end beh_ff_ce_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_pre is
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end beh_ff_pre;
architecture beh_ff_pre_arch of beh_ff_pre is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, PRE)
begin
if (PRE = '1') then
q_o <= '1';
elsif (C' event and C = '1') then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_pre_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_muxf7 is
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end beh_muxf7;
architecture beh_muxf7_arch of beh_muxf7 is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
else
O <= I1;
end if;
end process;
end beh_muxf7_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity STATE_LOGIC is
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic := '0';
I0 : in std_logic := '0';
I1 : in std_logic := '0';
I2 : in std_logic := '0';
I3 : in std_logic := '0';
I4 : in std_logic := '0';
I5 : in std_logic := '0'
);
end STATE_LOGIC;
architecture STATE_LOGIC_arch of STATE_LOGIC is
constant INIT_reg : std_logic_vector(63 downto 0) := INIT;
begin
LUT_beh:process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
begin
I_reg := I5 & I4 & I3 & I2 & I1 & I0;
O <= INIT_reg(conv_integer(I_reg));
end process;
end STATE_LOGIC_arch;
|
-------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v8_3_1.vhd
--
-- Description:
-- This file is the VHDL behvarial model for the
-- Block Memory Generator Core.
--
-------------------------------------------------------------------------------
-- Author: Xilinx
--
-- History: January 11, 2006: Initial revision
-- June 11, 2007 : Added independent register stages for
-- Port A and Port B (IP1_Jm/v2.5)
-- August 28, 2007 : Added mux pipeline stages feature (IP2_Jm/v2.6)
-- April 07, 2009 : Added support for Spartan-6 and Virtex-6
-- features, including the following:
-- (i) error injection, detection and/or correction
-- (ii) reset priority
-- (iii) special reset behavior
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
ENTITY blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END ENTITY blk_mem_axi_regs_fwd_v8_3;
ARCHITECTURE axi_regs_fwd_arch OF blk_mem_axi_regs_fwd_v8_3 IS
SIGNAL STORAGE_DATA : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_READY_I : STD_LOGIC := '0';
SIGNAL M_VALID_I : STD_LOGIC := '0';
SIGNAL ARESET_D : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');-- Reset delay register
BEGIN
--assign local signal to its output signal
S_READY <= S_READY_I;
M_VALID <= M_VALID_I;
PROCESS(ACLK)
BEGIN
IF(ACLK'event AND ACLK = '1') THEN
ARESET_D <= ARESET_D(0) & ARESET;
END IF;
END PROCESS;
--Save payload data whenever we have a transaction on the slave side
PROCESS(ACLK, ARESET)
BEGIN
IF (ARESET = '1') THEN
STORAGE_DATA <= (OTHERS => '0');
ELSIF(ACLK'event AND ACLK = '1') THEN
IF(S_VALID = '1' AND S_READY_I = '1') THEN
STORAGE_DATA <= S_PAYLOAD_DATA;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= STORAGE_DATA;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
PROCESS(ACLK,ARESET)
BEGIN
IF (ARESET_D /= "00") THEN
M_VALID_I <= '0';
ELSIF(ACLK'event AND ACLK = '1') THEN
IF (S_VALID = '1') THEN
--Always set M_VALID_I when slave side is valid
M_VALID_I <= '1';
ELSIF (M_READY = '1') THEN
--Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= '0';
END IF;
END IF;
END PROCESS;
--Slave Ready is either when Master side drives M_READY or we have space in our storage data
S_READY_I <= (M_READY OR (NOT M_VALID_I)) AND NOT(OR_REDUCE(ARESET_D));
END axi_regs_fwd_arch;
-------------------------------------------------------------------------------
-- Description:
-- This is the behavioral model of write_wrapper for the
-- Block Memory Generator Core.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_axi_write_wrapper_beh IS
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END blk_mem_axi_write_wrapper_beh;
ARCHITECTURE axi_write_wrap_arch OF blk_mem_axi_write_wrapper_beh IS
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_AXI_WDATA_WIDTH=8,0,
if_then_else((C_AXI_WDATA_WIDTH=16),1,
if_then_else((C_AXI_WDATA_WIDTH=32),2,
if_then_else((C_AXI_WDATA_WIDTH=64),3,
if_then_else((C_AXI_WDATA_WIDTH=128),4,
if_then_else((C_AXI_WDATA_WIDTH=256),5,0))))));
SIGNAL bvalid_c : std_logic := '0';
SIGNAL bready_timeout_c : std_logic := '0';
SIGNAL bvalid_rd_cnt_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_r : std_logic := '0';
SIGNAL bvalid_count_r : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL awaddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
C_AXI_AWADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL bvalid_wr_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_rd_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_last_c : std_logic := '0';
SIGNAL addr_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL aw_ready_r : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL awlen_cntr_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1');
SIGNAL awlen_int : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL awburst_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes : integer := 0;
SIGNAL wrap_boundary : integer := 0;
SIGNAL wrap_base_addr : integer := 0;
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
-- Array to store BIDs
TYPE id_array IS ARRAY (3 DOWNTO 0) OF std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
SIGNAL axi_bid_array : id_array := (others => (others => '0'));
COMPONENT write_netlist
GENERIC(
C_AXI_TYPE : integer
);
PORT(
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
S_AXI_AWVALID : IN std_logic;
aw_ready_r : OUT std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN std_logic;
S_AXI_WR_EN : OUT std_logic;
w_last_c : IN std_logic;
bready_timeout_c : IN std_logic;
addr_en_c : OUT std_logic;
incr_addr_c : OUT std_logic;
bvalid_c : OUT std_logic
);
END COMPONENT write_netlist;
BEGIN
---------------------------------------
--AXI WRITE FSM COMPONENT INSTANTIATION
---------------------------------------
axi_wr_fsm : write_netlist
GENERIC MAP (
C_AXI_TYPE => C_AXI_TYPE
)
PORT MAP (
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
S_AXI_AWVALID => S_AXI_AWVALID,
aw_ready_r => aw_ready_r,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BVALID => OPEN,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_WR_EN => S_AXI_WR_EN,
w_last_c => w_last_c,
bready_timeout_c => bready_timeout_c,
addr_en_c => addr_en_c,
incr_addr_c => incr_addr_c,
bvalid_c => bvalid_c
);
--Wrap Address boundary calculation
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWSIZE,"000"));
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(awlen_int)+1);
wrap_base_addr <= (conv_integer(awaddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary <= wrap_base_addr+total_bytes;
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awaddr_reg <= (OTHERS => '0');
num_of_bytes_r <= 0;
awburst_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awaddr_reg <= S_AXI_AWADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWBURST,"01");
ELSIF (incr_addr_c = '1') THEN
IF (awburst_int = "10") THEN
IF(conv_integer(awaddr_reg) = (wrap_boundary-num_of_bytes_r)) THEN
awaddr_reg <= conv_std_logic_vector(wrap_base_addr,C_AXI_AWADDR_WIDTH);
ELSE
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
ELSIF (awburst_int = "01" OR awburst_int = "11") THEN
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
S_AXI_AWADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
awaddr_reg(C_AXI_AWADDR_WIDTH-1 DOWNTO C_RANGE),awaddr_reg);
---------------------------------------------------------------------------
-- AXI wlast generation
---------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awlen_cntr_r <= (OTHERS => '1');
awlen_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awlen_int <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
awlen_cntr_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
ELSIF (dec_alen_c = '1') THEN
awlen_cntr_r <= awlen_cntr_r - ONE AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
w_last_c <= '1' WHEN (awlen_cntr_r = "00000000" AND S_AXI_WVALID = '1') ELSE '0';
dec_alen_c <= (incr_addr_c OR w_last_c);
---------------------------------------------------------------------------
-- Generation of bvalid counter for outstanding transactions
---------------------------------------------------------------------------
P_b_valid_os_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_count_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- bvalid_count_r generation
IF (bvalid_c = '1' AND bvalid_r = '1' AND S_AXI_BREADY = '1') THEN
bvalid_count_r <= bvalid_count_r AFTER FLOP_DELAY;
ELSIF (bvalid_c = '1') THEN
bvalid_count_r <= bvalid_count_r + "01" AFTER FLOP_DELAY;
ELSIF (bvalid_r = '1' AND S_AXI_BREADY = '1' AND bvalid_count_r /= "0") THEN
bvalid_count_r <= bvalid_count_r - "01" AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_os_r ;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is used
---------------------------------------------------------------------------
gaxi_bvalid_id_r:IF (C_HAS_AXI_ID = 1) GENERATE
SIGNAL bvalid_d1_c : std_logic := '0';
BEGIN
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
bvalid_d1_c <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
--external bvalid signal generation
IF (bvalid_d1_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_id_r;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is not used
---------------------------------------------------------------------------
gaxi_bvalid_noid_r:IF (C_HAS_AXI_ID = 0) GENERATE
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
--external bvalid signal generation
IF (bvalid_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_noid_r;
---------------------------------------------------------------------------
-- Generation of Bready timeout
---------------------------------------------------------------------------
P_brdy_tout_c: PROCESS (bvalid_count_r)
BEGIN
-- bready_timeout_c generation
IF(conv_integer(bvalid_count_r) = C_AXI_OS_WR-1) THEN
bready_timeout_c <= '1';
ELSE
bready_timeout_c <= '0';
END IF;
END PROCESS P_brdy_tout_c;
---------------------------------------------------------------------------
-- Generation of BID
---------------------------------------------------------------------------
gaxi_bid_gen:IF (C_HAS_AXI_ID = 1) GENERATE
P_bid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
bvalid_wr_cnt_r <= (OTHERS => '0');
bvalid_rd_cnt_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- STORE AWID IN AN ARRAY
IF(bvalid_c = '1') THEN
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + "01";
END IF;
-- GENERATE BID FROM AWID ARRAY
bvalid_rd_cnt_r <= bvalid_rd_cnt_c AFTER FLOP_DELAY;
S_AXI_BID <= axi_bid_array(conv_integer(bvalid_rd_cnt_c));
END IF;
END PROCESS P_bid_gen;
bvalid_rd_cnt_c <= bvalid_rd_cnt_r + "01" WHEN (bvalid_r = '1' AND S_AXI_BREADY = '1') ELSE bvalid_rd_cnt_r;
---------------------------------------------------------------------------
-- Storing AWID for generation of BID
---------------------------------------------------------------------------
P_awid_reg:PROCESS (S_ACLK)
BEGIN
IF (S_ACLK'event AND S_ACLK='1') THEN
IF(aw_ready_r = '1' AND S_AXI_AWVALID = '1') THEN
axi_bid_array(conv_integer(bvalid_wr_cnt_r)) <= S_AXI_AWID;
END IF;
END IF;
END PROCESS P_awid_reg;
END GENERATE gaxi_bid_gen;
S_AXI_BVALID <= bvalid_r;
S_AXI_AWREADY <= aw_ready_r;
END axi_write_wrap_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity write_netlist is
GENERIC(
C_AXI_TYPE : integer
);
port (
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_AWVALID : in STD_LOGIC := '0';
S_AXI_WVALID : in STD_LOGIC := '0';
S_AXI_BREADY : in STD_LOGIC := '0';
w_last_c : in STD_LOGIC := '0';
bready_timeout_c : in STD_LOGIC := '0';
aw_ready_r : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_WR_EN : out STD_LOGIC;
addr_en_c : out STD_LOGIC;
incr_addr_c : out STD_LOGIC;
bvalid_c : out STD_LOGIC
);
end write_netlist;
architecture STRUCTURE of write_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
BEGIN
---------------------------------------------------------------------------
-- AXI LITE
---------------------------------------------------------------------------
gbeh_axi_lite_sm: IF (C_AXI_TYPE = 0 ) GENERATE
signal w_ready_r_7 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSignal_bvalid_c : STD_LOGIC;
signal NlwRenamedSignal_incr_addr_c : STD_LOGIC;
signal present_state_FSM_FFd3_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal present_state_FSM_FFd1_15 : STD_LOGIC;
signal present_state_FSM_FFd4_16 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd4_In1_21 : STD_LOGIC;
signal Mmux_aw_ready_c : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
S_AXI_WREADY <= w_ready_r_7;
S_AXI_BVALID <= NlwRenamedSignal_incr_addr_c;
S_AXI_WR_EN <= NlwRenamedSignal_bvalid_c;
incr_addr_c <= NlwRenamedSignal_incr_addr_c;
bvalid_c <= NlwRenamedSignal_bvalid_c;
NlwRenamedSignal_incr_addr_c <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_7
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_16
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_13
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_15
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000055554440"
)
port map (
I0 => S_AXI_WVALID,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => '0',
O => present_state_FSM_FFd3_In
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"0000000088880800"
)
port map (
I0 => S_AXI_AWVALID,
I1 => S_AXI_WVALID,
I2 => bready_timeout_c,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => present_state_FSM_FFd2_In
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAA2000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_WVALID,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => addr_en_c
);
Mmux_w_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"F5F07570F5F05500"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => w_ready_c
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd3_13,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd1_15,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_14,
I2 => present_state_FSM_FFd3_13,
I3 => '0',
I4 => '0',
I5 => '0',
O => NlwRenamedSignal_bvalid_c
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"2F0F27072F0F2200"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => present_state_FSM_FFd4_In1_21
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_In1_21,
I3 => '0',
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_aw_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"7535753575305500"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => S_AXI_WVALID,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => present_state_FSM_FFd2_14,
O => Mmux_aw_ready_c(0)
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => Mmux_aw_ready_c(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => aw_ready_c
);
END GENERATE gbeh_axi_lite_sm;
---------------------------------------------------------------------------
-- AXI FULL
---------------------------------------------------------------------------
gbeh_axi_full_sm: IF (C_AXI_TYPE = 1 ) GENERATE
signal w_ready_r_8 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSig_OI_bvalid_c : STD_LOGIC;
signal present_state_FSM_FFd1_16 : STD_LOGIC;
signal present_state_FSM_FFd4_17 : STD_LOGIC;
signal present_state_FSM_FFd3_18 : STD_LOGIC;
signal present_state_FSM_FFd2_19 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd2_In1_24 : STD_LOGIC;
signal present_state_FSM_FFd4_In1_25 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal N4 : STD_LOGIC;
begin
S_AXI_WREADY <= w_ready_r_8;
bvalid_c <= NlwRenamedSig_OI_bvalid_c;
S_AXI_BVALID <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_8
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_17
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_18
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_19
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_16
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000000005540"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd4_17,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd3_In
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"BF3FBB33AF0FAA00"
)
port map (
I0 => S_AXI_BREADY,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd1_16,
I4 => present_state_FSM_FFd4_17,
I5 => NlwRenamedSig_OI_bvalid_c,
O => aw_ready_c
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"AAAAAAAA20000000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_19,
I3 => S_AXI_WVALID,
I4 => w_last_c,
I5 => present_state_FSM_FFd4_17,
O => addr_en_c
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_19,
I2 => present_state_FSM_FFd3_18,
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_WR_EN
);
Mmux_incr_addr_c_0_1 : STATE_LOGIC
generic map(
INIT => X"0000000000002220"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => incr_addr_c
);
Mmux_aw_ready_c_0_11 : STATE_LOGIC
generic map(
INIT => X"0000000000008880"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => NlwRenamedSig_OI_bvalid_c
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"000000000000D5C0"
)
port map (
I0 => w_last_c,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd4_17,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd2_In1_24
);
present_state_FSM_FFd2_In2 : STATE_LOGIC
generic map(
INIT => X"FFFFAAAA08AAAAAA"
)
port map (
I0 => present_state_FSM_FFd2_19,
I1 => S_AXI_AWVALID,
I2 => bready_timeout_c,
I3 => w_last_c,
I4 => S_AXI_WVALID,
I5 => present_state_FSM_FFd2_In1_24,
O => present_state_FSM_FFd2_In
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"00C0004000C00000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => w_last_c,
I2 => S_AXI_WVALID,
I3 => bready_timeout_c,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => present_state_FSM_FFd4_In1_25
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88F8"
)
port map (
I0 => present_state_FSM_FFd1_16,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_17,
I3 => S_AXI_AWVALID,
I4 => present_state_FSM_FFd4_In1_25,
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_w_ready_c_0_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => w_last_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_w_ready_c_0_Q : STATE_LOGIC
generic map(
INIT => X"FABAFABAFAAAF000"
)
port map (
I0 => N2,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd4_17,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => w_ready_c
);
Mmux_aw_ready_c_0_11_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => bready_timeout_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => w_last_c,
I1 => N4,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => present_state_FSM_FFd1_16,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
END GENERATE gbeh_axi_full_sm;
end STRUCTURE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--AXI Behavioral Model entities
ENTITY blk_mem_axi_read_wrapper_beh is
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
port (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END blk_mem_axi_read_wrapper_beh;
architecture blk_mem_axi_read_wrapper_beh_arch of blk_mem_axi_read_wrapper_beh is
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_WRITE_WIDTH_A=8,0,
if_then_else((C_WRITE_WIDTH_A=16),1,
if_then_else((C_WRITE_WIDTH_A=32),2,
if_then_else((C_WRITE_WIDTH_A=64),3,
if_then_else((C_WRITE_WIDTH_A=128),4,
if_then_else((C_WRITE_WIDTH_A=256),5,0))))));
SIGNAL ar_id_r : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
SIGNAL addr_en_c : std_logic := '0';
SIGNAL rd_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL single_trans_c : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL mux_sel_c : std_logic := '0';
SIGNAL r_last_c : std_logic := '0';
SIGNAL r_last_int_c : std_logic := '0';
SIGNAL arlen_int_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL arlen_cntr : std_logic_vector(7 DOWNTO 0) := ONE;
SIGNAL arburst_int_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL arburst_int_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL araddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),C_AXI_ARADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL total_bytes : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
SIGNAL wrap_base_addr_r : integer := 0;
SIGNAL wrap_boundary_r : integer := 0;
SIGNAL arlen_int_c : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes_c : integer := 0;
SIGNAL wrap_base_addr_c : integer := 0;
SIGNAL wrap_boundary_c : integer := 0;
SIGNAL araddr_out : std_logic_vector(C_ADDRB_WIDTH-1 downto 0) := (OTHERS => '0');
COMPONENT read_netlist
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_INCR_ADDR : OUT std_logic := '0';
S_AXI_ADDR_EN : OUT std_logic := '0';
S_AXI_SINGLE_TRANS : OUT std_logic := '0';
S_AXI_MUX_SEL : OUT std_logic := '0';
S_AXI_R_LAST : OUT std_logic := '0';
S_AXI_R_LAST_INT : IN std_logic := '0';
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT read_netlist;
BEGIN
dec_alen_c <= incr_addr_c OR r_last_int_c;
axi_read_fsm : read_netlist
GENERIC MAP(
C_AXI_TYPE => 1,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
S_AXI_INCR_ADDR => incr_addr_c,
S_AXI_ADDR_EN => addr_en_c,
S_AXI_SINGLE_TRANS => single_trans_c,
S_AXI_MUX_SEL => mux_sel_c,
S_AXI_R_LAST => r_last_c,
S_AXI_R_LAST_INT => r_last_int_c,
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN => rd_en_c
);
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(arlen_int_r)+1);
wrap_base_addr_r <= (conv_integer(araddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary_r <= wrap_base_addr_r+total_bytes;
---- combinatorial from interface
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARSIZE,"000"));
arlen_int_c <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
total_bytes_c <= conv_integer(num_of_bytes_c)*(conv_integer(arlen_int_c)+1);
wrap_base_addr_c <= (conv_integer(S_AXI_ARADDR)/if_then_else(total_bytes_c=0,1,total_bytes_c))*(total_bytes_c);
wrap_boundary_c <= wrap_base_addr_c+total_bytes_c;
arburst_int_c <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARBURST,"01");
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
araddr_reg <= (OTHERS => '0');
arburst_int_r <= (OTHERS => '0');
num_of_bytes_r <= 0;
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (incr_addr_c = '1' AND addr_en_c = '1' AND single_trans_c = '0') THEN
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
IF (arburst_int_c = "10") THEN
IF(conv_integer(S_AXI_ARADDR) = (wrap_boundary_c-num_of_bytes_c)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_c,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (arburst_int_c = "01" OR arburst_int_c = "11") THEN
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (addr_en_c = '1') THEN
araddr_reg <= S_AXI_ARADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
ELSIF (incr_addr_c = '1') THEN
IF (arburst_int_r = "10") THEN
IF(conv_integer(araddr_reg) = (wrap_boundary_r-num_of_bytes_r)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_r,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
ELSIF (arburst_int_r = "01" OR arburst_int_r = "11") THEN
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
araddr_out <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),araddr_reg(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),araddr_reg);
--------------------------------------------------------------------------
-- Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
--------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF S_ARESETN = '1' THEN
arlen_cntr <= ONE;
arlen_int_r <= (OTHERS => '0');
ELSIF S_ACLK'event AND S_ACLK = '1' THEN
IF (addr_en_c = '1' AND dec_alen_c = '1' AND single_trans_c = '0') THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= S_AXI_ARLEN - ONE AFTER FLOP_DELAY;
ELSIF addr_en_c = '1' THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
ELSIF dec_alen_c = '1' THEN
arlen_cntr <= arlen_cntr - ONE AFTER FLOP_DELAY;
ELSE
arlen_cntr <= arlen_cntr AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
r_last_int_c <= '1' WHEN (arlen_cntr = "00000000" AND S_AXI_RREADY = '1') ELSE '0' ;
--------------------------------------------------------------------------
-- AXI FULL FSM
-- Mux Selection of ARADDR
-- ARADDR is driven out from the read fsm based on the mux_sel_c
-- Based on mux_sel either ARADDR is given out or the latched ARADDR is
-- given out to BRAM
--------------------------------------------------------------------------
P_araddr_mux: PROCESS (mux_sel_c,S_AXI_ARADDR,araddr_out)
BEGIN
IF (mux_sel_c = '0') THEN
S_AXI_ARADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARADDR(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),S_AXI_ARADDR);
ELSE
S_AXI_ARADDR_OUT <= araddr_out;
END IF;
END PROCESS P_araddr_mux;
--------------------------------------------------------------------------
-- Assign output signals - AXI FULL FSM
--------------------------------------------------------------------------
S_AXI_RD_EN <= rd_en_c;
grid: IF (C_HAS_AXI_ID = 1) GENERATE
P_rid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
S_AXI_RID <= (OTHERS => '0');
ar_id_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
IF (addr_en_c = '1' AND rd_en_c = '1') THEN
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
ELSIF (addr_en_c = '1' AND rd_en_c = '0') THEN
ar_id_r <= S_AXI_ARID;
ELSIF (rd_en_c = '1') THEN
S_AXI_RID <= ar_id_r;
END IF;
END IF;
END PROCESS P_rid_gen;
END GENERATE grid;
END blk_mem_axi_read_wrapper_beh_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity read_netlist is
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_R_LAST_INT : in STD_LOGIC := '0';
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_ARVALID : in STD_LOGIC := '0';
S_AXI_RREADY : in STD_LOGIC := '0';
S_AXI_INCR_ADDR : out STD_LOGIC;
S_AXI_ADDR_EN : out STD_LOGIC;
S_AXI_SINGLE_TRANS : out STD_LOGIC;
S_AXI_MUX_SEL : out STD_LOGIC;
S_AXI_R_LAST : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RLAST : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RD_EN : out STD_LOGIC;
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end read_netlist;
architecture STRUCTURE of read_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
signal present_state_FSM_FFd1_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_r_15 : STD_LOGIC;
signal gaxi_full_sm_ar_ready_r_16 : STD_LOGIC;
signal gaxi_full_sm_r_last_r_17 : STD_LOGIC;
signal NlwRenamedSig_OI_gaxi_full_sm_r_valid_r : STD_LOGIC;
signal gaxi_full_sm_r_valid_c : STD_LOGIC;
signal S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o : STD_LOGIC;
signal gaxi_full_sm_ar_ready_c : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_c : STD_LOGIC;
signal NlwRenamedSig_OI_S_AXI_R_LAST : STD_LOGIC;
signal S_AXI_ARLEN_7_GND_8_o_equal_1_o : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal Mmux_S_AXI_R_LAST13 : STD_LOGIC;
signal N01 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal Mmux_gaxi_full_sm_ar_ready_c11 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N8 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N13 : STD_LOGIC;
begin
S_AXI_R_LAST <= NlwRenamedSig_OI_S_AXI_R_LAST;
S_AXI_ARREADY <= gaxi_full_sm_ar_ready_r_16;
S_AXI_RLAST <= gaxi_full_sm_r_last_r_17;
S_AXI_RVALID <= NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
gaxi_full_sm_outstanding_read_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_outstanding_read_c,
Q => gaxi_full_sm_outstanding_read_r_15
);
gaxi_full_sm_r_valid_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => gaxi_full_sm_r_valid_c,
Q => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r
);
gaxi_full_sm_ar_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_ar_ready_c,
Q => gaxi_full_sm_ar_ready_r_16
);
gaxi_full_sm_r_last_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => NlwRenamedSig_OI_S_AXI_R_LAST,
Q => gaxi_full_sm_r_last_r_17
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_13
);
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 : STATE_LOGIC
generic map(
INIT => X"000000000000000B"
)
port map (
I0 => S_AXI_RREADY,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o
);
Mmux_S_AXI_SINGLE_TRANS11 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_SINGLE_TRANS
);
Mmux_S_AXI_ADDR_EN11 : STATE_LOGIC
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_ADDR_EN
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"ECEE2022EEEE2022"
)
port map (
I0 => S_AXI_ARVALID,
I1 => present_state_FSM_FFd1_13,
I2 => S_AXI_RREADY,
I3 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I4 => present_state_FSM_FFd2_14,
I5 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
O => present_state_FSM_FFd2_In
);
Mmux_S_AXI_R_LAST131 : STATE_LOGIC
generic map(
INIT => X"0000000044440444"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_RREADY,
I5 => '0',
O => Mmux_S_AXI_R_LAST13
);
Mmux_S_AXI_INCR_ADDR11 : STATE_LOGIC
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => S_AXI_R_LAST_INT,
I1 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => Mmux_S_AXI_R_LAST13,
O => S_AXI_INCR_ADDR
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000FE"
)
port map (
I0 => S_AXI_ARLEN(2),
I1 => S_AXI_ARLEN(1),
I2 => S_AXI_ARLEN(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => N01
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q : STATE_LOGIC
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => S_AXI_ARLEN(7),
I1 => S_AXI_ARLEN(6),
I2 => S_AXI_ARLEN(5),
I3 => S_AXI_ARLEN(4),
I4 => S_AXI_ARLEN(3),
I5 => N01,
O => S_AXI_ARLEN_7_GND_8_o_equal_1_o
);
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_gaxi_full_sm_outstanding_read_c1 : STATE_LOGIC
generic map(
INIT => X"0020000002200200"
)
port map (
I0 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd1_13,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => N2,
O => gaxi_full_sm_outstanding_read_c
);
Mmux_gaxi_full_sm_ar_ready_c12 : STATE_LOGIC
generic map(
INIT => X"0000000000004555"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => '0',
I5 => '0',
O => Mmux_gaxi_full_sm_ar_ready_c11
);
Mmux_S_AXI_R_LAST11_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000EF"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
Mmux_S_AXI_R_LAST11 : STATE_LOGIC
generic map(
INIT => X"FCAAFC0A00AA000A"
)
port map (
I0 => S_AXI_ARVALID,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => N4,
I5 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
O => gaxi_full_sm_r_valid_c
);
S_AXI_MUX_SEL1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAAAA08"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => '0',
O => S_AXI_MUX_SEL
);
Mmux_S_AXI_RD_EN11 : STATE_LOGIC
generic map(
INIT => X"F3F3F755A2A2A200"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => gaxi_full_sm_outstanding_read_r_15,
I4 => present_state_FSM_FFd2_14,
I5 => S_AXI_ARVALID,
O => S_AXI_RD_EN
);
present_state_FSM_FFd1_In3 : beh_muxf7
port map (
I0 => N8,
I1 => N9,
S => present_state_FSM_FFd1_13,
O => present_state_FSM_FFd1_In
);
present_state_FSM_FFd1_In3_F : STATE_LOGIC
generic map(
INIT => X"000000005410F4F0"
)
port map (
I0 => S_AXI_RREADY,
I1 => present_state_FSM_FFd2_14,
I2 => S_AXI_ARVALID,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => '0',
O => N8
);
present_state_FSM_FFd1_In3_G : STATE_LOGIC
generic map(
INIT => X"0000000072FF7272"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N9
);
Mmux_gaxi_full_sm_ar_ready_c14 : beh_muxf7
port map (
I0 => N10,
I1 => N11,
S => present_state_FSM_FFd1_13,
O => gaxi_full_sm_ar_ready_c
);
Mmux_gaxi_full_sm_ar_ready_c14_F : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88A8"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => Mmux_gaxi_full_sm_ar_ready_c11,
I5 => '0',
O => N10
);
Mmux_gaxi_full_sm_ar_ready_c14_G : STATE_LOGIC
generic map(
INIT => X"000000008D008D8D"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N11
);
Mmux_S_AXI_R_LAST1 : beh_muxf7
port map (
I0 => N12,
I1 => N13,
S => present_state_FSM_FFd1_13,
O => NlwRenamedSig_OI_S_AXI_R_LAST
);
Mmux_S_AXI_R_LAST1_F : STATE_LOGIC
generic map(
INIT => X"0000000088088888"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N12
);
Mmux_S_AXI_R_LAST1_G : STATE_LOGIC
generic map(
INIT => X"00000000E400E4E4"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => S_AXI_R_LAST_INT,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N13
);
end STRUCTURE;
-------------------------------------------------------------------------------
-- Output Register Stage Entity
--
-- This module builds the output register stages of the memory. This module is
-- instantiated in the main memory module (blk_mem_gen_v8_3_1) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_output_stage IS
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_output_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6" and "virtex6l".
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
-- C_HAS_RST : Determines the presence of the RST port
-- C_RSTRAM : Determines if special reset behavior is used
-- C_RST_PRIORITY : Determines the priority between CE and SR
-- C_INIT_VAL : Initialization value
-- C_HAS_EN : Determines the presence of the EN port
-- C_HAS_REGCE : Determines the presence of the REGCE port
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
-- of the RAM primitive
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- NUM_STAGES : Determines the number of output stages
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE output_stage_behavioral OF blk_mem_gen_v8_3_1_output_stage IS
--*******************************************************
-- Functions used in the output stage ARCHITECTURE
--*******************************************************
-- Calculate num_reg_stages
FUNCTION get_num_reg_stages(NUM_STAGES: INTEGER) RETURN INTEGER IS
VARIABLE num_reg_stages : INTEGER := 0;
BEGIN
IF (NUM_STAGES = 0) THEN
num_reg_stages := 0;
ELSE
num_reg_stages := NUM_STAGES - 1;
END IF;
RETURN num_reg_stages;
END get_num_reg_stages;
-- Check if the INTEGER is zero or non-zero
FUNCTION int_to_bit(input: INTEGER) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = 0) THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END int_to_bit;
-- Constants
CONSTANT HAS_EN : STD_LOGIC := int_to_bit(C_HAS_EN);
CONSTANT HAS_REGCE : STD_LOGIC := int_to_bit(C_HAS_REGCE);
CONSTANT HAS_RST : STD_LOGIC := int_to_bit(C_HAS_RST);
CONSTANT REG_STAGES : INTEGER := get_num_reg_stages(NUM_STAGES);
-- Pipeline array
TYPE reg_data_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
TYPE reg_ecc_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC;
TYPE reg_eccaddr_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
CONSTANT REG_INIT : reg_data_array := (OTHERS => init_val);
SIGNAL out_regs : reg_data_array := REG_INIT;
SIGNAL sbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL dbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL rdaddrecc_regs: reg_eccaddr_array := (OTHERS => (OTHERS => '0'));
-- Internal signals
SIGNAL en_i : STD_LOGIC;
SIGNAL regce_i : STD_LOGIC;
SIGNAL rst_i : STD_LOGIC;
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := init_val;
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL DIN : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL RDADDRECC_IN : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ;
SIGNAL SBITERR_IN : STD_LOGIC := '0';
SIGNAL DBITERR_IN : STD_LOGIC := '0';
BEGIN
--***********************************************************************
-- Assign internal signals. This effectively wires off optional inputs.
--***********************************************************************
-- Internal enable for output registers is tied to user EN or '1' depending
-- on parameters
en_i <= EN OR (NOT HAS_EN);
-- Internal register enable for output registers is tied to user REGCE, EN
-- or '1' depending on parameters
regce_i <= (HAS_REGCE AND REGCE)
OR ((NOT HAS_REGCE) AND en_i);
-- Internal SRR is tied to user RST or '0' depending on parameters
rst_i <= RST AND HAS_RST;
--***************************************************************************
-- NUM_STAGES = 0 (No output registers. RAM only)
--***************************************************************************
zero_stages: IF (NUM_STAGES = 0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE zero_stages;
NO_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 0) GENERATE
DIN <= DIN_I;
RDADDRECC_IN <= RDADDRECC_IN_I;
SBITERR_IN <= SBITERR_IN_I;
DBITERR_IN <= DBITERR_IN_I;
END GENERATE NO_ECC_PIPE_REG;
WITH_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(ECCPIPECE = '1') THEN
DIN <= DIN_I AFTER FLOP_DELAY;
RDADDRECC_IN <= RDADDRECC_IN_I AFTER FLOP_DELAY;
SBITERR_IN <= SBITERR_IN_I AFTER FLOP_DELAY;
DBITERR_IN <= DBITERR_IN_I AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS;
END GENERATE WITH_ECC_PIPE_REG;
--***************************************************************************
-- NUM_STAGES = 1
-- (Mem Output Reg only or Mux Output Reg only)
--***************************************************************************
-- Possible valid combinations:
-- Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
-- +-----------------------------------------+
-- | C_RSTRAM_* | Reset Behavior |
-- +----------------+------------------------+
-- | 0 | Normal Behavior |
-- +----------------+------------------------+
-- | 1 | Special Behavior |
-- +----------------+------------------------+
--
-- Normal = REGCE gates reset, as in the case of all Virtex families and all
-- spartan families with the exception of S3ADSP and S6.
-- Special = EN gates reset, as in the case of S3ADSP and S6.
one_stage_norm: IF (NUM_STAGES = 1 AND
(C_RSTRAM=0 OR (C_RSTRAM=1 AND (C_XDEVICEFAMILY/="spartan3adsp" AND C_XDEVICEFAMILY/="aspartan3adsp")) OR
C_HAS_MEM_OUTPUT_REGS=0 OR C_HAS_RST=0)) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i = '1' AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
END IF;--CLK
END PROCESS;
END GENERATE one_stage_norm;
-- Special Reset Behavior for S6 and S3ADSP
one_stage_splbhv: IF (NUM_STAGES=1 AND C_RSTRAM=1 AND (C_XDEVICEFAMILY ="spartan3adsp" OR C_XDEVICEFAMILY ="aspartan3adsp"))
GENERATE
DOUT <= dout_i;
SBITERR <= '0';
DBITERR <= '0';
RDADDRECC <= (OTHERS => '0');
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (rst_i='1' AND en_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
ELSIF (regce_i='1' AND rst_i/='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE one_stage_splbhv;
--****************************************************************************
-- NUM_STAGES > 1
-- Mem Output Reg + Mux Output Reg
-- or
-- Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
-- or
-- Mux Pipeline Stages (>0) + Mux Output Reg
--****************************************************************************
multi_stage: IF (NUM_STAGES > 1) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i='1'AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
IF (en_i='1') THEN
-- Shift the data through the output stages
FOR i IN 1 TO REG_STAGES-1 LOOP
out_regs(i) <= out_regs(i-1) AFTER FLOP_DELAY;
sbiterr_regs(i) <= sbiterr_regs(i-1) AFTER FLOP_DELAY;
dbiterr_regs(i) <= dbiterr_regs(i-1) AFTER FLOP_DELAY;
rdaddrecc_regs(i) <= rdaddrecc_regs(i-1) AFTER FLOP_DELAY;
END LOOP;
out_regs(0) <= DIN;
sbiterr_regs(0) <= SBITERR_IN;
dbiterr_regs(0) <= DBITERR_IN;
rdaddrecc_regs(0) <= RDADDRECC_IN;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE multi_stage;
END output_stage_behavioral;
-------------------------------------------------------------------------------
-- SoftECC Output Register Stage Entity
-- This module builds the softecc output register stages. This module is
-- instantiated in the memory module (blk_mem_gen_v8_3_1_mem_module) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ;
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- of the RAM primitive
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE softecc_output_reg_stage_behavioral OF blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
-- Internal signals
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
--***************************************************************************
-- NO OUTPUT STAGES
--***************************************************************************
no_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE no_output_stage;
--****************************************************************************
-- WITH OUTPUT STAGE
--****************************************************************************
has_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END PROCESS;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
END GENERATE has_output_stage;
END softecc_output_reg_stage_behavioral;
--******************************************************************************
-- Main Memory module
--
-- This module is the behavioral model which implements the RAM
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
ENTITY blk_mem_gen_v8_3_1_mem_module IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_mem_module;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE mem_module_behavioral OF blk_mem_gen_v8_3_1_mem_module IS
--****************************************
-- min/max constant functions
--****************************************
-- get_max
----------
function SLV_TO_INT(SLV: in std_logic_vector
) return integer is
variable int : integer;
begin
int := 0;
for i in SLV'high downto SLV'low loop
int := int * 2;
if SLV(i) = '1' then
int := int + 1;
end if;
end loop;
return int;
end;
FUNCTION get_max(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a > b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-- get_min
----------
FUNCTION get_min(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
--***************************************************************
-- convert write_mode from STRING type for use in case statement
--***************************************************************
FUNCTION write_mode_to_vector(mode: STRING) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF (mode = "NO_CHANGE") THEN
RETURN "10";
ELSIF (mode = "READ_FIRST") THEN
RETURN "01";
ELSE
RETURN "00"; -- WRITE_FIRST
END IF;
END FUNCTION;
--***************************************************************
-- convert hex STRING to STD_LOGIC_VECTOR
--***************************************************************
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
--***************************************************************
-- locally derived constants to determine memory shape
--***************************************************************
CONSTANT MIN_WIDTH_A : INTEGER := get_min(C_WRITE_WIDTH_A, C_READ_WIDTH_A);
CONSTANT MIN_WIDTH_B : INTEGER := get_min(C_WRITE_WIDTH_B,C_READ_WIDTH_B);
CONSTANT MIN_WIDTH : INTEGER := get_min(MIN_WIDTH_A, MIN_WIDTH_B);
CONSTANT MAX_DEPTH_A : INTEGER := get_max(C_WRITE_DEPTH_A, C_READ_DEPTH_A);
CONSTANT MAX_DEPTH_B : INTEGER := get_max(C_WRITE_DEPTH_B, C_READ_DEPTH_B);
CONSTANT MAX_DEPTH : INTEGER := get_max(MAX_DEPTH_A, MAX_DEPTH_B);
TYPE int_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF std_logic_vector(C_WRITE_WIDTH_A-1 DOWNTO 0);
TYPE mem_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC_VECTOR(MIN_WIDTH-1 DOWNTO 0);
TYPE ecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
TYPE softecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
--***************************************************************
-- memory initialization function
--***************************************************************
IMPURE FUNCTION init_memory(DEFAULT_DATA :
STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
write_width_a : INTEGER;
depth : INTEGER;
width : INTEGER)
RETURN mem_array IS
VARIABLE init_return : mem_array := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(write_width_a-1 DOWNTO 0);
VARIABLE int_mem_vector : int_array:= (OTHERS => (OTHERS => '0'));
VARIABLE file_buffer : LINE;
VARIABLE i : INTEGER := 0;
VARIABLE j : INTEGER;
VARIABLE k : INTEGER;
VARIABLE ignore_line : BOOLEAN := false;
VARIABLE good_data : BOOLEAN := false;
VARIABLE char_tmp : CHARACTER;
VARIABLE index : INTEGER;
variable init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable data : std_logic_vector(255 downto 0) := (others => '0');
variable inside_init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable k_slv : std_logic_vector(31 downto 0) := (others => '0');
variable i_slv : std_logic_vector(31 downto 0) := (others => '0');
VARIABLE disp_line : line := null;
variable open_status : file_open_status;
variable input_initf_tmp : mem_array ;
variable input_initf : mem_array := (others => (others => '0'));
file int_infile : text;
variable data_line, data_line_tmp, out_data_line : line;
variable slv_width : integer;
VARIABLE d_l : LINE;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
index := 0;
FOR i IN 0 TO depth-1 LOOP
FOR j IN 0 TO width-1 LOOP
init_return(i)(j) := DEFAULT_DATA(index);
index := (index + 1) MOD C_WRITE_WIDTH_A;
END LOOP;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, file_buffer);
read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO write_width_a-1 LOOP
IF (j MOD width = 0 AND j /= 0) THEN
i := i + 1;
END IF;
init_return(i)(j MOD width) := bit_to_sl(mem_vector(j));
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
--Display output message indicating that the behavioral model is done
--initializing
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator data initialization complete." SEVERITY NOTE;
if (C_USE_BRAM_BLOCK = 1) then
--Display output message indicating that the behavioral model is being
--initialized
-- Read in the .mem file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_INIT_FILE /= "NONE") then
file_open(open_status, int_infile, C_INIT_FILE, read_mode);
while not endfile(int_infile) loop
readline(int_infile, data_line);
while (data_line /= null and data_line'length > 0) loop
if (data_line(data_line'low to data_line'low + 1) = "//") then
deallocate(data_line);
elsif ((data_line(data_line'low to data_line'low + 1) = "/*") and (data_line(data_line'high-1 to data_line'high) = "*/")) then
deallocate(data_line);
elsif (data_line(data_line'low to data_line'low + 1) = "/*") then
deallocate(data_line);
ignore_line := true;
elsif (ignore_line = true and data_line(data_line'high-1 to data_line'high) = "*/") then
deallocate(data_line);
ignore_line := false;
elsif (ignore_line = false and data_line(data_line'low) = '@') then
read(data_line, char_tmp);
hread(data_line, init_addr_slv, good_data);
i := SLV_TO_INT(init_addr_slv);
elsif (ignore_line = false) then
hread(data_line, input_initf_tmp(i), good_data);
init_return(i)(write_width_a - 1 downto 0) := input_initf_tmp(i)(write_width_a - 1 downto 0);
if (good_data = true) then
i := i + 1;
end if;
else
deallocate(data_line);
end if;
end loop;
end loop;
file_close(int_infile);
END IF;
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- memory type constants
--***************************************************************
CONSTANT MEM_TYPE_SP_RAM : INTEGER := 0;
CONSTANT MEM_TYPE_SDP_RAM : INTEGER := 1;
CONSTANT MEM_TYPE_TDP_RAM : INTEGER := 2;
CONSTANT MEM_TYPE_SP_ROM : INTEGER := 3;
CONSTANT MEM_TYPE_DP_ROM : INTEGER := 4;
--***************************************************************
-- memory configuration constant functions
--***************************************************************
--get_single_port
-----------------
FUNCTION get_single_port(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_RAM OR mem_type=MEM_TYPE_SP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_single_port;
--get_is_rom
--------------
FUNCTION get_is_rom(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_ROM OR mem_type=MEM_TYPE_DP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_is_rom;
--get_has_a_write
------------------
FUNCTION get_has_a_write(IS_ROM : INTEGER) RETURN INTEGER IS
BEGIN
IF (IS_ROM=0) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_a_write;
--get_has_b_write
------------------
FUNCTION get_has_b_write(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_TDP_RAM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_write;
--get_has_a_read
------------------
FUNCTION get_has_a_read(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SDP_RAM) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_a_read;
--get_has_b_read
------------------
FUNCTION get_has_b_read(SINGLE_PORT : INTEGER) RETURN INTEGER IS
BEGIN
IF (SINGLE_PORT=1) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_b_read;
--get_has_b_port
------------------
FUNCTION get_has_b_port(HAS_B_READ : INTEGER;
HAS_B_WRITE : INTEGER)
RETURN INTEGER IS
BEGIN
IF (HAS_B_READ=1 OR HAS_B_WRITE=1) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_port;
--get_num_output_stages
-----------------------
FUNCTION get_num_output_stages(has_mem_output_regs : INTEGER;
has_mux_output_regs : INTEGER;
mux_pipeline_stages : INTEGER)
RETURN INTEGER IS
VARIABLE actual_mux_pipeline_stages : INTEGER;
BEGIN
-- Mux pipeline stages can be non-zero only when there is a mux
-- output register.
IF (has_mux_output_regs=1) THEN
actual_mux_pipeline_stages := mux_pipeline_stages;
ELSE
actual_mux_pipeline_stages := 0;
END IF;
RETURN has_mem_output_regs+actual_mux_pipeline_stages+has_mux_output_regs;
END get_num_output_stages;
--***************************************************************************
-- Component declaration of the VARIABLE depth output register stage
--***************************************************************************
COMPONENT blk_mem_gen_v8_3_1_output_stage
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
EN : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
ECCPIPECE : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_output_stage;
COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************************************
-- locally derived constants to assist memory access
--******************************************************
CONSTANT WRITE_WIDTH_RATIO_A : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_A : INTEGER := C_READ_WIDTH_A/MIN_WIDTH;
CONSTANT WRITE_WIDTH_RATIO_B : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_B : INTEGER := C_READ_WIDTH_B/MIN_WIDTH;
--******************************************************
-- To modify the LSBs of the 'wider' data to the actual
-- address value
--******************************************************
CONSTANT WRITE_ADDR_A_DIV : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH_A;
CONSTANT READ_ADDR_A_DIV : INTEGER := C_READ_WIDTH_A/MIN_WIDTH_A;
CONSTANT WRITE_ADDR_B_DIV : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH_B;
CONSTANT READ_ADDR_B_DIV : INTEGER := C_READ_WIDTH_B/MIN_WIDTH_B;
--******************************************************
-- FUNCTION : log2roundup
--******************************************************
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
--******************************************************
-- Other constants and signals
--******************************************************
CONSTANT COLL_DELAY : TIME := 100 ps;
-- default data vector
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_DEFAULT_DATA,
C_WRITE_WIDTH_A);
CONSTANT CHKBIT_WIDTH : INTEGER := if_then_else(C_WRITE_WIDTH_A>57,8,if_then_else(C_WRITE_WIDTH_A>26,7,if_then_else(C_WRITE_WIDTH_A>11,6,if_then_else(C_WRITE_WIDTH_A>4,5,if_then_else(C_WRITE_WIDTH_A<5,4,0)))));
-- the init memory SIGNAL
SIGNAL memory_i : mem_array;
SIGNAL doublebit_error_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0);
SIGNAL current_contents_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
-- write mode constants
CONSTANT WRITE_MODE_A : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_A);
CONSTANT WRITE_MODE_B : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_B);
CONSTANT WRITE_MODES : STD_LOGIC_VECTOR(3 DOWNTO 0) :=
WRITE_MODE_A & WRITE_MODE_B;
-- reset values
CONSTANT INITA_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITA_VAL,
C_READ_WIDTH_A);
CONSTANT INITB_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITB_VAL,
C_READ_WIDTH_B);
-- memory output 'latches'
SIGNAL memory_out_a : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0) :=
INITA_VAL;
SIGNAL memory_out_b : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) :=
INITB_VAL;
SIGNAL sbiterr_in : STD_LOGIC := '0';
SIGNAL sbiterr_sdp : STD_LOGIC := '0';
SIGNAL dbiterr_in : STD_LOGIC := '0';
SIGNAL dbiterr_sdp : STD_LOGIC := '0';
SIGNAL rdaddrecc_in : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_sdp : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL doutb_i : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i : STD_LOGIC := '0';
SIGNAL dbiterr_i : STD_LOGIC := '0';
-- memory configuration constants
-----------------------------------------------
CONSTANT SINGLE_PORT : INTEGER := get_single_port(C_MEM_TYPE);
CONSTANT IS_ROM : INTEGER := get_is_rom(C_MEM_TYPE);
CONSTANT HAS_A_WRITE : INTEGER := get_has_a_write(IS_ROM);
CONSTANT HAS_B_WRITE : INTEGER := get_has_b_write(C_MEM_TYPE);
CONSTANT HAS_A_READ : INTEGER := get_has_a_read(C_MEM_TYPE);
CONSTANT HAS_B_READ : INTEGER := get_has_b_read(SINGLE_PORT);
CONSTANT HAS_B_PORT : INTEGER := get_has_b_port(HAS_B_READ, HAS_B_WRITE);
CONSTANT NUM_OUTPUT_STAGES_A : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_A,
C_MUX_PIPELINE_STAGES);
CONSTANT NUM_OUTPUT_STAGES_B : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES);
CONSTANT WEA0 : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT WEB0 : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-----------------------------------------------------------------------------
-- DEBUG CONTROL
-- DEBUG=0 : Debug output OFF
-- DEBUG=1 : Some debug info printed
-----------------------------------------------------------------------------
CONSTANT DEBUG : INTEGER := 0;
-- internal signals
-----------------------------------------------
SIGNAL ena_i : STD_LOGIC;
SIGNAL enb_i : STD_LOGIC;
SIGNAL reseta_i : STD_LOGIC;
SIGNAL resetb_i : STD_LOGIC;
SIGNAL wea_i : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL web_i : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL rea_i : STD_LOGIC;
SIGNAL reb_i : STD_LOGIC;
SIGNAL message_complete : BOOLEAN := false;
SIGNAL rsta_outp_stage : STD_LOGIC := '0';
SIGNAL rstb_outp_stage : STD_LOGIC := '0';
--*********************************************************
--FUNCTION : Collision check
--*********************************************************
FUNCTION collision_check (addr_a :
STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
iswrite_a : BOOLEAN;
addr_b :
STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
iswrite_b : BOOLEAN)
RETURN BOOLEAN IS
VARIABLE c_aw_bw : INTEGER;
VARIABLE c_aw_br : INTEGER;
VARIABLE c_ar_bw : INTEGER;
VARIABLE write_addr_a_width : INTEGER;
VARIABLE read_addr_a_width : INTEGER;
VARIABLE write_addr_b_width : INTEGER;
VARIABLE read_addr_b_width : INTEGER;
BEGIN
c_aw_bw := 0;
c_aw_br := 0;
c_ar_bw := 0;
-- Determine the effective address widths FOR each of the 4 ports
write_addr_a_width := C_ADDRA_WIDTH-log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width := C_ADDRA_WIDTH-log2roundup(READ_ADDR_A_DIV);
write_addr_b_width := C_ADDRB_WIDTH-log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width := C_ADDRB_WIDTH-log2roundup(READ_ADDR_B_DIV);
--Look FOR a write-write collision. In order FOR a write-write
--collision to exist, both ports must have a write transaction.
IF (iswrite_a AND iswrite_b) THEN
IF (write_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_a and iswrite_b
--If the B port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_a) THEN
IF (write_addr_a_width > read_addr_b_width) THEN
--read_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_b_width
--Once both are scaled to read_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
END IF; --width
END IF; --iswrite_a
--If the A port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_b) THEN
IF (read_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
ELSE
--read_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_a_width
--Once both are scaled to read_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_b
RETURN (c_aw_bw=1 OR c_aw_br=1 OR c_ar_bw=1);
END FUNCTION collision_check;
BEGIN -- Architecture
-----------------------------------------------------------------------------
-- SOFTECC and ECC SBITERR/DBITERR Outputs
-- The ECC Behavior is modeled by the behavioral models only for Virtex-6.
-- The SOFTECC Behavior is modeled by the behavioral models for Spartan-6.
-- For Virtex-5, these outputs will be tied to 0.
-----------------------------------------------------------------------------
SBITERR <= sbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_sdp WHEN (((C_FAMILY="virtex7") AND C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
-----------------------------------------------
-- This effectively wires off optional inputs
-----------------------------------------------
ena_i <= ENA WHEN (C_HAS_ENA=1) ELSE '1';
enb_i <= ENB WHEN (C_HAS_ENB=1 AND HAS_B_PORT=1) ELSE '1';
-- We are doing an "AND" operation of WEA and ENA and passing to Enbale pin of BRAM when built-in ECC is enabled,
-- what this means is that the write operation happens only when both WEA and ENA are high.
wea_i <= WEA WHEN (HAS_A_WRITE=1 AND ena_i='1') ELSE WEA0;
-- wea_i <= (OTHERS => '1') WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=1 AND ENA = '1') ELSE -- Use_ENA_pin
-- WEA WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=0) ELSE -- Always_enabled
-- WEA WHEN (HAS_A_WRITE=1 AND ena_i='1' AND C_USE_ECC = 0) ELSE
-- WEA0;
web_i <= WEB WHEN (HAS_B_WRITE=1 AND enb_i='1') ELSE WEB0;
rea_i <= ena_i WHEN (HAS_A_READ=1) ELSE '0';
reb_i <= enb_i WHEN (HAS_B_READ=1) ELSE '0';
-- these signals reset the memory latches
-- For the special reset behaviors in some of the families, the C_RSTRAM
-- attribute of the corresponding port is used to indicate if the latch is
-- reset or not.
reseta_i <= RSTA WHEN
((C_HAS_RSTA=1 AND NUM_OUTPUT_STAGES_A=0) OR
(C_HAS_RSTA=1 AND C_RSTRAM_A=1))
ELSE '0';
resetb_i <= RSTB WHEN
((C_HAS_RSTB=1 AND NUM_OUTPUT_STAGES_B=0) OR
(C_HAS_RSTB=1 AND C_RSTRAM_B=1) )
ELSE '0';
--***************************************************************************
-- This is the main PROCESS which includes the memory VARIABLE and the read
-- and write procedures. It also schedules read and write operations
--***************************************************************************
PROCESS (CLKA, CLKB,rea_i,reb_i,reseta_i,resetb_i)
-- Initialize the init memory array
------------------------------------
VARIABLE memory : mem_array := init_memory(DEFAULT_DATA,
C_WRITE_WIDTH_A,
MAX_DEPTH,
MIN_WIDTH);
-- Initialize the mem memory array
------------------------------------
VARIABLE softecc_sbiterr_arr : softecc_err_array;
VARIABLE softecc_dbiterr_arr : softecc_err_array;
VARIABLE sbiterr_arr : ecc_err_array;
VARIABLE dbiterr_arr : ecc_err_array;
CONSTANT doublebit_lsb : STD_LOGIC_VECTOR (1 DOWNTO 0):="11";
CONSTANT doublebit_msb : STD_LOGIC_VECTOR (C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 DOWNTO 0):= (OTHERS => '0');
VARIABLE doublebit_error : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0) := doublebit_msb & doublebit_lsb ;
VARIABLE current_contents_var : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
--***********************************
-- procedures to access the memory
--***********************************
-- write_a
----------
PROCEDURE write_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
inj_sbiterr : IN STD_LOGIC;
inj_dbiterr : IN STD_LOGIC) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
VARIABLE message : LINE;
VARIABLE errbit_current_contents : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
-- Block Memory Generator non-cycle-accurate message
ASSERT (message_complete) REPORT "Block Memory Generator module is using a behavioral model FOR simulation which will not precisely model memory collision behavior."
SEVERITY NOTE;
message_complete <= true;
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_A_DIV);
IF (address_i >= C_WRITE_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range FOR A Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEA = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_A + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEA_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Insert double bit errors:
IF (C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
current_contents(0) := NOT(current_contents(0));
current_contents(1) := NOT(current_contents(1));
--current_contents(0) := NOT(current_contents(30));
--current_contents(1) := NOT(current_contents(62));
END IF;
END IF;
-- Insert double bit errors:
IF (C_USE_SOFTECC=1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 downto 2) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 downto 0);
doublebit_error(0) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1);
doublebit_error(1) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-2);
current_contents := current_contents XOR doublebit_error(C_WRITE_WIDTH_A-1 DOWNTO 0);
END IF;
END IF;
IF(DEBUG=1) THEN
current_contents_var := current_contents; --for debugging current
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_A + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
-- Store address at which error is injected:
IF ((C_FAMILY = "virtex7") AND C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
sbiterr_arr(address_i) := '1';
ELSE
sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
dbiterr_arr(address_i) := '1';
ELSE
dbiterr_arr(address_i) := '0';
END IF;
END IF;
-- Store address at which softecc error is injected:
IF (C_USE_SOFTECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
softecc_sbiterr_arr(address_i) := '1';
ELSE
softecc_sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
softecc_dbiterr_arr(address_i) := '1';
ELSE
softecc_dbiterr_arr(address_i) := '0';
END IF;
END IF;
END IF;
END PROCEDURE;
-- write_b
----------
PROCEDURE write_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_B_DIV);
IF (address_i >= C_WRITE_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEB = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_B + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEB_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_B + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
END IF;
END PROCEDURE;
-- read_a
----------
PROCEDURE read_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_A_DIV);
IF (address_i >= C_READ_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for A Read"
SEVERITY WARNING;
END IF;
memory_out_a <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_A-1 LOOP
memory_out_a(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_A + i) AFTER FLOP_DELAY;
END LOOP;
END IF;
END IF;
END PROCEDURE;
-- read_b
----------
PROCEDURE read_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_B_DIV);
IF (address_i >= C_READ_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Read"
SEVERITY WARNING;
END IF;
memory_out_b <= (OTHERS => 'X') AFTER FLOP_DELAY;
sbiterr_in <= 'X' AFTER FLOP_DELAY;
dbiterr_in <= 'X' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_B-1 LOOP
memory_out_b(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_B + i) AFTER FLOP_DELAY;
END LOOP;
--assert sbiterr and dbiterr signals
IF ((C_FAMILY="virtex7") AND C_USE_ECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
--assert softecc sbiterr and dbiterr signals
ELSIF (C_USE_SOFTECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (softecc_sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (softecc_dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
END IF;
END IF;
END IF;
END PROCEDURE;
-- reset_a
----------
PROCEDURE reset_a
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
-- reset_b
----------
PROCEDURE reset_b
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
BEGIN -- begin the main PROCESS
--***************************************************************************
-- These are the main blocks which schedule read and write operations
-- Note that the reset priority feature at the latch stage is only supported
-- for Spartan-6. For other families, the default priority at the latch stage
-- is "CE"
--***************************************************************************
-- Synchronous clocks: schedule port operations with respect to both
-- write operating modes
IF (C_COMMON_CLK=1) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODES IS
WHEN "0000" => -- write_first write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "0100" => -- read_first write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "0001" => -- write_first read_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0101" => --read_first read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0010" => -- write_first no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0110" => -- read_first no_change
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1000" => -- no_change write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "1001" => -- no_change read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1010" => -- no_change no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Synchronous clocks
-- Asynchronous clocks: port operation is independent
IF (C_COMMON_CLK=0) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODE_A IS
WHEN "00" => -- write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN "01" => -- read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "10" => -- no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
IF (CLKB='1' AND CLKB'EVENT) THEN
CASE WRITE_MODE_B IS
WHEN "00" => -- write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "01" => -- read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "10" => -- no_change
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Asynchronous clocks
-- Assign the memory VARIABLE to the user_visible memory_i SIGNAL
IF(DEBUG=1) THEN
memory_i <= memory;
doublebit_error_i <= doublebit_error;
current_contents_i <= current_contents_var;
END IF;
END PROCESS;
--********************************************************************
-- Instantiate the VARIABLE depth output stage
--********************************************************************
-- Port A
rsta_outp_stage <= RSTA and not sleep;
rstb_outp_stage <= RSTB and not sleep;
reg_a : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTA,
C_RSTRAM => C_RSTRAM_A,
C_RST_PRIORITY => C_RST_PRIORITY_A,
init_val => INITA_VAL,
C_HAS_EN => C_HAS_ENA,
C_HAS_REGCE => C_HAS_REGCEA,
C_DATA_WIDTH => C_READ_WIDTH_A,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_A,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_A,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKA,
RST => rsta_outp_stage, --RSTA,
EN => ENA,
REGCE => REGCEA,
DIN_I => memory_out_a,
DOUT => DOUTA,
SBITERR_IN_I => '0',
DBITERR_IN_I => '0',
SBITERR => OPEN,
DBITERR => OPEN,
RDADDRECC_IN_I => (OTHERS => '0'),
ECCPIPECE => '0',
RDADDRECC => OPEN
);
-- Port B
reg_b : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTB,
C_RSTRAM => C_RSTRAM_B,
C_RST_PRIORITY => C_RST_PRIORITY_B,
init_val => INITB_VAL,
C_HAS_EN => C_HAS_ENB,
C_HAS_REGCE => C_HAS_REGCEB,
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_B,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKB,
RST => rstb_outp_stage,--RSTB,
EN => ENB,
REGCE => REGCEB,
DIN_I => memory_out_b,
DOUT => doutb_i,
SBITERR_IN_I => sbiterr_in,
DBITERR_IN_I => dbiterr_in,
SBITERR => sbiterr_i,
DBITERR => dbiterr_i,
RDADDRECC_IN_I => rdaddrecc_in,
ECCPIPECE => ECCPIPECE,
RDADDRECC => rdaddrecc_i
);
--********************************************************************
-- Instantiate the input / Output Register stages
--********************************************************************
output_reg_stage: blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC MAP(
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP(
CLK => CLKB,
DIN => doutb_i,
DOUT => DOUTB,
SBITERR_IN => sbiterr_i,
DBITERR_IN => dbiterr_i,
SBITERR => sbiterr_sdp,
DBITERR => dbiterr_sdp,
RDADDRECC_IN => rdaddrecc_i,
RDADDRECC => rdaddrecc_sdp
);
--*********************************
-- Synchronous collision checks
--*********************************
sync_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=1) GENERATE
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
-- collision detect
VARIABLE is_collision : BOOLEAN;
VARIABLE message : LINE;
BEGIN
IF (CLKA='1' AND CLKA'EVENT) THEN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision := false;
END IF;
-- If the write port is in READ_FIRST mode, there is no collision
IF (C_WRITE_MODE_A="READ_FIRST" AND wea_i/=WEA0 AND web_i=WEB0) THEN
is_collision := false;
END IF;
IF (C_WRITE_MODE_B="READ_FIRST" AND web_i/=WEB0 AND wea_i=WEA0) THEN
is_collision := false;
END IF;
-- Only flag if one of the accesses is a write
IF (is_collision AND (wea_i/=WEA0 OR web_i/=WEB0)) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END IF;
END PROCESS;
END GENERATE;
--*********************************
-- Asynchronous collision checks
--*********************************
async_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=0) GENERATE
SIGNAL addra_delay : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL wea_delay : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL ena_delay : STD_LOGIC;
SIGNAL addrb_delay : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
SIGNAL web_delay : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL enb_delay : STD_LOGIC;
BEGIN
-- Delay A and B addresses in order to mimic setup/hold times
PROCESS (ADDRA, wea_i, ena_i, ADDRB, web_i, enb_i)
BEGIN
addra_delay <= ADDRA AFTER COLL_DELAY;
wea_delay <= wea_i AFTER COLL_DELAY;
ena_delay <= ena_i AFTER COLL_DELAY;
addrb_delay <= ADDRB AFTER COLL_DELAY;
web_delay <= web_i AFTER COLL_DELAY;
enb_delay <= enb_i AFTER COLL_DELAY;
END PROCESS;
-- Do the checks w/rt A
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_a : BOOLEAN;
VARIABLE is_collision_delay_a : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_a := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_a := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_delay_a := collision_check(ADDRA,
wea_i/=WEA0,
addrb_delay,
web_delay/=WEB0);
ELSE
is_collision_delay_a := false;
END IF;
-- Only flag if B access is a write
IF (is_collision_a AND web_i/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_a AND web_delay/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, addrb_delay);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
-- Do the checks w/rt B
PROCESS (CLKB)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_b : BOOLEAN;
VARIABLE is_collision_delay_b : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA) /= 'X') THEN
is_collision_b := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_b := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(addra_delay) /= 'X') THEN
is_collision_delay_b := collision_check(addra_delay,
wea_delay/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_delay_b := false;
END IF;
-- Only flag if A access is a write
-- Modified condition checking (is_collision_b AND WEA0_i=/WEA0) to fix CR526228
IF (is_collision_b AND wea_i/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_b AND wea_delay/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, addra_delay);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
END GENERATE;
END mem_module_behavioral;
--******************************************************************************
-- Top module that wraps SoftECC Input register stage and the main memory module
--
-- This module is the top-level of behavioral model
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1 IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_CTRL_ECC_ALGO : STRING := "NONE";
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
--C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_SLEEP_PIN : INTEGER := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
PORT (
clka : IN STD_LOGIC := '0';
rsta : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '1';
regcea : IN STD_LOGIC := '1';
wea : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addra : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
dina : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
douta : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
clkb : IN STD_LOGIC := '0';
rstb : IN STD_LOGIC := '0';
enb : IN STD_LOGIC := '1';
regceb : IN STD_LOGIC := '1';
web : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addrb : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
dinb : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
doutb : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
injectsbiterr : IN STD_LOGIC := '0';
injectdbiterr : IN STD_LOGIC := '0';
sbiterr : OUT STD_LOGIC := '0';
dbiterr : OUT STD_LOGIC := '0';
rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : in std_logic := '0';
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic := '0';
rstb_busy : out std_logic := '0';
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
s_aclk : IN STD_LOGIC := '0';
s_aresetn : IN STD_LOGIC := '0';
-- axi full/lite slave Write (write side)
s_axi_awid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid : IN STD_LOGIC := '0';
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast : IN STD_LOGIC := '0';
s_axi_wvalid : IN STD_LOGIC := '0';
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC := '0';
-- axi full/lite slave Read (Write side)
s_axi_arid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid : IN STD_LOGIC := '0';
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_rdata : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC := '0';
-- axi full/lite sideband Signals
s_axi_injectsbiterr : IN STD_LOGIC := '0';
s_axi_injectdbiterr : IN STD_LOGIC := '0';
s_axi_sbiterr : OUT STD_LOGIC := '0';
s_axi_dbiterr : OUT STD_LOGIC := '0';
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END blk_mem_gen_v8_3_1;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE behavioral OF blk_mem_gen_v8_3_1 IS
COMPONENT blk_mem_gen_v8_3_1_mem_module
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_mem_module;
COMPONENT blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_axi_regs_fwd_v8_3;
COMPONENT blk_mem_axi_read_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT blk_mem_axi_read_wrapper_beh;
COMPONENT blk_mem_axi_write_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END COMPONENT blk_mem_axi_write_wrapper_beh;
CONSTANT FLOP_DELAY : TIME := 100 ps;
SIGNAL rsta_in : STD_LOGIC := '1';
SIGNAL ena_in : STD_LOGIC := '1';
SIGNAL regcea_in : STD_LOGIC := '1';
SIGNAL wea_in : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL addra_in : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL dina_in : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL injectsbiterr_in : STD_LOGIC := '0';
SIGNAL injectdbiterr_in : STD_LOGIC := '0';
-----------------------------------------------------------------------------
-- FUNCTION: toLowerCaseChar
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
-----------------------------------------------------------------------------
FUNCTION toLowerCaseChar(
char : character )
RETURN character IS
BEGIN
-- If char is not an upper case letter then return char
IF char<'A' OR char>'Z' THEN
RETURN char;
END IF;
-- Otherwise map char to its corresponding lower case character and
-- RETURN that
CASE char IS
WHEN 'A' => RETURN 'a';
WHEN 'B' => RETURN 'b';
WHEN 'C' => RETURN 'c';
WHEN 'D' => RETURN 'd';
WHEN 'E' => RETURN 'e';
WHEN 'F' => RETURN 'f';
WHEN 'G' => RETURN 'g';
WHEN 'H' => RETURN 'h';
WHEN 'I' => RETURN 'i';
WHEN 'J' => RETURN 'j';
WHEN 'K' => RETURN 'k';
WHEN 'L' => RETURN 'l';
WHEN 'M' => RETURN 'm';
WHEN 'N' => RETURN 'n';
WHEN 'O' => RETURN 'o';
WHEN 'P' => RETURN 'p';
WHEN 'Q' => RETURN 'q';
WHEN 'R' => RETURN 'r';
WHEN 'S' => RETURN 's';
WHEN 'T' => RETURN 't';
WHEN 'U' => RETURN 'u';
WHEN 'V' => RETURN 'v';
WHEN 'W' => RETURN 'w';
WHEN 'X' => RETURN 'x';
WHEN 'Y' => RETURN 'y';
WHEN 'Z' => RETURN 'z';
WHEN OTHERS => RETURN char;
END CASE;
END toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
FUNCTION equalIgnoreCase(
str1 : STRING;
str2 : STRING )
RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str2'left TO str1'right LOOP
IF NOT (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equalIgnoreCase;
-----------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
----------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
----------------------------------------------------------------------------
-- FUNCTION : log2roundup
----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
CONSTANT lower_limit : INTEGER := 1;
CONSTANT upper_limit : INTEGER := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
-----------------------------------------------------------------------------
-- FUNCTION : divroundup
-- Returns the ceiling value of the division
-- Data_value - the quantity to be divided, dividend
-- Divisor - the value to divide the data_value by
-----------------------------------------------------------------------------
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
SIGNAL s_axi_awaddr_out_c : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_araddr_out_c : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_wr_en_c : STD_LOGIC := '0';
SIGNAL s_axi_rd_en_c : STD_LOGIC := '0';
SIGNAL s_aresetn_a_c : STD_LOGIC := '0';
--**************************************************************************
-- AXI PARAMETERS
CONSTANT AXI_FULL_MEMORY_SLAVE : integer := if_then_else((C_AXI_SLAVE_TYPE = 0 AND C_AXI_TYPE = 1),1,0);
CONSTANT C_AXI_ADDR_WIDTH_MSB : integer := C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
CONSTANT C_AXI_ADDR_WIDTH : integer := C_AXI_ADDR_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT LOWER_BOUND_VAL : integer := if_then_else((log2roundup(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT C_AXI_ADDR_WIDTH_LSB : integer := if_then_else((AXI_FULL_MEMORY_SLAVE = 1),0,LOWER_BOUND_VAL);
CONSTANT C_AXI_OS_WR : integer := 2;
-- SAFETY LOGIC related Signals
SIGNAL RSTA_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_A : STD_LOGIC := '0';
SIGNAL RSTB_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_B : STD_LOGIC := '0';
SIGNAL ENA_dly : STD_LOGIC := '0';
SIGNAL ENA_dly_D : STD_LOGIC := '0';
SIGNAL ENB_dly : STD_LOGIC := '0';
SIGNAL ENB_dly_D : STD_LOGIC := '0';
SIGNAL RSTA_I_SAFE : STD_LOGIC := '0';
SIGNAL RSTB_I_SAFE : STD_LOGIC := '0';
SIGNAL ENA_I_SAFE : STD_LOGIC := '0';
SIGNAL ENB_I_SAFE : STD_LOGIC := '0';
SIGNAL ram_rstram_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstram_b_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_b_busy : STD_LOGIC := '0';
SIGNAL ENA_dly_reg : STD_LOGIC := '0';
SIGNAL ENB_dly_reg : STD_LOGIC := '0';
SIGNAL ENA_dly_reg_D : STD_LOGIC := '0';
SIGNAL ENB_dly_reg_D : STD_LOGIC := '0';
--**************************************************************************
BEGIN -- Architecture
--*************************************************************************
-- NO INPUT STAGE
--*************************************************************************
no_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=0) GENERATE
rsta_in <= RSTA;
ena_in <= ENA;
regcea_in <= REGCEA;
wea_in <= WEA;
addra_in <= ADDRA;
dina_in <= DINA;
injectsbiterr_in <= INJECTSBITERR;
injectdbiterr_in <= INJECTDBITERR;
END GENERATE no_input_stage;
--**************************************************************************
-- WITH INPUT STAGE
--**************************************************************************
has_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=1) GENERATE
PROCESS (CLKA)
BEGIN
IF (CLKA'EVENT AND CLKA = '1') THEN
rsta_in <= RSTA AFTER FLOP_DELAY;
ena_in <= ENA AFTER FLOP_DELAY;
regcea_in <= REGCEA AFTER FLOP_DELAY;
wea_in <= WEA AFTER FLOP_DELAY;
addra_in <= ADDRA AFTER FLOP_DELAY;
dina_in <= DINA AFTER FLOP_DELAY;
injectsbiterr_in <= INJECTSBITERR AFTER FLOP_DELAY;
injectdbiterr_in <= INJECTDBITERR AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE has_input_stage;
--**************************************************************************
-- NO SAFETY LOGIC
--**************************************************************************
NO_SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 0) GENERATE
ENA_I_SAFE <= ena_in;
ENB_I_SAFE <= ENB;
RSTA_I_SAFE <= rsta_in;
RSTB_I_SAFE <= RSTB;
END GENERATE NO_SAFETY_CKT_GEN;
--**************************************************************************
-- SAFETY LOGIC
--**************************************************************************
SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 1) GENERATE
-- RESET SAFETY LOGIC Generation
-- POR Generation
------------------------------------------------------------------------------
-- Power-ON Reset Generation
------------------------------------------------------------------------------
RST_SHFT_LOGIC_A : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
RSTA_SHFT_REG(4 DOWNTO 0) <= RSTA_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_A;
POR_RSTA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
POR_A <= RSTA_SHFT_REG(4) xor RSTA_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTA_GEN;
RST_SHFT_LOGIC_B : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
RSTB_SHFT_REG(4 DOWNTO 0) <= RSTB_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_B;
POR_RSTB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
POR_B <= RSTB_SHFT_REG(4) xor RSTB_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTB_GEN;
-----------------------------------------------------------------------------
-- Fix for the AR42571
-----------------------------------------------------------------------------
-- Reset Generation
-----------------------------------------------------------------------------
RSTA_I_SAFE <= rsta_in OR POR_A;
SPRAM_RST: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_I_SAFE <= '0';
END GENERATE SPRAM_RST;
nSPRAM_RST: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_I_SAFE <= RSTB OR POR_B;
END GENERATE nSPRAM_RST;
-----------------------------------------------------------------------------
-- RSTA/B_BUSY Generation
-----------------------------------------------------------------------------
RSTA_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
ram_rstram_a_busy <= rsta_in OR ENA_dly OR ENA_dly_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstram_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_NO_REG;
RSTA_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
ram_rstreg_a_busy <= rsta_in OR ENA_dly OR ENA_dly_reg_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstreg_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_WITH_REG;
SPRAM_RST_BUSY: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_BUSY <= '0';
END GENERATE SPRAM_RST_BUSY;
nSPRAM_RST_BUSY: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
ram_rstram_b_busy <= RSTB OR ENB_dly OR ENB_dly_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstram_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_NO_REG;
RSTB_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
ram_rstreg_b_busy <= RSTB OR ENB_dly OR ENB_dly_reg_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstreg_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_WITH_REG;
END GENERATE nSPRAM_RST_BUSY;
-----------------------------------------------------------------------------
-- ENA/ENB Generation
-----------------------------------------------------------------------------
ENA_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly <= rsta_in AFTER FLOP_DELAY;
ENA_dly_D <= ENA_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_D OR ena_in;
END GENERATE ENA_NO_REG;
ENA_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly_reg <= rsta_in AFTER FLOP_DELAY;
ENA_dly_reg_D <= ENA_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_reg_D OR ena_in;
END GENERATE ENA_WITH_REG;
SPRAM_ENB: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
ENB_I_SAFE <= '0';
END GENERATE SPRAM_ENB;
nSPRAM_ENB: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
ENB_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly <= RSTB AFTER FLOP_DELAY;
ENB_dly_D <= ENB_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_D OR ENB;
END GENERATE ENB_NO_REG;
ENB_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly_reg <= RSTB AFTER FLOP_DELAY;
ENB_dly_reg_D <= ENB_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_reg_D OR ENB;
END GENERATE ENB_WITH_REG;
END GENERATE nSPRAM_ENB;
END GENERATE SAFETY_CKT_GEN;
--**************************************************************************
-- NATIVE MEMORY MODULE INSTANCE
--**************************************************************************
native_mem_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 0) GENERATE
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,--rsta_in,
ENA => ENA_I_SAFE,--ena_in,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in,
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => RDADDRECC
);
END GENERATE native_mem_module;
--**************************************************************************
-- NATIVE MEMORY MAPPED MODULE INSTANCE
--**************************************************************************
native_mem_map_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 1) GENERATE
--**************************************************************************
-- NATIVE MEMORY MAPPED PARAMETERS
CONSTANT C_ADDRA_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_A);
CONSTANT C_ADDRB_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_B);
CONSTANT C_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
CONSTANT C_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
CONSTANT C_MEM_MAP_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_MSB;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT MEM_MAP_LOWER_BOUND_VAL_A : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT MEM_MAP_LOWER_BOUND_VAL_B : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_B,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_B,8)));
CONSTANT C_MEM_MAP_ADDRA_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_A;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_B;
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH_ACTUAL-1 DOWNTO 0) := (OTHERS => '0');
--**************************************************************************
BEGIN
RDADDRECC(C_ADDRB_WIDTH-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_MSB) <= (OTHERS => '0');
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB) <= rdaddrecc_i;
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_LSB-1 DOWNTO 0) <= (OTHERS => '0');
mem_map_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH_ACTUAL,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH_ACTUAL,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,
ENA => ENA_I_SAFE,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in(C_MEM_MAP_ADDRA_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRA_WIDTH_LSB),
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB),
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => rdaddrecc_i
);
END GENERATE native_mem_map_module;
--****************************************************************************
-- AXI MEMORY MODULE INSTANCE
--****************************************************************************
axi_mem_module: IF (C_INTERFACE_TYPE = 1) GENERATE
SIGNAL s_axi_rid_c : STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rdata_c : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rresp_c : STD_LOGIC_VECTOR(2-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rlast_c : STD_LOGIC := '0';
SIGNAL s_axi_rvalid_c : STD_LOGIC := '0';
SIGNAL s_axi_rready_c : STD_LOGIC := '0';
SIGNAL regceb_c : STD_LOGIC := '0';
BEGIN
s_aresetn_a_c <= NOT S_ARESETN;
S_AXI_BRESP <= (OTHERS => '0');
s_axi_rresp_c <= (OTHERS => '0');
no_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 0 AND C_HAS_MUX_OUTPUT_REGS_B = 0 ) GENERATE
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RLAST <= s_axi_rlast_c;
S_AXI_RVALID <= s_axi_rvalid_c;
S_AXI_RID <= s_axi_rid_c;
S_AXI_RRESP <= s_axi_rresp_c;
s_axi_rready_c <= S_AXI_RREADY;
END GENERATE no_regs;
has_regs_fwd: IF (C_HAS_MUX_OUTPUT_REGS_B = 1 OR C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
CONSTANT C_AXI_PAYLOAD : INTEGER := if_then_else((C_HAS_MUX_OUTPUT_REGS_B = 1),C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3,C_AXI_ID_WIDTH+3);
SIGNAL s_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
has_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
regceb_c <= s_axi_rvalid_c AND s_axi_rready_c;
END GENERATE has_regceb;
no_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 0) GENERATE
regceb_c <= REGCEB;
END GENERATE no_regceb;
only_core_op_regs: IF (C_HAS_MUX_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rdata_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RDATA <= m_axi_payload_c(C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_core_op_regs;
only_emb_op_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_emb_op_regs;
axi_regs_inst : blk_mem_axi_regs_fwd_v8_3
GENERIC MAP(
C_DATA_WIDTH => C_AXI_PAYLOAD
)
PORT MAP (
ACLK => S_ACLK,
ARESET => s_aresetn_a_c,
S_VALID => s_axi_rvalid_c,
S_READY => s_axi_rready_c,
S_PAYLOAD_DATA => s_axi_payload_c,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY,
M_PAYLOAD_DATA => m_axi_payload_c
);
END GENERATE has_regs_fwd;
axi_wr_fsm : blk_mem_axi_write_wrapper_beh
GENERIC MAP(
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_AXI_AWADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_WDATA_WIDTH => C_WRITE_WIDTH_A,
C_AXI_OS_WR => C_AXI_OS_WR
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Slave Write Interface
S_AXI_AWADDR => S_AXI_AWADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_AWLEN => S_AXI_AWLEN,
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BID => S_AXI_BID,
-- Signals for BRAM interface
S_AXI_AWADDR_OUT =>s_axi_awaddr_out_c,
S_AXI_WR_EN =>s_axi_wr_en_c
);
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => 1, -- For AXI, Read Enable is always C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => 1, -- For AXI C_USE_BYTE_WEA is always 1,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => 1, -- For AXI, Read Enable is always C_HAS_ENB,
C_HAS_REGCEB => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_BYTE_WEB => 1, -- For AXI C_USE_BYTE_WEB is always 1,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => 0, --For AXI, Primitive Registers A is not supported C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => 0,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
--Port A:
CLKA => S_AClk,
RSTA => s_aresetn_a_c,
ENA => s_axi_wr_en_c,
REGCEA => regcea_in,
WEA => S_AXI_WSTRB,
ADDRA => s_axi_awaddr_out_c,
DINA => S_AXI_WDATA,
DOUTA => DOUTA,
--Port B:
CLKB => S_AClk,
RSTB => s_aresetn_a_c,
ENB => s_axi_rd_en_c,
REGCEB => regceb_c,
WEB => (OTHERS => '0'),
ADDRB => s_axi_araddr_out_c,
DINB => DINB,
DOUTB => s_axi_rdata_c,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => '0',
SLEEP => '0',
RDADDRECC => RDADDRECC
);
axi_rd_sm : blk_mem_axi_read_wrapper_beh
GENERIC MAP (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_PIPELINE_STAGES => 1,
C_AXI_ARADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_AClk,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Read Side
S_AXI_ARADDR => S_AXI_ARADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARSIZE => S_AXI_ARSIZE,
S_AXI_ARBURST => S_AXI_ARBURST,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => s_axi_rlast_c,
S_AXI_RVALID => s_axi_rvalid_c,
S_AXI_RREADY => s_axi_rready_c,
S_AXI_ARID => S_AXI_ARID,
S_AXI_RID => s_axi_rid_c,
-- AXI Full/Lite Read FSM Outputs
S_AXI_ARADDR_OUT => s_axi_araddr_out_c,
S_AXI_RD_EN => s_axi_rd_en_c
);
END GENERATE axi_mem_module;
END behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_clr is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_clr;
architecture beh_ff_clr_arch of beh_ff_clr is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(CLR, C)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_clr_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_ce is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_ce;
architecture beh_ff_ce_arch of beh_ff_ce is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, CLR)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
if (CE = '1') then
q_o <= D after 100 ps;
end if;
end if;
end process;
end beh_ff_ce_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_pre is
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end beh_ff_pre;
architecture beh_ff_pre_arch of beh_ff_pre is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, PRE)
begin
if (PRE = '1') then
q_o <= '1';
elsif (C' event and C = '1') then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_pre_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_muxf7 is
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end beh_muxf7;
architecture beh_muxf7_arch of beh_muxf7 is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
else
O <= I1;
end if;
end process;
end beh_muxf7_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity STATE_LOGIC is
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic := '0';
I0 : in std_logic := '0';
I1 : in std_logic := '0';
I2 : in std_logic := '0';
I3 : in std_logic := '0';
I4 : in std_logic := '0';
I5 : in std_logic := '0'
);
end STATE_LOGIC;
architecture STATE_LOGIC_arch of STATE_LOGIC is
constant INIT_reg : std_logic_vector(63 downto 0) := INIT;
begin
LUT_beh:process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
begin
I_reg := I5 & I4 & I3 & I2 & I1 & I0;
O <= INIT_reg(conv_integer(I_reg));
end process;
end STATE_LOGIC_arch;
|
-------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v8_3_1.vhd
--
-- Description:
-- This file is the VHDL behvarial model for the
-- Block Memory Generator Core.
--
-------------------------------------------------------------------------------
-- Author: Xilinx
--
-- History: January 11, 2006: Initial revision
-- June 11, 2007 : Added independent register stages for
-- Port A and Port B (IP1_Jm/v2.5)
-- August 28, 2007 : Added mux pipeline stages feature (IP2_Jm/v2.6)
-- April 07, 2009 : Added support for Spartan-6 and Virtex-6
-- features, including the following:
-- (i) error injection, detection and/or correction
-- (ii) reset priority
-- (iii) special reset behavior
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
ENTITY blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END ENTITY blk_mem_axi_regs_fwd_v8_3;
ARCHITECTURE axi_regs_fwd_arch OF blk_mem_axi_regs_fwd_v8_3 IS
SIGNAL STORAGE_DATA : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_READY_I : STD_LOGIC := '0';
SIGNAL M_VALID_I : STD_LOGIC := '0';
SIGNAL ARESET_D : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');-- Reset delay register
BEGIN
--assign local signal to its output signal
S_READY <= S_READY_I;
M_VALID <= M_VALID_I;
PROCESS(ACLK)
BEGIN
IF(ACLK'event AND ACLK = '1') THEN
ARESET_D <= ARESET_D(0) & ARESET;
END IF;
END PROCESS;
--Save payload data whenever we have a transaction on the slave side
PROCESS(ACLK, ARESET)
BEGIN
IF (ARESET = '1') THEN
STORAGE_DATA <= (OTHERS => '0');
ELSIF(ACLK'event AND ACLK = '1') THEN
IF(S_VALID = '1' AND S_READY_I = '1') THEN
STORAGE_DATA <= S_PAYLOAD_DATA;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= STORAGE_DATA;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
PROCESS(ACLK,ARESET)
BEGIN
IF (ARESET_D /= "00") THEN
M_VALID_I <= '0';
ELSIF(ACLK'event AND ACLK = '1') THEN
IF (S_VALID = '1') THEN
--Always set M_VALID_I when slave side is valid
M_VALID_I <= '1';
ELSIF (M_READY = '1') THEN
--Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= '0';
END IF;
END IF;
END PROCESS;
--Slave Ready is either when Master side drives M_READY or we have space in our storage data
S_READY_I <= (M_READY OR (NOT M_VALID_I)) AND NOT(OR_REDUCE(ARESET_D));
END axi_regs_fwd_arch;
-------------------------------------------------------------------------------
-- Description:
-- This is the behavioral model of write_wrapper for the
-- Block Memory Generator Core.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_axi_write_wrapper_beh IS
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END blk_mem_axi_write_wrapper_beh;
ARCHITECTURE axi_write_wrap_arch OF blk_mem_axi_write_wrapper_beh IS
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_AXI_WDATA_WIDTH=8,0,
if_then_else((C_AXI_WDATA_WIDTH=16),1,
if_then_else((C_AXI_WDATA_WIDTH=32),2,
if_then_else((C_AXI_WDATA_WIDTH=64),3,
if_then_else((C_AXI_WDATA_WIDTH=128),4,
if_then_else((C_AXI_WDATA_WIDTH=256),5,0))))));
SIGNAL bvalid_c : std_logic := '0';
SIGNAL bready_timeout_c : std_logic := '0';
SIGNAL bvalid_rd_cnt_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_r : std_logic := '0';
SIGNAL bvalid_count_r : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL awaddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
C_AXI_AWADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL bvalid_wr_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_rd_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_last_c : std_logic := '0';
SIGNAL addr_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL aw_ready_r : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL awlen_cntr_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1');
SIGNAL awlen_int : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL awburst_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes : integer := 0;
SIGNAL wrap_boundary : integer := 0;
SIGNAL wrap_base_addr : integer := 0;
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
-- Array to store BIDs
TYPE id_array IS ARRAY (3 DOWNTO 0) OF std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
SIGNAL axi_bid_array : id_array := (others => (others => '0'));
COMPONENT write_netlist
GENERIC(
C_AXI_TYPE : integer
);
PORT(
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
S_AXI_AWVALID : IN std_logic;
aw_ready_r : OUT std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN std_logic;
S_AXI_WR_EN : OUT std_logic;
w_last_c : IN std_logic;
bready_timeout_c : IN std_logic;
addr_en_c : OUT std_logic;
incr_addr_c : OUT std_logic;
bvalid_c : OUT std_logic
);
END COMPONENT write_netlist;
BEGIN
---------------------------------------
--AXI WRITE FSM COMPONENT INSTANTIATION
---------------------------------------
axi_wr_fsm : write_netlist
GENERIC MAP (
C_AXI_TYPE => C_AXI_TYPE
)
PORT MAP (
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
S_AXI_AWVALID => S_AXI_AWVALID,
aw_ready_r => aw_ready_r,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BVALID => OPEN,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_WR_EN => S_AXI_WR_EN,
w_last_c => w_last_c,
bready_timeout_c => bready_timeout_c,
addr_en_c => addr_en_c,
incr_addr_c => incr_addr_c,
bvalid_c => bvalid_c
);
--Wrap Address boundary calculation
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWSIZE,"000"));
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(awlen_int)+1);
wrap_base_addr <= (conv_integer(awaddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary <= wrap_base_addr+total_bytes;
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awaddr_reg <= (OTHERS => '0');
num_of_bytes_r <= 0;
awburst_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awaddr_reg <= S_AXI_AWADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWBURST,"01");
ELSIF (incr_addr_c = '1') THEN
IF (awburst_int = "10") THEN
IF(conv_integer(awaddr_reg) = (wrap_boundary-num_of_bytes_r)) THEN
awaddr_reg <= conv_std_logic_vector(wrap_base_addr,C_AXI_AWADDR_WIDTH);
ELSE
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
ELSIF (awburst_int = "01" OR awburst_int = "11") THEN
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
S_AXI_AWADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
awaddr_reg(C_AXI_AWADDR_WIDTH-1 DOWNTO C_RANGE),awaddr_reg);
---------------------------------------------------------------------------
-- AXI wlast generation
---------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awlen_cntr_r <= (OTHERS => '1');
awlen_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awlen_int <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
awlen_cntr_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
ELSIF (dec_alen_c = '1') THEN
awlen_cntr_r <= awlen_cntr_r - ONE AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
w_last_c <= '1' WHEN (awlen_cntr_r = "00000000" AND S_AXI_WVALID = '1') ELSE '0';
dec_alen_c <= (incr_addr_c OR w_last_c);
---------------------------------------------------------------------------
-- Generation of bvalid counter for outstanding transactions
---------------------------------------------------------------------------
P_b_valid_os_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_count_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- bvalid_count_r generation
IF (bvalid_c = '1' AND bvalid_r = '1' AND S_AXI_BREADY = '1') THEN
bvalid_count_r <= bvalid_count_r AFTER FLOP_DELAY;
ELSIF (bvalid_c = '1') THEN
bvalid_count_r <= bvalid_count_r + "01" AFTER FLOP_DELAY;
ELSIF (bvalid_r = '1' AND S_AXI_BREADY = '1' AND bvalid_count_r /= "0") THEN
bvalid_count_r <= bvalid_count_r - "01" AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_os_r ;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is used
---------------------------------------------------------------------------
gaxi_bvalid_id_r:IF (C_HAS_AXI_ID = 1) GENERATE
SIGNAL bvalid_d1_c : std_logic := '0';
BEGIN
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
bvalid_d1_c <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
--external bvalid signal generation
IF (bvalid_d1_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_id_r;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is not used
---------------------------------------------------------------------------
gaxi_bvalid_noid_r:IF (C_HAS_AXI_ID = 0) GENERATE
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
--external bvalid signal generation
IF (bvalid_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_noid_r;
---------------------------------------------------------------------------
-- Generation of Bready timeout
---------------------------------------------------------------------------
P_brdy_tout_c: PROCESS (bvalid_count_r)
BEGIN
-- bready_timeout_c generation
IF(conv_integer(bvalid_count_r) = C_AXI_OS_WR-1) THEN
bready_timeout_c <= '1';
ELSE
bready_timeout_c <= '0';
END IF;
END PROCESS P_brdy_tout_c;
---------------------------------------------------------------------------
-- Generation of BID
---------------------------------------------------------------------------
gaxi_bid_gen:IF (C_HAS_AXI_ID = 1) GENERATE
P_bid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
bvalid_wr_cnt_r <= (OTHERS => '0');
bvalid_rd_cnt_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- STORE AWID IN AN ARRAY
IF(bvalid_c = '1') THEN
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + "01";
END IF;
-- GENERATE BID FROM AWID ARRAY
bvalid_rd_cnt_r <= bvalid_rd_cnt_c AFTER FLOP_DELAY;
S_AXI_BID <= axi_bid_array(conv_integer(bvalid_rd_cnt_c));
END IF;
END PROCESS P_bid_gen;
bvalid_rd_cnt_c <= bvalid_rd_cnt_r + "01" WHEN (bvalid_r = '1' AND S_AXI_BREADY = '1') ELSE bvalid_rd_cnt_r;
---------------------------------------------------------------------------
-- Storing AWID for generation of BID
---------------------------------------------------------------------------
P_awid_reg:PROCESS (S_ACLK)
BEGIN
IF (S_ACLK'event AND S_ACLK='1') THEN
IF(aw_ready_r = '1' AND S_AXI_AWVALID = '1') THEN
axi_bid_array(conv_integer(bvalid_wr_cnt_r)) <= S_AXI_AWID;
END IF;
END IF;
END PROCESS P_awid_reg;
END GENERATE gaxi_bid_gen;
S_AXI_BVALID <= bvalid_r;
S_AXI_AWREADY <= aw_ready_r;
END axi_write_wrap_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity write_netlist is
GENERIC(
C_AXI_TYPE : integer
);
port (
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_AWVALID : in STD_LOGIC := '0';
S_AXI_WVALID : in STD_LOGIC := '0';
S_AXI_BREADY : in STD_LOGIC := '0';
w_last_c : in STD_LOGIC := '0';
bready_timeout_c : in STD_LOGIC := '0';
aw_ready_r : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_WR_EN : out STD_LOGIC;
addr_en_c : out STD_LOGIC;
incr_addr_c : out STD_LOGIC;
bvalid_c : out STD_LOGIC
);
end write_netlist;
architecture STRUCTURE of write_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
BEGIN
---------------------------------------------------------------------------
-- AXI LITE
---------------------------------------------------------------------------
gbeh_axi_lite_sm: IF (C_AXI_TYPE = 0 ) GENERATE
signal w_ready_r_7 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSignal_bvalid_c : STD_LOGIC;
signal NlwRenamedSignal_incr_addr_c : STD_LOGIC;
signal present_state_FSM_FFd3_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal present_state_FSM_FFd1_15 : STD_LOGIC;
signal present_state_FSM_FFd4_16 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd4_In1_21 : STD_LOGIC;
signal Mmux_aw_ready_c : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
S_AXI_WREADY <= w_ready_r_7;
S_AXI_BVALID <= NlwRenamedSignal_incr_addr_c;
S_AXI_WR_EN <= NlwRenamedSignal_bvalid_c;
incr_addr_c <= NlwRenamedSignal_incr_addr_c;
bvalid_c <= NlwRenamedSignal_bvalid_c;
NlwRenamedSignal_incr_addr_c <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_7
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_16
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_13
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_15
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000055554440"
)
port map (
I0 => S_AXI_WVALID,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => '0',
O => present_state_FSM_FFd3_In
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"0000000088880800"
)
port map (
I0 => S_AXI_AWVALID,
I1 => S_AXI_WVALID,
I2 => bready_timeout_c,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => present_state_FSM_FFd2_In
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAA2000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_WVALID,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => addr_en_c
);
Mmux_w_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"F5F07570F5F05500"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => w_ready_c
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd3_13,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd1_15,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_14,
I2 => present_state_FSM_FFd3_13,
I3 => '0',
I4 => '0',
I5 => '0',
O => NlwRenamedSignal_bvalid_c
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"2F0F27072F0F2200"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => present_state_FSM_FFd4_In1_21
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_In1_21,
I3 => '0',
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_aw_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"7535753575305500"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => S_AXI_WVALID,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => present_state_FSM_FFd2_14,
O => Mmux_aw_ready_c(0)
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => Mmux_aw_ready_c(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => aw_ready_c
);
END GENERATE gbeh_axi_lite_sm;
---------------------------------------------------------------------------
-- AXI FULL
---------------------------------------------------------------------------
gbeh_axi_full_sm: IF (C_AXI_TYPE = 1 ) GENERATE
signal w_ready_r_8 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSig_OI_bvalid_c : STD_LOGIC;
signal present_state_FSM_FFd1_16 : STD_LOGIC;
signal present_state_FSM_FFd4_17 : STD_LOGIC;
signal present_state_FSM_FFd3_18 : STD_LOGIC;
signal present_state_FSM_FFd2_19 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd2_In1_24 : STD_LOGIC;
signal present_state_FSM_FFd4_In1_25 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal N4 : STD_LOGIC;
begin
S_AXI_WREADY <= w_ready_r_8;
bvalid_c <= NlwRenamedSig_OI_bvalid_c;
S_AXI_BVALID <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_8
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_17
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_18
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_19
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_16
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000000005540"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd4_17,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd3_In
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"BF3FBB33AF0FAA00"
)
port map (
I0 => S_AXI_BREADY,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd1_16,
I4 => present_state_FSM_FFd4_17,
I5 => NlwRenamedSig_OI_bvalid_c,
O => aw_ready_c
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"AAAAAAAA20000000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_19,
I3 => S_AXI_WVALID,
I4 => w_last_c,
I5 => present_state_FSM_FFd4_17,
O => addr_en_c
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_19,
I2 => present_state_FSM_FFd3_18,
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_WR_EN
);
Mmux_incr_addr_c_0_1 : STATE_LOGIC
generic map(
INIT => X"0000000000002220"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => incr_addr_c
);
Mmux_aw_ready_c_0_11 : STATE_LOGIC
generic map(
INIT => X"0000000000008880"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => NlwRenamedSig_OI_bvalid_c
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"000000000000D5C0"
)
port map (
I0 => w_last_c,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd4_17,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd2_In1_24
);
present_state_FSM_FFd2_In2 : STATE_LOGIC
generic map(
INIT => X"FFFFAAAA08AAAAAA"
)
port map (
I0 => present_state_FSM_FFd2_19,
I1 => S_AXI_AWVALID,
I2 => bready_timeout_c,
I3 => w_last_c,
I4 => S_AXI_WVALID,
I5 => present_state_FSM_FFd2_In1_24,
O => present_state_FSM_FFd2_In
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"00C0004000C00000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => w_last_c,
I2 => S_AXI_WVALID,
I3 => bready_timeout_c,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => present_state_FSM_FFd4_In1_25
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88F8"
)
port map (
I0 => present_state_FSM_FFd1_16,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_17,
I3 => S_AXI_AWVALID,
I4 => present_state_FSM_FFd4_In1_25,
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_w_ready_c_0_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => w_last_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_w_ready_c_0_Q : STATE_LOGIC
generic map(
INIT => X"FABAFABAFAAAF000"
)
port map (
I0 => N2,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd4_17,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => w_ready_c
);
Mmux_aw_ready_c_0_11_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => bready_timeout_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => w_last_c,
I1 => N4,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => present_state_FSM_FFd1_16,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
END GENERATE gbeh_axi_full_sm;
end STRUCTURE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--AXI Behavioral Model entities
ENTITY blk_mem_axi_read_wrapper_beh is
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
port (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END blk_mem_axi_read_wrapper_beh;
architecture blk_mem_axi_read_wrapper_beh_arch of blk_mem_axi_read_wrapper_beh is
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_WRITE_WIDTH_A=8,0,
if_then_else((C_WRITE_WIDTH_A=16),1,
if_then_else((C_WRITE_WIDTH_A=32),2,
if_then_else((C_WRITE_WIDTH_A=64),3,
if_then_else((C_WRITE_WIDTH_A=128),4,
if_then_else((C_WRITE_WIDTH_A=256),5,0))))));
SIGNAL ar_id_r : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
SIGNAL addr_en_c : std_logic := '0';
SIGNAL rd_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL single_trans_c : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL mux_sel_c : std_logic := '0';
SIGNAL r_last_c : std_logic := '0';
SIGNAL r_last_int_c : std_logic := '0';
SIGNAL arlen_int_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL arlen_cntr : std_logic_vector(7 DOWNTO 0) := ONE;
SIGNAL arburst_int_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL arburst_int_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL araddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),C_AXI_ARADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL total_bytes : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
SIGNAL wrap_base_addr_r : integer := 0;
SIGNAL wrap_boundary_r : integer := 0;
SIGNAL arlen_int_c : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes_c : integer := 0;
SIGNAL wrap_base_addr_c : integer := 0;
SIGNAL wrap_boundary_c : integer := 0;
SIGNAL araddr_out : std_logic_vector(C_ADDRB_WIDTH-1 downto 0) := (OTHERS => '0');
COMPONENT read_netlist
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_INCR_ADDR : OUT std_logic := '0';
S_AXI_ADDR_EN : OUT std_logic := '0';
S_AXI_SINGLE_TRANS : OUT std_logic := '0';
S_AXI_MUX_SEL : OUT std_logic := '0';
S_AXI_R_LAST : OUT std_logic := '0';
S_AXI_R_LAST_INT : IN std_logic := '0';
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT read_netlist;
BEGIN
dec_alen_c <= incr_addr_c OR r_last_int_c;
axi_read_fsm : read_netlist
GENERIC MAP(
C_AXI_TYPE => 1,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
S_AXI_INCR_ADDR => incr_addr_c,
S_AXI_ADDR_EN => addr_en_c,
S_AXI_SINGLE_TRANS => single_trans_c,
S_AXI_MUX_SEL => mux_sel_c,
S_AXI_R_LAST => r_last_c,
S_AXI_R_LAST_INT => r_last_int_c,
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN => rd_en_c
);
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(arlen_int_r)+1);
wrap_base_addr_r <= (conv_integer(araddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary_r <= wrap_base_addr_r+total_bytes;
---- combinatorial from interface
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARSIZE,"000"));
arlen_int_c <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
total_bytes_c <= conv_integer(num_of_bytes_c)*(conv_integer(arlen_int_c)+1);
wrap_base_addr_c <= (conv_integer(S_AXI_ARADDR)/if_then_else(total_bytes_c=0,1,total_bytes_c))*(total_bytes_c);
wrap_boundary_c <= wrap_base_addr_c+total_bytes_c;
arburst_int_c <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARBURST,"01");
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
araddr_reg <= (OTHERS => '0');
arburst_int_r <= (OTHERS => '0');
num_of_bytes_r <= 0;
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (incr_addr_c = '1' AND addr_en_c = '1' AND single_trans_c = '0') THEN
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
IF (arburst_int_c = "10") THEN
IF(conv_integer(S_AXI_ARADDR) = (wrap_boundary_c-num_of_bytes_c)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_c,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (arburst_int_c = "01" OR arburst_int_c = "11") THEN
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (addr_en_c = '1') THEN
araddr_reg <= S_AXI_ARADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
ELSIF (incr_addr_c = '1') THEN
IF (arburst_int_r = "10") THEN
IF(conv_integer(araddr_reg) = (wrap_boundary_r-num_of_bytes_r)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_r,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
ELSIF (arburst_int_r = "01" OR arburst_int_r = "11") THEN
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
araddr_out <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),araddr_reg(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),araddr_reg);
--------------------------------------------------------------------------
-- Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
--------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF S_ARESETN = '1' THEN
arlen_cntr <= ONE;
arlen_int_r <= (OTHERS => '0');
ELSIF S_ACLK'event AND S_ACLK = '1' THEN
IF (addr_en_c = '1' AND dec_alen_c = '1' AND single_trans_c = '0') THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= S_AXI_ARLEN - ONE AFTER FLOP_DELAY;
ELSIF addr_en_c = '1' THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
ELSIF dec_alen_c = '1' THEN
arlen_cntr <= arlen_cntr - ONE AFTER FLOP_DELAY;
ELSE
arlen_cntr <= arlen_cntr AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
r_last_int_c <= '1' WHEN (arlen_cntr = "00000000" AND S_AXI_RREADY = '1') ELSE '0' ;
--------------------------------------------------------------------------
-- AXI FULL FSM
-- Mux Selection of ARADDR
-- ARADDR is driven out from the read fsm based on the mux_sel_c
-- Based on mux_sel either ARADDR is given out or the latched ARADDR is
-- given out to BRAM
--------------------------------------------------------------------------
P_araddr_mux: PROCESS (mux_sel_c,S_AXI_ARADDR,araddr_out)
BEGIN
IF (mux_sel_c = '0') THEN
S_AXI_ARADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARADDR(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),S_AXI_ARADDR);
ELSE
S_AXI_ARADDR_OUT <= araddr_out;
END IF;
END PROCESS P_araddr_mux;
--------------------------------------------------------------------------
-- Assign output signals - AXI FULL FSM
--------------------------------------------------------------------------
S_AXI_RD_EN <= rd_en_c;
grid: IF (C_HAS_AXI_ID = 1) GENERATE
P_rid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
S_AXI_RID <= (OTHERS => '0');
ar_id_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
IF (addr_en_c = '1' AND rd_en_c = '1') THEN
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
ELSIF (addr_en_c = '1' AND rd_en_c = '0') THEN
ar_id_r <= S_AXI_ARID;
ELSIF (rd_en_c = '1') THEN
S_AXI_RID <= ar_id_r;
END IF;
END IF;
END PROCESS P_rid_gen;
END GENERATE grid;
END blk_mem_axi_read_wrapper_beh_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity read_netlist is
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_R_LAST_INT : in STD_LOGIC := '0';
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_ARVALID : in STD_LOGIC := '0';
S_AXI_RREADY : in STD_LOGIC := '0';
S_AXI_INCR_ADDR : out STD_LOGIC;
S_AXI_ADDR_EN : out STD_LOGIC;
S_AXI_SINGLE_TRANS : out STD_LOGIC;
S_AXI_MUX_SEL : out STD_LOGIC;
S_AXI_R_LAST : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RLAST : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RD_EN : out STD_LOGIC;
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end read_netlist;
architecture STRUCTURE of read_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
signal present_state_FSM_FFd1_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_r_15 : STD_LOGIC;
signal gaxi_full_sm_ar_ready_r_16 : STD_LOGIC;
signal gaxi_full_sm_r_last_r_17 : STD_LOGIC;
signal NlwRenamedSig_OI_gaxi_full_sm_r_valid_r : STD_LOGIC;
signal gaxi_full_sm_r_valid_c : STD_LOGIC;
signal S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o : STD_LOGIC;
signal gaxi_full_sm_ar_ready_c : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_c : STD_LOGIC;
signal NlwRenamedSig_OI_S_AXI_R_LAST : STD_LOGIC;
signal S_AXI_ARLEN_7_GND_8_o_equal_1_o : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal Mmux_S_AXI_R_LAST13 : STD_LOGIC;
signal N01 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal Mmux_gaxi_full_sm_ar_ready_c11 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N8 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N13 : STD_LOGIC;
begin
S_AXI_R_LAST <= NlwRenamedSig_OI_S_AXI_R_LAST;
S_AXI_ARREADY <= gaxi_full_sm_ar_ready_r_16;
S_AXI_RLAST <= gaxi_full_sm_r_last_r_17;
S_AXI_RVALID <= NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
gaxi_full_sm_outstanding_read_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_outstanding_read_c,
Q => gaxi_full_sm_outstanding_read_r_15
);
gaxi_full_sm_r_valid_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => gaxi_full_sm_r_valid_c,
Q => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r
);
gaxi_full_sm_ar_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_ar_ready_c,
Q => gaxi_full_sm_ar_ready_r_16
);
gaxi_full_sm_r_last_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => NlwRenamedSig_OI_S_AXI_R_LAST,
Q => gaxi_full_sm_r_last_r_17
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_13
);
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 : STATE_LOGIC
generic map(
INIT => X"000000000000000B"
)
port map (
I0 => S_AXI_RREADY,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o
);
Mmux_S_AXI_SINGLE_TRANS11 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_SINGLE_TRANS
);
Mmux_S_AXI_ADDR_EN11 : STATE_LOGIC
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_ADDR_EN
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"ECEE2022EEEE2022"
)
port map (
I0 => S_AXI_ARVALID,
I1 => present_state_FSM_FFd1_13,
I2 => S_AXI_RREADY,
I3 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I4 => present_state_FSM_FFd2_14,
I5 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
O => present_state_FSM_FFd2_In
);
Mmux_S_AXI_R_LAST131 : STATE_LOGIC
generic map(
INIT => X"0000000044440444"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_RREADY,
I5 => '0',
O => Mmux_S_AXI_R_LAST13
);
Mmux_S_AXI_INCR_ADDR11 : STATE_LOGIC
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => S_AXI_R_LAST_INT,
I1 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => Mmux_S_AXI_R_LAST13,
O => S_AXI_INCR_ADDR
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000FE"
)
port map (
I0 => S_AXI_ARLEN(2),
I1 => S_AXI_ARLEN(1),
I2 => S_AXI_ARLEN(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => N01
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q : STATE_LOGIC
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => S_AXI_ARLEN(7),
I1 => S_AXI_ARLEN(6),
I2 => S_AXI_ARLEN(5),
I3 => S_AXI_ARLEN(4),
I4 => S_AXI_ARLEN(3),
I5 => N01,
O => S_AXI_ARLEN_7_GND_8_o_equal_1_o
);
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_gaxi_full_sm_outstanding_read_c1 : STATE_LOGIC
generic map(
INIT => X"0020000002200200"
)
port map (
I0 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd1_13,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => N2,
O => gaxi_full_sm_outstanding_read_c
);
Mmux_gaxi_full_sm_ar_ready_c12 : STATE_LOGIC
generic map(
INIT => X"0000000000004555"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => '0',
I5 => '0',
O => Mmux_gaxi_full_sm_ar_ready_c11
);
Mmux_S_AXI_R_LAST11_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000EF"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
Mmux_S_AXI_R_LAST11 : STATE_LOGIC
generic map(
INIT => X"FCAAFC0A00AA000A"
)
port map (
I0 => S_AXI_ARVALID,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => N4,
I5 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
O => gaxi_full_sm_r_valid_c
);
S_AXI_MUX_SEL1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAAAA08"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => '0',
O => S_AXI_MUX_SEL
);
Mmux_S_AXI_RD_EN11 : STATE_LOGIC
generic map(
INIT => X"F3F3F755A2A2A200"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => gaxi_full_sm_outstanding_read_r_15,
I4 => present_state_FSM_FFd2_14,
I5 => S_AXI_ARVALID,
O => S_AXI_RD_EN
);
present_state_FSM_FFd1_In3 : beh_muxf7
port map (
I0 => N8,
I1 => N9,
S => present_state_FSM_FFd1_13,
O => present_state_FSM_FFd1_In
);
present_state_FSM_FFd1_In3_F : STATE_LOGIC
generic map(
INIT => X"000000005410F4F0"
)
port map (
I0 => S_AXI_RREADY,
I1 => present_state_FSM_FFd2_14,
I2 => S_AXI_ARVALID,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => '0',
O => N8
);
present_state_FSM_FFd1_In3_G : STATE_LOGIC
generic map(
INIT => X"0000000072FF7272"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N9
);
Mmux_gaxi_full_sm_ar_ready_c14 : beh_muxf7
port map (
I0 => N10,
I1 => N11,
S => present_state_FSM_FFd1_13,
O => gaxi_full_sm_ar_ready_c
);
Mmux_gaxi_full_sm_ar_ready_c14_F : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88A8"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => Mmux_gaxi_full_sm_ar_ready_c11,
I5 => '0',
O => N10
);
Mmux_gaxi_full_sm_ar_ready_c14_G : STATE_LOGIC
generic map(
INIT => X"000000008D008D8D"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N11
);
Mmux_S_AXI_R_LAST1 : beh_muxf7
port map (
I0 => N12,
I1 => N13,
S => present_state_FSM_FFd1_13,
O => NlwRenamedSig_OI_S_AXI_R_LAST
);
Mmux_S_AXI_R_LAST1_F : STATE_LOGIC
generic map(
INIT => X"0000000088088888"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N12
);
Mmux_S_AXI_R_LAST1_G : STATE_LOGIC
generic map(
INIT => X"00000000E400E4E4"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => S_AXI_R_LAST_INT,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N13
);
end STRUCTURE;
-------------------------------------------------------------------------------
-- Output Register Stage Entity
--
-- This module builds the output register stages of the memory. This module is
-- instantiated in the main memory module (blk_mem_gen_v8_3_1) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_output_stage IS
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_output_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6" and "virtex6l".
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
-- C_HAS_RST : Determines the presence of the RST port
-- C_RSTRAM : Determines if special reset behavior is used
-- C_RST_PRIORITY : Determines the priority between CE and SR
-- C_INIT_VAL : Initialization value
-- C_HAS_EN : Determines the presence of the EN port
-- C_HAS_REGCE : Determines the presence of the REGCE port
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
-- of the RAM primitive
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- NUM_STAGES : Determines the number of output stages
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE output_stage_behavioral OF blk_mem_gen_v8_3_1_output_stage IS
--*******************************************************
-- Functions used in the output stage ARCHITECTURE
--*******************************************************
-- Calculate num_reg_stages
FUNCTION get_num_reg_stages(NUM_STAGES: INTEGER) RETURN INTEGER IS
VARIABLE num_reg_stages : INTEGER := 0;
BEGIN
IF (NUM_STAGES = 0) THEN
num_reg_stages := 0;
ELSE
num_reg_stages := NUM_STAGES - 1;
END IF;
RETURN num_reg_stages;
END get_num_reg_stages;
-- Check if the INTEGER is zero or non-zero
FUNCTION int_to_bit(input: INTEGER) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = 0) THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END int_to_bit;
-- Constants
CONSTANT HAS_EN : STD_LOGIC := int_to_bit(C_HAS_EN);
CONSTANT HAS_REGCE : STD_LOGIC := int_to_bit(C_HAS_REGCE);
CONSTANT HAS_RST : STD_LOGIC := int_to_bit(C_HAS_RST);
CONSTANT REG_STAGES : INTEGER := get_num_reg_stages(NUM_STAGES);
-- Pipeline array
TYPE reg_data_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
TYPE reg_ecc_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC;
TYPE reg_eccaddr_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
CONSTANT REG_INIT : reg_data_array := (OTHERS => init_val);
SIGNAL out_regs : reg_data_array := REG_INIT;
SIGNAL sbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL dbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL rdaddrecc_regs: reg_eccaddr_array := (OTHERS => (OTHERS => '0'));
-- Internal signals
SIGNAL en_i : STD_LOGIC;
SIGNAL regce_i : STD_LOGIC;
SIGNAL rst_i : STD_LOGIC;
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := init_val;
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL DIN : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL RDADDRECC_IN : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ;
SIGNAL SBITERR_IN : STD_LOGIC := '0';
SIGNAL DBITERR_IN : STD_LOGIC := '0';
BEGIN
--***********************************************************************
-- Assign internal signals. This effectively wires off optional inputs.
--***********************************************************************
-- Internal enable for output registers is tied to user EN or '1' depending
-- on parameters
en_i <= EN OR (NOT HAS_EN);
-- Internal register enable for output registers is tied to user REGCE, EN
-- or '1' depending on parameters
regce_i <= (HAS_REGCE AND REGCE)
OR ((NOT HAS_REGCE) AND en_i);
-- Internal SRR is tied to user RST or '0' depending on parameters
rst_i <= RST AND HAS_RST;
--***************************************************************************
-- NUM_STAGES = 0 (No output registers. RAM only)
--***************************************************************************
zero_stages: IF (NUM_STAGES = 0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE zero_stages;
NO_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 0) GENERATE
DIN <= DIN_I;
RDADDRECC_IN <= RDADDRECC_IN_I;
SBITERR_IN <= SBITERR_IN_I;
DBITERR_IN <= DBITERR_IN_I;
END GENERATE NO_ECC_PIPE_REG;
WITH_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(ECCPIPECE = '1') THEN
DIN <= DIN_I AFTER FLOP_DELAY;
RDADDRECC_IN <= RDADDRECC_IN_I AFTER FLOP_DELAY;
SBITERR_IN <= SBITERR_IN_I AFTER FLOP_DELAY;
DBITERR_IN <= DBITERR_IN_I AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS;
END GENERATE WITH_ECC_PIPE_REG;
--***************************************************************************
-- NUM_STAGES = 1
-- (Mem Output Reg only or Mux Output Reg only)
--***************************************************************************
-- Possible valid combinations:
-- Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
-- +-----------------------------------------+
-- | C_RSTRAM_* | Reset Behavior |
-- +----------------+------------------------+
-- | 0 | Normal Behavior |
-- +----------------+------------------------+
-- | 1 | Special Behavior |
-- +----------------+------------------------+
--
-- Normal = REGCE gates reset, as in the case of all Virtex families and all
-- spartan families with the exception of S3ADSP and S6.
-- Special = EN gates reset, as in the case of S3ADSP and S6.
one_stage_norm: IF (NUM_STAGES = 1 AND
(C_RSTRAM=0 OR (C_RSTRAM=1 AND (C_XDEVICEFAMILY/="spartan3adsp" AND C_XDEVICEFAMILY/="aspartan3adsp")) OR
C_HAS_MEM_OUTPUT_REGS=0 OR C_HAS_RST=0)) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i = '1' AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
END IF;--CLK
END PROCESS;
END GENERATE one_stage_norm;
-- Special Reset Behavior for S6 and S3ADSP
one_stage_splbhv: IF (NUM_STAGES=1 AND C_RSTRAM=1 AND (C_XDEVICEFAMILY ="spartan3adsp" OR C_XDEVICEFAMILY ="aspartan3adsp"))
GENERATE
DOUT <= dout_i;
SBITERR <= '0';
DBITERR <= '0';
RDADDRECC <= (OTHERS => '0');
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (rst_i='1' AND en_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
ELSIF (regce_i='1' AND rst_i/='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE one_stage_splbhv;
--****************************************************************************
-- NUM_STAGES > 1
-- Mem Output Reg + Mux Output Reg
-- or
-- Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
-- or
-- Mux Pipeline Stages (>0) + Mux Output Reg
--****************************************************************************
multi_stage: IF (NUM_STAGES > 1) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i='1'AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
IF (en_i='1') THEN
-- Shift the data through the output stages
FOR i IN 1 TO REG_STAGES-1 LOOP
out_regs(i) <= out_regs(i-1) AFTER FLOP_DELAY;
sbiterr_regs(i) <= sbiterr_regs(i-1) AFTER FLOP_DELAY;
dbiterr_regs(i) <= dbiterr_regs(i-1) AFTER FLOP_DELAY;
rdaddrecc_regs(i) <= rdaddrecc_regs(i-1) AFTER FLOP_DELAY;
END LOOP;
out_regs(0) <= DIN;
sbiterr_regs(0) <= SBITERR_IN;
dbiterr_regs(0) <= DBITERR_IN;
rdaddrecc_regs(0) <= RDADDRECC_IN;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE multi_stage;
END output_stage_behavioral;
-------------------------------------------------------------------------------
-- SoftECC Output Register Stage Entity
-- This module builds the softecc output register stages. This module is
-- instantiated in the memory module (blk_mem_gen_v8_3_1_mem_module) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ;
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- of the RAM primitive
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE softecc_output_reg_stage_behavioral OF blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
-- Internal signals
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
--***************************************************************************
-- NO OUTPUT STAGES
--***************************************************************************
no_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE no_output_stage;
--****************************************************************************
-- WITH OUTPUT STAGE
--****************************************************************************
has_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END PROCESS;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
END GENERATE has_output_stage;
END softecc_output_reg_stage_behavioral;
--******************************************************************************
-- Main Memory module
--
-- This module is the behavioral model which implements the RAM
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
ENTITY blk_mem_gen_v8_3_1_mem_module IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_mem_module;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE mem_module_behavioral OF blk_mem_gen_v8_3_1_mem_module IS
--****************************************
-- min/max constant functions
--****************************************
-- get_max
----------
function SLV_TO_INT(SLV: in std_logic_vector
) return integer is
variable int : integer;
begin
int := 0;
for i in SLV'high downto SLV'low loop
int := int * 2;
if SLV(i) = '1' then
int := int + 1;
end if;
end loop;
return int;
end;
FUNCTION get_max(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a > b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-- get_min
----------
FUNCTION get_min(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
--***************************************************************
-- convert write_mode from STRING type for use in case statement
--***************************************************************
FUNCTION write_mode_to_vector(mode: STRING) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF (mode = "NO_CHANGE") THEN
RETURN "10";
ELSIF (mode = "READ_FIRST") THEN
RETURN "01";
ELSE
RETURN "00"; -- WRITE_FIRST
END IF;
END FUNCTION;
--***************************************************************
-- convert hex STRING to STD_LOGIC_VECTOR
--***************************************************************
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
--***************************************************************
-- locally derived constants to determine memory shape
--***************************************************************
CONSTANT MIN_WIDTH_A : INTEGER := get_min(C_WRITE_WIDTH_A, C_READ_WIDTH_A);
CONSTANT MIN_WIDTH_B : INTEGER := get_min(C_WRITE_WIDTH_B,C_READ_WIDTH_B);
CONSTANT MIN_WIDTH : INTEGER := get_min(MIN_WIDTH_A, MIN_WIDTH_B);
CONSTANT MAX_DEPTH_A : INTEGER := get_max(C_WRITE_DEPTH_A, C_READ_DEPTH_A);
CONSTANT MAX_DEPTH_B : INTEGER := get_max(C_WRITE_DEPTH_B, C_READ_DEPTH_B);
CONSTANT MAX_DEPTH : INTEGER := get_max(MAX_DEPTH_A, MAX_DEPTH_B);
TYPE int_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF std_logic_vector(C_WRITE_WIDTH_A-1 DOWNTO 0);
TYPE mem_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC_VECTOR(MIN_WIDTH-1 DOWNTO 0);
TYPE ecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
TYPE softecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
--***************************************************************
-- memory initialization function
--***************************************************************
IMPURE FUNCTION init_memory(DEFAULT_DATA :
STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
write_width_a : INTEGER;
depth : INTEGER;
width : INTEGER)
RETURN mem_array IS
VARIABLE init_return : mem_array := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(write_width_a-1 DOWNTO 0);
VARIABLE int_mem_vector : int_array:= (OTHERS => (OTHERS => '0'));
VARIABLE file_buffer : LINE;
VARIABLE i : INTEGER := 0;
VARIABLE j : INTEGER;
VARIABLE k : INTEGER;
VARIABLE ignore_line : BOOLEAN := false;
VARIABLE good_data : BOOLEAN := false;
VARIABLE char_tmp : CHARACTER;
VARIABLE index : INTEGER;
variable init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable data : std_logic_vector(255 downto 0) := (others => '0');
variable inside_init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable k_slv : std_logic_vector(31 downto 0) := (others => '0');
variable i_slv : std_logic_vector(31 downto 0) := (others => '0');
VARIABLE disp_line : line := null;
variable open_status : file_open_status;
variable input_initf_tmp : mem_array ;
variable input_initf : mem_array := (others => (others => '0'));
file int_infile : text;
variable data_line, data_line_tmp, out_data_line : line;
variable slv_width : integer;
VARIABLE d_l : LINE;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
index := 0;
FOR i IN 0 TO depth-1 LOOP
FOR j IN 0 TO width-1 LOOP
init_return(i)(j) := DEFAULT_DATA(index);
index := (index + 1) MOD C_WRITE_WIDTH_A;
END LOOP;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, file_buffer);
read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO write_width_a-1 LOOP
IF (j MOD width = 0 AND j /= 0) THEN
i := i + 1;
END IF;
init_return(i)(j MOD width) := bit_to_sl(mem_vector(j));
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
--Display output message indicating that the behavioral model is done
--initializing
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator data initialization complete." SEVERITY NOTE;
if (C_USE_BRAM_BLOCK = 1) then
--Display output message indicating that the behavioral model is being
--initialized
-- Read in the .mem file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_INIT_FILE /= "NONE") then
file_open(open_status, int_infile, C_INIT_FILE, read_mode);
while not endfile(int_infile) loop
readline(int_infile, data_line);
while (data_line /= null and data_line'length > 0) loop
if (data_line(data_line'low to data_line'low + 1) = "//") then
deallocate(data_line);
elsif ((data_line(data_line'low to data_line'low + 1) = "/*") and (data_line(data_line'high-1 to data_line'high) = "*/")) then
deallocate(data_line);
elsif (data_line(data_line'low to data_line'low + 1) = "/*") then
deallocate(data_line);
ignore_line := true;
elsif (ignore_line = true and data_line(data_line'high-1 to data_line'high) = "*/") then
deallocate(data_line);
ignore_line := false;
elsif (ignore_line = false and data_line(data_line'low) = '@') then
read(data_line, char_tmp);
hread(data_line, init_addr_slv, good_data);
i := SLV_TO_INT(init_addr_slv);
elsif (ignore_line = false) then
hread(data_line, input_initf_tmp(i), good_data);
init_return(i)(write_width_a - 1 downto 0) := input_initf_tmp(i)(write_width_a - 1 downto 0);
if (good_data = true) then
i := i + 1;
end if;
else
deallocate(data_line);
end if;
end loop;
end loop;
file_close(int_infile);
END IF;
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- memory type constants
--***************************************************************
CONSTANT MEM_TYPE_SP_RAM : INTEGER := 0;
CONSTANT MEM_TYPE_SDP_RAM : INTEGER := 1;
CONSTANT MEM_TYPE_TDP_RAM : INTEGER := 2;
CONSTANT MEM_TYPE_SP_ROM : INTEGER := 3;
CONSTANT MEM_TYPE_DP_ROM : INTEGER := 4;
--***************************************************************
-- memory configuration constant functions
--***************************************************************
--get_single_port
-----------------
FUNCTION get_single_port(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_RAM OR mem_type=MEM_TYPE_SP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_single_port;
--get_is_rom
--------------
FUNCTION get_is_rom(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_ROM OR mem_type=MEM_TYPE_DP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_is_rom;
--get_has_a_write
------------------
FUNCTION get_has_a_write(IS_ROM : INTEGER) RETURN INTEGER IS
BEGIN
IF (IS_ROM=0) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_a_write;
--get_has_b_write
------------------
FUNCTION get_has_b_write(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_TDP_RAM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_write;
--get_has_a_read
------------------
FUNCTION get_has_a_read(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SDP_RAM) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_a_read;
--get_has_b_read
------------------
FUNCTION get_has_b_read(SINGLE_PORT : INTEGER) RETURN INTEGER IS
BEGIN
IF (SINGLE_PORT=1) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_b_read;
--get_has_b_port
------------------
FUNCTION get_has_b_port(HAS_B_READ : INTEGER;
HAS_B_WRITE : INTEGER)
RETURN INTEGER IS
BEGIN
IF (HAS_B_READ=1 OR HAS_B_WRITE=1) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_port;
--get_num_output_stages
-----------------------
FUNCTION get_num_output_stages(has_mem_output_regs : INTEGER;
has_mux_output_regs : INTEGER;
mux_pipeline_stages : INTEGER)
RETURN INTEGER IS
VARIABLE actual_mux_pipeline_stages : INTEGER;
BEGIN
-- Mux pipeline stages can be non-zero only when there is a mux
-- output register.
IF (has_mux_output_regs=1) THEN
actual_mux_pipeline_stages := mux_pipeline_stages;
ELSE
actual_mux_pipeline_stages := 0;
END IF;
RETURN has_mem_output_regs+actual_mux_pipeline_stages+has_mux_output_regs;
END get_num_output_stages;
--***************************************************************************
-- Component declaration of the VARIABLE depth output register stage
--***************************************************************************
COMPONENT blk_mem_gen_v8_3_1_output_stage
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
EN : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
ECCPIPECE : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_output_stage;
COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************************************
-- locally derived constants to assist memory access
--******************************************************
CONSTANT WRITE_WIDTH_RATIO_A : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_A : INTEGER := C_READ_WIDTH_A/MIN_WIDTH;
CONSTANT WRITE_WIDTH_RATIO_B : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_B : INTEGER := C_READ_WIDTH_B/MIN_WIDTH;
--******************************************************
-- To modify the LSBs of the 'wider' data to the actual
-- address value
--******************************************************
CONSTANT WRITE_ADDR_A_DIV : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH_A;
CONSTANT READ_ADDR_A_DIV : INTEGER := C_READ_WIDTH_A/MIN_WIDTH_A;
CONSTANT WRITE_ADDR_B_DIV : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH_B;
CONSTANT READ_ADDR_B_DIV : INTEGER := C_READ_WIDTH_B/MIN_WIDTH_B;
--******************************************************
-- FUNCTION : log2roundup
--******************************************************
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
--******************************************************
-- Other constants and signals
--******************************************************
CONSTANT COLL_DELAY : TIME := 100 ps;
-- default data vector
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_DEFAULT_DATA,
C_WRITE_WIDTH_A);
CONSTANT CHKBIT_WIDTH : INTEGER := if_then_else(C_WRITE_WIDTH_A>57,8,if_then_else(C_WRITE_WIDTH_A>26,7,if_then_else(C_WRITE_WIDTH_A>11,6,if_then_else(C_WRITE_WIDTH_A>4,5,if_then_else(C_WRITE_WIDTH_A<5,4,0)))));
-- the init memory SIGNAL
SIGNAL memory_i : mem_array;
SIGNAL doublebit_error_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0);
SIGNAL current_contents_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
-- write mode constants
CONSTANT WRITE_MODE_A : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_A);
CONSTANT WRITE_MODE_B : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_B);
CONSTANT WRITE_MODES : STD_LOGIC_VECTOR(3 DOWNTO 0) :=
WRITE_MODE_A & WRITE_MODE_B;
-- reset values
CONSTANT INITA_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITA_VAL,
C_READ_WIDTH_A);
CONSTANT INITB_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITB_VAL,
C_READ_WIDTH_B);
-- memory output 'latches'
SIGNAL memory_out_a : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0) :=
INITA_VAL;
SIGNAL memory_out_b : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) :=
INITB_VAL;
SIGNAL sbiterr_in : STD_LOGIC := '0';
SIGNAL sbiterr_sdp : STD_LOGIC := '0';
SIGNAL dbiterr_in : STD_LOGIC := '0';
SIGNAL dbiterr_sdp : STD_LOGIC := '0';
SIGNAL rdaddrecc_in : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_sdp : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL doutb_i : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i : STD_LOGIC := '0';
SIGNAL dbiterr_i : STD_LOGIC := '0';
-- memory configuration constants
-----------------------------------------------
CONSTANT SINGLE_PORT : INTEGER := get_single_port(C_MEM_TYPE);
CONSTANT IS_ROM : INTEGER := get_is_rom(C_MEM_TYPE);
CONSTANT HAS_A_WRITE : INTEGER := get_has_a_write(IS_ROM);
CONSTANT HAS_B_WRITE : INTEGER := get_has_b_write(C_MEM_TYPE);
CONSTANT HAS_A_READ : INTEGER := get_has_a_read(C_MEM_TYPE);
CONSTANT HAS_B_READ : INTEGER := get_has_b_read(SINGLE_PORT);
CONSTANT HAS_B_PORT : INTEGER := get_has_b_port(HAS_B_READ, HAS_B_WRITE);
CONSTANT NUM_OUTPUT_STAGES_A : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_A,
C_MUX_PIPELINE_STAGES);
CONSTANT NUM_OUTPUT_STAGES_B : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES);
CONSTANT WEA0 : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT WEB0 : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-----------------------------------------------------------------------------
-- DEBUG CONTROL
-- DEBUG=0 : Debug output OFF
-- DEBUG=1 : Some debug info printed
-----------------------------------------------------------------------------
CONSTANT DEBUG : INTEGER := 0;
-- internal signals
-----------------------------------------------
SIGNAL ena_i : STD_LOGIC;
SIGNAL enb_i : STD_LOGIC;
SIGNAL reseta_i : STD_LOGIC;
SIGNAL resetb_i : STD_LOGIC;
SIGNAL wea_i : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL web_i : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL rea_i : STD_LOGIC;
SIGNAL reb_i : STD_LOGIC;
SIGNAL message_complete : BOOLEAN := false;
SIGNAL rsta_outp_stage : STD_LOGIC := '0';
SIGNAL rstb_outp_stage : STD_LOGIC := '0';
--*********************************************************
--FUNCTION : Collision check
--*********************************************************
FUNCTION collision_check (addr_a :
STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
iswrite_a : BOOLEAN;
addr_b :
STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
iswrite_b : BOOLEAN)
RETURN BOOLEAN IS
VARIABLE c_aw_bw : INTEGER;
VARIABLE c_aw_br : INTEGER;
VARIABLE c_ar_bw : INTEGER;
VARIABLE write_addr_a_width : INTEGER;
VARIABLE read_addr_a_width : INTEGER;
VARIABLE write_addr_b_width : INTEGER;
VARIABLE read_addr_b_width : INTEGER;
BEGIN
c_aw_bw := 0;
c_aw_br := 0;
c_ar_bw := 0;
-- Determine the effective address widths FOR each of the 4 ports
write_addr_a_width := C_ADDRA_WIDTH-log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width := C_ADDRA_WIDTH-log2roundup(READ_ADDR_A_DIV);
write_addr_b_width := C_ADDRB_WIDTH-log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width := C_ADDRB_WIDTH-log2roundup(READ_ADDR_B_DIV);
--Look FOR a write-write collision. In order FOR a write-write
--collision to exist, both ports must have a write transaction.
IF (iswrite_a AND iswrite_b) THEN
IF (write_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_a and iswrite_b
--If the B port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_a) THEN
IF (write_addr_a_width > read_addr_b_width) THEN
--read_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_b_width
--Once both are scaled to read_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
END IF; --width
END IF; --iswrite_a
--If the A port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_b) THEN
IF (read_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
ELSE
--read_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_a_width
--Once both are scaled to read_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_b
RETURN (c_aw_bw=1 OR c_aw_br=1 OR c_ar_bw=1);
END FUNCTION collision_check;
BEGIN -- Architecture
-----------------------------------------------------------------------------
-- SOFTECC and ECC SBITERR/DBITERR Outputs
-- The ECC Behavior is modeled by the behavioral models only for Virtex-6.
-- The SOFTECC Behavior is modeled by the behavioral models for Spartan-6.
-- For Virtex-5, these outputs will be tied to 0.
-----------------------------------------------------------------------------
SBITERR <= sbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_sdp WHEN (((C_FAMILY="virtex7") AND C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
-----------------------------------------------
-- This effectively wires off optional inputs
-----------------------------------------------
ena_i <= ENA WHEN (C_HAS_ENA=1) ELSE '1';
enb_i <= ENB WHEN (C_HAS_ENB=1 AND HAS_B_PORT=1) ELSE '1';
-- We are doing an "AND" operation of WEA and ENA and passing to Enbale pin of BRAM when built-in ECC is enabled,
-- what this means is that the write operation happens only when both WEA and ENA are high.
wea_i <= WEA WHEN (HAS_A_WRITE=1 AND ena_i='1') ELSE WEA0;
-- wea_i <= (OTHERS => '1') WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=1 AND ENA = '1') ELSE -- Use_ENA_pin
-- WEA WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=0) ELSE -- Always_enabled
-- WEA WHEN (HAS_A_WRITE=1 AND ena_i='1' AND C_USE_ECC = 0) ELSE
-- WEA0;
web_i <= WEB WHEN (HAS_B_WRITE=1 AND enb_i='1') ELSE WEB0;
rea_i <= ena_i WHEN (HAS_A_READ=1) ELSE '0';
reb_i <= enb_i WHEN (HAS_B_READ=1) ELSE '0';
-- these signals reset the memory latches
-- For the special reset behaviors in some of the families, the C_RSTRAM
-- attribute of the corresponding port is used to indicate if the latch is
-- reset or not.
reseta_i <= RSTA WHEN
((C_HAS_RSTA=1 AND NUM_OUTPUT_STAGES_A=0) OR
(C_HAS_RSTA=1 AND C_RSTRAM_A=1))
ELSE '0';
resetb_i <= RSTB WHEN
((C_HAS_RSTB=1 AND NUM_OUTPUT_STAGES_B=0) OR
(C_HAS_RSTB=1 AND C_RSTRAM_B=1) )
ELSE '0';
--***************************************************************************
-- This is the main PROCESS which includes the memory VARIABLE and the read
-- and write procedures. It also schedules read and write operations
--***************************************************************************
PROCESS (CLKA, CLKB,rea_i,reb_i,reseta_i,resetb_i)
-- Initialize the init memory array
------------------------------------
VARIABLE memory : mem_array := init_memory(DEFAULT_DATA,
C_WRITE_WIDTH_A,
MAX_DEPTH,
MIN_WIDTH);
-- Initialize the mem memory array
------------------------------------
VARIABLE softecc_sbiterr_arr : softecc_err_array;
VARIABLE softecc_dbiterr_arr : softecc_err_array;
VARIABLE sbiterr_arr : ecc_err_array;
VARIABLE dbiterr_arr : ecc_err_array;
CONSTANT doublebit_lsb : STD_LOGIC_VECTOR (1 DOWNTO 0):="11";
CONSTANT doublebit_msb : STD_LOGIC_VECTOR (C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 DOWNTO 0):= (OTHERS => '0');
VARIABLE doublebit_error : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0) := doublebit_msb & doublebit_lsb ;
VARIABLE current_contents_var : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
--***********************************
-- procedures to access the memory
--***********************************
-- write_a
----------
PROCEDURE write_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
inj_sbiterr : IN STD_LOGIC;
inj_dbiterr : IN STD_LOGIC) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
VARIABLE message : LINE;
VARIABLE errbit_current_contents : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
-- Block Memory Generator non-cycle-accurate message
ASSERT (message_complete) REPORT "Block Memory Generator module is using a behavioral model FOR simulation which will not precisely model memory collision behavior."
SEVERITY NOTE;
message_complete <= true;
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_A_DIV);
IF (address_i >= C_WRITE_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range FOR A Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEA = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_A + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEA_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Insert double bit errors:
IF (C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
current_contents(0) := NOT(current_contents(0));
current_contents(1) := NOT(current_contents(1));
--current_contents(0) := NOT(current_contents(30));
--current_contents(1) := NOT(current_contents(62));
END IF;
END IF;
-- Insert double bit errors:
IF (C_USE_SOFTECC=1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 downto 2) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 downto 0);
doublebit_error(0) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1);
doublebit_error(1) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-2);
current_contents := current_contents XOR doublebit_error(C_WRITE_WIDTH_A-1 DOWNTO 0);
END IF;
END IF;
IF(DEBUG=1) THEN
current_contents_var := current_contents; --for debugging current
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_A + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
-- Store address at which error is injected:
IF ((C_FAMILY = "virtex7") AND C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
sbiterr_arr(address_i) := '1';
ELSE
sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
dbiterr_arr(address_i) := '1';
ELSE
dbiterr_arr(address_i) := '0';
END IF;
END IF;
-- Store address at which softecc error is injected:
IF (C_USE_SOFTECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
softecc_sbiterr_arr(address_i) := '1';
ELSE
softecc_sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
softecc_dbiterr_arr(address_i) := '1';
ELSE
softecc_dbiterr_arr(address_i) := '0';
END IF;
END IF;
END IF;
END PROCEDURE;
-- write_b
----------
PROCEDURE write_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_B_DIV);
IF (address_i >= C_WRITE_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEB = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_B + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEB_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_B + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
END IF;
END PROCEDURE;
-- read_a
----------
PROCEDURE read_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_A_DIV);
IF (address_i >= C_READ_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for A Read"
SEVERITY WARNING;
END IF;
memory_out_a <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_A-1 LOOP
memory_out_a(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_A + i) AFTER FLOP_DELAY;
END LOOP;
END IF;
END IF;
END PROCEDURE;
-- read_b
----------
PROCEDURE read_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_B_DIV);
IF (address_i >= C_READ_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Read"
SEVERITY WARNING;
END IF;
memory_out_b <= (OTHERS => 'X') AFTER FLOP_DELAY;
sbiterr_in <= 'X' AFTER FLOP_DELAY;
dbiterr_in <= 'X' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_B-1 LOOP
memory_out_b(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_B + i) AFTER FLOP_DELAY;
END LOOP;
--assert sbiterr and dbiterr signals
IF ((C_FAMILY="virtex7") AND C_USE_ECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
--assert softecc sbiterr and dbiterr signals
ELSIF (C_USE_SOFTECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (softecc_sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (softecc_dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
END IF;
END IF;
END IF;
END PROCEDURE;
-- reset_a
----------
PROCEDURE reset_a
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
-- reset_b
----------
PROCEDURE reset_b
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
BEGIN -- begin the main PROCESS
--***************************************************************************
-- These are the main blocks which schedule read and write operations
-- Note that the reset priority feature at the latch stage is only supported
-- for Spartan-6. For other families, the default priority at the latch stage
-- is "CE"
--***************************************************************************
-- Synchronous clocks: schedule port operations with respect to both
-- write operating modes
IF (C_COMMON_CLK=1) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODES IS
WHEN "0000" => -- write_first write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "0100" => -- read_first write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "0001" => -- write_first read_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0101" => --read_first read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0010" => -- write_first no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0110" => -- read_first no_change
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1000" => -- no_change write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "1001" => -- no_change read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1010" => -- no_change no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Synchronous clocks
-- Asynchronous clocks: port operation is independent
IF (C_COMMON_CLK=0) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODE_A IS
WHEN "00" => -- write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN "01" => -- read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "10" => -- no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
IF (CLKB='1' AND CLKB'EVENT) THEN
CASE WRITE_MODE_B IS
WHEN "00" => -- write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "01" => -- read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "10" => -- no_change
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Asynchronous clocks
-- Assign the memory VARIABLE to the user_visible memory_i SIGNAL
IF(DEBUG=1) THEN
memory_i <= memory;
doublebit_error_i <= doublebit_error;
current_contents_i <= current_contents_var;
END IF;
END PROCESS;
--********************************************************************
-- Instantiate the VARIABLE depth output stage
--********************************************************************
-- Port A
rsta_outp_stage <= RSTA and not sleep;
rstb_outp_stage <= RSTB and not sleep;
reg_a : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTA,
C_RSTRAM => C_RSTRAM_A,
C_RST_PRIORITY => C_RST_PRIORITY_A,
init_val => INITA_VAL,
C_HAS_EN => C_HAS_ENA,
C_HAS_REGCE => C_HAS_REGCEA,
C_DATA_WIDTH => C_READ_WIDTH_A,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_A,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_A,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKA,
RST => rsta_outp_stage, --RSTA,
EN => ENA,
REGCE => REGCEA,
DIN_I => memory_out_a,
DOUT => DOUTA,
SBITERR_IN_I => '0',
DBITERR_IN_I => '0',
SBITERR => OPEN,
DBITERR => OPEN,
RDADDRECC_IN_I => (OTHERS => '0'),
ECCPIPECE => '0',
RDADDRECC => OPEN
);
-- Port B
reg_b : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTB,
C_RSTRAM => C_RSTRAM_B,
C_RST_PRIORITY => C_RST_PRIORITY_B,
init_val => INITB_VAL,
C_HAS_EN => C_HAS_ENB,
C_HAS_REGCE => C_HAS_REGCEB,
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_B,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKB,
RST => rstb_outp_stage,--RSTB,
EN => ENB,
REGCE => REGCEB,
DIN_I => memory_out_b,
DOUT => doutb_i,
SBITERR_IN_I => sbiterr_in,
DBITERR_IN_I => dbiterr_in,
SBITERR => sbiterr_i,
DBITERR => dbiterr_i,
RDADDRECC_IN_I => rdaddrecc_in,
ECCPIPECE => ECCPIPECE,
RDADDRECC => rdaddrecc_i
);
--********************************************************************
-- Instantiate the input / Output Register stages
--********************************************************************
output_reg_stage: blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC MAP(
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP(
CLK => CLKB,
DIN => doutb_i,
DOUT => DOUTB,
SBITERR_IN => sbiterr_i,
DBITERR_IN => dbiterr_i,
SBITERR => sbiterr_sdp,
DBITERR => dbiterr_sdp,
RDADDRECC_IN => rdaddrecc_i,
RDADDRECC => rdaddrecc_sdp
);
--*********************************
-- Synchronous collision checks
--*********************************
sync_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=1) GENERATE
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
-- collision detect
VARIABLE is_collision : BOOLEAN;
VARIABLE message : LINE;
BEGIN
IF (CLKA='1' AND CLKA'EVENT) THEN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision := false;
END IF;
-- If the write port is in READ_FIRST mode, there is no collision
IF (C_WRITE_MODE_A="READ_FIRST" AND wea_i/=WEA0 AND web_i=WEB0) THEN
is_collision := false;
END IF;
IF (C_WRITE_MODE_B="READ_FIRST" AND web_i/=WEB0 AND wea_i=WEA0) THEN
is_collision := false;
END IF;
-- Only flag if one of the accesses is a write
IF (is_collision AND (wea_i/=WEA0 OR web_i/=WEB0)) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END IF;
END PROCESS;
END GENERATE;
--*********************************
-- Asynchronous collision checks
--*********************************
async_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=0) GENERATE
SIGNAL addra_delay : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL wea_delay : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL ena_delay : STD_LOGIC;
SIGNAL addrb_delay : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
SIGNAL web_delay : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL enb_delay : STD_LOGIC;
BEGIN
-- Delay A and B addresses in order to mimic setup/hold times
PROCESS (ADDRA, wea_i, ena_i, ADDRB, web_i, enb_i)
BEGIN
addra_delay <= ADDRA AFTER COLL_DELAY;
wea_delay <= wea_i AFTER COLL_DELAY;
ena_delay <= ena_i AFTER COLL_DELAY;
addrb_delay <= ADDRB AFTER COLL_DELAY;
web_delay <= web_i AFTER COLL_DELAY;
enb_delay <= enb_i AFTER COLL_DELAY;
END PROCESS;
-- Do the checks w/rt A
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_a : BOOLEAN;
VARIABLE is_collision_delay_a : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_a := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_a := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_delay_a := collision_check(ADDRA,
wea_i/=WEA0,
addrb_delay,
web_delay/=WEB0);
ELSE
is_collision_delay_a := false;
END IF;
-- Only flag if B access is a write
IF (is_collision_a AND web_i/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_a AND web_delay/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, addrb_delay);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
-- Do the checks w/rt B
PROCESS (CLKB)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_b : BOOLEAN;
VARIABLE is_collision_delay_b : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA) /= 'X') THEN
is_collision_b := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_b := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(addra_delay) /= 'X') THEN
is_collision_delay_b := collision_check(addra_delay,
wea_delay/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_delay_b := false;
END IF;
-- Only flag if A access is a write
-- Modified condition checking (is_collision_b AND WEA0_i=/WEA0) to fix CR526228
IF (is_collision_b AND wea_i/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_b AND wea_delay/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, addra_delay);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
END GENERATE;
END mem_module_behavioral;
--******************************************************************************
-- Top module that wraps SoftECC Input register stage and the main memory module
--
-- This module is the top-level of behavioral model
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1 IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_CTRL_ECC_ALGO : STRING := "NONE";
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
--C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_SLEEP_PIN : INTEGER := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
PORT (
clka : IN STD_LOGIC := '0';
rsta : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '1';
regcea : IN STD_LOGIC := '1';
wea : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addra : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
dina : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
douta : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
clkb : IN STD_LOGIC := '0';
rstb : IN STD_LOGIC := '0';
enb : IN STD_LOGIC := '1';
regceb : IN STD_LOGIC := '1';
web : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addrb : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
dinb : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
doutb : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
injectsbiterr : IN STD_LOGIC := '0';
injectdbiterr : IN STD_LOGIC := '0';
sbiterr : OUT STD_LOGIC := '0';
dbiterr : OUT STD_LOGIC := '0';
rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : in std_logic := '0';
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic := '0';
rstb_busy : out std_logic := '0';
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
s_aclk : IN STD_LOGIC := '0';
s_aresetn : IN STD_LOGIC := '0';
-- axi full/lite slave Write (write side)
s_axi_awid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid : IN STD_LOGIC := '0';
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast : IN STD_LOGIC := '0';
s_axi_wvalid : IN STD_LOGIC := '0';
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC := '0';
-- axi full/lite slave Read (Write side)
s_axi_arid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid : IN STD_LOGIC := '0';
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_rdata : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC := '0';
-- axi full/lite sideband Signals
s_axi_injectsbiterr : IN STD_LOGIC := '0';
s_axi_injectdbiterr : IN STD_LOGIC := '0';
s_axi_sbiterr : OUT STD_LOGIC := '0';
s_axi_dbiterr : OUT STD_LOGIC := '0';
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END blk_mem_gen_v8_3_1;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE behavioral OF blk_mem_gen_v8_3_1 IS
COMPONENT blk_mem_gen_v8_3_1_mem_module
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_mem_module;
COMPONENT blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_axi_regs_fwd_v8_3;
COMPONENT blk_mem_axi_read_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT blk_mem_axi_read_wrapper_beh;
COMPONENT blk_mem_axi_write_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END COMPONENT blk_mem_axi_write_wrapper_beh;
CONSTANT FLOP_DELAY : TIME := 100 ps;
SIGNAL rsta_in : STD_LOGIC := '1';
SIGNAL ena_in : STD_LOGIC := '1';
SIGNAL regcea_in : STD_LOGIC := '1';
SIGNAL wea_in : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL addra_in : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL dina_in : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL injectsbiterr_in : STD_LOGIC := '0';
SIGNAL injectdbiterr_in : STD_LOGIC := '0';
-----------------------------------------------------------------------------
-- FUNCTION: toLowerCaseChar
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
-----------------------------------------------------------------------------
FUNCTION toLowerCaseChar(
char : character )
RETURN character IS
BEGIN
-- If char is not an upper case letter then return char
IF char<'A' OR char>'Z' THEN
RETURN char;
END IF;
-- Otherwise map char to its corresponding lower case character and
-- RETURN that
CASE char IS
WHEN 'A' => RETURN 'a';
WHEN 'B' => RETURN 'b';
WHEN 'C' => RETURN 'c';
WHEN 'D' => RETURN 'd';
WHEN 'E' => RETURN 'e';
WHEN 'F' => RETURN 'f';
WHEN 'G' => RETURN 'g';
WHEN 'H' => RETURN 'h';
WHEN 'I' => RETURN 'i';
WHEN 'J' => RETURN 'j';
WHEN 'K' => RETURN 'k';
WHEN 'L' => RETURN 'l';
WHEN 'M' => RETURN 'm';
WHEN 'N' => RETURN 'n';
WHEN 'O' => RETURN 'o';
WHEN 'P' => RETURN 'p';
WHEN 'Q' => RETURN 'q';
WHEN 'R' => RETURN 'r';
WHEN 'S' => RETURN 's';
WHEN 'T' => RETURN 't';
WHEN 'U' => RETURN 'u';
WHEN 'V' => RETURN 'v';
WHEN 'W' => RETURN 'w';
WHEN 'X' => RETURN 'x';
WHEN 'Y' => RETURN 'y';
WHEN 'Z' => RETURN 'z';
WHEN OTHERS => RETURN char;
END CASE;
END toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
FUNCTION equalIgnoreCase(
str1 : STRING;
str2 : STRING )
RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str2'left TO str1'right LOOP
IF NOT (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equalIgnoreCase;
-----------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
----------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
----------------------------------------------------------------------------
-- FUNCTION : log2roundup
----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
CONSTANT lower_limit : INTEGER := 1;
CONSTANT upper_limit : INTEGER := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
-----------------------------------------------------------------------------
-- FUNCTION : divroundup
-- Returns the ceiling value of the division
-- Data_value - the quantity to be divided, dividend
-- Divisor - the value to divide the data_value by
-----------------------------------------------------------------------------
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
SIGNAL s_axi_awaddr_out_c : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_araddr_out_c : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_wr_en_c : STD_LOGIC := '0';
SIGNAL s_axi_rd_en_c : STD_LOGIC := '0';
SIGNAL s_aresetn_a_c : STD_LOGIC := '0';
--**************************************************************************
-- AXI PARAMETERS
CONSTANT AXI_FULL_MEMORY_SLAVE : integer := if_then_else((C_AXI_SLAVE_TYPE = 0 AND C_AXI_TYPE = 1),1,0);
CONSTANT C_AXI_ADDR_WIDTH_MSB : integer := C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
CONSTANT C_AXI_ADDR_WIDTH : integer := C_AXI_ADDR_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT LOWER_BOUND_VAL : integer := if_then_else((log2roundup(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT C_AXI_ADDR_WIDTH_LSB : integer := if_then_else((AXI_FULL_MEMORY_SLAVE = 1),0,LOWER_BOUND_VAL);
CONSTANT C_AXI_OS_WR : integer := 2;
-- SAFETY LOGIC related Signals
SIGNAL RSTA_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_A : STD_LOGIC := '0';
SIGNAL RSTB_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_B : STD_LOGIC := '0';
SIGNAL ENA_dly : STD_LOGIC := '0';
SIGNAL ENA_dly_D : STD_LOGIC := '0';
SIGNAL ENB_dly : STD_LOGIC := '0';
SIGNAL ENB_dly_D : STD_LOGIC := '0';
SIGNAL RSTA_I_SAFE : STD_LOGIC := '0';
SIGNAL RSTB_I_SAFE : STD_LOGIC := '0';
SIGNAL ENA_I_SAFE : STD_LOGIC := '0';
SIGNAL ENB_I_SAFE : STD_LOGIC := '0';
SIGNAL ram_rstram_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstram_b_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_b_busy : STD_LOGIC := '0';
SIGNAL ENA_dly_reg : STD_LOGIC := '0';
SIGNAL ENB_dly_reg : STD_LOGIC := '0';
SIGNAL ENA_dly_reg_D : STD_LOGIC := '0';
SIGNAL ENB_dly_reg_D : STD_LOGIC := '0';
--**************************************************************************
BEGIN -- Architecture
--*************************************************************************
-- NO INPUT STAGE
--*************************************************************************
no_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=0) GENERATE
rsta_in <= RSTA;
ena_in <= ENA;
regcea_in <= REGCEA;
wea_in <= WEA;
addra_in <= ADDRA;
dina_in <= DINA;
injectsbiterr_in <= INJECTSBITERR;
injectdbiterr_in <= INJECTDBITERR;
END GENERATE no_input_stage;
--**************************************************************************
-- WITH INPUT STAGE
--**************************************************************************
has_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=1) GENERATE
PROCESS (CLKA)
BEGIN
IF (CLKA'EVENT AND CLKA = '1') THEN
rsta_in <= RSTA AFTER FLOP_DELAY;
ena_in <= ENA AFTER FLOP_DELAY;
regcea_in <= REGCEA AFTER FLOP_DELAY;
wea_in <= WEA AFTER FLOP_DELAY;
addra_in <= ADDRA AFTER FLOP_DELAY;
dina_in <= DINA AFTER FLOP_DELAY;
injectsbiterr_in <= INJECTSBITERR AFTER FLOP_DELAY;
injectdbiterr_in <= INJECTDBITERR AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE has_input_stage;
--**************************************************************************
-- NO SAFETY LOGIC
--**************************************************************************
NO_SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 0) GENERATE
ENA_I_SAFE <= ena_in;
ENB_I_SAFE <= ENB;
RSTA_I_SAFE <= rsta_in;
RSTB_I_SAFE <= RSTB;
END GENERATE NO_SAFETY_CKT_GEN;
--**************************************************************************
-- SAFETY LOGIC
--**************************************************************************
SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 1) GENERATE
-- RESET SAFETY LOGIC Generation
-- POR Generation
------------------------------------------------------------------------------
-- Power-ON Reset Generation
------------------------------------------------------------------------------
RST_SHFT_LOGIC_A : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
RSTA_SHFT_REG(4 DOWNTO 0) <= RSTA_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_A;
POR_RSTA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
POR_A <= RSTA_SHFT_REG(4) xor RSTA_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTA_GEN;
RST_SHFT_LOGIC_B : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
RSTB_SHFT_REG(4 DOWNTO 0) <= RSTB_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_B;
POR_RSTB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
POR_B <= RSTB_SHFT_REG(4) xor RSTB_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTB_GEN;
-----------------------------------------------------------------------------
-- Fix for the AR42571
-----------------------------------------------------------------------------
-- Reset Generation
-----------------------------------------------------------------------------
RSTA_I_SAFE <= rsta_in OR POR_A;
SPRAM_RST: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_I_SAFE <= '0';
END GENERATE SPRAM_RST;
nSPRAM_RST: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_I_SAFE <= RSTB OR POR_B;
END GENERATE nSPRAM_RST;
-----------------------------------------------------------------------------
-- RSTA/B_BUSY Generation
-----------------------------------------------------------------------------
RSTA_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
ram_rstram_a_busy <= rsta_in OR ENA_dly OR ENA_dly_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstram_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_NO_REG;
RSTA_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
ram_rstreg_a_busy <= rsta_in OR ENA_dly OR ENA_dly_reg_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstreg_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_WITH_REG;
SPRAM_RST_BUSY: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_BUSY <= '0';
END GENERATE SPRAM_RST_BUSY;
nSPRAM_RST_BUSY: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
ram_rstram_b_busy <= RSTB OR ENB_dly OR ENB_dly_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstram_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_NO_REG;
RSTB_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
ram_rstreg_b_busy <= RSTB OR ENB_dly OR ENB_dly_reg_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstreg_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_WITH_REG;
END GENERATE nSPRAM_RST_BUSY;
-----------------------------------------------------------------------------
-- ENA/ENB Generation
-----------------------------------------------------------------------------
ENA_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly <= rsta_in AFTER FLOP_DELAY;
ENA_dly_D <= ENA_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_D OR ena_in;
END GENERATE ENA_NO_REG;
ENA_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly_reg <= rsta_in AFTER FLOP_DELAY;
ENA_dly_reg_D <= ENA_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_reg_D OR ena_in;
END GENERATE ENA_WITH_REG;
SPRAM_ENB: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
ENB_I_SAFE <= '0';
END GENERATE SPRAM_ENB;
nSPRAM_ENB: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
ENB_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly <= RSTB AFTER FLOP_DELAY;
ENB_dly_D <= ENB_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_D OR ENB;
END GENERATE ENB_NO_REG;
ENB_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly_reg <= RSTB AFTER FLOP_DELAY;
ENB_dly_reg_D <= ENB_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_reg_D OR ENB;
END GENERATE ENB_WITH_REG;
END GENERATE nSPRAM_ENB;
END GENERATE SAFETY_CKT_GEN;
--**************************************************************************
-- NATIVE MEMORY MODULE INSTANCE
--**************************************************************************
native_mem_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 0) GENERATE
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,--rsta_in,
ENA => ENA_I_SAFE,--ena_in,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in,
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => RDADDRECC
);
END GENERATE native_mem_module;
--**************************************************************************
-- NATIVE MEMORY MAPPED MODULE INSTANCE
--**************************************************************************
native_mem_map_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 1) GENERATE
--**************************************************************************
-- NATIVE MEMORY MAPPED PARAMETERS
CONSTANT C_ADDRA_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_A);
CONSTANT C_ADDRB_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_B);
CONSTANT C_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
CONSTANT C_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
CONSTANT C_MEM_MAP_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_MSB;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT MEM_MAP_LOWER_BOUND_VAL_A : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT MEM_MAP_LOWER_BOUND_VAL_B : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_B,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_B,8)));
CONSTANT C_MEM_MAP_ADDRA_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_A;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_B;
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH_ACTUAL-1 DOWNTO 0) := (OTHERS => '0');
--**************************************************************************
BEGIN
RDADDRECC(C_ADDRB_WIDTH-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_MSB) <= (OTHERS => '0');
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB) <= rdaddrecc_i;
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_LSB-1 DOWNTO 0) <= (OTHERS => '0');
mem_map_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH_ACTUAL,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH_ACTUAL,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,
ENA => ENA_I_SAFE,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in(C_MEM_MAP_ADDRA_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRA_WIDTH_LSB),
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB),
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => rdaddrecc_i
);
END GENERATE native_mem_map_module;
--****************************************************************************
-- AXI MEMORY MODULE INSTANCE
--****************************************************************************
axi_mem_module: IF (C_INTERFACE_TYPE = 1) GENERATE
SIGNAL s_axi_rid_c : STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rdata_c : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rresp_c : STD_LOGIC_VECTOR(2-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rlast_c : STD_LOGIC := '0';
SIGNAL s_axi_rvalid_c : STD_LOGIC := '0';
SIGNAL s_axi_rready_c : STD_LOGIC := '0';
SIGNAL regceb_c : STD_LOGIC := '0';
BEGIN
s_aresetn_a_c <= NOT S_ARESETN;
S_AXI_BRESP <= (OTHERS => '0');
s_axi_rresp_c <= (OTHERS => '0');
no_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 0 AND C_HAS_MUX_OUTPUT_REGS_B = 0 ) GENERATE
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RLAST <= s_axi_rlast_c;
S_AXI_RVALID <= s_axi_rvalid_c;
S_AXI_RID <= s_axi_rid_c;
S_AXI_RRESP <= s_axi_rresp_c;
s_axi_rready_c <= S_AXI_RREADY;
END GENERATE no_regs;
has_regs_fwd: IF (C_HAS_MUX_OUTPUT_REGS_B = 1 OR C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
CONSTANT C_AXI_PAYLOAD : INTEGER := if_then_else((C_HAS_MUX_OUTPUT_REGS_B = 1),C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3,C_AXI_ID_WIDTH+3);
SIGNAL s_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
has_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
regceb_c <= s_axi_rvalid_c AND s_axi_rready_c;
END GENERATE has_regceb;
no_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 0) GENERATE
regceb_c <= REGCEB;
END GENERATE no_regceb;
only_core_op_regs: IF (C_HAS_MUX_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rdata_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RDATA <= m_axi_payload_c(C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_core_op_regs;
only_emb_op_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_emb_op_regs;
axi_regs_inst : blk_mem_axi_regs_fwd_v8_3
GENERIC MAP(
C_DATA_WIDTH => C_AXI_PAYLOAD
)
PORT MAP (
ACLK => S_ACLK,
ARESET => s_aresetn_a_c,
S_VALID => s_axi_rvalid_c,
S_READY => s_axi_rready_c,
S_PAYLOAD_DATA => s_axi_payload_c,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY,
M_PAYLOAD_DATA => m_axi_payload_c
);
END GENERATE has_regs_fwd;
axi_wr_fsm : blk_mem_axi_write_wrapper_beh
GENERIC MAP(
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_AXI_AWADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_WDATA_WIDTH => C_WRITE_WIDTH_A,
C_AXI_OS_WR => C_AXI_OS_WR
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Slave Write Interface
S_AXI_AWADDR => S_AXI_AWADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_AWLEN => S_AXI_AWLEN,
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BID => S_AXI_BID,
-- Signals for BRAM interface
S_AXI_AWADDR_OUT =>s_axi_awaddr_out_c,
S_AXI_WR_EN =>s_axi_wr_en_c
);
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => 1, -- For AXI, Read Enable is always C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => 1, -- For AXI C_USE_BYTE_WEA is always 1,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => 1, -- For AXI, Read Enable is always C_HAS_ENB,
C_HAS_REGCEB => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_BYTE_WEB => 1, -- For AXI C_USE_BYTE_WEB is always 1,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => 0, --For AXI, Primitive Registers A is not supported C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => 0,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
--Port A:
CLKA => S_AClk,
RSTA => s_aresetn_a_c,
ENA => s_axi_wr_en_c,
REGCEA => regcea_in,
WEA => S_AXI_WSTRB,
ADDRA => s_axi_awaddr_out_c,
DINA => S_AXI_WDATA,
DOUTA => DOUTA,
--Port B:
CLKB => S_AClk,
RSTB => s_aresetn_a_c,
ENB => s_axi_rd_en_c,
REGCEB => regceb_c,
WEB => (OTHERS => '0'),
ADDRB => s_axi_araddr_out_c,
DINB => DINB,
DOUTB => s_axi_rdata_c,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => '0',
SLEEP => '0',
RDADDRECC => RDADDRECC
);
axi_rd_sm : blk_mem_axi_read_wrapper_beh
GENERIC MAP (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_PIPELINE_STAGES => 1,
C_AXI_ARADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_AClk,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Read Side
S_AXI_ARADDR => S_AXI_ARADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARSIZE => S_AXI_ARSIZE,
S_AXI_ARBURST => S_AXI_ARBURST,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => s_axi_rlast_c,
S_AXI_RVALID => s_axi_rvalid_c,
S_AXI_RREADY => s_axi_rready_c,
S_AXI_ARID => S_AXI_ARID,
S_AXI_RID => s_axi_rid_c,
-- AXI Full/Lite Read FSM Outputs
S_AXI_ARADDR_OUT => s_axi_araddr_out_c,
S_AXI_RD_EN => s_axi_rd_en_c
);
END GENERATE axi_mem_module;
END behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_clr is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_clr;
architecture beh_ff_clr_arch of beh_ff_clr is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(CLR, C)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_clr_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_ce is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_ce;
architecture beh_ff_ce_arch of beh_ff_ce is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, CLR)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
if (CE = '1') then
q_o <= D after 100 ps;
end if;
end if;
end process;
end beh_ff_ce_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_pre is
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end beh_ff_pre;
architecture beh_ff_pre_arch of beh_ff_pre is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, PRE)
begin
if (PRE = '1') then
q_o <= '1';
elsif (C' event and C = '1') then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_pre_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_muxf7 is
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end beh_muxf7;
architecture beh_muxf7_arch of beh_muxf7 is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
else
O <= I1;
end if;
end process;
end beh_muxf7_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity STATE_LOGIC is
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic := '0';
I0 : in std_logic := '0';
I1 : in std_logic := '0';
I2 : in std_logic := '0';
I3 : in std_logic := '0';
I4 : in std_logic := '0';
I5 : in std_logic := '0'
);
end STATE_LOGIC;
architecture STATE_LOGIC_arch of STATE_LOGIC is
constant INIT_reg : std_logic_vector(63 downto 0) := INIT;
begin
LUT_beh:process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
begin
I_reg := I5 & I4 & I3 & I2 & I1 & I0;
O <= INIT_reg(conv_integer(I_reg));
end process;
end STATE_LOGIC_arch;
|
-------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v8_3_1.vhd
--
-- Description:
-- This file is the VHDL behvarial model for the
-- Block Memory Generator Core.
--
-------------------------------------------------------------------------------
-- Author: Xilinx
--
-- History: January 11, 2006: Initial revision
-- June 11, 2007 : Added independent register stages for
-- Port A and Port B (IP1_Jm/v2.5)
-- August 28, 2007 : Added mux pipeline stages feature (IP2_Jm/v2.6)
-- April 07, 2009 : Added support for Spartan-6 and Virtex-6
-- features, including the following:
-- (i) error injection, detection and/or correction
-- (ii) reset priority
-- (iii) special reset behavior
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
ENTITY blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END ENTITY blk_mem_axi_regs_fwd_v8_3;
ARCHITECTURE axi_regs_fwd_arch OF blk_mem_axi_regs_fwd_v8_3 IS
SIGNAL STORAGE_DATA : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_READY_I : STD_LOGIC := '0';
SIGNAL M_VALID_I : STD_LOGIC := '0';
SIGNAL ARESET_D : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');-- Reset delay register
BEGIN
--assign local signal to its output signal
S_READY <= S_READY_I;
M_VALID <= M_VALID_I;
PROCESS(ACLK)
BEGIN
IF(ACLK'event AND ACLK = '1') THEN
ARESET_D <= ARESET_D(0) & ARESET;
END IF;
END PROCESS;
--Save payload data whenever we have a transaction on the slave side
PROCESS(ACLK, ARESET)
BEGIN
IF (ARESET = '1') THEN
STORAGE_DATA <= (OTHERS => '0');
ELSIF(ACLK'event AND ACLK = '1') THEN
IF(S_VALID = '1' AND S_READY_I = '1') THEN
STORAGE_DATA <= S_PAYLOAD_DATA;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= STORAGE_DATA;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
PROCESS(ACLK,ARESET)
BEGIN
IF (ARESET_D /= "00") THEN
M_VALID_I <= '0';
ELSIF(ACLK'event AND ACLK = '1') THEN
IF (S_VALID = '1') THEN
--Always set M_VALID_I when slave side is valid
M_VALID_I <= '1';
ELSIF (M_READY = '1') THEN
--Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= '0';
END IF;
END IF;
END PROCESS;
--Slave Ready is either when Master side drives M_READY or we have space in our storage data
S_READY_I <= (M_READY OR (NOT M_VALID_I)) AND NOT(OR_REDUCE(ARESET_D));
END axi_regs_fwd_arch;
-------------------------------------------------------------------------------
-- Description:
-- This is the behavioral model of write_wrapper for the
-- Block Memory Generator Core.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_axi_write_wrapper_beh IS
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END blk_mem_axi_write_wrapper_beh;
ARCHITECTURE axi_write_wrap_arch OF blk_mem_axi_write_wrapper_beh IS
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_AXI_WDATA_WIDTH=8,0,
if_then_else((C_AXI_WDATA_WIDTH=16),1,
if_then_else((C_AXI_WDATA_WIDTH=32),2,
if_then_else((C_AXI_WDATA_WIDTH=64),3,
if_then_else((C_AXI_WDATA_WIDTH=128),4,
if_then_else((C_AXI_WDATA_WIDTH=256),5,0))))));
SIGNAL bvalid_c : std_logic := '0';
SIGNAL bready_timeout_c : std_logic := '0';
SIGNAL bvalid_rd_cnt_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_r : std_logic := '0';
SIGNAL bvalid_count_r : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL awaddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
C_AXI_AWADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL bvalid_wr_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_rd_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_last_c : std_logic := '0';
SIGNAL addr_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL aw_ready_r : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL awlen_cntr_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1');
SIGNAL awlen_int : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL awburst_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes : integer := 0;
SIGNAL wrap_boundary : integer := 0;
SIGNAL wrap_base_addr : integer := 0;
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
-- Array to store BIDs
TYPE id_array IS ARRAY (3 DOWNTO 0) OF std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
SIGNAL axi_bid_array : id_array := (others => (others => '0'));
COMPONENT write_netlist
GENERIC(
C_AXI_TYPE : integer
);
PORT(
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
S_AXI_AWVALID : IN std_logic;
aw_ready_r : OUT std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN std_logic;
S_AXI_WR_EN : OUT std_logic;
w_last_c : IN std_logic;
bready_timeout_c : IN std_logic;
addr_en_c : OUT std_logic;
incr_addr_c : OUT std_logic;
bvalid_c : OUT std_logic
);
END COMPONENT write_netlist;
BEGIN
---------------------------------------
--AXI WRITE FSM COMPONENT INSTANTIATION
---------------------------------------
axi_wr_fsm : write_netlist
GENERIC MAP (
C_AXI_TYPE => C_AXI_TYPE
)
PORT MAP (
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
S_AXI_AWVALID => S_AXI_AWVALID,
aw_ready_r => aw_ready_r,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BVALID => OPEN,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_WR_EN => S_AXI_WR_EN,
w_last_c => w_last_c,
bready_timeout_c => bready_timeout_c,
addr_en_c => addr_en_c,
incr_addr_c => incr_addr_c,
bvalid_c => bvalid_c
);
--Wrap Address boundary calculation
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWSIZE,"000"));
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(awlen_int)+1);
wrap_base_addr <= (conv_integer(awaddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary <= wrap_base_addr+total_bytes;
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awaddr_reg <= (OTHERS => '0');
num_of_bytes_r <= 0;
awburst_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awaddr_reg <= S_AXI_AWADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWBURST,"01");
ELSIF (incr_addr_c = '1') THEN
IF (awburst_int = "10") THEN
IF(conv_integer(awaddr_reg) = (wrap_boundary-num_of_bytes_r)) THEN
awaddr_reg <= conv_std_logic_vector(wrap_base_addr,C_AXI_AWADDR_WIDTH);
ELSE
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
ELSIF (awburst_int = "01" OR awburst_int = "11") THEN
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
S_AXI_AWADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
awaddr_reg(C_AXI_AWADDR_WIDTH-1 DOWNTO C_RANGE),awaddr_reg);
---------------------------------------------------------------------------
-- AXI wlast generation
---------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awlen_cntr_r <= (OTHERS => '1');
awlen_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awlen_int <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
awlen_cntr_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
ELSIF (dec_alen_c = '1') THEN
awlen_cntr_r <= awlen_cntr_r - ONE AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
w_last_c <= '1' WHEN (awlen_cntr_r = "00000000" AND S_AXI_WVALID = '1') ELSE '0';
dec_alen_c <= (incr_addr_c OR w_last_c);
---------------------------------------------------------------------------
-- Generation of bvalid counter for outstanding transactions
---------------------------------------------------------------------------
P_b_valid_os_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_count_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- bvalid_count_r generation
IF (bvalid_c = '1' AND bvalid_r = '1' AND S_AXI_BREADY = '1') THEN
bvalid_count_r <= bvalid_count_r AFTER FLOP_DELAY;
ELSIF (bvalid_c = '1') THEN
bvalid_count_r <= bvalid_count_r + "01" AFTER FLOP_DELAY;
ELSIF (bvalid_r = '1' AND S_AXI_BREADY = '1' AND bvalid_count_r /= "0") THEN
bvalid_count_r <= bvalid_count_r - "01" AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_os_r ;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is used
---------------------------------------------------------------------------
gaxi_bvalid_id_r:IF (C_HAS_AXI_ID = 1) GENERATE
SIGNAL bvalid_d1_c : std_logic := '0';
BEGIN
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
bvalid_d1_c <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
--external bvalid signal generation
IF (bvalid_d1_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_id_r;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is not used
---------------------------------------------------------------------------
gaxi_bvalid_noid_r:IF (C_HAS_AXI_ID = 0) GENERATE
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
--external bvalid signal generation
IF (bvalid_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_noid_r;
---------------------------------------------------------------------------
-- Generation of Bready timeout
---------------------------------------------------------------------------
P_brdy_tout_c: PROCESS (bvalid_count_r)
BEGIN
-- bready_timeout_c generation
IF(conv_integer(bvalid_count_r) = C_AXI_OS_WR-1) THEN
bready_timeout_c <= '1';
ELSE
bready_timeout_c <= '0';
END IF;
END PROCESS P_brdy_tout_c;
---------------------------------------------------------------------------
-- Generation of BID
---------------------------------------------------------------------------
gaxi_bid_gen:IF (C_HAS_AXI_ID = 1) GENERATE
P_bid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
bvalid_wr_cnt_r <= (OTHERS => '0');
bvalid_rd_cnt_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- STORE AWID IN AN ARRAY
IF(bvalid_c = '1') THEN
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + "01";
END IF;
-- GENERATE BID FROM AWID ARRAY
bvalid_rd_cnt_r <= bvalid_rd_cnt_c AFTER FLOP_DELAY;
S_AXI_BID <= axi_bid_array(conv_integer(bvalid_rd_cnt_c));
END IF;
END PROCESS P_bid_gen;
bvalid_rd_cnt_c <= bvalid_rd_cnt_r + "01" WHEN (bvalid_r = '1' AND S_AXI_BREADY = '1') ELSE bvalid_rd_cnt_r;
---------------------------------------------------------------------------
-- Storing AWID for generation of BID
---------------------------------------------------------------------------
P_awid_reg:PROCESS (S_ACLK)
BEGIN
IF (S_ACLK'event AND S_ACLK='1') THEN
IF(aw_ready_r = '1' AND S_AXI_AWVALID = '1') THEN
axi_bid_array(conv_integer(bvalid_wr_cnt_r)) <= S_AXI_AWID;
END IF;
END IF;
END PROCESS P_awid_reg;
END GENERATE gaxi_bid_gen;
S_AXI_BVALID <= bvalid_r;
S_AXI_AWREADY <= aw_ready_r;
END axi_write_wrap_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity write_netlist is
GENERIC(
C_AXI_TYPE : integer
);
port (
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_AWVALID : in STD_LOGIC := '0';
S_AXI_WVALID : in STD_LOGIC := '0';
S_AXI_BREADY : in STD_LOGIC := '0';
w_last_c : in STD_LOGIC := '0';
bready_timeout_c : in STD_LOGIC := '0';
aw_ready_r : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_WR_EN : out STD_LOGIC;
addr_en_c : out STD_LOGIC;
incr_addr_c : out STD_LOGIC;
bvalid_c : out STD_LOGIC
);
end write_netlist;
architecture STRUCTURE of write_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
BEGIN
---------------------------------------------------------------------------
-- AXI LITE
---------------------------------------------------------------------------
gbeh_axi_lite_sm: IF (C_AXI_TYPE = 0 ) GENERATE
signal w_ready_r_7 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSignal_bvalid_c : STD_LOGIC;
signal NlwRenamedSignal_incr_addr_c : STD_LOGIC;
signal present_state_FSM_FFd3_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal present_state_FSM_FFd1_15 : STD_LOGIC;
signal present_state_FSM_FFd4_16 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd4_In1_21 : STD_LOGIC;
signal Mmux_aw_ready_c : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
S_AXI_WREADY <= w_ready_r_7;
S_AXI_BVALID <= NlwRenamedSignal_incr_addr_c;
S_AXI_WR_EN <= NlwRenamedSignal_bvalid_c;
incr_addr_c <= NlwRenamedSignal_incr_addr_c;
bvalid_c <= NlwRenamedSignal_bvalid_c;
NlwRenamedSignal_incr_addr_c <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_7
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_16
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_13
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_15
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000055554440"
)
port map (
I0 => S_AXI_WVALID,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => '0',
O => present_state_FSM_FFd3_In
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"0000000088880800"
)
port map (
I0 => S_AXI_AWVALID,
I1 => S_AXI_WVALID,
I2 => bready_timeout_c,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => present_state_FSM_FFd2_In
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAA2000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_WVALID,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => addr_en_c
);
Mmux_w_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"F5F07570F5F05500"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => w_ready_c
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd3_13,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd1_15,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_14,
I2 => present_state_FSM_FFd3_13,
I3 => '0',
I4 => '0',
I5 => '0',
O => NlwRenamedSignal_bvalid_c
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"2F0F27072F0F2200"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => present_state_FSM_FFd4_In1_21
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_In1_21,
I3 => '0',
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_aw_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"7535753575305500"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => S_AXI_WVALID,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => present_state_FSM_FFd2_14,
O => Mmux_aw_ready_c(0)
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => Mmux_aw_ready_c(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => aw_ready_c
);
END GENERATE gbeh_axi_lite_sm;
---------------------------------------------------------------------------
-- AXI FULL
---------------------------------------------------------------------------
gbeh_axi_full_sm: IF (C_AXI_TYPE = 1 ) GENERATE
signal w_ready_r_8 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSig_OI_bvalid_c : STD_LOGIC;
signal present_state_FSM_FFd1_16 : STD_LOGIC;
signal present_state_FSM_FFd4_17 : STD_LOGIC;
signal present_state_FSM_FFd3_18 : STD_LOGIC;
signal present_state_FSM_FFd2_19 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd2_In1_24 : STD_LOGIC;
signal present_state_FSM_FFd4_In1_25 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal N4 : STD_LOGIC;
begin
S_AXI_WREADY <= w_ready_r_8;
bvalid_c <= NlwRenamedSig_OI_bvalid_c;
S_AXI_BVALID <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_8
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_17
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_18
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_19
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_16
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000000005540"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd4_17,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd3_In
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"BF3FBB33AF0FAA00"
)
port map (
I0 => S_AXI_BREADY,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd1_16,
I4 => present_state_FSM_FFd4_17,
I5 => NlwRenamedSig_OI_bvalid_c,
O => aw_ready_c
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"AAAAAAAA20000000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_19,
I3 => S_AXI_WVALID,
I4 => w_last_c,
I5 => present_state_FSM_FFd4_17,
O => addr_en_c
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_19,
I2 => present_state_FSM_FFd3_18,
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_WR_EN
);
Mmux_incr_addr_c_0_1 : STATE_LOGIC
generic map(
INIT => X"0000000000002220"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => incr_addr_c
);
Mmux_aw_ready_c_0_11 : STATE_LOGIC
generic map(
INIT => X"0000000000008880"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => NlwRenamedSig_OI_bvalid_c
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"000000000000D5C0"
)
port map (
I0 => w_last_c,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd4_17,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd2_In1_24
);
present_state_FSM_FFd2_In2 : STATE_LOGIC
generic map(
INIT => X"FFFFAAAA08AAAAAA"
)
port map (
I0 => present_state_FSM_FFd2_19,
I1 => S_AXI_AWVALID,
I2 => bready_timeout_c,
I3 => w_last_c,
I4 => S_AXI_WVALID,
I5 => present_state_FSM_FFd2_In1_24,
O => present_state_FSM_FFd2_In
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"00C0004000C00000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => w_last_c,
I2 => S_AXI_WVALID,
I3 => bready_timeout_c,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => present_state_FSM_FFd4_In1_25
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88F8"
)
port map (
I0 => present_state_FSM_FFd1_16,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_17,
I3 => S_AXI_AWVALID,
I4 => present_state_FSM_FFd4_In1_25,
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_w_ready_c_0_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => w_last_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_w_ready_c_0_Q : STATE_LOGIC
generic map(
INIT => X"FABAFABAFAAAF000"
)
port map (
I0 => N2,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd4_17,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => w_ready_c
);
Mmux_aw_ready_c_0_11_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => bready_timeout_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => w_last_c,
I1 => N4,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => present_state_FSM_FFd1_16,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
END GENERATE gbeh_axi_full_sm;
end STRUCTURE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--AXI Behavioral Model entities
ENTITY blk_mem_axi_read_wrapper_beh is
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
port (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END blk_mem_axi_read_wrapper_beh;
architecture blk_mem_axi_read_wrapper_beh_arch of blk_mem_axi_read_wrapper_beh is
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_WRITE_WIDTH_A=8,0,
if_then_else((C_WRITE_WIDTH_A=16),1,
if_then_else((C_WRITE_WIDTH_A=32),2,
if_then_else((C_WRITE_WIDTH_A=64),3,
if_then_else((C_WRITE_WIDTH_A=128),4,
if_then_else((C_WRITE_WIDTH_A=256),5,0))))));
SIGNAL ar_id_r : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
SIGNAL addr_en_c : std_logic := '0';
SIGNAL rd_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL single_trans_c : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL mux_sel_c : std_logic := '0';
SIGNAL r_last_c : std_logic := '0';
SIGNAL r_last_int_c : std_logic := '0';
SIGNAL arlen_int_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL arlen_cntr : std_logic_vector(7 DOWNTO 0) := ONE;
SIGNAL arburst_int_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL arburst_int_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL araddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),C_AXI_ARADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL total_bytes : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
SIGNAL wrap_base_addr_r : integer := 0;
SIGNAL wrap_boundary_r : integer := 0;
SIGNAL arlen_int_c : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes_c : integer := 0;
SIGNAL wrap_base_addr_c : integer := 0;
SIGNAL wrap_boundary_c : integer := 0;
SIGNAL araddr_out : std_logic_vector(C_ADDRB_WIDTH-1 downto 0) := (OTHERS => '0');
COMPONENT read_netlist
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_INCR_ADDR : OUT std_logic := '0';
S_AXI_ADDR_EN : OUT std_logic := '0';
S_AXI_SINGLE_TRANS : OUT std_logic := '0';
S_AXI_MUX_SEL : OUT std_logic := '0';
S_AXI_R_LAST : OUT std_logic := '0';
S_AXI_R_LAST_INT : IN std_logic := '0';
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT read_netlist;
BEGIN
dec_alen_c <= incr_addr_c OR r_last_int_c;
axi_read_fsm : read_netlist
GENERIC MAP(
C_AXI_TYPE => 1,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
S_AXI_INCR_ADDR => incr_addr_c,
S_AXI_ADDR_EN => addr_en_c,
S_AXI_SINGLE_TRANS => single_trans_c,
S_AXI_MUX_SEL => mux_sel_c,
S_AXI_R_LAST => r_last_c,
S_AXI_R_LAST_INT => r_last_int_c,
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN => rd_en_c
);
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(arlen_int_r)+1);
wrap_base_addr_r <= (conv_integer(araddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary_r <= wrap_base_addr_r+total_bytes;
---- combinatorial from interface
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARSIZE,"000"));
arlen_int_c <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
total_bytes_c <= conv_integer(num_of_bytes_c)*(conv_integer(arlen_int_c)+1);
wrap_base_addr_c <= (conv_integer(S_AXI_ARADDR)/if_then_else(total_bytes_c=0,1,total_bytes_c))*(total_bytes_c);
wrap_boundary_c <= wrap_base_addr_c+total_bytes_c;
arburst_int_c <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARBURST,"01");
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
araddr_reg <= (OTHERS => '0');
arburst_int_r <= (OTHERS => '0');
num_of_bytes_r <= 0;
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (incr_addr_c = '1' AND addr_en_c = '1' AND single_trans_c = '0') THEN
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
IF (arburst_int_c = "10") THEN
IF(conv_integer(S_AXI_ARADDR) = (wrap_boundary_c-num_of_bytes_c)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_c,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (arburst_int_c = "01" OR arburst_int_c = "11") THEN
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (addr_en_c = '1') THEN
araddr_reg <= S_AXI_ARADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
ELSIF (incr_addr_c = '1') THEN
IF (arburst_int_r = "10") THEN
IF(conv_integer(araddr_reg) = (wrap_boundary_r-num_of_bytes_r)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_r,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
ELSIF (arburst_int_r = "01" OR arburst_int_r = "11") THEN
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
araddr_out <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),araddr_reg(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),araddr_reg);
--------------------------------------------------------------------------
-- Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
--------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF S_ARESETN = '1' THEN
arlen_cntr <= ONE;
arlen_int_r <= (OTHERS => '0');
ELSIF S_ACLK'event AND S_ACLK = '1' THEN
IF (addr_en_c = '1' AND dec_alen_c = '1' AND single_trans_c = '0') THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= S_AXI_ARLEN - ONE AFTER FLOP_DELAY;
ELSIF addr_en_c = '1' THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
ELSIF dec_alen_c = '1' THEN
arlen_cntr <= arlen_cntr - ONE AFTER FLOP_DELAY;
ELSE
arlen_cntr <= arlen_cntr AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
r_last_int_c <= '1' WHEN (arlen_cntr = "00000000" AND S_AXI_RREADY = '1') ELSE '0' ;
--------------------------------------------------------------------------
-- AXI FULL FSM
-- Mux Selection of ARADDR
-- ARADDR is driven out from the read fsm based on the mux_sel_c
-- Based on mux_sel either ARADDR is given out or the latched ARADDR is
-- given out to BRAM
--------------------------------------------------------------------------
P_araddr_mux: PROCESS (mux_sel_c,S_AXI_ARADDR,araddr_out)
BEGIN
IF (mux_sel_c = '0') THEN
S_AXI_ARADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARADDR(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),S_AXI_ARADDR);
ELSE
S_AXI_ARADDR_OUT <= araddr_out;
END IF;
END PROCESS P_araddr_mux;
--------------------------------------------------------------------------
-- Assign output signals - AXI FULL FSM
--------------------------------------------------------------------------
S_AXI_RD_EN <= rd_en_c;
grid: IF (C_HAS_AXI_ID = 1) GENERATE
P_rid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
S_AXI_RID <= (OTHERS => '0');
ar_id_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
IF (addr_en_c = '1' AND rd_en_c = '1') THEN
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
ELSIF (addr_en_c = '1' AND rd_en_c = '0') THEN
ar_id_r <= S_AXI_ARID;
ELSIF (rd_en_c = '1') THEN
S_AXI_RID <= ar_id_r;
END IF;
END IF;
END PROCESS P_rid_gen;
END GENERATE grid;
END blk_mem_axi_read_wrapper_beh_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity read_netlist is
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_R_LAST_INT : in STD_LOGIC := '0';
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_ARVALID : in STD_LOGIC := '0';
S_AXI_RREADY : in STD_LOGIC := '0';
S_AXI_INCR_ADDR : out STD_LOGIC;
S_AXI_ADDR_EN : out STD_LOGIC;
S_AXI_SINGLE_TRANS : out STD_LOGIC;
S_AXI_MUX_SEL : out STD_LOGIC;
S_AXI_R_LAST : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RLAST : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RD_EN : out STD_LOGIC;
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end read_netlist;
architecture STRUCTURE of read_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
signal present_state_FSM_FFd1_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_r_15 : STD_LOGIC;
signal gaxi_full_sm_ar_ready_r_16 : STD_LOGIC;
signal gaxi_full_sm_r_last_r_17 : STD_LOGIC;
signal NlwRenamedSig_OI_gaxi_full_sm_r_valid_r : STD_LOGIC;
signal gaxi_full_sm_r_valid_c : STD_LOGIC;
signal S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o : STD_LOGIC;
signal gaxi_full_sm_ar_ready_c : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_c : STD_LOGIC;
signal NlwRenamedSig_OI_S_AXI_R_LAST : STD_LOGIC;
signal S_AXI_ARLEN_7_GND_8_o_equal_1_o : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal Mmux_S_AXI_R_LAST13 : STD_LOGIC;
signal N01 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal Mmux_gaxi_full_sm_ar_ready_c11 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N8 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N13 : STD_LOGIC;
begin
S_AXI_R_LAST <= NlwRenamedSig_OI_S_AXI_R_LAST;
S_AXI_ARREADY <= gaxi_full_sm_ar_ready_r_16;
S_AXI_RLAST <= gaxi_full_sm_r_last_r_17;
S_AXI_RVALID <= NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
gaxi_full_sm_outstanding_read_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_outstanding_read_c,
Q => gaxi_full_sm_outstanding_read_r_15
);
gaxi_full_sm_r_valid_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => gaxi_full_sm_r_valid_c,
Q => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r
);
gaxi_full_sm_ar_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_ar_ready_c,
Q => gaxi_full_sm_ar_ready_r_16
);
gaxi_full_sm_r_last_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => NlwRenamedSig_OI_S_AXI_R_LAST,
Q => gaxi_full_sm_r_last_r_17
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_13
);
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 : STATE_LOGIC
generic map(
INIT => X"000000000000000B"
)
port map (
I0 => S_AXI_RREADY,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o
);
Mmux_S_AXI_SINGLE_TRANS11 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_SINGLE_TRANS
);
Mmux_S_AXI_ADDR_EN11 : STATE_LOGIC
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_ADDR_EN
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"ECEE2022EEEE2022"
)
port map (
I0 => S_AXI_ARVALID,
I1 => present_state_FSM_FFd1_13,
I2 => S_AXI_RREADY,
I3 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I4 => present_state_FSM_FFd2_14,
I5 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
O => present_state_FSM_FFd2_In
);
Mmux_S_AXI_R_LAST131 : STATE_LOGIC
generic map(
INIT => X"0000000044440444"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_RREADY,
I5 => '0',
O => Mmux_S_AXI_R_LAST13
);
Mmux_S_AXI_INCR_ADDR11 : STATE_LOGIC
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => S_AXI_R_LAST_INT,
I1 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => Mmux_S_AXI_R_LAST13,
O => S_AXI_INCR_ADDR
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000FE"
)
port map (
I0 => S_AXI_ARLEN(2),
I1 => S_AXI_ARLEN(1),
I2 => S_AXI_ARLEN(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => N01
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q : STATE_LOGIC
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => S_AXI_ARLEN(7),
I1 => S_AXI_ARLEN(6),
I2 => S_AXI_ARLEN(5),
I3 => S_AXI_ARLEN(4),
I4 => S_AXI_ARLEN(3),
I5 => N01,
O => S_AXI_ARLEN_7_GND_8_o_equal_1_o
);
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_gaxi_full_sm_outstanding_read_c1 : STATE_LOGIC
generic map(
INIT => X"0020000002200200"
)
port map (
I0 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd1_13,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => N2,
O => gaxi_full_sm_outstanding_read_c
);
Mmux_gaxi_full_sm_ar_ready_c12 : STATE_LOGIC
generic map(
INIT => X"0000000000004555"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => '0',
I5 => '0',
O => Mmux_gaxi_full_sm_ar_ready_c11
);
Mmux_S_AXI_R_LAST11_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000EF"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
Mmux_S_AXI_R_LAST11 : STATE_LOGIC
generic map(
INIT => X"FCAAFC0A00AA000A"
)
port map (
I0 => S_AXI_ARVALID,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => N4,
I5 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
O => gaxi_full_sm_r_valid_c
);
S_AXI_MUX_SEL1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAAAA08"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => '0',
O => S_AXI_MUX_SEL
);
Mmux_S_AXI_RD_EN11 : STATE_LOGIC
generic map(
INIT => X"F3F3F755A2A2A200"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => gaxi_full_sm_outstanding_read_r_15,
I4 => present_state_FSM_FFd2_14,
I5 => S_AXI_ARVALID,
O => S_AXI_RD_EN
);
present_state_FSM_FFd1_In3 : beh_muxf7
port map (
I0 => N8,
I1 => N9,
S => present_state_FSM_FFd1_13,
O => present_state_FSM_FFd1_In
);
present_state_FSM_FFd1_In3_F : STATE_LOGIC
generic map(
INIT => X"000000005410F4F0"
)
port map (
I0 => S_AXI_RREADY,
I1 => present_state_FSM_FFd2_14,
I2 => S_AXI_ARVALID,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => '0',
O => N8
);
present_state_FSM_FFd1_In3_G : STATE_LOGIC
generic map(
INIT => X"0000000072FF7272"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N9
);
Mmux_gaxi_full_sm_ar_ready_c14 : beh_muxf7
port map (
I0 => N10,
I1 => N11,
S => present_state_FSM_FFd1_13,
O => gaxi_full_sm_ar_ready_c
);
Mmux_gaxi_full_sm_ar_ready_c14_F : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88A8"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => Mmux_gaxi_full_sm_ar_ready_c11,
I5 => '0',
O => N10
);
Mmux_gaxi_full_sm_ar_ready_c14_G : STATE_LOGIC
generic map(
INIT => X"000000008D008D8D"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N11
);
Mmux_S_AXI_R_LAST1 : beh_muxf7
port map (
I0 => N12,
I1 => N13,
S => present_state_FSM_FFd1_13,
O => NlwRenamedSig_OI_S_AXI_R_LAST
);
Mmux_S_AXI_R_LAST1_F : STATE_LOGIC
generic map(
INIT => X"0000000088088888"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N12
);
Mmux_S_AXI_R_LAST1_G : STATE_LOGIC
generic map(
INIT => X"00000000E400E4E4"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => S_AXI_R_LAST_INT,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N13
);
end STRUCTURE;
-------------------------------------------------------------------------------
-- Output Register Stage Entity
--
-- This module builds the output register stages of the memory. This module is
-- instantiated in the main memory module (blk_mem_gen_v8_3_1) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_output_stage IS
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_output_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6" and "virtex6l".
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
-- C_HAS_RST : Determines the presence of the RST port
-- C_RSTRAM : Determines if special reset behavior is used
-- C_RST_PRIORITY : Determines the priority between CE and SR
-- C_INIT_VAL : Initialization value
-- C_HAS_EN : Determines the presence of the EN port
-- C_HAS_REGCE : Determines the presence of the REGCE port
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
-- of the RAM primitive
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- NUM_STAGES : Determines the number of output stages
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE output_stage_behavioral OF blk_mem_gen_v8_3_1_output_stage IS
--*******************************************************
-- Functions used in the output stage ARCHITECTURE
--*******************************************************
-- Calculate num_reg_stages
FUNCTION get_num_reg_stages(NUM_STAGES: INTEGER) RETURN INTEGER IS
VARIABLE num_reg_stages : INTEGER := 0;
BEGIN
IF (NUM_STAGES = 0) THEN
num_reg_stages := 0;
ELSE
num_reg_stages := NUM_STAGES - 1;
END IF;
RETURN num_reg_stages;
END get_num_reg_stages;
-- Check if the INTEGER is zero or non-zero
FUNCTION int_to_bit(input: INTEGER) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = 0) THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END int_to_bit;
-- Constants
CONSTANT HAS_EN : STD_LOGIC := int_to_bit(C_HAS_EN);
CONSTANT HAS_REGCE : STD_LOGIC := int_to_bit(C_HAS_REGCE);
CONSTANT HAS_RST : STD_LOGIC := int_to_bit(C_HAS_RST);
CONSTANT REG_STAGES : INTEGER := get_num_reg_stages(NUM_STAGES);
-- Pipeline array
TYPE reg_data_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
TYPE reg_ecc_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC;
TYPE reg_eccaddr_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
CONSTANT REG_INIT : reg_data_array := (OTHERS => init_val);
SIGNAL out_regs : reg_data_array := REG_INIT;
SIGNAL sbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL dbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL rdaddrecc_regs: reg_eccaddr_array := (OTHERS => (OTHERS => '0'));
-- Internal signals
SIGNAL en_i : STD_LOGIC;
SIGNAL regce_i : STD_LOGIC;
SIGNAL rst_i : STD_LOGIC;
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := init_val;
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL DIN : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL RDADDRECC_IN : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ;
SIGNAL SBITERR_IN : STD_LOGIC := '0';
SIGNAL DBITERR_IN : STD_LOGIC := '0';
BEGIN
--***********************************************************************
-- Assign internal signals. This effectively wires off optional inputs.
--***********************************************************************
-- Internal enable for output registers is tied to user EN or '1' depending
-- on parameters
en_i <= EN OR (NOT HAS_EN);
-- Internal register enable for output registers is tied to user REGCE, EN
-- or '1' depending on parameters
regce_i <= (HAS_REGCE AND REGCE)
OR ((NOT HAS_REGCE) AND en_i);
-- Internal SRR is tied to user RST or '0' depending on parameters
rst_i <= RST AND HAS_RST;
--***************************************************************************
-- NUM_STAGES = 0 (No output registers. RAM only)
--***************************************************************************
zero_stages: IF (NUM_STAGES = 0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE zero_stages;
NO_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 0) GENERATE
DIN <= DIN_I;
RDADDRECC_IN <= RDADDRECC_IN_I;
SBITERR_IN <= SBITERR_IN_I;
DBITERR_IN <= DBITERR_IN_I;
END GENERATE NO_ECC_PIPE_REG;
WITH_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(ECCPIPECE = '1') THEN
DIN <= DIN_I AFTER FLOP_DELAY;
RDADDRECC_IN <= RDADDRECC_IN_I AFTER FLOP_DELAY;
SBITERR_IN <= SBITERR_IN_I AFTER FLOP_DELAY;
DBITERR_IN <= DBITERR_IN_I AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS;
END GENERATE WITH_ECC_PIPE_REG;
--***************************************************************************
-- NUM_STAGES = 1
-- (Mem Output Reg only or Mux Output Reg only)
--***************************************************************************
-- Possible valid combinations:
-- Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
-- +-----------------------------------------+
-- | C_RSTRAM_* | Reset Behavior |
-- +----------------+------------------------+
-- | 0 | Normal Behavior |
-- +----------------+------------------------+
-- | 1 | Special Behavior |
-- +----------------+------------------------+
--
-- Normal = REGCE gates reset, as in the case of all Virtex families and all
-- spartan families with the exception of S3ADSP and S6.
-- Special = EN gates reset, as in the case of S3ADSP and S6.
one_stage_norm: IF (NUM_STAGES = 1 AND
(C_RSTRAM=0 OR (C_RSTRAM=1 AND (C_XDEVICEFAMILY/="spartan3adsp" AND C_XDEVICEFAMILY/="aspartan3adsp")) OR
C_HAS_MEM_OUTPUT_REGS=0 OR C_HAS_RST=0)) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i = '1' AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
END IF;--CLK
END PROCESS;
END GENERATE one_stage_norm;
-- Special Reset Behavior for S6 and S3ADSP
one_stage_splbhv: IF (NUM_STAGES=1 AND C_RSTRAM=1 AND (C_XDEVICEFAMILY ="spartan3adsp" OR C_XDEVICEFAMILY ="aspartan3adsp"))
GENERATE
DOUT <= dout_i;
SBITERR <= '0';
DBITERR <= '0';
RDADDRECC <= (OTHERS => '0');
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (rst_i='1' AND en_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
ELSIF (regce_i='1' AND rst_i/='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE one_stage_splbhv;
--****************************************************************************
-- NUM_STAGES > 1
-- Mem Output Reg + Mux Output Reg
-- or
-- Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
-- or
-- Mux Pipeline Stages (>0) + Mux Output Reg
--****************************************************************************
multi_stage: IF (NUM_STAGES > 1) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i='1'AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
IF (en_i='1') THEN
-- Shift the data through the output stages
FOR i IN 1 TO REG_STAGES-1 LOOP
out_regs(i) <= out_regs(i-1) AFTER FLOP_DELAY;
sbiterr_regs(i) <= sbiterr_regs(i-1) AFTER FLOP_DELAY;
dbiterr_regs(i) <= dbiterr_regs(i-1) AFTER FLOP_DELAY;
rdaddrecc_regs(i) <= rdaddrecc_regs(i-1) AFTER FLOP_DELAY;
END LOOP;
out_regs(0) <= DIN;
sbiterr_regs(0) <= SBITERR_IN;
dbiterr_regs(0) <= DBITERR_IN;
rdaddrecc_regs(0) <= RDADDRECC_IN;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE multi_stage;
END output_stage_behavioral;
-------------------------------------------------------------------------------
-- SoftECC Output Register Stage Entity
-- This module builds the softecc output register stages. This module is
-- instantiated in the memory module (blk_mem_gen_v8_3_1_mem_module) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ;
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- of the RAM primitive
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE softecc_output_reg_stage_behavioral OF blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
-- Internal signals
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
--***************************************************************************
-- NO OUTPUT STAGES
--***************************************************************************
no_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE no_output_stage;
--****************************************************************************
-- WITH OUTPUT STAGE
--****************************************************************************
has_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END PROCESS;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
END GENERATE has_output_stage;
END softecc_output_reg_stage_behavioral;
--******************************************************************************
-- Main Memory module
--
-- This module is the behavioral model which implements the RAM
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
ENTITY blk_mem_gen_v8_3_1_mem_module IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_mem_module;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE mem_module_behavioral OF blk_mem_gen_v8_3_1_mem_module IS
--****************************************
-- min/max constant functions
--****************************************
-- get_max
----------
function SLV_TO_INT(SLV: in std_logic_vector
) return integer is
variable int : integer;
begin
int := 0;
for i in SLV'high downto SLV'low loop
int := int * 2;
if SLV(i) = '1' then
int := int + 1;
end if;
end loop;
return int;
end;
FUNCTION get_max(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a > b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-- get_min
----------
FUNCTION get_min(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
--***************************************************************
-- convert write_mode from STRING type for use in case statement
--***************************************************************
FUNCTION write_mode_to_vector(mode: STRING) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF (mode = "NO_CHANGE") THEN
RETURN "10";
ELSIF (mode = "READ_FIRST") THEN
RETURN "01";
ELSE
RETURN "00"; -- WRITE_FIRST
END IF;
END FUNCTION;
--***************************************************************
-- convert hex STRING to STD_LOGIC_VECTOR
--***************************************************************
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
--***************************************************************
-- locally derived constants to determine memory shape
--***************************************************************
CONSTANT MIN_WIDTH_A : INTEGER := get_min(C_WRITE_WIDTH_A, C_READ_WIDTH_A);
CONSTANT MIN_WIDTH_B : INTEGER := get_min(C_WRITE_WIDTH_B,C_READ_WIDTH_B);
CONSTANT MIN_WIDTH : INTEGER := get_min(MIN_WIDTH_A, MIN_WIDTH_B);
CONSTANT MAX_DEPTH_A : INTEGER := get_max(C_WRITE_DEPTH_A, C_READ_DEPTH_A);
CONSTANT MAX_DEPTH_B : INTEGER := get_max(C_WRITE_DEPTH_B, C_READ_DEPTH_B);
CONSTANT MAX_DEPTH : INTEGER := get_max(MAX_DEPTH_A, MAX_DEPTH_B);
TYPE int_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF std_logic_vector(C_WRITE_WIDTH_A-1 DOWNTO 0);
TYPE mem_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC_VECTOR(MIN_WIDTH-1 DOWNTO 0);
TYPE ecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
TYPE softecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
--***************************************************************
-- memory initialization function
--***************************************************************
IMPURE FUNCTION init_memory(DEFAULT_DATA :
STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
write_width_a : INTEGER;
depth : INTEGER;
width : INTEGER)
RETURN mem_array IS
VARIABLE init_return : mem_array := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(write_width_a-1 DOWNTO 0);
VARIABLE int_mem_vector : int_array:= (OTHERS => (OTHERS => '0'));
VARIABLE file_buffer : LINE;
VARIABLE i : INTEGER := 0;
VARIABLE j : INTEGER;
VARIABLE k : INTEGER;
VARIABLE ignore_line : BOOLEAN := false;
VARIABLE good_data : BOOLEAN := false;
VARIABLE char_tmp : CHARACTER;
VARIABLE index : INTEGER;
variable init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable data : std_logic_vector(255 downto 0) := (others => '0');
variable inside_init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable k_slv : std_logic_vector(31 downto 0) := (others => '0');
variable i_slv : std_logic_vector(31 downto 0) := (others => '0');
VARIABLE disp_line : line := null;
variable open_status : file_open_status;
variable input_initf_tmp : mem_array ;
variable input_initf : mem_array := (others => (others => '0'));
file int_infile : text;
variable data_line, data_line_tmp, out_data_line : line;
variable slv_width : integer;
VARIABLE d_l : LINE;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
index := 0;
FOR i IN 0 TO depth-1 LOOP
FOR j IN 0 TO width-1 LOOP
init_return(i)(j) := DEFAULT_DATA(index);
index := (index + 1) MOD C_WRITE_WIDTH_A;
END LOOP;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, file_buffer);
read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO write_width_a-1 LOOP
IF (j MOD width = 0 AND j /= 0) THEN
i := i + 1;
END IF;
init_return(i)(j MOD width) := bit_to_sl(mem_vector(j));
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
--Display output message indicating that the behavioral model is done
--initializing
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator data initialization complete." SEVERITY NOTE;
if (C_USE_BRAM_BLOCK = 1) then
--Display output message indicating that the behavioral model is being
--initialized
-- Read in the .mem file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_INIT_FILE /= "NONE") then
file_open(open_status, int_infile, C_INIT_FILE, read_mode);
while not endfile(int_infile) loop
readline(int_infile, data_line);
while (data_line /= null and data_line'length > 0) loop
if (data_line(data_line'low to data_line'low + 1) = "//") then
deallocate(data_line);
elsif ((data_line(data_line'low to data_line'low + 1) = "/*") and (data_line(data_line'high-1 to data_line'high) = "*/")) then
deallocate(data_line);
elsif (data_line(data_line'low to data_line'low + 1) = "/*") then
deallocate(data_line);
ignore_line := true;
elsif (ignore_line = true and data_line(data_line'high-1 to data_line'high) = "*/") then
deallocate(data_line);
ignore_line := false;
elsif (ignore_line = false and data_line(data_line'low) = '@') then
read(data_line, char_tmp);
hread(data_line, init_addr_slv, good_data);
i := SLV_TO_INT(init_addr_slv);
elsif (ignore_line = false) then
hread(data_line, input_initf_tmp(i), good_data);
init_return(i)(write_width_a - 1 downto 0) := input_initf_tmp(i)(write_width_a - 1 downto 0);
if (good_data = true) then
i := i + 1;
end if;
else
deallocate(data_line);
end if;
end loop;
end loop;
file_close(int_infile);
END IF;
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- memory type constants
--***************************************************************
CONSTANT MEM_TYPE_SP_RAM : INTEGER := 0;
CONSTANT MEM_TYPE_SDP_RAM : INTEGER := 1;
CONSTANT MEM_TYPE_TDP_RAM : INTEGER := 2;
CONSTANT MEM_TYPE_SP_ROM : INTEGER := 3;
CONSTANT MEM_TYPE_DP_ROM : INTEGER := 4;
--***************************************************************
-- memory configuration constant functions
--***************************************************************
--get_single_port
-----------------
FUNCTION get_single_port(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_RAM OR mem_type=MEM_TYPE_SP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_single_port;
--get_is_rom
--------------
FUNCTION get_is_rom(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_ROM OR mem_type=MEM_TYPE_DP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_is_rom;
--get_has_a_write
------------------
FUNCTION get_has_a_write(IS_ROM : INTEGER) RETURN INTEGER IS
BEGIN
IF (IS_ROM=0) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_a_write;
--get_has_b_write
------------------
FUNCTION get_has_b_write(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_TDP_RAM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_write;
--get_has_a_read
------------------
FUNCTION get_has_a_read(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SDP_RAM) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_a_read;
--get_has_b_read
------------------
FUNCTION get_has_b_read(SINGLE_PORT : INTEGER) RETURN INTEGER IS
BEGIN
IF (SINGLE_PORT=1) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_b_read;
--get_has_b_port
------------------
FUNCTION get_has_b_port(HAS_B_READ : INTEGER;
HAS_B_WRITE : INTEGER)
RETURN INTEGER IS
BEGIN
IF (HAS_B_READ=1 OR HAS_B_WRITE=1) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_port;
--get_num_output_stages
-----------------------
FUNCTION get_num_output_stages(has_mem_output_regs : INTEGER;
has_mux_output_regs : INTEGER;
mux_pipeline_stages : INTEGER)
RETURN INTEGER IS
VARIABLE actual_mux_pipeline_stages : INTEGER;
BEGIN
-- Mux pipeline stages can be non-zero only when there is a mux
-- output register.
IF (has_mux_output_regs=1) THEN
actual_mux_pipeline_stages := mux_pipeline_stages;
ELSE
actual_mux_pipeline_stages := 0;
END IF;
RETURN has_mem_output_regs+actual_mux_pipeline_stages+has_mux_output_regs;
END get_num_output_stages;
--***************************************************************************
-- Component declaration of the VARIABLE depth output register stage
--***************************************************************************
COMPONENT blk_mem_gen_v8_3_1_output_stage
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
EN : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
ECCPIPECE : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_output_stage;
COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************************************
-- locally derived constants to assist memory access
--******************************************************
CONSTANT WRITE_WIDTH_RATIO_A : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_A : INTEGER := C_READ_WIDTH_A/MIN_WIDTH;
CONSTANT WRITE_WIDTH_RATIO_B : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_B : INTEGER := C_READ_WIDTH_B/MIN_WIDTH;
--******************************************************
-- To modify the LSBs of the 'wider' data to the actual
-- address value
--******************************************************
CONSTANT WRITE_ADDR_A_DIV : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH_A;
CONSTANT READ_ADDR_A_DIV : INTEGER := C_READ_WIDTH_A/MIN_WIDTH_A;
CONSTANT WRITE_ADDR_B_DIV : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH_B;
CONSTANT READ_ADDR_B_DIV : INTEGER := C_READ_WIDTH_B/MIN_WIDTH_B;
--******************************************************
-- FUNCTION : log2roundup
--******************************************************
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
--******************************************************
-- Other constants and signals
--******************************************************
CONSTANT COLL_DELAY : TIME := 100 ps;
-- default data vector
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_DEFAULT_DATA,
C_WRITE_WIDTH_A);
CONSTANT CHKBIT_WIDTH : INTEGER := if_then_else(C_WRITE_WIDTH_A>57,8,if_then_else(C_WRITE_WIDTH_A>26,7,if_then_else(C_WRITE_WIDTH_A>11,6,if_then_else(C_WRITE_WIDTH_A>4,5,if_then_else(C_WRITE_WIDTH_A<5,4,0)))));
-- the init memory SIGNAL
SIGNAL memory_i : mem_array;
SIGNAL doublebit_error_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0);
SIGNAL current_contents_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
-- write mode constants
CONSTANT WRITE_MODE_A : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_A);
CONSTANT WRITE_MODE_B : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_B);
CONSTANT WRITE_MODES : STD_LOGIC_VECTOR(3 DOWNTO 0) :=
WRITE_MODE_A & WRITE_MODE_B;
-- reset values
CONSTANT INITA_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITA_VAL,
C_READ_WIDTH_A);
CONSTANT INITB_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITB_VAL,
C_READ_WIDTH_B);
-- memory output 'latches'
SIGNAL memory_out_a : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0) :=
INITA_VAL;
SIGNAL memory_out_b : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) :=
INITB_VAL;
SIGNAL sbiterr_in : STD_LOGIC := '0';
SIGNAL sbiterr_sdp : STD_LOGIC := '0';
SIGNAL dbiterr_in : STD_LOGIC := '0';
SIGNAL dbiterr_sdp : STD_LOGIC := '0';
SIGNAL rdaddrecc_in : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_sdp : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL doutb_i : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i : STD_LOGIC := '0';
SIGNAL dbiterr_i : STD_LOGIC := '0';
-- memory configuration constants
-----------------------------------------------
CONSTANT SINGLE_PORT : INTEGER := get_single_port(C_MEM_TYPE);
CONSTANT IS_ROM : INTEGER := get_is_rom(C_MEM_TYPE);
CONSTANT HAS_A_WRITE : INTEGER := get_has_a_write(IS_ROM);
CONSTANT HAS_B_WRITE : INTEGER := get_has_b_write(C_MEM_TYPE);
CONSTANT HAS_A_READ : INTEGER := get_has_a_read(C_MEM_TYPE);
CONSTANT HAS_B_READ : INTEGER := get_has_b_read(SINGLE_PORT);
CONSTANT HAS_B_PORT : INTEGER := get_has_b_port(HAS_B_READ, HAS_B_WRITE);
CONSTANT NUM_OUTPUT_STAGES_A : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_A,
C_MUX_PIPELINE_STAGES);
CONSTANT NUM_OUTPUT_STAGES_B : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES);
CONSTANT WEA0 : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT WEB0 : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-----------------------------------------------------------------------------
-- DEBUG CONTROL
-- DEBUG=0 : Debug output OFF
-- DEBUG=1 : Some debug info printed
-----------------------------------------------------------------------------
CONSTANT DEBUG : INTEGER := 0;
-- internal signals
-----------------------------------------------
SIGNAL ena_i : STD_LOGIC;
SIGNAL enb_i : STD_LOGIC;
SIGNAL reseta_i : STD_LOGIC;
SIGNAL resetb_i : STD_LOGIC;
SIGNAL wea_i : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL web_i : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL rea_i : STD_LOGIC;
SIGNAL reb_i : STD_LOGIC;
SIGNAL message_complete : BOOLEAN := false;
SIGNAL rsta_outp_stage : STD_LOGIC := '0';
SIGNAL rstb_outp_stage : STD_LOGIC := '0';
--*********************************************************
--FUNCTION : Collision check
--*********************************************************
FUNCTION collision_check (addr_a :
STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
iswrite_a : BOOLEAN;
addr_b :
STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
iswrite_b : BOOLEAN)
RETURN BOOLEAN IS
VARIABLE c_aw_bw : INTEGER;
VARIABLE c_aw_br : INTEGER;
VARIABLE c_ar_bw : INTEGER;
VARIABLE write_addr_a_width : INTEGER;
VARIABLE read_addr_a_width : INTEGER;
VARIABLE write_addr_b_width : INTEGER;
VARIABLE read_addr_b_width : INTEGER;
BEGIN
c_aw_bw := 0;
c_aw_br := 0;
c_ar_bw := 0;
-- Determine the effective address widths FOR each of the 4 ports
write_addr_a_width := C_ADDRA_WIDTH-log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width := C_ADDRA_WIDTH-log2roundup(READ_ADDR_A_DIV);
write_addr_b_width := C_ADDRB_WIDTH-log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width := C_ADDRB_WIDTH-log2roundup(READ_ADDR_B_DIV);
--Look FOR a write-write collision. In order FOR a write-write
--collision to exist, both ports must have a write transaction.
IF (iswrite_a AND iswrite_b) THEN
IF (write_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_a and iswrite_b
--If the B port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_a) THEN
IF (write_addr_a_width > read_addr_b_width) THEN
--read_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_b_width
--Once both are scaled to read_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
END IF; --width
END IF; --iswrite_a
--If the A port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_b) THEN
IF (read_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
ELSE
--read_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_a_width
--Once both are scaled to read_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_b
RETURN (c_aw_bw=1 OR c_aw_br=1 OR c_ar_bw=1);
END FUNCTION collision_check;
BEGIN -- Architecture
-----------------------------------------------------------------------------
-- SOFTECC and ECC SBITERR/DBITERR Outputs
-- The ECC Behavior is modeled by the behavioral models only for Virtex-6.
-- The SOFTECC Behavior is modeled by the behavioral models for Spartan-6.
-- For Virtex-5, these outputs will be tied to 0.
-----------------------------------------------------------------------------
SBITERR <= sbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_sdp WHEN (((C_FAMILY="virtex7") AND C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
-----------------------------------------------
-- This effectively wires off optional inputs
-----------------------------------------------
ena_i <= ENA WHEN (C_HAS_ENA=1) ELSE '1';
enb_i <= ENB WHEN (C_HAS_ENB=1 AND HAS_B_PORT=1) ELSE '1';
-- We are doing an "AND" operation of WEA and ENA and passing to Enbale pin of BRAM when built-in ECC is enabled,
-- what this means is that the write operation happens only when both WEA and ENA are high.
wea_i <= WEA WHEN (HAS_A_WRITE=1 AND ena_i='1') ELSE WEA0;
-- wea_i <= (OTHERS => '1') WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=1 AND ENA = '1') ELSE -- Use_ENA_pin
-- WEA WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=0) ELSE -- Always_enabled
-- WEA WHEN (HAS_A_WRITE=1 AND ena_i='1' AND C_USE_ECC = 0) ELSE
-- WEA0;
web_i <= WEB WHEN (HAS_B_WRITE=1 AND enb_i='1') ELSE WEB0;
rea_i <= ena_i WHEN (HAS_A_READ=1) ELSE '0';
reb_i <= enb_i WHEN (HAS_B_READ=1) ELSE '0';
-- these signals reset the memory latches
-- For the special reset behaviors in some of the families, the C_RSTRAM
-- attribute of the corresponding port is used to indicate if the latch is
-- reset or not.
reseta_i <= RSTA WHEN
((C_HAS_RSTA=1 AND NUM_OUTPUT_STAGES_A=0) OR
(C_HAS_RSTA=1 AND C_RSTRAM_A=1))
ELSE '0';
resetb_i <= RSTB WHEN
((C_HAS_RSTB=1 AND NUM_OUTPUT_STAGES_B=0) OR
(C_HAS_RSTB=1 AND C_RSTRAM_B=1) )
ELSE '0';
--***************************************************************************
-- This is the main PROCESS which includes the memory VARIABLE and the read
-- and write procedures. It also schedules read and write operations
--***************************************************************************
PROCESS (CLKA, CLKB,rea_i,reb_i,reseta_i,resetb_i)
-- Initialize the init memory array
------------------------------------
VARIABLE memory : mem_array := init_memory(DEFAULT_DATA,
C_WRITE_WIDTH_A,
MAX_DEPTH,
MIN_WIDTH);
-- Initialize the mem memory array
------------------------------------
VARIABLE softecc_sbiterr_arr : softecc_err_array;
VARIABLE softecc_dbiterr_arr : softecc_err_array;
VARIABLE sbiterr_arr : ecc_err_array;
VARIABLE dbiterr_arr : ecc_err_array;
CONSTANT doublebit_lsb : STD_LOGIC_VECTOR (1 DOWNTO 0):="11";
CONSTANT doublebit_msb : STD_LOGIC_VECTOR (C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 DOWNTO 0):= (OTHERS => '0');
VARIABLE doublebit_error : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0) := doublebit_msb & doublebit_lsb ;
VARIABLE current_contents_var : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
--***********************************
-- procedures to access the memory
--***********************************
-- write_a
----------
PROCEDURE write_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
inj_sbiterr : IN STD_LOGIC;
inj_dbiterr : IN STD_LOGIC) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
VARIABLE message : LINE;
VARIABLE errbit_current_contents : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
-- Block Memory Generator non-cycle-accurate message
ASSERT (message_complete) REPORT "Block Memory Generator module is using a behavioral model FOR simulation which will not precisely model memory collision behavior."
SEVERITY NOTE;
message_complete <= true;
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_A_DIV);
IF (address_i >= C_WRITE_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range FOR A Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEA = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_A + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEA_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Insert double bit errors:
IF (C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
current_contents(0) := NOT(current_contents(0));
current_contents(1) := NOT(current_contents(1));
--current_contents(0) := NOT(current_contents(30));
--current_contents(1) := NOT(current_contents(62));
END IF;
END IF;
-- Insert double bit errors:
IF (C_USE_SOFTECC=1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 downto 2) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 downto 0);
doublebit_error(0) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1);
doublebit_error(1) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-2);
current_contents := current_contents XOR doublebit_error(C_WRITE_WIDTH_A-1 DOWNTO 0);
END IF;
END IF;
IF(DEBUG=1) THEN
current_contents_var := current_contents; --for debugging current
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_A + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
-- Store address at which error is injected:
IF ((C_FAMILY = "virtex7") AND C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
sbiterr_arr(address_i) := '1';
ELSE
sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
dbiterr_arr(address_i) := '1';
ELSE
dbiterr_arr(address_i) := '0';
END IF;
END IF;
-- Store address at which softecc error is injected:
IF (C_USE_SOFTECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
softecc_sbiterr_arr(address_i) := '1';
ELSE
softecc_sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
softecc_dbiterr_arr(address_i) := '1';
ELSE
softecc_dbiterr_arr(address_i) := '0';
END IF;
END IF;
END IF;
END PROCEDURE;
-- write_b
----------
PROCEDURE write_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_B_DIV);
IF (address_i >= C_WRITE_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEB = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_B + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEB_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_B + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
END IF;
END PROCEDURE;
-- read_a
----------
PROCEDURE read_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_A_DIV);
IF (address_i >= C_READ_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for A Read"
SEVERITY WARNING;
END IF;
memory_out_a <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_A-1 LOOP
memory_out_a(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_A + i) AFTER FLOP_DELAY;
END LOOP;
END IF;
END IF;
END PROCEDURE;
-- read_b
----------
PROCEDURE read_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_B_DIV);
IF (address_i >= C_READ_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Read"
SEVERITY WARNING;
END IF;
memory_out_b <= (OTHERS => 'X') AFTER FLOP_DELAY;
sbiterr_in <= 'X' AFTER FLOP_DELAY;
dbiterr_in <= 'X' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_B-1 LOOP
memory_out_b(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_B + i) AFTER FLOP_DELAY;
END LOOP;
--assert sbiterr and dbiterr signals
IF ((C_FAMILY="virtex7") AND C_USE_ECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
--assert softecc sbiterr and dbiterr signals
ELSIF (C_USE_SOFTECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (softecc_sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (softecc_dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
END IF;
END IF;
END IF;
END PROCEDURE;
-- reset_a
----------
PROCEDURE reset_a
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
-- reset_b
----------
PROCEDURE reset_b
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
BEGIN -- begin the main PROCESS
--***************************************************************************
-- These are the main blocks which schedule read and write operations
-- Note that the reset priority feature at the latch stage is only supported
-- for Spartan-6. For other families, the default priority at the latch stage
-- is "CE"
--***************************************************************************
-- Synchronous clocks: schedule port operations with respect to both
-- write operating modes
IF (C_COMMON_CLK=1) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODES IS
WHEN "0000" => -- write_first write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "0100" => -- read_first write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "0001" => -- write_first read_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0101" => --read_first read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0010" => -- write_first no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0110" => -- read_first no_change
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1000" => -- no_change write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "1001" => -- no_change read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1010" => -- no_change no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Synchronous clocks
-- Asynchronous clocks: port operation is independent
IF (C_COMMON_CLK=0) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODE_A IS
WHEN "00" => -- write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN "01" => -- read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "10" => -- no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
IF (CLKB='1' AND CLKB'EVENT) THEN
CASE WRITE_MODE_B IS
WHEN "00" => -- write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "01" => -- read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "10" => -- no_change
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Asynchronous clocks
-- Assign the memory VARIABLE to the user_visible memory_i SIGNAL
IF(DEBUG=1) THEN
memory_i <= memory;
doublebit_error_i <= doublebit_error;
current_contents_i <= current_contents_var;
END IF;
END PROCESS;
--********************************************************************
-- Instantiate the VARIABLE depth output stage
--********************************************************************
-- Port A
rsta_outp_stage <= RSTA and not sleep;
rstb_outp_stage <= RSTB and not sleep;
reg_a : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTA,
C_RSTRAM => C_RSTRAM_A,
C_RST_PRIORITY => C_RST_PRIORITY_A,
init_val => INITA_VAL,
C_HAS_EN => C_HAS_ENA,
C_HAS_REGCE => C_HAS_REGCEA,
C_DATA_WIDTH => C_READ_WIDTH_A,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_A,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_A,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKA,
RST => rsta_outp_stage, --RSTA,
EN => ENA,
REGCE => REGCEA,
DIN_I => memory_out_a,
DOUT => DOUTA,
SBITERR_IN_I => '0',
DBITERR_IN_I => '0',
SBITERR => OPEN,
DBITERR => OPEN,
RDADDRECC_IN_I => (OTHERS => '0'),
ECCPIPECE => '0',
RDADDRECC => OPEN
);
-- Port B
reg_b : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTB,
C_RSTRAM => C_RSTRAM_B,
C_RST_PRIORITY => C_RST_PRIORITY_B,
init_val => INITB_VAL,
C_HAS_EN => C_HAS_ENB,
C_HAS_REGCE => C_HAS_REGCEB,
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_B,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKB,
RST => rstb_outp_stage,--RSTB,
EN => ENB,
REGCE => REGCEB,
DIN_I => memory_out_b,
DOUT => doutb_i,
SBITERR_IN_I => sbiterr_in,
DBITERR_IN_I => dbiterr_in,
SBITERR => sbiterr_i,
DBITERR => dbiterr_i,
RDADDRECC_IN_I => rdaddrecc_in,
ECCPIPECE => ECCPIPECE,
RDADDRECC => rdaddrecc_i
);
--********************************************************************
-- Instantiate the input / Output Register stages
--********************************************************************
output_reg_stage: blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC MAP(
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP(
CLK => CLKB,
DIN => doutb_i,
DOUT => DOUTB,
SBITERR_IN => sbiterr_i,
DBITERR_IN => dbiterr_i,
SBITERR => sbiterr_sdp,
DBITERR => dbiterr_sdp,
RDADDRECC_IN => rdaddrecc_i,
RDADDRECC => rdaddrecc_sdp
);
--*********************************
-- Synchronous collision checks
--*********************************
sync_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=1) GENERATE
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
-- collision detect
VARIABLE is_collision : BOOLEAN;
VARIABLE message : LINE;
BEGIN
IF (CLKA='1' AND CLKA'EVENT) THEN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision := false;
END IF;
-- If the write port is in READ_FIRST mode, there is no collision
IF (C_WRITE_MODE_A="READ_FIRST" AND wea_i/=WEA0 AND web_i=WEB0) THEN
is_collision := false;
END IF;
IF (C_WRITE_MODE_B="READ_FIRST" AND web_i/=WEB0 AND wea_i=WEA0) THEN
is_collision := false;
END IF;
-- Only flag if one of the accesses is a write
IF (is_collision AND (wea_i/=WEA0 OR web_i/=WEB0)) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END IF;
END PROCESS;
END GENERATE;
--*********************************
-- Asynchronous collision checks
--*********************************
async_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=0) GENERATE
SIGNAL addra_delay : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL wea_delay : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL ena_delay : STD_LOGIC;
SIGNAL addrb_delay : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
SIGNAL web_delay : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL enb_delay : STD_LOGIC;
BEGIN
-- Delay A and B addresses in order to mimic setup/hold times
PROCESS (ADDRA, wea_i, ena_i, ADDRB, web_i, enb_i)
BEGIN
addra_delay <= ADDRA AFTER COLL_DELAY;
wea_delay <= wea_i AFTER COLL_DELAY;
ena_delay <= ena_i AFTER COLL_DELAY;
addrb_delay <= ADDRB AFTER COLL_DELAY;
web_delay <= web_i AFTER COLL_DELAY;
enb_delay <= enb_i AFTER COLL_DELAY;
END PROCESS;
-- Do the checks w/rt A
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_a : BOOLEAN;
VARIABLE is_collision_delay_a : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_a := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_a := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_delay_a := collision_check(ADDRA,
wea_i/=WEA0,
addrb_delay,
web_delay/=WEB0);
ELSE
is_collision_delay_a := false;
END IF;
-- Only flag if B access is a write
IF (is_collision_a AND web_i/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_a AND web_delay/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, addrb_delay);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
-- Do the checks w/rt B
PROCESS (CLKB)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_b : BOOLEAN;
VARIABLE is_collision_delay_b : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA) /= 'X') THEN
is_collision_b := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_b := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(addra_delay) /= 'X') THEN
is_collision_delay_b := collision_check(addra_delay,
wea_delay/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_delay_b := false;
END IF;
-- Only flag if A access is a write
-- Modified condition checking (is_collision_b AND WEA0_i=/WEA0) to fix CR526228
IF (is_collision_b AND wea_i/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_b AND wea_delay/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, addra_delay);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
END GENERATE;
END mem_module_behavioral;
--******************************************************************************
-- Top module that wraps SoftECC Input register stage and the main memory module
--
-- This module is the top-level of behavioral model
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1 IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_CTRL_ECC_ALGO : STRING := "NONE";
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
--C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_SLEEP_PIN : INTEGER := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
PORT (
clka : IN STD_LOGIC := '0';
rsta : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '1';
regcea : IN STD_LOGIC := '1';
wea : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addra : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
dina : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
douta : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
clkb : IN STD_LOGIC := '0';
rstb : IN STD_LOGIC := '0';
enb : IN STD_LOGIC := '1';
regceb : IN STD_LOGIC := '1';
web : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addrb : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
dinb : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
doutb : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
injectsbiterr : IN STD_LOGIC := '0';
injectdbiterr : IN STD_LOGIC := '0';
sbiterr : OUT STD_LOGIC := '0';
dbiterr : OUT STD_LOGIC := '0';
rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : in std_logic := '0';
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic := '0';
rstb_busy : out std_logic := '0';
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
s_aclk : IN STD_LOGIC := '0';
s_aresetn : IN STD_LOGIC := '0';
-- axi full/lite slave Write (write side)
s_axi_awid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid : IN STD_LOGIC := '0';
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast : IN STD_LOGIC := '0';
s_axi_wvalid : IN STD_LOGIC := '0';
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC := '0';
-- axi full/lite slave Read (Write side)
s_axi_arid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid : IN STD_LOGIC := '0';
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_rdata : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC := '0';
-- axi full/lite sideband Signals
s_axi_injectsbiterr : IN STD_LOGIC := '0';
s_axi_injectdbiterr : IN STD_LOGIC := '0';
s_axi_sbiterr : OUT STD_LOGIC := '0';
s_axi_dbiterr : OUT STD_LOGIC := '0';
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END blk_mem_gen_v8_3_1;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE behavioral OF blk_mem_gen_v8_3_1 IS
COMPONENT blk_mem_gen_v8_3_1_mem_module
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_mem_module;
COMPONENT blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_axi_regs_fwd_v8_3;
COMPONENT blk_mem_axi_read_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT blk_mem_axi_read_wrapper_beh;
COMPONENT blk_mem_axi_write_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END COMPONENT blk_mem_axi_write_wrapper_beh;
CONSTANT FLOP_DELAY : TIME := 100 ps;
SIGNAL rsta_in : STD_LOGIC := '1';
SIGNAL ena_in : STD_LOGIC := '1';
SIGNAL regcea_in : STD_LOGIC := '1';
SIGNAL wea_in : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL addra_in : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL dina_in : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL injectsbiterr_in : STD_LOGIC := '0';
SIGNAL injectdbiterr_in : STD_LOGIC := '0';
-----------------------------------------------------------------------------
-- FUNCTION: toLowerCaseChar
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
-----------------------------------------------------------------------------
FUNCTION toLowerCaseChar(
char : character )
RETURN character IS
BEGIN
-- If char is not an upper case letter then return char
IF char<'A' OR char>'Z' THEN
RETURN char;
END IF;
-- Otherwise map char to its corresponding lower case character and
-- RETURN that
CASE char IS
WHEN 'A' => RETURN 'a';
WHEN 'B' => RETURN 'b';
WHEN 'C' => RETURN 'c';
WHEN 'D' => RETURN 'd';
WHEN 'E' => RETURN 'e';
WHEN 'F' => RETURN 'f';
WHEN 'G' => RETURN 'g';
WHEN 'H' => RETURN 'h';
WHEN 'I' => RETURN 'i';
WHEN 'J' => RETURN 'j';
WHEN 'K' => RETURN 'k';
WHEN 'L' => RETURN 'l';
WHEN 'M' => RETURN 'm';
WHEN 'N' => RETURN 'n';
WHEN 'O' => RETURN 'o';
WHEN 'P' => RETURN 'p';
WHEN 'Q' => RETURN 'q';
WHEN 'R' => RETURN 'r';
WHEN 'S' => RETURN 's';
WHEN 'T' => RETURN 't';
WHEN 'U' => RETURN 'u';
WHEN 'V' => RETURN 'v';
WHEN 'W' => RETURN 'w';
WHEN 'X' => RETURN 'x';
WHEN 'Y' => RETURN 'y';
WHEN 'Z' => RETURN 'z';
WHEN OTHERS => RETURN char;
END CASE;
END toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
FUNCTION equalIgnoreCase(
str1 : STRING;
str2 : STRING )
RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str2'left TO str1'right LOOP
IF NOT (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equalIgnoreCase;
-----------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
----------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
----------------------------------------------------------------------------
-- FUNCTION : log2roundup
----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
CONSTANT lower_limit : INTEGER := 1;
CONSTANT upper_limit : INTEGER := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
-----------------------------------------------------------------------------
-- FUNCTION : divroundup
-- Returns the ceiling value of the division
-- Data_value - the quantity to be divided, dividend
-- Divisor - the value to divide the data_value by
-----------------------------------------------------------------------------
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
SIGNAL s_axi_awaddr_out_c : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_araddr_out_c : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_wr_en_c : STD_LOGIC := '0';
SIGNAL s_axi_rd_en_c : STD_LOGIC := '0';
SIGNAL s_aresetn_a_c : STD_LOGIC := '0';
--**************************************************************************
-- AXI PARAMETERS
CONSTANT AXI_FULL_MEMORY_SLAVE : integer := if_then_else((C_AXI_SLAVE_TYPE = 0 AND C_AXI_TYPE = 1),1,0);
CONSTANT C_AXI_ADDR_WIDTH_MSB : integer := C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
CONSTANT C_AXI_ADDR_WIDTH : integer := C_AXI_ADDR_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT LOWER_BOUND_VAL : integer := if_then_else((log2roundup(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT C_AXI_ADDR_WIDTH_LSB : integer := if_then_else((AXI_FULL_MEMORY_SLAVE = 1),0,LOWER_BOUND_VAL);
CONSTANT C_AXI_OS_WR : integer := 2;
-- SAFETY LOGIC related Signals
SIGNAL RSTA_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_A : STD_LOGIC := '0';
SIGNAL RSTB_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_B : STD_LOGIC := '0';
SIGNAL ENA_dly : STD_LOGIC := '0';
SIGNAL ENA_dly_D : STD_LOGIC := '0';
SIGNAL ENB_dly : STD_LOGIC := '0';
SIGNAL ENB_dly_D : STD_LOGIC := '0';
SIGNAL RSTA_I_SAFE : STD_LOGIC := '0';
SIGNAL RSTB_I_SAFE : STD_LOGIC := '0';
SIGNAL ENA_I_SAFE : STD_LOGIC := '0';
SIGNAL ENB_I_SAFE : STD_LOGIC := '0';
SIGNAL ram_rstram_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstram_b_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_b_busy : STD_LOGIC := '0';
SIGNAL ENA_dly_reg : STD_LOGIC := '0';
SIGNAL ENB_dly_reg : STD_LOGIC := '0';
SIGNAL ENA_dly_reg_D : STD_LOGIC := '0';
SIGNAL ENB_dly_reg_D : STD_LOGIC := '0';
--**************************************************************************
BEGIN -- Architecture
--*************************************************************************
-- NO INPUT STAGE
--*************************************************************************
no_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=0) GENERATE
rsta_in <= RSTA;
ena_in <= ENA;
regcea_in <= REGCEA;
wea_in <= WEA;
addra_in <= ADDRA;
dina_in <= DINA;
injectsbiterr_in <= INJECTSBITERR;
injectdbiterr_in <= INJECTDBITERR;
END GENERATE no_input_stage;
--**************************************************************************
-- WITH INPUT STAGE
--**************************************************************************
has_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=1) GENERATE
PROCESS (CLKA)
BEGIN
IF (CLKA'EVENT AND CLKA = '1') THEN
rsta_in <= RSTA AFTER FLOP_DELAY;
ena_in <= ENA AFTER FLOP_DELAY;
regcea_in <= REGCEA AFTER FLOP_DELAY;
wea_in <= WEA AFTER FLOP_DELAY;
addra_in <= ADDRA AFTER FLOP_DELAY;
dina_in <= DINA AFTER FLOP_DELAY;
injectsbiterr_in <= INJECTSBITERR AFTER FLOP_DELAY;
injectdbiterr_in <= INJECTDBITERR AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE has_input_stage;
--**************************************************************************
-- NO SAFETY LOGIC
--**************************************************************************
NO_SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 0) GENERATE
ENA_I_SAFE <= ena_in;
ENB_I_SAFE <= ENB;
RSTA_I_SAFE <= rsta_in;
RSTB_I_SAFE <= RSTB;
END GENERATE NO_SAFETY_CKT_GEN;
--**************************************************************************
-- SAFETY LOGIC
--**************************************************************************
SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 1) GENERATE
-- RESET SAFETY LOGIC Generation
-- POR Generation
------------------------------------------------------------------------------
-- Power-ON Reset Generation
------------------------------------------------------------------------------
RST_SHFT_LOGIC_A : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
RSTA_SHFT_REG(4 DOWNTO 0) <= RSTA_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_A;
POR_RSTA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
POR_A <= RSTA_SHFT_REG(4) xor RSTA_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTA_GEN;
RST_SHFT_LOGIC_B : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
RSTB_SHFT_REG(4 DOWNTO 0) <= RSTB_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_B;
POR_RSTB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
POR_B <= RSTB_SHFT_REG(4) xor RSTB_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTB_GEN;
-----------------------------------------------------------------------------
-- Fix for the AR42571
-----------------------------------------------------------------------------
-- Reset Generation
-----------------------------------------------------------------------------
RSTA_I_SAFE <= rsta_in OR POR_A;
SPRAM_RST: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_I_SAFE <= '0';
END GENERATE SPRAM_RST;
nSPRAM_RST: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_I_SAFE <= RSTB OR POR_B;
END GENERATE nSPRAM_RST;
-----------------------------------------------------------------------------
-- RSTA/B_BUSY Generation
-----------------------------------------------------------------------------
RSTA_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
ram_rstram_a_busy <= rsta_in OR ENA_dly OR ENA_dly_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstram_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_NO_REG;
RSTA_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
ram_rstreg_a_busy <= rsta_in OR ENA_dly OR ENA_dly_reg_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstreg_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_WITH_REG;
SPRAM_RST_BUSY: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_BUSY <= '0';
END GENERATE SPRAM_RST_BUSY;
nSPRAM_RST_BUSY: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
ram_rstram_b_busy <= RSTB OR ENB_dly OR ENB_dly_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstram_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_NO_REG;
RSTB_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
ram_rstreg_b_busy <= RSTB OR ENB_dly OR ENB_dly_reg_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstreg_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_WITH_REG;
END GENERATE nSPRAM_RST_BUSY;
-----------------------------------------------------------------------------
-- ENA/ENB Generation
-----------------------------------------------------------------------------
ENA_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly <= rsta_in AFTER FLOP_DELAY;
ENA_dly_D <= ENA_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_D OR ena_in;
END GENERATE ENA_NO_REG;
ENA_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly_reg <= rsta_in AFTER FLOP_DELAY;
ENA_dly_reg_D <= ENA_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_reg_D OR ena_in;
END GENERATE ENA_WITH_REG;
SPRAM_ENB: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
ENB_I_SAFE <= '0';
END GENERATE SPRAM_ENB;
nSPRAM_ENB: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
ENB_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly <= RSTB AFTER FLOP_DELAY;
ENB_dly_D <= ENB_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_D OR ENB;
END GENERATE ENB_NO_REG;
ENB_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly_reg <= RSTB AFTER FLOP_DELAY;
ENB_dly_reg_D <= ENB_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_reg_D OR ENB;
END GENERATE ENB_WITH_REG;
END GENERATE nSPRAM_ENB;
END GENERATE SAFETY_CKT_GEN;
--**************************************************************************
-- NATIVE MEMORY MODULE INSTANCE
--**************************************************************************
native_mem_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 0) GENERATE
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,--rsta_in,
ENA => ENA_I_SAFE,--ena_in,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in,
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => RDADDRECC
);
END GENERATE native_mem_module;
--**************************************************************************
-- NATIVE MEMORY MAPPED MODULE INSTANCE
--**************************************************************************
native_mem_map_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 1) GENERATE
--**************************************************************************
-- NATIVE MEMORY MAPPED PARAMETERS
CONSTANT C_ADDRA_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_A);
CONSTANT C_ADDRB_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_B);
CONSTANT C_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
CONSTANT C_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
CONSTANT C_MEM_MAP_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_MSB;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT MEM_MAP_LOWER_BOUND_VAL_A : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT MEM_MAP_LOWER_BOUND_VAL_B : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_B,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_B,8)));
CONSTANT C_MEM_MAP_ADDRA_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_A;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_B;
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH_ACTUAL-1 DOWNTO 0) := (OTHERS => '0');
--**************************************************************************
BEGIN
RDADDRECC(C_ADDRB_WIDTH-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_MSB) <= (OTHERS => '0');
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB) <= rdaddrecc_i;
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_LSB-1 DOWNTO 0) <= (OTHERS => '0');
mem_map_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH_ACTUAL,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH_ACTUAL,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,
ENA => ENA_I_SAFE,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in(C_MEM_MAP_ADDRA_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRA_WIDTH_LSB),
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB),
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => rdaddrecc_i
);
END GENERATE native_mem_map_module;
--****************************************************************************
-- AXI MEMORY MODULE INSTANCE
--****************************************************************************
axi_mem_module: IF (C_INTERFACE_TYPE = 1) GENERATE
SIGNAL s_axi_rid_c : STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rdata_c : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rresp_c : STD_LOGIC_VECTOR(2-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rlast_c : STD_LOGIC := '0';
SIGNAL s_axi_rvalid_c : STD_LOGIC := '0';
SIGNAL s_axi_rready_c : STD_LOGIC := '0';
SIGNAL regceb_c : STD_LOGIC := '0';
BEGIN
s_aresetn_a_c <= NOT S_ARESETN;
S_AXI_BRESP <= (OTHERS => '0');
s_axi_rresp_c <= (OTHERS => '0');
no_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 0 AND C_HAS_MUX_OUTPUT_REGS_B = 0 ) GENERATE
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RLAST <= s_axi_rlast_c;
S_AXI_RVALID <= s_axi_rvalid_c;
S_AXI_RID <= s_axi_rid_c;
S_AXI_RRESP <= s_axi_rresp_c;
s_axi_rready_c <= S_AXI_RREADY;
END GENERATE no_regs;
has_regs_fwd: IF (C_HAS_MUX_OUTPUT_REGS_B = 1 OR C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
CONSTANT C_AXI_PAYLOAD : INTEGER := if_then_else((C_HAS_MUX_OUTPUT_REGS_B = 1),C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3,C_AXI_ID_WIDTH+3);
SIGNAL s_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
has_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
regceb_c <= s_axi_rvalid_c AND s_axi_rready_c;
END GENERATE has_regceb;
no_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 0) GENERATE
regceb_c <= REGCEB;
END GENERATE no_regceb;
only_core_op_regs: IF (C_HAS_MUX_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rdata_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RDATA <= m_axi_payload_c(C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_core_op_regs;
only_emb_op_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_emb_op_regs;
axi_regs_inst : blk_mem_axi_regs_fwd_v8_3
GENERIC MAP(
C_DATA_WIDTH => C_AXI_PAYLOAD
)
PORT MAP (
ACLK => S_ACLK,
ARESET => s_aresetn_a_c,
S_VALID => s_axi_rvalid_c,
S_READY => s_axi_rready_c,
S_PAYLOAD_DATA => s_axi_payload_c,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY,
M_PAYLOAD_DATA => m_axi_payload_c
);
END GENERATE has_regs_fwd;
axi_wr_fsm : blk_mem_axi_write_wrapper_beh
GENERIC MAP(
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_AXI_AWADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_WDATA_WIDTH => C_WRITE_WIDTH_A,
C_AXI_OS_WR => C_AXI_OS_WR
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Slave Write Interface
S_AXI_AWADDR => S_AXI_AWADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_AWLEN => S_AXI_AWLEN,
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BID => S_AXI_BID,
-- Signals for BRAM interface
S_AXI_AWADDR_OUT =>s_axi_awaddr_out_c,
S_AXI_WR_EN =>s_axi_wr_en_c
);
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => 1, -- For AXI, Read Enable is always C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => 1, -- For AXI C_USE_BYTE_WEA is always 1,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => 1, -- For AXI, Read Enable is always C_HAS_ENB,
C_HAS_REGCEB => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_BYTE_WEB => 1, -- For AXI C_USE_BYTE_WEB is always 1,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => 0, --For AXI, Primitive Registers A is not supported C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => 0,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
--Port A:
CLKA => S_AClk,
RSTA => s_aresetn_a_c,
ENA => s_axi_wr_en_c,
REGCEA => regcea_in,
WEA => S_AXI_WSTRB,
ADDRA => s_axi_awaddr_out_c,
DINA => S_AXI_WDATA,
DOUTA => DOUTA,
--Port B:
CLKB => S_AClk,
RSTB => s_aresetn_a_c,
ENB => s_axi_rd_en_c,
REGCEB => regceb_c,
WEB => (OTHERS => '0'),
ADDRB => s_axi_araddr_out_c,
DINB => DINB,
DOUTB => s_axi_rdata_c,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => '0',
SLEEP => '0',
RDADDRECC => RDADDRECC
);
axi_rd_sm : blk_mem_axi_read_wrapper_beh
GENERIC MAP (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_PIPELINE_STAGES => 1,
C_AXI_ARADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_AClk,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Read Side
S_AXI_ARADDR => S_AXI_ARADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARSIZE => S_AXI_ARSIZE,
S_AXI_ARBURST => S_AXI_ARBURST,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => s_axi_rlast_c,
S_AXI_RVALID => s_axi_rvalid_c,
S_AXI_RREADY => s_axi_rready_c,
S_AXI_ARID => S_AXI_ARID,
S_AXI_RID => s_axi_rid_c,
-- AXI Full/Lite Read FSM Outputs
S_AXI_ARADDR_OUT => s_axi_araddr_out_c,
S_AXI_RD_EN => s_axi_rd_en_c
);
END GENERATE axi_mem_module;
END behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_clr is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_clr;
architecture beh_ff_clr_arch of beh_ff_clr is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(CLR, C)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_clr_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_ce is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_ce;
architecture beh_ff_ce_arch of beh_ff_ce is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, CLR)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
if (CE = '1') then
q_o <= D after 100 ps;
end if;
end if;
end process;
end beh_ff_ce_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_pre is
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end beh_ff_pre;
architecture beh_ff_pre_arch of beh_ff_pre is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, PRE)
begin
if (PRE = '1') then
q_o <= '1';
elsif (C' event and C = '1') then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_pre_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_muxf7 is
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end beh_muxf7;
architecture beh_muxf7_arch of beh_muxf7 is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
else
O <= I1;
end if;
end process;
end beh_muxf7_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity STATE_LOGIC is
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic := '0';
I0 : in std_logic := '0';
I1 : in std_logic := '0';
I2 : in std_logic := '0';
I3 : in std_logic := '0';
I4 : in std_logic := '0';
I5 : in std_logic := '0'
);
end STATE_LOGIC;
architecture STATE_LOGIC_arch of STATE_LOGIC is
constant INIT_reg : std_logic_vector(63 downto 0) := INIT;
begin
LUT_beh:process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
begin
I_reg := I5 & I4 & I3 & I2 & I1 & I0;
O <= INIT_reg(conv_integer(I_reg));
end process;
end STATE_LOGIC_arch;
|
-------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v8_3_1.vhd
--
-- Description:
-- This file is the VHDL behvarial model for the
-- Block Memory Generator Core.
--
-------------------------------------------------------------------------------
-- Author: Xilinx
--
-- History: January 11, 2006: Initial revision
-- June 11, 2007 : Added independent register stages for
-- Port A and Port B (IP1_Jm/v2.5)
-- August 28, 2007 : Added mux pipeline stages feature (IP2_Jm/v2.6)
-- April 07, 2009 : Added support for Spartan-6 and Virtex-6
-- features, including the following:
-- (i) error injection, detection and/or correction
-- (ii) reset priority
-- (iii) special reset behavior
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
ENTITY blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END ENTITY blk_mem_axi_regs_fwd_v8_3;
ARCHITECTURE axi_regs_fwd_arch OF blk_mem_axi_regs_fwd_v8_3 IS
SIGNAL STORAGE_DATA : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_READY_I : STD_LOGIC := '0';
SIGNAL M_VALID_I : STD_LOGIC := '0';
SIGNAL ARESET_D : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');-- Reset delay register
BEGIN
--assign local signal to its output signal
S_READY <= S_READY_I;
M_VALID <= M_VALID_I;
PROCESS(ACLK)
BEGIN
IF(ACLK'event AND ACLK = '1') THEN
ARESET_D <= ARESET_D(0) & ARESET;
END IF;
END PROCESS;
--Save payload data whenever we have a transaction on the slave side
PROCESS(ACLK, ARESET)
BEGIN
IF (ARESET = '1') THEN
STORAGE_DATA <= (OTHERS => '0');
ELSIF(ACLK'event AND ACLK = '1') THEN
IF(S_VALID = '1' AND S_READY_I = '1') THEN
STORAGE_DATA <= S_PAYLOAD_DATA;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= STORAGE_DATA;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
PROCESS(ACLK,ARESET)
BEGIN
IF (ARESET_D /= "00") THEN
M_VALID_I <= '0';
ELSIF(ACLK'event AND ACLK = '1') THEN
IF (S_VALID = '1') THEN
--Always set M_VALID_I when slave side is valid
M_VALID_I <= '1';
ELSIF (M_READY = '1') THEN
--Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= '0';
END IF;
END IF;
END PROCESS;
--Slave Ready is either when Master side drives M_READY or we have space in our storage data
S_READY_I <= (M_READY OR (NOT M_VALID_I)) AND NOT(OR_REDUCE(ARESET_D));
END axi_regs_fwd_arch;
-------------------------------------------------------------------------------
-- Description:
-- This is the behavioral model of write_wrapper for the
-- Block Memory Generator Core.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_axi_write_wrapper_beh IS
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END blk_mem_axi_write_wrapper_beh;
ARCHITECTURE axi_write_wrap_arch OF blk_mem_axi_write_wrapper_beh IS
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_AXI_WDATA_WIDTH=8,0,
if_then_else((C_AXI_WDATA_WIDTH=16),1,
if_then_else((C_AXI_WDATA_WIDTH=32),2,
if_then_else((C_AXI_WDATA_WIDTH=64),3,
if_then_else((C_AXI_WDATA_WIDTH=128),4,
if_then_else((C_AXI_WDATA_WIDTH=256),5,0))))));
SIGNAL bvalid_c : std_logic := '0';
SIGNAL bready_timeout_c : std_logic := '0';
SIGNAL bvalid_rd_cnt_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_r : std_logic := '0';
SIGNAL bvalid_count_r : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL awaddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
C_AXI_AWADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL bvalid_wr_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_rd_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_last_c : std_logic := '0';
SIGNAL addr_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL aw_ready_r : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL awlen_cntr_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1');
SIGNAL awlen_int : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL awburst_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes : integer := 0;
SIGNAL wrap_boundary : integer := 0;
SIGNAL wrap_base_addr : integer := 0;
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
-- Array to store BIDs
TYPE id_array IS ARRAY (3 DOWNTO 0) OF std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
SIGNAL axi_bid_array : id_array := (others => (others => '0'));
COMPONENT write_netlist
GENERIC(
C_AXI_TYPE : integer
);
PORT(
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
S_AXI_AWVALID : IN std_logic;
aw_ready_r : OUT std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN std_logic;
S_AXI_WR_EN : OUT std_logic;
w_last_c : IN std_logic;
bready_timeout_c : IN std_logic;
addr_en_c : OUT std_logic;
incr_addr_c : OUT std_logic;
bvalid_c : OUT std_logic
);
END COMPONENT write_netlist;
BEGIN
---------------------------------------
--AXI WRITE FSM COMPONENT INSTANTIATION
---------------------------------------
axi_wr_fsm : write_netlist
GENERIC MAP (
C_AXI_TYPE => C_AXI_TYPE
)
PORT MAP (
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
S_AXI_AWVALID => S_AXI_AWVALID,
aw_ready_r => aw_ready_r,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BVALID => OPEN,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_WR_EN => S_AXI_WR_EN,
w_last_c => w_last_c,
bready_timeout_c => bready_timeout_c,
addr_en_c => addr_en_c,
incr_addr_c => incr_addr_c,
bvalid_c => bvalid_c
);
--Wrap Address boundary calculation
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWSIZE,"000"));
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(awlen_int)+1);
wrap_base_addr <= (conv_integer(awaddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary <= wrap_base_addr+total_bytes;
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awaddr_reg <= (OTHERS => '0');
num_of_bytes_r <= 0;
awburst_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awaddr_reg <= S_AXI_AWADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWBURST,"01");
ELSIF (incr_addr_c = '1') THEN
IF (awburst_int = "10") THEN
IF(conv_integer(awaddr_reg) = (wrap_boundary-num_of_bytes_r)) THEN
awaddr_reg <= conv_std_logic_vector(wrap_base_addr,C_AXI_AWADDR_WIDTH);
ELSE
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
ELSIF (awburst_int = "01" OR awburst_int = "11") THEN
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
S_AXI_AWADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
awaddr_reg(C_AXI_AWADDR_WIDTH-1 DOWNTO C_RANGE),awaddr_reg);
---------------------------------------------------------------------------
-- AXI wlast generation
---------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awlen_cntr_r <= (OTHERS => '1');
awlen_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awlen_int <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
awlen_cntr_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
ELSIF (dec_alen_c = '1') THEN
awlen_cntr_r <= awlen_cntr_r - ONE AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
w_last_c <= '1' WHEN (awlen_cntr_r = "00000000" AND S_AXI_WVALID = '1') ELSE '0';
dec_alen_c <= (incr_addr_c OR w_last_c);
---------------------------------------------------------------------------
-- Generation of bvalid counter for outstanding transactions
---------------------------------------------------------------------------
P_b_valid_os_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_count_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- bvalid_count_r generation
IF (bvalid_c = '1' AND bvalid_r = '1' AND S_AXI_BREADY = '1') THEN
bvalid_count_r <= bvalid_count_r AFTER FLOP_DELAY;
ELSIF (bvalid_c = '1') THEN
bvalid_count_r <= bvalid_count_r + "01" AFTER FLOP_DELAY;
ELSIF (bvalid_r = '1' AND S_AXI_BREADY = '1' AND bvalid_count_r /= "0") THEN
bvalid_count_r <= bvalid_count_r - "01" AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_os_r ;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is used
---------------------------------------------------------------------------
gaxi_bvalid_id_r:IF (C_HAS_AXI_ID = 1) GENERATE
SIGNAL bvalid_d1_c : std_logic := '0';
BEGIN
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
bvalid_d1_c <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
--external bvalid signal generation
IF (bvalid_d1_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_id_r;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is not used
---------------------------------------------------------------------------
gaxi_bvalid_noid_r:IF (C_HAS_AXI_ID = 0) GENERATE
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
--external bvalid signal generation
IF (bvalid_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_noid_r;
---------------------------------------------------------------------------
-- Generation of Bready timeout
---------------------------------------------------------------------------
P_brdy_tout_c: PROCESS (bvalid_count_r)
BEGIN
-- bready_timeout_c generation
IF(conv_integer(bvalid_count_r) = C_AXI_OS_WR-1) THEN
bready_timeout_c <= '1';
ELSE
bready_timeout_c <= '0';
END IF;
END PROCESS P_brdy_tout_c;
---------------------------------------------------------------------------
-- Generation of BID
---------------------------------------------------------------------------
gaxi_bid_gen:IF (C_HAS_AXI_ID = 1) GENERATE
P_bid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
bvalid_wr_cnt_r <= (OTHERS => '0');
bvalid_rd_cnt_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- STORE AWID IN AN ARRAY
IF(bvalid_c = '1') THEN
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + "01";
END IF;
-- GENERATE BID FROM AWID ARRAY
bvalid_rd_cnt_r <= bvalid_rd_cnt_c AFTER FLOP_DELAY;
S_AXI_BID <= axi_bid_array(conv_integer(bvalid_rd_cnt_c));
END IF;
END PROCESS P_bid_gen;
bvalid_rd_cnt_c <= bvalid_rd_cnt_r + "01" WHEN (bvalid_r = '1' AND S_AXI_BREADY = '1') ELSE bvalid_rd_cnt_r;
---------------------------------------------------------------------------
-- Storing AWID for generation of BID
---------------------------------------------------------------------------
P_awid_reg:PROCESS (S_ACLK)
BEGIN
IF (S_ACLK'event AND S_ACLK='1') THEN
IF(aw_ready_r = '1' AND S_AXI_AWVALID = '1') THEN
axi_bid_array(conv_integer(bvalid_wr_cnt_r)) <= S_AXI_AWID;
END IF;
END IF;
END PROCESS P_awid_reg;
END GENERATE gaxi_bid_gen;
S_AXI_BVALID <= bvalid_r;
S_AXI_AWREADY <= aw_ready_r;
END axi_write_wrap_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity write_netlist is
GENERIC(
C_AXI_TYPE : integer
);
port (
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_AWVALID : in STD_LOGIC := '0';
S_AXI_WVALID : in STD_LOGIC := '0';
S_AXI_BREADY : in STD_LOGIC := '0';
w_last_c : in STD_LOGIC := '0';
bready_timeout_c : in STD_LOGIC := '0';
aw_ready_r : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_WR_EN : out STD_LOGIC;
addr_en_c : out STD_LOGIC;
incr_addr_c : out STD_LOGIC;
bvalid_c : out STD_LOGIC
);
end write_netlist;
architecture STRUCTURE of write_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
BEGIN
---------------------------------------------------------------------------
-- AXI LITE
---------------------------------------------------------------------------
gbeh_axi_lite_sm: IF (C_AXI_TYPE = 0 ) GENERATE
signal w_ready_r_7 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSignal_bvalid_c : STD_LOGIC;
signal NlwRenamedSignal_incr_addr_c : STD_LOGIC;
signal present_state_FSM_FFd3_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal present_state_FSM_FFd1_15 : STD_LOGIC;
signal present_state_FSM_FFd4_16 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd4_In1_21 : STD_LOGIC;
signal Mmux_aw_ready_c : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
S_AXI_WREADY <= w_ready_r_7;
S_AXI_BVALID <= NlwRenamedSignal_incr_addr_c;
S_AXI_WR_EN <= NlwRenamedSignal_bvalid_c;
incr_addr_c <= NlwRenamedSignal_incr_addr_c;
bvalid_c <= NlwRenamedSignal_bvalid_c;
NlwRenamedSignal_incr_addr_c <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_7
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_16
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_13
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_15
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000055554440"
)
port map (
I0 => S_AXI_WVALID,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => '0',
O => present_state_FSM_FFd3_In
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"0000000088880800"
)
port map (
I0 => S_AXI_AWVALID,
I1 => S_AXI_WVALID,
I2 => bready_timeout_c,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => present_state_FSM_FFd2_In
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAA2000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_WVALID,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => addr_en_c
);
Mmux_w_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"F5F07570F5F05500"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => w_ready_c
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd3_13,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd1_15,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_14,
I2 => present_state_FSM_FFd3_13,
I3 => '0',
I4 => '0',
I5 => '0',
O => NlwRenamedSignal_bvalid_c
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"2F0F27072F0F2200"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => present_state_FSM_FFd4_In1_21
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_In1_21,
I3 => '0',
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_aw_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"7535753575305500"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => S_AXI_WVALID,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => present_state_FSM_FFd2_14,
O => Mmux_aw_ready_c(0)
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => Mmux_aw_ready_c(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => aw_ready_c
);
END GENERATE gbeh_axi_lite_sm;
---------------------------------------------------------------------------
-- AXI FULL
---------------------------------------------------------------------------
gbeh_axi_full_sm: IF (C_AXI_TYPE = 1 ) GENERATE
signal w_ready_r_8 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSig_OI_bvalid_c : STD_LOGIC;
signal present_state_FSM_FFd1_16 : STD_LOGIC;
signal present_state_FSM_FFd4_17 : STD_LOGIC;
signal present_state_FSM_FFd3_18 : STD_LOGIC;
signal present_state_FSM_FFd2_19 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd2_In1_24 : STD_LOGIC;
signal present_state_FSM_FFd4_In1_25 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal N4 : STD_LOGIC;
begin
S_AXI_WREADY <= w_ready_r_8;
bvalid_c <= NlwRenamedSig_OI_bvalid_c;
S_AXI_BVALID <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_8
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_17
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_18
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_19
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_16
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000000005540"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd4_17,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd3_In
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"BF3FBB33AF0FAA00"
)
port map (
I0 => S_AXI_BREADY,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd1_16,
I4 => present_state_FSM_FFd4_17,
I5 => NlwRenamedSig_OI_bvalid_c,
O => aw_ready_c
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"AAAAAAAA20000000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_19,
I3 => S_AXI_WVALID,
I4 => w_last_c,
I5 => present_state_FSM_FFd4_17,
O => addr_en_c
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_19,
I2 => present_state_FSM_FFd3_18,
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_WR_EN
);
Mmux_incr_addr_c_0_1 : STATE_LOGIC
generic map(
INIT => X"0000000000002220"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => incr_addr_c
);
Mmux_aw_ready_c_0_11 : STATE_LOGIC
generic map(
INIT => X"0000000000008880"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => NlwRenamedSig_OI_bvalid_c
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"000000000000D5C0"
)
port map (
I0 => w_last_c,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd4_17,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd2_In1_24
);
present_state_FSM_FFd2_In2 : STATE_LOGIC
generic map(
INIT => X"FFFFAAAA08AAAAAA"
)
port map (
I0 => present_state_FSM_FFd2_19,
I1 => S_AXI_AWVALID,
I2 => bready_timeout_c,
I3 => w_last_c,
I4 => S_AXI_WVALID,
I5 => present_state_FSM_FFd2_In1_24,
O => present_state_FSM_FFd2_In
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"00C0004000C00000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => w_last_c,
I2 => S_AXI_WVALID,
I3 => bready_timeout_c,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => present_state_FSM_FFd4_In1_25
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88F8"
)
port map (
I0 => present_state_FSM_FFd1_16,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_17,
I3 => S_AXI_AWVALID,
I4 => present_state_FSM_FFd4_In1_25,
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_w_ready_c_0_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => w_last_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_w_ready_c_0_Q : STATE_LOGIC
generic map(
INIT => X"FABAFABAFAAAF000"
)
port map (
I0 => N2,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd4_17,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => w_ready_c
);
Mmux_aw_ready_c_0_11_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => bready_timeout_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => w_last_c,
I1 => N4,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => present_state_FSM_FFd1_16,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
END GENERATE gbeh_axi_full_sm;
end STRUCTURE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--AXI Behavioral Model entities
ENTITY blk_mem_axi_read_wrapper_beh is
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
port (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END blk_mem_axi_read_wrapper_beh;
architecture blk_mem_axi_read_wrapper_beh_arch of blk_mem_axi_read_wrapper_beh is
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_WRITE_WIDTH_A=8,0,
if_then_else((C_WRITE_WIDTH_A=16),1,
if_then_else((C_WRITE_WIDTH_A=32),2,
if_then_else((C_WRITE_WIDTH_A=64),3,
if_then_else((C_WRITE_WIDTH_A=128),4,
if_then_else((C_WRITE_WIDTH_A=256),5,0))))));
SIGNAL ar_id_r : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
SIGNAL addr_en_c : std_logic := '0';
SIGNAL rd_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL single_trans_c : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL mux_sel_c : std_logic := '0';
SIGNAL r_last_c : std_logic := '0';
SIGNAL r_last_int_c : std_logic := '0';
SIGNAL arlen_int_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL arlen_cntr : std_logic_vector(7 DOWNTO 0) := ONE;
SIGNAL arburst_int_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL arburst_int_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL araddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),C_AXI_ARADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL total_bytes : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
SIGNAL wrap_base_addr_r : integer := 0;
SIGNAL wrap_boundary_r : integer := 0;
SIGNAL arlen_int_c : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes_c : integer := 0;
SIGNAL wrap_base_addr_c : integer := 0;
SIGNAL wrap_boundary_c : integer := 0;
SIGNAL araddr_out : std_logic_vector(C_ADDRB_WIDTH-1 downto 0) := (OTHERS => '0');
COMPONENT read_netlist
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_INCR_ADDR : OUT std_logic := '0';
S_AXI_ADDR_EN : OUT std_logic := '0';
S_AXI_SINGLE_TRANS : OUT std_logic := '0';
S_AXI_MUX_SEL : OUT std_logic := '0';
S_AXI_R_LAST : OUT std_logic := '0';
S_AXI_R_LAST_INT : IN std_logic := '0';
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT read_netlist;
BEGIN
dec_alen_c <= incr_addr_c OR r_last_int_c;
axi_read_fsm : read_netlist
GENERIC MAP(
C_AXI_TYPE => 1,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
S_AXI_INCR_ADDR => incr_addr_c,
S_AXI_ADDR_EN => addr_en_c,
S_AXI_SINGLE_TRANS => single_trans_c,
S_AXI_MUX_SEL => mux_sel_c,
S_AXI_R_LAST => r_last_c,
S_AXI_R_LAST_INT => r_last_int_c,
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN => rd_en_c
);
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(arlen_int_r)+1);
wrap_base_addr_r <= (conv_integer(araddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary_r <= wrap_base_addr_r+total_bytes;
---- combinatorial from interface
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARSIZE,"000"));
arlen_int_c <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
total_bytes_c <= conv_integer(num_of_bytes_c)*(conv_integer(arlen_int_c)+1);
wrap_base_addr_c <= (conv_integer(S_AXI_ARADDR)/if_then_else(total_bytes_c=0,1,total_bytes_c))*(total_bytes_c);
wrap_boundary_c <= wrap_base_addr_c+total_bytes_c;
arburst_int_c <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARBURST,"01");
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
araddr_reg <= (OTHERS => '0');
arburst_int_r <= (OTHERS => '0');
num_of_bytes_r <= 0;
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (incr_addr_c = '1' AND addr_en_c = '1' AND single_trans_c = '0') THEN
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
IF (arburst_int_c = "10") THEN
IF(conv_integer(S_AXI_ARADDR) = (wrap_boundary_c-num_of_bytes_c)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_c,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (arburst_int_c = "01" OR arburst_int_c = "11") THEN
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (addr_en_c = '1') THEN
araddr_reg <= S_AXI_ARADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
ELSIF (incr_addr_c = '1') THEN
IF (arburst_int_r = "10") THEN
IF(conv_integer(araddr_reg) = (wrap_boundary_r-num_of_bytes_r)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_r,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
ELSIF (arburst_int_r = "01" OR arburst_int_r = "11") THEN
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
araddr_out <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),araddr_reg(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),araddr_reg);
--------------------------------------------------------------------------
-- Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
--------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF S_ARESETN = '1' THEN
arlen_cntr <= ONE;
arlen_int_r <= (OTHERS => '0');
ELSIF S_ACLK'event AND S_ACLK = '1' THEN
IF (addr_en_c = '1' AND dec_alen_c = '1' AND single_trans_c = '0') THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= S_AXI_ARLEN - ONE AFTER FLOP_DELAY;
ELSIF addr_en_c = '1' THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
ELSIF dec_alen_c = '1' THEN
arlen_cntr <= arlen_cntr - ONE AFTER FLOP_DELAY;
ELSE
arlen_cntr <= arlen_cntr AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
r_last_int_c <= '1' WHEN (arlen_cntr = "00000000" AND S_AXI_RREADY = '1') ELSE '0' ;
--------------------------------------------------------------------------
-- AXI FULL FSM
-- Mux Selection of ARADDR
-- ARADDR is driven out from the read fsm based on the mux_sel_c
-- Based on mux_sel either ARADDR is given out or the latched ARADDR is
-- given out to BRAM
--------------------------------------------------------------------------
P_araddr_mux: PROCESS (mux_sel_c,S_AXI_ARADDR,araddr_out)
BEGIN
IF (mux_sel_c = '0') THEN
S_AXI_ARADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARADDR(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),S_AXI_ARADDR);
ELSE
S_AXI_ARADDR_OUT <= araddr_out;
END IF;
END PROCESS P_araddr_mux;
--------------------------------------------------------------------------
-- Assign output signals - AXI FULL FSM
--------------------------------------------------------------------------
S_AXI_RD_EN <= rd_en_c;
grid: IF (C_HAS_AXI_ID = 1) GENERATE
P_rid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
S_AXI_RID <= (OTHERS => '0');
ar_id_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
IF (addr_en_c = '1' AND rd_en_c = '1') THEN
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
ELSIF (addr_en_c = '1' AND rd_en_c = '0') THEN
ar_id_r <= S_AXI_ARID;
ELSIF (rd_en_c = '1') THEN
S_AXI_RID <= ar_id_r;
END IF;
END IF;
END PROCESS P_rid_gen;
END GENERATE grid;
END blk_mem_axi_read_wrapper_beh_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity read_netlist is
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_R_LAST_INT : in STD_LOGIC := '0';
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_ARVALID : in STD_LOGIC := '0';
S_AXI_RREADY : in STD_LOGIC := '0';
S_AXI_INCR_ADDR : out STD_LOGIC;
S_AXI_ADDR_EN : out STD_LOGIC;
S_AXI_SINGLE_TRANS : out STD_LOGIC;
S_AXI_MUX_SEL : out STD_LOGIC;
S_AXI_R_LAST : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RLAST : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RD_EN : out STD_LOGIC;
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end read_netlist;
architecture STRUCTURE of read_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
signal present_state_FSM_FFd1_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_r_15 : STD_LOGIC;
signal gaxi_full_sm_ar_ready_r_16 : STD_LOGIC;
signal gaxi_full_sm_r_last_r_17 : STD_LOGIC;
signal NlwRenamedSig_OI_gaxi_full_sm_r_valid_r : STD_LOGIC;
signal gaxi_full_sm_r_valid_c : STD_LOGIC;
signal S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o : STD_LOGIC;
signal gaxi_full_sm_ar_ready_c : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_c : STD_LOGIC;
signal NlwRenamedSig_OI_S_AXI_R_LAST : STD_LOGIC;
signal S_AXI_ARLEN_7_GND_8_o_equal_1_o : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal Mmux_S_AXI_R_LAST13 : STD_LOGIC;
signal N01 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal Mmux_gaxi_full_sm_ar_ready_c11 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N8 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N13 : STD_LOGIC;
begin
S_AXI_R_LAST <= NlwRenamedSig_OI_S_AXI_R_LAST;
S_AXI_ARREADY <= gaxi_full_sm_ar_ready_r_16;
S_AXI_RLAST <= gaxi_full_sm_r_last_r_17;
S_AXI_RVALID <= NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
gaxi_full_sm_outstanding_read_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_outstanding_read_c,
Q => gaxi_full_sm_outstanding_read_r_15
);
gaxi_full_sm_r_valid_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => gaxi_full_sm_r_valid_c,
Q => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r
);
gaxi_full_sm_ar_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_ar_ready_c,
Q => gaxi_full_sm_ar_ready_r_16
);
gaxi_full_sm_r_last_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => NlwRenamedSig_OI_S_AXI_R_LAST,
Q => gaxi_full_sm_r_last_r_17
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_13
);
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 : STATE_LOGIC
generic map(
INIT => X"000000000000000B"
)
port map (
I0 => S_AXI_RREADY,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o
);
Mmux_S_AXI_SINGLE_TRANS11 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_SINGLE_TRANS
);
Mmux_S_AXI_ADDR_EN11 : STATE_LOGIC
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_ADDR_EN
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"ECEE2022EEEE2022"
)
port map (
I0 => S_AXI_ARVALID,
I1 => present_state_FSM_FFd1_13,
I2 => S_AXI_RREADY,
I3 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I4 => present_state_FSM_FFd2_14,
I5 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
O => present_state_FSM_FFd2_In
);
Mmux_S_AXI_R_LAST131 : STATE_LOGIC
generic map(
INIT => X"0000000044440444"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_RREADY,
I5 => '0',
O => Mmux_S_AXI_R_LAST13
);
Mmux_S_AXI_INCR_ADDR11 : STATE_LOGIC
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => S_AXI_R_LAST_INT,
I1 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => Mmux_S_AXI_R_LAST13,
O => S_AXI_INCR_ADDR
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000FE"
)
port map (
I0 => S_AXI_ARLEN(2),
I1 => S_AXI_ARLEN(1),
I2 => S_AXI_ARLEN(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => N01
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q : STATE_LOGIC
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => S_AXI_ARLEN(7),
I1 => S_AXI_ARLEN(6),
I2 => S_AXI_ARLEN(5),
I3 => S_AXI_ARLEN(4),
I4 => S_AXI_ARLEN(3),
I5 => N01,
O => S_AXI_ARLEN_7_GND_8_o_equal_1_o
);
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_gaxi_full_sm_outstanding_read_c1 : STATE_LOGIC
generic map(
INIT => X"0020000002200200"
)
port map (
I0 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd1_13,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => N2,
O => gaxi_full_sm_outstanding_read_c
);
Mmux_gaxi_full_sm_ar_ready_c12 : STATE_LOGIC
generic map(
INIT => X"0000000000004555"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => '0',
I5 => '0',
O => Mmux_gaxi_full_sm_ar_ready_c11
);
Mmux_S_AXI_R_LAST11_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000EF"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
Mmux_S_AXI_R_LAST11 : STATE_LOGIC
generic map(
INIT => X"FCAAFC0A00AA000A"
)
port map (
I0 => S_AXI_ARVALID,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => N4,
I5 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
O => gaxi_full_sm_r_valid_c
);
S_AXI_MUX_SEL1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAAAA08"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => '0',
O => S_AXI_MUX_SEL
);
Mmux_S_AXI_RD_EN11 : STATE_LOGIC
generic map(
INIT => X"F3F3F755A2A2A200"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => gaxi_full_sm_outstanding_read_r_15,
I4 => present_state_FSM_FFd2_14,
I5 => S_AXI_ARVALID,
O => S_AXI_RD_EN
);
present_state_FSM_FFd1_In3 : beh_muxf7
port map (
I0 => N8,
I1 => N9,
S => present_state_FSM_FFd1_13,
O => present_state_FSM_FFd1_In
);
present_state_FSM_FFd1_In3_F : STATE_LOGIC
generic map(
INIT => X"000000005410F4F0"
)
port map (
I0 => S_AXI_RREADY,
I1 => present_state_FSM_FFd2_14,
I2 => S_AXI_ARVALID,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => '0',
O => N8
);
present_state_FSM_FFd1_In3_G : STATE_LOGIC
generic map(
INIT => X"0000000072FF7272"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N9
);
Mmux_gaxi_full_sm_ar_ready_c14 : beh_muxf7
port map (
I0 => N10,
I1 => N11,
S => present_state_FSM_FFd1_13,
O => gaxi_full_sm_ar_ready_c
);
Mmux_gaxi_full_sm_ar_ready_c14_F : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88A8"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => Mmux_gaxi_full_sm_ar_ready_c11,
I5 => '0',
O => N10
);
Mmux_gaxi_full_sm_ar_ready_c14_G : STATE_LOGIC
generic map(
INIT => X"000000008D008D8D"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N11
);
Mmux_S_AXI_R_LAST1 : beh_muxf7
port map (
I0 => N12,
I1 => N13,
S => present_state_FSM_FFd1_13,
O => NlwRenamedSig_OI_S_AXI_R_LAST
);
Mmux_S_AXI_R_LAST1_F : STATE_LOGIC
generic map(
INIT => X"0000000088088888"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N12
);
Mmux_S_AXI_R_LAST1_G : STATE_LOGIC
generic map(
INIT => X"00000000E400E4E4"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => S_AXI_R_LAST_INT,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N13
);
end STRUCTURE;
-------------------------------------------------------------------------------
-- Output Register Stage Entity
--
-- This module builds the output register stages of the memory. This module is
-- instantiated in the main memory module (blk_mem_gen_v8_3_1) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_output_stage IS
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_output_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6" and "virtex6l".
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
-- C_HAS_RST : Determines the presence of the RST port
-- C_RSTRAM : Determines if special reset behavior is used
-- C_RST_PRIORITY : Determines the priority between CE and SR
-- C_INIT_VAL : Initialization value
-- C_HAS_EN : Determines the presence of the EN port
-- C_HAS_REGCE : Determines the presence of the REGCE port
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
-- of the RAM primitive
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- NUM_STAGES : Determines the number of output stages
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE output_stage_behavioral OF blk_mem_gen_v8_3_1_output_stage IS
--*******************************************************
-- Functions used in the output stage ARCHITECTURE
--*******************************************************
-- Calculate num_reg_stages
FUNCTION get_num_reg_stages(NUM_STAGES: INTEGER) RETURN INTEGER IS
VARIABLE num_reg_stages : INTEGER := 0;
BEGIN
IF (NUM_STAGES = 0) THEN
num_reg_stages := 0;
ELSE
num_reg_stages := NUM_STAGES - 1;
END IF;
RETURN num_reg_stages;
END get_num_reg_stages;
-- Check if the INTEGER is zero or non-zero
FUNCTION int_to_bit(input: INTEGER) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = 0) THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END int_to_bit;
-- Constants
CONSTANT HAS_EN : STD_LOGIC := int_to_bit(C_HAS_EN);
CONSTANT HAS_REGCE : STD_LOGIC := int_to_bit(C_HAS_REGCE);
CONSTANT HAS_RST : STD_LOGIC := int_to_bit(C_HAS_RST);
CONSTANT REG_STAGES : INTEGER := get_num_reg_stages(NUM_STAGES);
-- Pipeline array
TYPE reg_data_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
TYPE reg_ecc_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC;
TYPE reg_eccaddr_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
CONSTANT REG_INIT : reg_data_array := (OTHERS => init_val);
SIGNAL out_regs : reg_data_array := REG_INIT;
SIGNAL sbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL dbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL rdaddrecc_regs: reg_eccaddr_array := (OTHERS => (OTHERS => '0'));
-- Internal signals
SIGNAL en_i : STD_LOGIC;
SIGNAL regce_i : STD_LOGIC;
SIGNAL rst_i : STD_LOGIC;
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := init_val;
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL DIN : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL RDADDRECC_IN : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ;
SIGNAL SBITERR_IN : STD_LOGIC := '0';
SIGNAL DBITERR_IN : STD_LOGIC := '0';
BEGIN
--***********************************************************************
-- Assign internal signals. This effectively wires off optional inputs.
--***********************************************************************
-- Internal enable for output registers is tied to user EN or '1' depending
-- on parameters
en_i <= EN OR (NOT HAS_EN);
-- Internal register enable for output registers is tied to user REGCE, EN
-- or '1' depending on parameters
regce_i <= (HAS_REGCE AND REGCE)
OR ((NOT HAS_REGCE) AND en_i);
-- Internal SRR is tied to user RST or '0' depending on parameters
rst_i <= RST AND HAS_RST;
--***************************************************************************
-- NUM_STAGES = 0 (No output registers. RAM only)
--***************************************************************************
zero_stages: IF (NUM_STAGES = 0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE zero_stages;
NO_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 0) GENERATE
DIN <= DIN_I;
RDADDRECC_IN <= RDADDRECC_IN_I;
SBITERR_IN <= SBITERR_IN_I;
DBITERR_IN <= DBITERR_IN_I;
END GENERATE NO_ECC_PIPE_REG;
WITH_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(ECCPIPECE = '1') THEN
DIN <= DIN_I AFTER FLOP_DELAY;
RDADDRECC_IN <= RDADDRECC_IN_I AFTER FLOP_DELAY;
SBITERR_IN <= SBITERR_IN_I AFTER FLOP_DELAY;
DBITERR_IN <= DBITERR_IN_I AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS;
END GENERATE WITH_ECC_PIPE_REG;
--***************************************************************************
-- NUM_STAGES = 1
-- (Mem Output Reg only or Mux Output Reg only)
--***************************************************************************
-- Possible valid combinations:
-- Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
-- +-----------------------------------------+
-- | C_RSTRAM_* | Reset Behavior |
-- +----------------+------------------------+
-- | 0 | Normal Behavior |
-- +----------------+------------------------+
-- | 1 | Special Behavior |
-- +----------------+------------------------+
--
-- Normal = REGCE gates reset, as in the case of all Virtex families and all
-- spartan families with the exception of S3ADSP and S6.
-- Special = EN gates reset, as in the case of S3ADSP and S6.
one_stage_norm: IF (NUM_STAGES = 1 AND
(C_RSTRAM=0 OR (C_RSTRAM=1 AND (C_XDEVICEFAMILY/="spartan3adsp" AND C_XDEVICEFAMILY/="aspartan3adsp")) OR
C_HAS_MEM_OUTPUT_REGS=0 OR C_HAS_RST=0)) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i = '1' AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
END IF;--CLK
END PROCESS;
END GENERATE one_stage_norm;
-- Special Reset Behavior for S6 and S3ADSP
one_stage_splbhv: IF (NUM_STAGES=1 AND C_RSTRAM=1 AND (C_XDEVICEFAMILY ="spartan3adsp" OR C_XDEVICEFAMILY ="aspartan3adsp"))
GENERATE
DOUT <= dout_i;
SBITERR <= '0';
DBITERR <= '0';
RDADDRECC <= (OTHERS => '0');
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (rst_i='1' AND en_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
ELSIF (regce_i='1' AND rst_i/='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE one_stage_splbhv;
--****************************************************************************
-- NUM_STAGES > 1
-- Mem Output Reg + Mux Output Reg
-- or
-- Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
-- or
-- Mux Pipeline Stages (>0) + Mux Output Reg
--****************************************************************************
multi_stage: IF (NUM_STAGES > 1) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i='1'AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
IF (en_i='1') THEN
-- Shift the data through the output stages
FOR i IN 1 TO REG_STAGES-1 LOOP
out_regs(i) <= out_regs(i-1) AFTER FLOP_DELAY;
sbiterr_regs(i) <= sbiterr_regs(i-1) AFTER FLOP_DELAY;
dbiterr_regs(i) <= dbiterr_regs(i-1) AFTER FLOP_DELAY;
rdaddrecc_regs(i) <= rdaddrecc_regs(i-1) AFTER FLOP_DELAY;
END LOOP;
out_regs(0) <= DIN;
sbiterr_regs(0) <= SBITERR_IN;
dbiterr_regs(0) <= DBITERR_IN;
rdaddrecc_regs(0) <= RDADDRECC_IN;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE multi_stage;
END output_stage_behavioral;
-------------------------------------------------------------------------------
-- SoftECC Output Register Stage Entity
-- This module builds the softecc output register stages. This module is
-- instantiated in the memory module (blk_mem_gen_v8_3_1_mem_module) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ;
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- of the RAM primitive
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE softecc_output_reg_stage_behavioral OF blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
-- Internal signals
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
--***************************************************************************
-- NO OUTPUT STAGES
--***************************************************************************
no_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE no_output_stage;
--****************************************************************************
-- WITH OUTPUT STAGE
--****************************************************************************
has_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END PROCESS;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
END GENERATE has_output_stage;
END softecc_output_reg_stage_behavioral;
--******************************************************************************
-- Main Memory module
--
-- This module is the behavioral model which implements the RAM
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
ENTITY blk_mem_gen_v8_3_1_mem_module IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_mem_module;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE mem_module_behavioral OF blk_mem_gen_v8_3_1_mem_module IS
--****************************************
-- min/max constant functions
--****************************************
-- get_max
----------
function SLV_TO_INT(SLV: in std_logic_vector
) return integer is
variable int : integer;
begin
int := 0;
for i in SLV'high downto SLV'low loop
int := int * 2;
if SLV(i) = '1' then
int := int + 1;
end if;
end loop;
return int;
end;
FUNCTION get_max(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a > b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-- get_min
----------
FUNCTION get_min(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
--***************************************************************
-- convert write_mode from STRING type for use in case statement
--***************************************************************
FUNCTION write_mode_to_vector(mode: STRING) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF (mode = "NO_CHANGE") THEN
RETURN "10";
ELSIF (mode = "READ_FIRST") THEN
RETURN "01";
ELSE
RETURN "00"; -- WRITE_FIRST
END IF;
END FUNCTION;
--***************************************************************
-- convert hex STRING to STD_LOGIC_VECTOR
--***************************************************************
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
--***************************************************************
-- locally derived constants to determine memory shape
--***************************************************************
CONSTANT MIN_WIDTH_A : INTEGER := get_min(C_WRITE_WIDTH_A, C_READ_WIDTH_A);
CONSTANT MIN_WIDTH_B : INTEGER := get_min(C_WRITE_WIDTH_B,C_READ_WIDTH_B);
CONSTANT MIN_WIDTH : INTEGER := get_min(MIN_WIDTH_A, MIN_WIDTH_B);
CONSTANT MAX_DEPTH_A : INTEGER := get_max(C_WRITE_DEPTH_A, C_READ_DEPTH_A);
CONSTANT MAX_DEPTH_B : INTEGER := get_max(C_WRITE_DEPTH_B, C_READ_DEPTH_B);
CONSTANT MAX_DEPTH : INTEGER := get_max(MAX_DEPTH_A, MAX_DEPTH_B);
TYPE int_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF std_logic_vector(C_WRITE_WIDTH_A-1 DOWNTO 0);
TYPE mem_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC_VECTOR(MIN_WIDTH-1 DOWNTO 0);
TYPE ecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
TYPE softecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
--***************************************************************
-- memory initialization function
--***************************************************************
IMPURE FUNCTION init_memory(DEFAULT_DATA :
STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
write_width_a : INTEGER;
depth : INTEGER;
width : INTEGER)
RETURN mem_array IS
VARIABLE init_return : mem_array := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(write_width_a-1 DOWNTO 0);
VARIABLE int_mem_vector : int_array:= (OTHERS => (OTHERS => '0'));
VARIABLE file_buffer : LINE;
VARIABLE i : INTEGER := 0;
VARIABLE j : INTEGER;
VARIABLE k : INTEGER;
VARIABLE ignore_line : BOOLEAN := false;
VARIABLE good_data : BOOLEAN := false;
VARIABLE char_tmp : CHARACTER;
VARIABLE index : INTEGER;
variable init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable data : std_logic_vector(255 downto 0) := (others => '0');
variable inside_init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable k_slv : std_logic_vector(31 downto 0) := (others => '0');
variable i_slv : std_logic_vector(31 downto 0) := (others => '0');
VARIABLE disp_line : line := null;
variable open_status : file_open_status;
variable input_initf_tmp : mem_array ;
variable input_initf : mem_array := (others => (others => '0'));
file int_infile : text;
variable data_line, data_line_tmp, out_data_line : line;
variable slv_width : integer;
VARIABLE d_l : LINE;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
index := 0;
FOR i IN 0 TO depth-1 LOOP
FOR j IN 0 TO width-1 LOOP
init_return(i)(j) := DEFAULT_DATA(index);
index := (index + 1) MOD C_WRITE_WIDTH_A;
END LOOP;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, file_buffer);
read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO write_width_a-1 LOOP
IF (j MOD width = 0 AND j /= 0) THEN
i := i + 1;
END IF;
init_return(i)(j MOD width) := bit_to_sl(mem_vector(j));
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
--Display output message indicating that the behavioral model is done
--initializing
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator data initialization complete." SEVERITY NOTE;
if (C_USE_BRAM_BLOCK = 1) then
--Display output message indicating that the behavioral model is being
--initialized
-- Read in the .mem file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_INIT_FILE /= "NONE") then
file_open(open_status, int_infile, C_INIT_FILE, read_mode);
while not endfile(int_infile) loop
readline(int_infile, data_line);
while (data_line /= null and data_line'length > 0) loop
if (data_line(data_line'low to data_line'low + 1) = "//") then
deallocate(data_line);
elsif ((data_line(data_line'low to data_line'low + 1) = "/*") and (data_line(data_line'high-1 to data_line'high) = "*/")) then
deallocate(data_line);
elsif (data_line(data_line'low to data_line'low + 1) = "/*") then
deallocate(data_line);
ignore_line := true;
elsif (ignore_line = true and data_line(data_line'high-1 to data_line'high) = "*/") then
deallocate(data_line);
ignore_line := false;
elsif (ignore_line = false and data_line(data_line'low) = '@') then
read(data_line, char_tmp);
hread(data_line, init_addr_slv, good_data);
i := SLV_TO_INT(init_addr_slv);
elsif (ignore_line = false) then
hread(data_line, input_initf_tmp(i), good_data);
init_return(i)(write_width_a - 1 downto 0) := input_initf_tmp(i)(write_width_a - 1 downto 0);
if (good_data = true) then
i := i + 1;
end if;
else
deallocate(data_line);
end if;
end loop;
end loop;
file_close(int_infile);
END IF;
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- memory type constants
--***************************************************************
CONSTANT MEM_TYPE_SP_RAM : INTEGER := 0;
CONSTANT MEM_TYPE_SDP_RAM : INTEGER := 1;
CONSTANT MEM_TYPE_TDP_RAM : INTEGER := 2;
CONSTANT MEM_TYPE_SP_ROM : INTEGER := 3;
CONSTANT MEM_TYPE_DP_ROM : INTEGER := 4;
--***************************************************************
-- memory configuration constant functions
--***************************************************************
--get_single_port
-----------------
FUNCTION get_single_port(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_RAM OR mem_type=MEM_TYPE_SP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_single_port;
--get_is_rom
--------------
FUNCTION get_is_rom(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_ROM OR mem_type=MEM_TYPE_DP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_is_rom;
--get_has_a_write
------------------
FUNCTION get_has_a_write(IS_ROM : INTEGER) RETURN INTEGER IS
BEGIN
IF (IS_ROM=0) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_a_write;
--get_has_b_write
------------------
FUNCTION get_has_b_write(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_TDP_RAM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_write;
--get_has_a_read
------------------
FUNCTION get_has_a_read(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SDP_RAM) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_a_read;
--get_has_b_read
------------------
FUNCTION get_has_b_read(SINGLE_PORT : INTEGER) RETURN INTEGER IS
BEGIN
IF (SINGLE_PORT=1) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_b_read;
--get_has_b_port
------------------
FUNCTION get_has_b_port(HAS_B_READ : INTEGER;
HAS_B_WRITE : INTEGER)
RETURN INTEGER IS
BEGIN
IF (HAS_B_READ=1 OR HAS_B_WRITE=1) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_port;
--get_num_output_stages
-----------------------
FUNCTION get_num_output_stages(has_mem_output_regs : INTEGER;
has_mux_output_regs : INTEGER;
mux_pipeline_stages : INTEGER)
RETURN INTEGER IS
VARIABLE actual_mux_pipeline_stages : INTEGER;
BEGIN
-- Mux pipeline stages can be non-zero only when there is a mux
-- output register.
IF (has_mux_output_regs=1) THEN
actual_mux_pipeline_stages := mux_pipeline_stages;
ELSE
actual_mux_pipeline_stages := 0;
END IF;
RETURN has_mem_output_regs+actual_mux_pipeline_stages+has_mux_output_regs;
END get_num_output_stages;
--***************************************************************************
-- Component declaration of the VARIABLE depth output register stage
--***************************************************************************
COMPONENT blk_mem_gen_v8_3_1_output_stage
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
EN : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
ECCPIPECE : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_output_stage;
COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************************************
-- locally derived constants to assist memory access
--******************************************************
CONSTANT WRITE_WIDTH_RATIO_A : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_A : INTEGER := C_READ_WIDTH_A/MIN_WIDTH;
CONSTANT WRITE_WIDTH_RATIO_B : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_B : INTEGER := C_READ_WIDTH_B/MIN_WIDTH;
--******************************************************
-- To modify the LSBs of the 'wider' data to the actual
-- address value
--******************************************************
CONSTANT WRITE_ADDR_A_DIV : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH_A;
CONSTANT READ_ADDR_A_DIV : INTEGER := C_READ_WIDTH_A/MIN_WIDTH_A;
CONSTANT WRITE_ADDR_B_DIV : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH_B;
CONSTANT READ_ADDR_B_DIV : INTEGER := C_READ_WIDTH_B/MIN_WIDTH_B;
--******************************************************
-- FUNCTION : log2roundup
--******************************************************
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
--******************************************************
-- Other constants and signals
--******************************************************
CONSTANT COLL_DELAY : TIME := 100 ps;
-- default data vector
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_DEFAULT_DATA,
C_WRITE_WIDTH_A);
CONSTANT CHKBIT_WIDTH : INTEGER := if_then_else(C_WRITE_WIDTH_A>57,8,if_then_else(C_WRITE_WIDTH_A>26,7,if_then_else(C_WRITE_WIDTH_A>11,6,if_then_else(C_WRITE_WIDTH_A>4,5,if_then_else(C_WRITE_WIDTH_A<5,4,0)))));
-- the init memory SIGNAL
SIGNAL memory_i : mem_array;
SIGNAL doublebit_error_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0);
SIGNAL current_contents_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
-- write mode constants
CONSTANT WRITE_MODE_A : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_A);
CONSTANT WRITE_MODE_B : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_B);
CONSTANT WRITE_MODES : STD_LOGIC_VECTOR(3 DOWNTO 0) :=
WRITE_MODE_A & WRITE_MODE_B;
-- reset values
CONSTANT INITA_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITA_VAL,
C_READ_WIDTH_A);
CONSTANT INITB_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITB_VAL,
C_READ_WIDTH_B);
-- memory output 'latches'
SIGNAL memory_out_a : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0) :=
INITA_VAL;
SIGNAL memory_out_b : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) :=
INITB_VAL;
SIGNAL sbiterr_in : STD_LOGIC := '0';
SIGNAL sbiterr_sdp : STD_LOGIC := '0';
SIGNAL dbiterr_in : STD_LOGIC := '0';
SIGNAL dbiterr_sdp : STD_LOGIC := '0';
SIGNAL rdaddrecc_in : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_sdp : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL doutb_i : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i : STD_LOGIC := '0';
SIGNAL dbiterr_i : STD_LOGIC := '0';
-- memory configuration constants
-----------------------------------------------
CONSTANT SINGLE_PORT : INTEGER := get_single_port(C_MEM_TYPE);
CONSTANT IS_ROM : INTEGER := get_is_rom(C_MEM_TYPE);
CONSTANT HAS_A_WRITE : INTEGER := get_has_a_write(IS_ROM);
CONSTANT HAS_B_WRITE : INTEGER := get_has_b_write(C_MEM_TYPE);
CONSTANT HAS_A_READ : INTEGER := get_has_a_read(C_MEM_TYPE);
CONSTANT HAS_B_READ : INTEGER := get_has_b_read(SINGLE_PORT);
CONSTANT HAS_B_PORT : INTEGER := get_has_b_port(HAS_B_READ, HAS_B_WRITE);
CONSTANT NUM_OUTPUT_STAGES_A : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_A,
C_MUX_PIPELINE_STAGES);
CONSTANT NUM_OUTPUT_STAGES_B : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES);
CONSTANT WEA0 : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT WEB0 : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-----------------------------------------------------------------------------
-- DEBUG CONTROL
-- DEBUG=0 : Debug output OFF
-- DEBUG=1 : Some debug info printed
-----------------------------------------------------------------------------
CONSTANT DEBUG : INTEGER := 0;
-- internal signals
-----------------------------------------------
SIGNAL ena_i : STD_LOGIC;
SIGNAL enb_i : STD_LOGIC;
SIGNAL reseta_i : STD_LOGIC;
SIGNAL resetb_i : STD_LOGIC;
SIGNAL wea_i : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL web_i : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL rea_i : STD_LOGIC;
SIGNAL reb_i : STD_LOGIC;
SIGNAL message_complete : BOOLEAN := false;
SIGNAL rsta_outp_stage : STD_LOGIC := '0';
SIGNAL rstb_outp_stage : STD_LOGIC := '0';
--*********************************************************
--FUNCTION : Collision check
--*********************************************************
FUNCTION collision_check (addr_a :
STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
iswrite_a : BOOLEAN;
addr_b :
STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
iswrite_b : BOOLEAN)
RETURN BOOLEAN IS
VARIABLE c_aw_bw : INTEGER;
VARIABLE c_aw_br : INTEGER;
VARIABLE c_ar_bw : INTEGER;
VARIABLE write_addr_a_width : INTEGER;
VARIABLE read_addr_a_width : INTEGER;
VARIABLE write_addr_b_width : INTEGER;
VARIABLE read_addr_b_width : INTEGER;
BEGIN
c_aw_bw := 0;
c_aw_br := 0;
c_ar_bw := 0;
-- Determine the effective address widths FOR each of the 4 ports
write_addr_a_width := C_ADDRA_WIDTH-log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width := C_ADDRA_WIDTH-log2roundup(READ_ADDR_A_DIV);
write_addr_b_width := C_ADDRB_WIDTH-log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width := C_ADDRB_WIDTH-log2roundup(READ_ADDR_B_DIV);
--Look FOR a write-write collision. In order FOR a write-write
--collision to exist, both ports must have a write transaction.
IF (iswrite_a AND iswrite_b) THEN
IF (write_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_a and iswrite_b
--If the B port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_a) THEN
IF (write_addr_a_width > read_addr_b_width) THEN
--read_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_b_width
--Once both are scaled to read_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
END IF; --width
END IF; --iswrite_a
--If the A port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_b) THEN
IF (read_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
ELSE
--read_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_a_width
--Once both are scaled to read_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_b
RETURN (c_aw_bw=1 OR c_aw_br=1 OR c_ar_bw=1);
END FUNCTION collision_check;
BEGIN -- Architecture
-----------------------------------------------------------------------------
-- SOFTECC and ECC SBITERR/DBITERR Outputs
-- The ECC Behavior is modeled by the behavioral models only for Virtex-6.
-- The SOFTECC Behavior is modeled by the behavioral models for Spartan-6.
-- For Virtex-5, these outputs will be tied to 0.
-----------------------------------------------------------------------------
SBITERR <= sbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_sdp WHEN (((C_FAMILY="virtex7") AND C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
-----------------------------------------------
-- This effectively wires off optional inputs
-----------------------------------------------
ena_i <= ENA WHEN (C_HAS_ENA=1) ELSE '1';
enb_i <= ENB WHEN (C_HAS_ENB=1 AND HAS_B_PORT=1) ELSE '1';
-- We are doing an "AND" operation of WEA and ENA and passing to Enbale pin of BRAM when built-in ECC is enabled,
-- what this means is that the write operation happens only when both WEA and ENA are high.
wea_i <= WEA WHEN (HAS_A_WRITE=1 AND ena_i='1') ELSE WEA0;
-- wea_i <= (OTHERS => '1') WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=1 AND ENA = '1') ELSE -- Use_ENA_pin
-- WEA WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=0) ELSE -- Always_enabled
-- WEA WHEN (HAS_A_WRITE=1 AND ena_i='1' AND C_USE_ECC = 0) ELSE
-- WEA0;
web_i <= WEB WHEN (HAS_B_WRITE=1 AND enb_i='1') ELSE WEB0;
rea_i <= ena_i WHEN (HAS_A_READ=1) ELSE '0';
reb_i <= enb_i WHEN (HAS_B_READ=1) ELSE '0';
-- these signals reset the memory latches
-- For the special reset behaviors in some of the families, the C_RSTRAM
-- attribute of the corresponding port is used to indicate if the latch is
-- reset or not.
reseta_i <= RSTA WHEN
((C_HAS_RSTA=1 AND NUM_OUTPUT_STAGES_A=0) OR
(C_HAS_RSTA=1 AND C_RSTRAM_A=1))
ELSE '0';
resetb_i <= RSTB WHEN
((C_HAS_RSTB=1 AND NUM_OUTPUT_STAGES_B=0) OR
(C_HAS_RSTB=1 AND C_RSTRAM_B=1) )
ELSE '0';
--***************************************************************************
-- This is the main PROCESS which includes the memory VARIABLE and the read
-- and write procedures. It also schedules read and write operations
--***************************************************************************
PROCESS (CLKA, CLKB,rea_i,reb_i,reseta_i,resetb_i)
-- Initialize the init memory array
------------------------------------
VARIABLE memory : mem_array := init_memory(DEFAULT_DATA,
C_WRITE_WIDTH_A,
MAX_DEPTH,
MIN_WIDTH);
-- Initialize the mem memory array
------------------------------------
VARIABLE softecc_sbiterr_arr : softecc_err_array;
VARIABLE softecc_dbiterr_arr : softecc_err_array;
VARIABLE sbiterr_arr : ecc_err_array;
VARIABLE dbiterr_arr : ecc_err_array;
CONSTANT doublebit_lsb : STD_LOGIC_VECTOR (1 DOWNTO 0):="11";
CONSTANT doublebit_msb : STD_LOGIC_VECTOR (C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 DOWNTO 0):= (OTHERS => '0');
VARIABLE doublebit_error : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0) := doublebit_msb & doublebit_lsb ;
VARIABLE current_contents_var : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
--***********************************
-- procedures to access the memory
--***********************************
-- write_a
----------
PROCEDURE write_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
inj_sbiterr : IN STD_LOGIC;
inj_dbiterr : IN STD_LOGIC) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
VARIABLE message : LINE;
VARIABLE errbit_current_contents : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
-- Block Memory Generator non-cycle-accurate message
ASSERT (message_complete) REPORT "Block Memory Generator module is using a behavioral model FOR simulation which will not precisely model memory collision behavior."
SEVERITY NOTE;
message_complete <= true;
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_A_DIV);
IF (address_i >= C_WRITE_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range FOR A Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEA = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_A + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEA_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Insert double bit errors:
IF (C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
current_contents(0) := NOT(current_contents(0));
current_contents(1) := NOT(current_contents(1));
--current_contents(0) := NOT(current_contents(30));
--current_contents(1) := NOT(current_contents(62));
END IF;
END IF;
-- Insert double bit errors:
IF (C_USE_SOFTECC=1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 downto 2) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 downto 0);
doublebit_error(0) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1);
doublebit_error(1) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-2);
current_contents := current_contents XOR doublebit_error(C_WRITE_WIDTH_A-1 DOWNTO 0);
END IF;
END IF;
IF(DEBUG=1) THEN
current_contents_var := current_contents; --for debugging current
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_A + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
-- Store address at which error is injected:
IF ((C_FAMILY = "virtex7") AND C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
sbiterr_arr(address_i) := '1';
ELSE
sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
dbiterr_arr(address_i) := '1';
ELSE
dbiterr_arr(address_i) := '0';
END IF;
END IF;
-- Store address at which softecc error is injected:
IF (C_USE_SOFTECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
softecc_sbiterr_arr(address_i) := '1';
ELSE
softecc_sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
softecc_dbiterr_arr(address_i) := '1';
ELSE
softecc_dbiterr_arr(address_i) := '0';
END IF;
END IF;
END IF;
END PROCEDURE;
-- write_b
----------
PROCEDURE write_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_B_DIV);
IF (address_i >= C_WRITE_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEB = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_B + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEB_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_B + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
END IF;
END PROCEDURE;
-- read_a
----------
PROCEDURE read_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_A_DIV);
IF (address_i >= C_READ_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for A Read"
SEVERITY WARNING;
END IF;
memory_out_a <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_A-1 LOOP
memory_out_a(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_A + i) AFTER FLOP_DELAY;
END LOOP;
END IF;
END IF;
END PROCEDURE;
-- read_b
----------
PROCEDURE read_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_B_DIV);
IF (address_i >= C_READ_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Read"
SEVERITY WARNING;
END IF;
memory_out_b <= (OTHERS => 'X') AFTER FLOP_DELAY;
sbiterr_in <= 'X' AFTER FLOP_DELAY;
dbiterr_in <= 'X' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_B-1 LOOP
memory_out_b(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_B + i) AFTER FLOP_DELAY;
END LOOP;
--assert sbiterr and dbiterr signals
IF ((C_FAMILY="virtex7") AND C_USE_ECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
--assert softecc sbiterr and dbiterr signals
ELSIF (C_USE_SOFTECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (softecc_sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (softecc_dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
END IF;
END IF;
END IF;
END PROCEDURE;
-- reset_a
----------
PROCEDURE reset_a
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
-- reset_b
----------
PROCEDURE reset_b
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
BEGIN -- begin the main PROCESS
--***************************************************************************
-- These are the main blocks which schedule read and write operations
-- Note that the reset priority feature at the latch stage is only supported
-- for Spartan-6. For other families, the default priority at the latch stage
-- is "CE"
--***************************************************************************
-- Synchronous clocks: schedule port operations with respect to both
-- write operating modes
IF (C_COMMON_CLK=1) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODES IS
WHEN "0000" => -- write_first write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "0100" => -- read_first write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "0001" => -- write_first read_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0101" => --read_first read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0010" => -- write_first no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0110" => -- read_first no_change
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1000" => -- no_change write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "1001" => -- no_change read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1010" => -- no_change no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Synchronous clocks
-- Asynchronous clocks: port operation is independent
IF (C_COMMON_CLK=0) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODE_A IS
WHEN "00" => -- write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN "01" => -- read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "10" => -- no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
IF (CLKB='1' AND CLKB'EVENT) THEN
CASE WRITE_MODE_B IS
WHEN "00" => -- write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "01" => -- read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "10" => -- no_change
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Asynchronous clocks
-- Assign the memory VARIABLE to the user_visible memory_i SIGNAL
IF(DEBUG=1) THEN
memory_i <= memory;
doublebit_error_i <= doublebit_error;
current_contents_i <= current_contents_var;
END IF;
END PROCESS;
--********************************************************************
-- Instantiate the VARIABLE depth output stage
--********************************************************************
-- Port A
rsta_outp_stage <= RSTA and not sleep;
rstb_outp_stage <= RSTB and not sleep;
reg_a : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTA,
C_RSTRAM => C_RSTRAM_A,
C_RST_PRIORITY => C_RST_PRIORITY_A,
init_val => INITA_VAL,
C_HAS_EN => C_HAS_ENA,
C_HAS_REGCE => C_HAS_REGCEA,
C_DATA_WIDTH => C_READ_WIDTH_A,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_A,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_A,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKA,
RST => rsta_outp_stage, --RSTA,
EN => ENA,
REGCE => REGCEA,
DIN_I => memory_out_a,
DOUT => DOUTA,
SBITERR_IN_I => '0',
DBITERR_IN_I => '0',
SBITERR => OPEN,
DBITERR => OPEN,
RDADDRECC_IN_I => (OTHERS => '0'),
ECCPIPECE => '0',
RDADDRECC => OPEN
);
-- Port B
reg_b : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTB,
C_RSTRAM => C_RSTRAM_B,
C_RST_PRIORITY => C_RST_PRIORITY_B,
init_val => INITB_VAL,
C_HAS_EN => C_HAS_ENB,
C_HAS_REGCE => C_HAS_REGCEB,
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_B,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKB,
RST => rstb_outp_stage,--RSTB,
EN => ENB,
REGCE => REGCEB,
DIN_I => memory_out_b,
DOUT => doutb_i,
SBITERR_IN_I => sbiterr_in,
DBITERR_IN_I => dbiterr_in,
SBITERR => sbiterr_i,
DBITERR => dbiterr_i,
RDADDRECC_IN_I => rdaddrecc_in,
ECCPIPECE => ECCPIPECE,
RDADDRECC => rdaddrecc_i
);
--********************************************************************
-- Instantiate the input / Output Register stages
--********************************************************************
output_reg_stage: blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC MAP(
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP(
CLK => CLKB,
DIN => doutb_i,
DOUT => DOUTB,
SBITERR_IN => sbiterr_i,
DBITERR_IN => dbiterr_i,
SBITERR => sbiterr_sdp,
DBITERR => dbiterr_sdp,
RDADDRECC_IN => rdaddrecc_i,
RDADDRECC => rdaddrecc_sdp
);
--*********************************
-- Synchronous collision checks
--*********************************
sync_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=1) GENERATE
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
-- collision detect
VARIABLE is_collision : BOOLEAN;
VARIABLE message : LINE;
BEGIN
IF (CLKA='1' AND CLKA'EVENT) THEN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision := false;
END IF;
-- If the write port is in READ_FIRST mode, there is no collision
IF (C_WRITE_MODE_A="READ_FIRST" AND wea_i/=WEA0 AND web_i=WEB0) THEN
is_collision := false;
END IF;
IF (C_WRITE_MODE_B="READ_FIRST" AND web_i/=WEB0 AND wea_i=WEA0) THEN
is_collision := false;
END IF;
-- Only flag if one of the accesses is a write
IF (is_collision AND (wea_i/=WEA0 OR web_i/=WEB0)) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END IF;
END PROCESS;
END GENERATE;
--*********************************
-- Asynchronous collision checks
--*********************************
async_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=0) GENERATE
SIGNAL addra_delay : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL wea_delay : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL ena_delay : STD_LOGIC;
SIGNAL addrb_delay : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
SIGNAL web_delay : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL enb_delay : STD_LOGIC;
BEGIN
-- Delay A and B addresses in order to mimic setup/hold times
PROCESS (ADDRA, wea_i, ena_i, ADDRB, web_i, enb_i)
BEGIN
addra_delay <= ADDRA AFTER COLL_DELAY;
wea_delay <= wea_i AFTER COLL_DELAY;
ena_delay <= ena_i AFTER COLL_DELAY;
addrb_delay <= ADDRB AFTER COLL_DELAY;
web_delay <= web_i AFTER COLL_DELAY;
enb_delay <= enb_i AFTER COLL_DELAY;
END PROCESS;
-- Do the checks w/rt A
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_a : BOOLEAN;
VARIABLE is_collision_delay_a : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_a := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_a := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_delay_a := collision_check(ADDRA,
wea_i/=WEA0,
addrb_delay,
web_delay/=WEB0);
ELSE
is_collision_delay_a := false;
END IF;
-- Only flag if B access is a write
IF (is_collision_a AND web_i/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_a AND web_delay/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, addrb_delay);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
-- Do the checks w/rt B
PROCESS (CLKB)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_b : BOOLEAN;
VARIABLE is_collision_delay_b : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA) /= 'X') THEN
is_collision_b := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_b := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(addra_delay) /= 'X') THEN
is_collision_delay_b := collision_check(addra_delay,
wea_delay/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_delay_b := false;
END IF;
-- Only flag if A access is a write
-- Modified condition checking (is_collision_b AND WEA0_i=/WEA0) to fix CR526228
IF (is_collision_b AND wea_i/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_b AND wea_delay/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, addra_delay);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
END GENERATE;
END mem_module_behavioral;
--******************************************************************************
-- Top module that wraps SoftECC Input register stage and the main memory module
--
-- This module is the top-level of behavioral model
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1 IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_CTRL_ECC_ALGO : STRING := "NONE";
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
--C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_SLEEP_PIN : INTEGER := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
PORT (
clka : IN STD_LOGIC := '0';
rsta : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '1';
regcea : IN STD_LOGIC := '1';
wea : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addra : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
dina : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
douta : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
clkb : IN STD_LOGIC := '0';
rstb : IN STD_LOGIC := '0';
enb : IN STD_LOGIC := '1';
regceb : IN STD_LOGIC := '1';
web : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addrb : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
dinb : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
doutb : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
injectsbiterr : IN STD_LOGIC := '0';
injectdbiterr : IN STD_LOGIC := '0';
sbiterr : OUT STD_LOGIC := '0';
dbiterr : OUT STD_LOGIC := '0';
rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : in std_logic := '0';
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic := '0';
rstb_busy : out std_logic := '0';
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
s_aclk : IN STD_LOGIC := '0';
s_aresetn : IN STD_LOGIC := '0';
-- axi full/lite slave Write (write side)
s_axi_awid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid : IN STD_LOGIC := '0';
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast : IN STD_LOGIC := '0';
s_axi_wvalid : IN STD_LOGIC := '0';
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC := '0';
-- axi full/lite slave Read (Write side)
s_axi_arid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid : IN STD_LOGIC := '0';
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_rdata : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC := '0';
-- axi full/lite sideband Signals
s_axi_injectsbiterr : IN STD_LOGIC := '0';
s_axi_injectdbiterr : IN STD_LOGIC := '0';
s_axi_sbiterr : OUT STD_LOGIC := '0';
s_axi_dbiterr : OUT STD_LOGIC := '0';
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END blk_mem_gen_v8_3_1;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE behavioral OF blk_mem_gen_v8_3_1 IS
COMPONENT blk_mem_gen_v8_3_1_mem_module
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_mem_module;
COMPONENT blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_axi_regs_fwd_v8_3;
COMPONENT blk_mem_axi_read_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT blk_mem_axi_read_wrapper_beh;
COMPONENT blk_mem_axi_write_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END COMPONENT blk_mem_axi_write_wrapper_beh;
CONSTANT FLOP_DELAY : TIME := 100 ps;
SIGNAL rsta_in : STD_LOGIC := '1';
SIGNAL ena_in : STD_LOGIC := '1';
SIGNAL regcea_in : STD_LOGIC := '1';
SIGNAL wea_in : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL addra_in : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL dina_in : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL injectsbiterr_in : STD_LOGIC := '0';
SIGNAL injectdbiterr_in : STD_LOGIC := '0';
-----------------------------------------------------------------------------
-- FUNCTION: toLowerCaseChar
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
-----------------------------------------------------------------------------
FUNCTION toLowerCaseChar(
char : character )
RETURN character IS
BEGIN
-- If char is not an upper case letter then return char
IF char<'A' OR char>'Z' THEN
RETURN char;
END IF;
-- Otherwise map char to its corresponding lower case character and
-- RETURN that
CASE char IS
WHEN 'A' => RETURN 'a';
WHEN 'B' => RETURN 'b';
WHEN 'C' => RETURN 'c';
WHEN 'D' => RETURN 'd';
WHEN 'E' => RETURN 'e';
WHEN 'F' => RETURN 'f';
WHEN 'G' => RETURN 'g';
WHEN 'H' => RETURN 'h';
WHEN 'I' => RETURN 'i';
WHEN 'J' => RETURN 'j';
WHEN 'K' => RETURN 'k';
WHEN 'L' => RETURN 'l';
WHEN 'M' => RETURN 'm';
WHEN 'N' => RETURN 'n';
WHEN 'O' => RETURN 'o';
WHEN 'P' => RETURN 'p';
WHEN 'Q' => RETURN 'q';
WHEN 'R' => RETURN 'r';
WHEN 'S' => RETURN 's';
WHEN 'T' => RETURN 't';
WHEN 'U' => RETURN 'u';
WHEN 'V' => RETURN 'v';
WHEN 'W' => RETURN 'w';
WHEN 'X' => RETURN 'x';
WHEN 'Y' => RETURN 'y';
WHEN 'Z' => RETURN 'z';
WHEN OTHERS => RETURN char;
END CASE;
END toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
FUNCTION equalIgnoreCase(
str1 : STRING;
str2 : STRING )
RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str2'left TO str1'right LOOP
IF NOT (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equalIgnoreCase;
-----------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
----------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
----------------------------------------------------------------------------
-- FUNCTION : log2roundup
----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
CONSTANT lower_limit : INTEGER := 1;
CONSTANT upper_limit : INTEGER := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
-----------------------------------------------------------------------------
-- FUNCTION : divroundup
-- Returns the ceiling value of the division
-- Data_value - the quantity to be divided, dividend
-- Divisor - the value to divide the data_value by
-----------------------------------------------------------------------------
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
SIGNAL s_axi_awaddr_out_c : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_araddr_out_c : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_wr_en_c : STD_LOGIC := '0';
SIGNAL s_axi_rd_en_c : STD_LOGIC := '0';
SIGNAL s_aresetn_a_c : STD_LOGIC := '0';
--**************************************************************************
-- AXI PARAMETERS
CONSTANT AXI_FULL_MEMORY_SLAVE : integer := if_then_else((C_AXI_SLAVE_TYPE = 0 AND C_AXI_TYPE = 1),1,0);
CONSTANT C_AXI_ADDR_WIDTH_MSB : integer := C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
CONSTANT C_AXI_ADDR_WIDTH : integer := C_AXI_ADDR_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT LOWER_BOUND_VAL : integer := if_then_else((log2roundup(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT C_AXI_ADDR_WIDTH_LSB : integer := if_then_else((AXI_FULL_MEMORY_SLAVE = 1),0,LOWER_BOUND_VAL);
CONSTANT C_AXI_OS_WR : integer := 2;
-- SAFETY LOGIC related Signals
SIGNAL RSTA_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_A : STD_LOGIC := '0';
SIGNAL RSTB_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_B : STD_LOGIC := '0';
SIGNAL ENA_dly : STD_LOGIC := '0';
SIGNAL ENA_dly_D : STD_LOGIC := '0';
SIGNAL ENB_dly : STD_LOGIC := '0';
SIGNAL ENB_dly_D : STD_LOGIC := '0';
SIGNAL RSTA_I_SAFE : STD_LOGIC := '0';
SIGNAL RSTB_I_SAFE : STD_LOGIC := '0';
SIGNAL ENA_I_SAFE : STD_LOGIC := '0';
SIGNAL ENB_I_SAFE : STD_LOGIC := '0';
SIGNAL ram_rstram_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstram_b_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_b_busy : STD_LOGIC := '0';
SIGNAL ENA_dly_reg : STD_LOGIC := '0';
SIGNAL ENB_dly_reg : STD_LOGIC := '0';
SIGNAL ENA_dly_reg_D : STD_LOGIC := '0';
SIGNAL ENB_dly_reg_D : STD_LOGIC := '0';
--**************************************************************************
BEGIN -- Architecture
--*************************************************************************
-- NO INPUT STAGE
--*************************************************************************
no_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=0) GENERATE
rsta_in <= RSTA;
ena_in <= ENA;
regcea_in <= REGCEA;
wea_in <= WEA;
addra_in <= ADDRA;
dina_in <= DINA;
injectsbiterr_in <= INJECTSBITERR;
injectdbiterr_in <= INJECTDBITERR;
END GENERATE no_input_stage;
--**************************************************************************
-- WITH INPUT STAGE
--**************************************************************************
has_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=1) GENERATE
PROCESS (CLKA)
BEGIN
IF (CLKA'EVENT AND CLKA = '1') THEN
rsta_in <= RSTA AFTER FLOP_DELAY;
ena_in <= ENA AFTER FLOP_DELAY;
regcea_in <= REGCEA AFTER FLOP_DELAY;
wea_in <= WEA AFTER FLOP_DELAY;
addra_in <= ADDRA AFTER FLOP_DELAY;
dina_in <= DINA AFTER FLOP_DELAY;
injectsbiterr_in <= INJECTSBITERR AFTER FLOP_DELAY;
injectdbiterr_in <= INJECTDBITERR AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE has_input_stage;
--**************************************************************************
-- NO SAFETY LOGIC
--**************************************************************************
NO_SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 0) GENERATE
ENA_I_SAFE <= ena_in;
ENB_I_SAFE <= ENB;
RSTA_I_SAFE <= rsta_in;
RSTB_I_SAFE <= RSTB;
END GENERATE NO_SAFETY_CKT_GEN;
--**************************************************************************
-- SAFETY LOGIC
--**************************************************************************
SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 1) GENERATE
-- RESET SAFETY LOGIC Generation
-- POR Generation
------------------------------------------------------------------------------
-- Power-ON Reset Generation
------------------------------------------------------------------------------
RST_SHFT_LOGIC_A : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
RSTA_SHFT_REG(4 DOWNTO 0) <= RSTA_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_A;
POR_RSTA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
POR_A <= RSTA_SHFT_REG(4) xor RSTA_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTA_GEN;
RST_SHFT_LOGIC_B : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
RSTB_SHFT_REG(4 DOWNTO 0) <= RSTB_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_B;
POR_RSTB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
POR_B <= RSTB_SHFT_REG(4) xor RSTB_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTB_GEN;
-----------------------------------------------------------------------------
-- Fix for the AR42571
-----------------------------------------------------------------------------
-- Reset Generation
-----------------------------------------------------------------------------
RSTA_I_SAFE <= rsta_in OR POR_A;
SPRAM_RST: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_I_SAFE <= '0';
END GENERATE SPRAM_RST;
nSPRAM_RST: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_I_SAFE <= RSTB OR POR_B;
END GENERATE nSPRAM_RST;
-----------------------------------------------------------------------------
-- RSTA/B_BUSY Generation
-----------------------------------------------------------------------------
RSTA_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
ram_rstram_a_busy <= rsta_in OR ENA_dly OR ENA_dly_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstram_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_NO_REG;
RSTA_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
ram_rstreg_a_busy <= rsta_in OR ENA_dly OR ENA_dly_reg_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstreg_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_WITH_REG;
SPRAM_RST_BUSY: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_BUSY <= '0';
END GENERATE SPRAM_RST_BUSY;
nSPRAM_RST_BUSY: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
ram_rstram_b_busy <= RSTB OR ENB_dly OR ENB_dly_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstram_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_NO_REG;
RSTB_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
ram_rstreg_b_busy <= RSTB OR ENB_dly OR ENB_dly_reg_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstreg_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_WITH_REG;
END GENERATE nSPRAM_RST_BUSY;
-----------------------------------------------------------------------------
-- ENA/ENB Generation
-----------------------------------------------------------------------------
ENA_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly <= rsta_in AFTER FLOP_DELAY;
ENA_dly_D <= ENA_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_D OR ena_in;
END GENERATE ENA_NO_REG;
ENA_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly_reg <= rsta_in AFTER FLOP_DELAY;
ENA_dly_reg_D <= ENA_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_reg_D OR ena_in;
END GENERATE ENA_WITH_REG;
SPRAM_ENB: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
ENB_I_SAFE <= '0';
END GENERATE SPRAM_ENB;
nSPRAM_ENB: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
ENB_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly <= RSTB AFTER FLOP_DELAY;
ENB_dly_D <= ENB_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_D OR ENB;
END GENERATE ENB_NO_REG;
ENB_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly_reg <= RSTB AFTER FLOP_DELAY;
ENB_dly_reg_D <= ENB_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_reg_D OR ENB;
END GENERATE ENB_WITH_REG;
END GENERATE nSPRAM_ENB;
END GENERATE SAFETY_CKT_GEN;
--**************************************************************************
-- NATIVE MEMORY MODULE INSTANCE
--**************************************************************************
native_mem_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 0) GENERATE
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,--rsta_in,
ENA => ENA_I_SAFE,--ena_in,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in,
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => RDADDRECC
);
END GENERATE native_mem_module;
--**************************************************************************
-- NATIVE MEMORY MAPPED MODULE INSTANCE
--**************************************************************************
native_mem_map_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 1) GENERATE
--**************************************************************************
-- NATIVE MEMORY MAPPED PARAMETERS
CONSTANT C_ADDRA_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_A);
CONSTANT C_ADDRB_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_B);
CONSTANT C_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
CONSTANT C_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
CONSTANT C_MEM_MAP_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_MSB;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT MEM_MAP_LOWER_BOUND_VAL_A : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT MEM_MAP_LOWER_BOUND_VAL_B : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_B,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_B,8)));
CONSTANT C_MEM_MAP_ADDRA_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_A;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_B;
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH_ACTUAL-1 DOWNTO 0) := (OTHERS => '0');
--**************************************************************************
BEGIN
RDADDRECC(C_ADDRB_WIDTH-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_MSB) <= (OTHERS => '0');
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB) <= rdaddrecc_i;
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_LSB-1 DOWNTO 0) <= (OTHERS => '0');
mem_map_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH_ACTUAL,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH_ACTUAL,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,
ENA => ENA_I_SAFE,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in(C_MEM_MAP_ADDRA_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRA_WIDTH_LSB),
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB),
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => rdaddrecc_i
);
END GENERATE native_mem_map_module;
--****************************************************************************
-- AXI MEMORY MODULE INSTANCE
--****************************************************************************
axi_mem_module: IF (C_INTERFACE_TYPE = 1) GENERATE
SIGNAL s_axi_rid_c : STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rdata_c : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rresp_c : STD_LOGIC_VECTOR(2-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rlast_c : STD_LOGIC := '0';
SIGNAL s_axi_rvalid_c : STD_LOGIC := '0';
SIGNAL s_axi_rready_c : STD_LOGIC := '0';
SIGNAL regceb_c : STD_LOGIC := '0';
BEGIN
s_aresetn_a_c <= NOT S_ARESETN;
S_AXI_BRESP <= (OTHERS => '0');
s_axi_rresp_c <= (OTHERS => '0');
no_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 0 AND C_HAS_MUX_OUTPUT_REGS_B = 0 ) GENERATE
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RLAST <= s_axi_rlast_c;
S_AXI_RVALID <= s_axi_rvalid_c;
S_AXI_RID <= s_axi_rid_c;
S_AXI_RRESP <= s_axi_rresp_c;
s_axi_rready_c <= S_AXI_RREADY;
END GENERATE no_regs;
has_regs_fwd: IF (C_HAS_MUX_OUTPUT_REGS_B = 1 OR C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
CONSTANT C_AXI_PAYLOAD : INTEGER := if_then_else((C_HAS_MUX_OUTPUT_REGS_B = 1),C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3,C_AXI_ID_WIDTH+3);
SIGNAL s_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
has_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
regceb_c <= s_axi_rvalid_c AND s_axi_rready_c;
END GENERATE has_regceb;
no_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 0) GENERATE
regceb_c <= REGCEB;
END GENERATE no_regceb;
only_core_op_regs: IF (C_HAS_MUX_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rdata_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RDATA <= m_axi_payload_c(C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_core_op_regs;
only_emb_op_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_emb_op_regs;
axi_regs_inst : blk_mem_axi_regs_fwd_v8_3
GENERIC MAP(
C_DATA_WIDTH => C_AXI_PAYLOAD
)
PORT MAP (
ACLK => S_ACLK,
ARESET => s_aresetn_a_c,
S_VALID => s_axi_rvalid_c,
S_READY => s_axi_rready_c,
S_PAYLOAD_DATA => s_axi_payload_c,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY,
M_PAYLOAD_DATA => m_axi_payload_c
);
END GENERATE has_regs_fwd;
axi_wr_fsm : blk_mem_axi_write_wrapper_beh
GENERIC MAP(
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_AXI_AWADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_WDATA_WIDTH => C_WRITE_WIDTH_A,
C_AXI_OS_WR => C_AXI_OS_WR
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Slave Write Interface
S_AXI_AWADDR => S_AXI_AWADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_AWLEN => S_AXI_AWLEN,
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BID => S_AXI_BID,
-- Signals for BRAM interface
S_AXI_AWADDR_OUT =>s_axi_awaddr_out_c,
S_AXI_WR_EN =>s_axi_wr_en_c
);
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => 1, -- For AXI, Read Enable is always C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => 1, -- For AXI C_USE_BYTE_WEA is always 1,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => 1, -- For AXI, Read Enable is always C_HAS_ENB,
C_HAS_REGCEB => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_BYTE_WEB => 1, -- For AXI C_USE_BYTE_WEB is always 1,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => 0, --For AXI, Primitive Registers A is not supported C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => 0,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
--Port A:
CLKA => S_AClk,
RSTA => s_aresetn_a_c,
ENA => s_axi_wr_en_c,
REGCEA => regcea_in,
WEA => S_AXI_WSTRB,
ADDRA => s_axi_awaddr_out_c,
DINA => S_AXI_WDATA,
DOUTA => DOUTA,
--Port B:
CLKB => S_AClk,
RSTB => s_aresetn_a_c,
ENB => s_axi_rd_en_c,
REGCEB => regceb_c,
WEB => (OTHERS => '0'),
ADDRB => s_axi_araddr_out_c,
DINB => DINB,
DOUTB => s_axi_rdata_c,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => '0',
SLEEP => '0',
RDADDRECC => RDADDRECC
);
axi_rd_sm : blk_mem_axi_read_wrapper_beh
GENERIC MAP (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_PIPELINE_STAGES => 1,
C_AXI_ARADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_AClk,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Read Side
S_AXI_ARADDR => S_AXI_ARADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARSIZE => S_AXI_ARSIZE,
S_AXI_ARBURST => S_AXI_ARBURST,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => s_axi_rlast_c,
S_AXI_RVALID => s_axi_rvalid_c,
S_AXI_RREADY => s_axi_rready_c,
S_AXI_ARID => S_AXI_ARID,
S_AXI_RID => s_axi_rid_c,
-- AXI Full/Lite Read FSM Outputs
S_AXI_ARADDR_OUT => s_axi_araddr_out_c,
S_AXI_RD_EN => s_axi_rd_en_c
);
END GENERATE axi_mem_module;
END behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_clr is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_clr;
architecture beh_ff_clr_arch of beh_ff_clr is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(CLR, C)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_clr_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_ce is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_ce;
architecture beh_ff_ce_arch of beh_ff_ce is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, CLR)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
if (CE = '1') then
q_o <= D after 100 ps;
end if;
end if;
end process;
end beh_ff_ce_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_pre is
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end beh_ff_pre;
architecture beh_ff_pre_arch of beh_ff_pre is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, PRE)
begin
if (PRE = '1') then
q_o <= '1';
elsif (C' event and C = '1') then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_pre_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_muxf7 is
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end beh_muxf7;
architecture beh_muxf7_arch of beh_muxf7 is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
else
O <= I1;
end if;
end process;
end beh_muxf7_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity STATE_LOGIC is
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic := '0';
I0 : in std_logic := '0';
I1 : in std_logic := '0';
I2 : in std_logic := '0';
I3 : in std_logic := '0';
I4 : in std_logic := '0';
I5 : in std_logic := '0'
);
end STATE_LOGIC;
architecture STATE_LOGIC_arch of STATE_LOGIC is
constant INIT_reg : std_logic_vector(63 downto 0) := INIT;
begin
LUT_beh:process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
begin
I_reg := I5 & I4 & I3 & I2 & I1 & I0;
O <= INIT_reg(conv_integer(I_reg));
end process;
end STATE_LOGIC_arch;
|
-------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v8_3_1.vhd
--
-- Description:
-- This file is the VHDL behvarial model for the
-- Block Memory Generator Core.
--
-------------------------------------------------------------------------------
-- Author: Xilinx
--
-- History: January 11, 2006: Initial revision
-- June 11, 2007 : Added independent register stages for
-- Port A and Port B (IP1_Jm/v2.5)
-- August 28, 2007 : Added mux pipeline stages feature (IP2_Jm/v2.6)
-- April 07, 2009 : Added support for Spartan-6 and Virtex-6
-- features, including the following:
-- (i) error injection, detection and/or correction
-- (ii) reset priority
-- (iii) special reset behavior
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
ENTITY blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END ENTITY blk_mem_axi_regs_fwd_v8_3;
ARCHITECTURE axi_regs_fwd_arch OF blk_mem_axi_regs_fwd_v8_3 IS
SIGNAL STORAGE_DATA : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_READY_I : STD_LOGIC := '0';
SIGNAL M_VALID_I : STD_LOGIC := '0';
SIGNAL ARESET_D : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');-- Reset delay register
BEGIN
--assign local signal to its output signal
S_READY <= S_READY_I;
M_VALID <= M_VALID_I;
PROCESS(ACLK)
BEGIN
IF(ACLK'event AND ACLK = '1') THEN
ARESET_D <= ARESET_D(0) & ARESET;
END IF;
END PROCESS;
--Save payload data whenever we have a transaction on the slave side
PROCESS(ACLK, ARESET)
BEGIN
IF (ARESET = '1') THEN
STORAGE_DATA <= (OTHERS => '0');
ELSIF(ACLK'event AND ACLK = '1') THEN
IF(S_VALID = '1' AND S_READY_I = '1') THEN
STORAGE_DATA <= S_PAYLOAD_DATA;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= STORAGE_DATA;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
PROCESS(ACLK,ARESET)
BEGIN
IF (ARESET_D /= "00") THEN
M_VALID_I <= '0';
ELSIF(ACLK'event AND ACLK = '1') THEN
IF (S_VALID = '1') THEN
--Always set M_VALID_I when slave side is valid
M_VALID_I <= '1';
ELSIF (M_READY = '1') THEN
--Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= '0';
END IF;
END IF;
END PROCESS;
--Slave Ready is either when Master side drives M_READY or we have space in our storage data
S_READY_I <= (M_READY OR (NOT M_VALID_I)) AND NOT(OR_REDUCE(ARESET_D));
END axi_regs_fwd_arch;
-------------------------------------------------------------------------------
-- Description:
-- This is the behavioral model of write_wrapper for the
-- Block Memory Generator Core.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_axi_write_wrapper_beh IS
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END blk_mem_axi_write_wrapper_beh;
ARCHITECTURE axi_write_wrap_arch OF blk_mem_axi_write_wrapper_beh IS
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_AXI_WDATA_WIDTH=8,0,
if_then_else((C_AXI_WDATA_WIDTH=16),1,
if_then_else((C_AXI_WDATA_WIDTH=32),2,
if_then_else((C_AXI_WDATA_WIDTH=64),3,
if_then_else((C_AXI_WDATA_WIDTH=128),4,
if_then_else((C_AXI_WDATA_WIDTH=256),5,0))))));
SIGNAL bvalid_c : std_logic := '0';
SIGNAL bready_timeout_c : std_logic := '0';
SIGNAL bvalid_rd_cnt_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_r : std_logic := '0';
SIGNAL bvalid_count_r : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL awaddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
C_AXI_AWADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL bvalid_wr_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_rd_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_last_c : std_logic := '0';
SIGNAL addr_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL aw_ready_r : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL awlen_cntr_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1');
SIGNAL awlen_int : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL awburst_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes : integer := 0;
SIGNAL wrap_boundary : integer := 0;
SIGNAL wrap_base_addr : integer := 0;
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
-- Array to store BIDs
TYPE id_array IS ARRAY (3 DOWNTO 0) OF std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
SIGNAL axi_bid_array : id_array := (others => (others => '0'));
COMPONENT write_netlist
GENERIC(
C_AXI_TYPE : integer
);
PORT(
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
S_AXI_AWVALID : IN std_logic;
aw_ready_r : OUT std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN std_logic;
S_AXI_WR_EN : OUT std_logic;
w_last_c : IN std_logic;
bready_timeout_c : IN std_logic;
addr_en_c : OUT std_logic;
incr_addr_c : OUT std_logic;
bvalid_c : OUT std_logic
);
END COMPONENT write_netlist;
BEGIN
---------------------------------------
--AXI WRITE FSM COMPONENT INSTANTIATION
---------------------------------------
axi_wr_fsm : write_netlist
GENERIC MAP (
C_AXI_TYPE => C_AXI_TYPE
)
PORT MAP (
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
S_AXI_AWVALID => S_AXI_AWVALID,
aw_ready_r => aw_ready_r,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BVALID => OPEN,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_WR_EN => S_AXI_WR_EN,
w_last_c => w_last_c,
bready_timeout_c => bready_timeout_c,
addr_en_c => addr_en_c,
incr_addr_c => incr_addr_c,
bvalid_c => bvalid_c
);
--Wrap Address boundary calculation
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWSIZE,"000"));
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(awlen_int)+1);
wrap_base_addr <= (conv_integer(awaddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary <= wrap_base_addr+total_bytes;
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awaddr_reg <= (OTHERS => '0');
num_of_bytes_r <= 0;
awburst_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awaddr_reg <= S_AXI_AWADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWBURST,"01");
ELSIF (incr_addr_c = '1') THEN
IF (awburst_int = "10") THEN
IF(conv_integer(awaddr_reg) = (wrap_boundary-num_of_bytes_r)) THEN
awaddr_reg <= conv_std_logic_vector(wrap_base_addr,C_AXI_AWADDR_WIDTH);
ELSE
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
ELSIF (awburst_int = "01" OR awburst_int = "11") THEN
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
S_AXI_AWADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
awaddr_reg(C_AXI_AWADDR_WIDTH-1 DOWNTO C_RANGE),awaddr_reg);
---------------------------------------------------------------------------
-- AXI wlast generation
---------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awlen_cntr_r <= (OTHERS => '1');
awlen_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awlen_int <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
awlen_cntr_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
ELSIF (dec_alen_c = '1') THEN
awlen_cntr_r <= awlen_cntr_r - ONE AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
w_last_c <= '1' WHEN (awlen_cntr_r = "00000000" AND S_AXI_WVALID = '1') ELSE '0';
dec_alen_c <= (incr_addr_c OR w_last_c);
---------------------------------------------------------------------------
-- Generation of bvalid counter for outstanding transactions
---------------------------------------------------------------------------
P_b_valid_os_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_count_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- bvalid_count_r generation
IF (bvalid_c = '1' AND bvalid_r = '1' AND S_AXI_BREADY = '1') THEN
bvalid_count_r <= bvalid_count_r AFTER FLOP_DELAY;
ELSIF (bvalid_c = '1') THEN
bvalid_count_r <= bvalid_count_r + "01" AFTER FLOP_DELAY;
ELSIF (bvalid_r = '1' AND S_AXI_BREADY = '1' AND bvalid_count_r /= "0") THEN
bvalid_count_r <= bvalid_count_r - "01" AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_os_r ;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is used
---------------------------------------------------------------------------
gaxi_bvalid_id_r:IF (C_HAS_AXI_ID = 1) GENERATE
SIGNAL bvalid_d1_c : std_logic := '0';
BEGIN
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
bvalid_d1_c <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
--external bvalid signal generation
IF (bvalid_d1_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_id_r;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is not used
---------------------------------------------------------------------------
gaxi_bvalid_noid_r:IF (C_HAS_AXI_ID = 0) GENERATE
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
--external bvalid signal generation
IF (bvalid_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_noid_r;
---------------------------------------------------------------------------
-- Generation of Bready timeout
---------------------------------------------------------------------------
P_brdy_tout_c: PROCESS (bvalid_count_r)
BEGIN
-- bready_timeout_c generation
IF(conv_integer(bvalid_count_r) = C_AXI_OS_WR-1) THEN
bready_timeout_c <= '1';
ELSE
bready_timeout_c <= '0';
END IF;
END PROCESS P_brdy_tout_c;
---------------------------------------------------------------------------
-- Generation of BID
---------------------------------------------------------------------------
gaxi_bid_gen:IF (C_HAS_AXI_ID = 1) GENERATE
P_bid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
bvalid_wr_cnt_r <= (OTHERS => '0');
bvalid_rd_cnt_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- STORE AWID IN AN ARRAY
IF(bvalid_c = '1') THEN
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + "01";
END IF;
-- GENERATE BID FROM AWID ARRAY
bvalid_rd_cnt_r <= bvalid_rd_cnt_c AFTER FLOP_DELAY;
S_AXI_BID <= axi_bid_array(conv_integer(bvalid_rd_cnt_c));
END IF;
END PROCESS P_bid_gen;
bvalid_rd_cnt_c <= bvalid_rd_cnt_r + "01" WHEN (bvalid_r = '1' AND S_AXI_BREADY = '1') ELSE bvalid_rd_cnt_r;
---------------------------------------------------------------------------
-- Storing AWID for generation of BID
---------------------------------------------------------------------------
P_awid_reg:PROCESS (S_ACLK)
BEGIN
IF (S_ACLK'event AND S_ACLK='1') THEN
IF(aw_ready_r = '1' AND S_AXI_AWVALID = '1') THEN
axi_bid_array(conv_integer(bvalid_wr_cnt_r)) <= S_AXI_AWID;
END IF;
END IF;
END PROCESS P_awid_reg;
END GENERATE gaxi_bid_gen;
S_AXI_BVALID <= bvalid_r;
S_AXI_AWREADY <= aw_ready_r;
END axi_write_wrap_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity write_netlist is
GENERIC(
C_AXI_TYPE : integer
);
port (
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_AWVALID : in STD_LOGIC := '0';
S_AXI_WVALID : in STD_LOGIC := '0';
S_AXI_BREADY : in STD_LOGIC := '0';
w_last_c : in STD_LOGIC := '0';
bready_timeout_c : in STD_LOGIC := '0';
aw_ready_r : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_WR_EN : out STD_LOGIC;
addr_en_c : out STD_LOGIC;
incr_addr_c : out STD_LOGIC;
bvalid_c : out STD_LOGIC
);
end write_netlist;
architecture STRUCTURE of write_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
BEGIN
---------------------------------------------------------------------------
-- AXI LITE
---------------------------------------------------------------------------
gbeh_axi_lite_sm: IF (C_AXI_TYPE = 0 ) GENERATE
signal w_ready_r_7 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSignal_bvalid_c : STD_LOGIC;
signal NlwRenamedSignal_incr_addr_c : STD_LOGIC;
signal present_state_FSM_FFd3_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal present_state_FSM_FFd1_15 : STD_LOGIC;
signal present_state_FSM_FFd4_16 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd4_In1_21 : STD_LOGIC;
signal Mmux_aw_ready_c : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
S_AXI_WREADY <= w_ready_r_7;
S_AXI_BVALID <= NlwRenamedSignal_incr_addr_c;
S_AXI_WR_EN <= NlwRenamedSignal_bvalid_c;
incr_addr_c <= NlwRenamedSignal_incr_addr_c;
bvalid_c <= NlwRenamedSignal_bvalid_c;
NlwRenamedSignal_incr_addr_c <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_7
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_16
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_13
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_15
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000055554440"
)
port map (
I0 => S_AXI_WVALID,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => '0',
O => present_state_FSM_FFd3_In
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"0000000088880800"
)
port map (
I0 => S_AXI_AWVALID,
I1 => S_AXI_WVALID,
I2 => bready_timeout_c,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => present_state_FSM_FFd2_In
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAA2000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_WVALID,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => addr_en_c
);
Mmux_w_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"F5F07570F5F05500"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => w_ready_c
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd3_13,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd1_15,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_14,
I2 => present_state_FSM_FFd3_13,
I3 => '0',
I4 => '0',
I5 => '0',
O => NlwRenamedSignal_bvalid_c
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"2F0F27072F0F2200"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => present_state_FSM_FFd4_In1_21
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_In1_21,
I3 => '0',
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_aw_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"7535753575305500"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => S_AXI_WVALID,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => present_state_FSM_FFd2_14,
O => Mmux_aw_ready_c(0)
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => Mmux_aw_ready_c(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => aw_ready_c
);
END GENERATE gbeh_axi_lite_sm;
---------------------------------------------------------------------------
-- AXI FULL
---------------------------------------------------------------------------
gbeh_axi_full_sm: IF (C_AXI_TYPE = 1 ) GENERATE
signal w_ready_r_8 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSig_OI_bvalid_c : STD_LOGIC;
signal present_state_FSM_FFd1_16 : STD_LOGIC;
signal present_state_FSM_FFd4_17 : STD_LOGIC;
signal present_state_FSM_FFd3_18 : STD_LOGIC;
signal present_state_FSM_FFd2_19 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd2_In1_24 : STD_LOGIC;
signal present_state_FSM_FFd4_In1_25 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal N4 : STD_LOGIC;
begin
S_AXI_WREADY <= w_ready_r_8;
bvalid_c <= NlwRenamedSig_OI_bvalid_c;
S_AXI_BVALID <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_8
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_17
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_18
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_19
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_16
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000000005540"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd4_17,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd3_In
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"BF3FBB33AF0FAA00"
)
port map (
I0 => S_AXI_BREADY,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd1_16,
I4 => present_state_FSM_FFd4_17,
I5 => NlwRenamedSig_OI_bvalid_c,
O => aw_ready_c
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"AAAAAAAA20000000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_19,
I3 => S_AXI_WVALID,
I4 => w_last_c,
I5 => present_state_FSM_FFd4_17,
O => addr_en_c
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_19,
I2 => present_state_FSM_FFd3_18,
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_WR_EN
);
Mmux_incr_addr_c_0_1 : STATE_LOGIC
generic map(
INIT => X"0000000000002220"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => incr_addr_c
);
Mmux_aw_ready_c_0_11 : STATE_LOGIC
generic map(
INIT => X"0000000000008880"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => NlwRenamedSig_OI_bvalid_c
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"000000000000D5C0"
)
port map (
I0 => w_last_c,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd4_17,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd2_In1_24
);
present_state_FSM_FFd2_In2 : STATE_LOGIC
generic map(
INIT => X"FFFFAAAA08AAAAAA"
)
port map (
I0 => present_state_FSM_FFd2_19,
I1 => S_AXI_AWVALID,
I2 => bready_timeout_c,
I3 => w_last_c,
I4 => S_AXI_WVALID,
I5 => present_state_FSM_FFd2_In1_24,
O => present_state_FSM_FFd2_In
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"00C0004000C00000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => w_last_c,
I2 => S_AXI_WVALID,
I3 => bready_timeout_c,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => present_state_FSM_FFd4_In1_25
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88F8"
)
port map (
I0 => present_state_FSM_FFd1_16,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_17,
I3 => S_AXI_AWVALID,
I4 => present_state_FSM_FFd4_In1_25,
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_w_ready_c_0_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => w_last_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_w_ready_c_0_Q : STATE_LOGIC
generic map(
INIT => X"FABAFABAFAAAF000"
)
port map (
I0 => N2,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd4_17,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => w_ready_c
);
Mmux_aw_ready_c_0_11_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => bready_timeout_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => w_last_c,
I1 => N4,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => present_state_FSM_FFd1_16,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
END GENERATE gbeh_axi_full_sm;
end STRUCTURE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--AXI Behavioral Model entities
ENTITY blk_mem_axi_read_wrapper_beh is
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
port (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END blk_mem_axi_read_wrapper_beh;
architecture blk_mem_axi_read_wrapper_beh_arch of blk_mem_axi_read_wrapper_beh is
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_WRITE_WIDTH_A=8,0,
if_then_else((C_WRITE_WIDTH_A=16),1,
if_then_else((C_WRITE_WIDTH_A=32),2,
if_then_else((C_WRITE_WIDTH_A=64),3,
if_then_else((C_WRITE_WIDTH_A=128),4,
if_then_else((C_WRITE_WIDTH_A=256),5,0))))));
SIGNAL ar_id_r : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
SIGNAL addr_en_c : std_logic := '0';
SIGNAL rd_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL single_trans_c : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL mux_sel_c : std_logic := '0';
SIGNAL r_last_c : std_logic := '0';
SIGNAL r_last_int_c : std_logic := '0';
SIGNAL arlen_int_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL arlen_cntr : std_logic_vector(7 DOWNTO 0) := ONE;
SIGNAL arburst_int_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL arburst_int_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL araddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),C_AXI_ARADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL total_bytes : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
SIGNAL wrap_base_addr_r : integer := 0;
SIGNAL wrap_boundary_r : integer := 0;
SIGNAL arlen_int_c : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes_c : integer := 0;
SIGNAL wrap_base_addr_c : integer := 0;
SIGNAL wrap_boundary_c : integer := 0;
SIGNAL araddr_out : std_logic_vector(C_ADDRB_WIDTH-1 downto 0) := (OTHERS => '0');
COMPONENT read_netlist
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_INCR_ADDR : OUT std_logic := '0';
S_AXI_ADDR_EN : OUT std_logic := '0';
S_AXI_SINGLE_TRANS : OUT std_logic := '0';
S_AXI_MUX_SEL : OUT std_logic := '0';
S_AXI_R_LAST : OUT std_logic := '0';
S_AXI_R_LAST_INT : IN std_logic := '0';
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT read_netlist;
BEGIN
dec_alen_c <= incr_addr_c OR r_last_int_c;
axi_read_fsm : read_netlist
GENERIC MAP(
C_AXI_TYPE => 1,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
S_AXI_INCR_ADDR => incr_addr_c,
S_AXI_ADDR_EN => addr_en_c,
S_AXI_SINGLE_TRANS => single_trans_c,
S_AXI_MUX_SEL => mux_sel_c,
S_AXI_R_LAST => r_last_c,
S_AXI_R_LAST_INT => r_last_int_c,
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN => rd_en_c
);
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(arlen_int_r)+1);
wrap_base_addr_r <= (conv_integer(araddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary_r <= wrap_base_addr_r+total_bytes;
---- combinatorial from interface
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARSIZE,"000"));
arlen_int_c <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
total_bytes_c <= conv_integer(num_of_bytes_c)*(conv_integer(arlen_int_c)+1);
wrap_base_addr_c <= (conv_integer(S_AXI_ARADDR)/if_then_else(total_bytes_c=0,1,total_bytes_c))*(total_bytes_c);
wrap_boundary_c <= wrap_base_addr_c+total_bytes_c;
arburst_int_c <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARBURST,"01");
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
araddr_reg <= (OTHERS => '0');
arburst_int_r <= (OTHERS => '0');
num_of_bytes_r <= 0;
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (incr_addr_c = '1' AND addr_en_c = '1' AND single_trans_c = '0') THEN
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
IF (arburst_int_c = "10") THEN
IF(conv_integer(S_AXI_ARADDR) = (wrap_boundary_c-num_of_bytes_c)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_c,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (arburst_int_c = "01" OR arburst_int_c = "11") THEN
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (addr_en_c = '1') THEN
araddr_reg <= S_AXI_ARADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
ELSIF (incr_addr_c = '1') THEN
IF (arburst_int_r = "10") THEN
IF(conv_integer(araddr_reg) = (wrap_boundary_r-num_of_bytes_r)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_r,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
ELSIF (arburst_int_r = "01" OR arburst_int_r = "11") THEN
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
araddr_out <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),araddr_reg(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),araddr_reg);
--------------------------------------------------------------------------
-- Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
--------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF S_ARESETN = '1' THEN
arlen_cntr <= ONE;
arlen_int_r <= (OTHERS => '0');
ELSIF S_ACLK'event AND S_ACLK = '1' THEN
IF (addr_en_c = '1' AND dec_alen_c = '1' AND single_trans_c = '0') THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= S_AXI_ARLEN - ONE AFTER FLOP_DELAY;
ELSIF addr_en_c = '1' THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
ELSIF dec_alen_c = '1' THEN
arlen_cntr <= arlen_cntr - ONE AFTER FLOP_DELAY;
ELSE
arlen_cntr <= arlen_cntr AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
r_last_int_c <= '1' WHEN (arlen_cntr = "00000000" AND S_AXI_RREADY = '1') ELSE '0' ;
--------------------------------------------------------------------------
-- AXI FULL FSM
-- Mux Selection of ARADDR
-- ARADDR is driven out from the read fsm based on the mux_sel_c
-- Based on mux_sel either ARADDR is given out or the latched ARADDR is
-- given out to BRAM
--------------------------------------------------------------------------
P_araddr_mux: PROCESS (mux_sel_c,S_AXI_ARADDR,araddr_out)
BEGIN
IF (mux_sel_c = '0') THEN
S_AXI_ARADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARADDR(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),S_AXI_ARADDR);
ELSE
S_AXI_ARADDR_OUT <= araddr_out;
END IF;
END PROCESS P_araddr_mux;
--------------------------------------------------------------------------
-- Assign output signals - AXI FULL FSM
--------------------------------------------------------------------------
S_AXI_RD_EN <= rd_en_c;
grid: IF (C_HAS_AXI_ID = 1) GENERATE
P_rid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
S_AXI_RID <= (OTHERS => '0');
ar_id_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
IF (addr_en_c = '1' AND rd_en_c = '1') THEN
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
ELSIF (addr_en_c = '1' AND rd_en_c = '0') THEN
ar_id_r <= S_AXI_ARID;
ELSIF (rd_en_c = '1') THEN
S_AXI_RID <= ar_id_r;
END IF;
END IF;
END PROCESS P_rid_gen;
END GENERATE grid;
END blk_mem_axi_read_wrapper_beh_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity read_netlist is
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_R_LAST_INT : in STD_LOGIC := '0';
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_ARVALID : in STD_LOGIC := '0';
S_AXI_RREADY : in STD_LOGIC := '0';
S_AXI_INCR_ADDR : out STD_LOGIC;
S_AXI_ADDR_EN : out STD_LOGIC;
S_AXI_SINGLE_TRANS : out STD_LOGIC;
S_AXI_MUX_SEL : out STD_LOGIC;
S_AXI_R_LAST : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RLAST : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RD_EN : out STD_LOGIC;
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end read_netlist;
architecture STRUCTURE of read_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
signal present_state_FSM_FFd1_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_r_15 : STD_LOGIC;
signal gaxi_full_sm_ar_ready_r_16 : STD_LOGIC;
signal gaxi_full_sm_r_last_r_17 : STD_LOGIC;
signal NlwRenamedSig_OI_gaxi_full_sm_r_valid_r : STD_LOGIC;
signal gaxi_full_sm_r_valid_c : STD_LOGIC;
signal S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o : STD_LOGIC;
signal gaxi_full_sm_ar_ready_c : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_c : STD_LOGIC;
signal NlwRenamedSig_OI_S_AXI_R_LAST : STD_LOGIC;
signal S_AXI_ARLEN_7_GND_8_o_equal_1_o : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal Mmux_S_AXI_R_LAST13 : STD_LOGIC;
signal N01 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal Mmux_gaxi_full_sm_ar_ready_c11 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N8 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N13 : STD_LOGIC;
begin
S_AXI_R_LAST <= NlwRenamedSig_OI_S_AXI_R_LAST;
S_AXI_ARREADY <= gaxi_full_sm_ar_ready_r_16;
S_AXI_RLAST <= gaxi_full_sm_r_last_r_17;
S_AXI_RVALID <= NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
gaxi_full_sm_outstanding_read_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_outstanding_read_c,
Q => gaxi_full_sm_outstanding_read_r_15
);
gaxi_full_sm_r_valid_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => gaxi_full_sm_r_valid_c,
Q => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r
);
gaxi_full_sm_ar_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_ar_ready_c,
Q => gaxi_full_sm_ar_ready_r_16
);
gaxi_full_sm_r_last_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => NlwRenamedSig_OI_S_AXI_R_LAST,
Q => gaxi_full_sm_r_last_r_17
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_13
);
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 : STATE_LOGIC
generic map(
INIT => X"000000000000000B"
)
port map (
I0 => S_AXI_RREADY,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o
);
Mmux_S_AXI_SINGLE_TRANS11 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_SINGLE_TRANS
);
Mmux_S_AXI_ADDR_EN11 : STATE_LOGIC
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_ADDR_EN
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"ECEE2022EEEE2022"
)
port map (
I0 => S_AXI_ARVALID,
I1 => present_state_FSM_FFd1_13,
I2 => S_AXI_RREADY,
I3 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I4 => present_state_FSM_FFd2_14,
I5 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
O => present_state_FSM_FFd2_In
);
Mmux_S_AXI_R_LAST131 : STATE_LOGIC
generic map(
INIT => X"0000000044440444"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_RREADY,
I5 => '0',
O => Mmux_S_AXI_R_LAST13
);
Mmux_S_AXI_INCR_ADDR11 : STATE_LOGIC
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => S_AXI_R_LAST_INT,
I1 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => Mmux_S_AXI_R_LAST13,
O => S_AXI_INCR_ADDR
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000FE"
)
port map (
I0 => S_AXI_ARLEN(2),
I1 => S_AXI_ARLEN(1),
I2 => S_AXI_ARLEN(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => N01
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q : STATE_LOGIC
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => S_AXI_ARLEN(7),
I1 => S_AXI_ARLEN(6),
I2 => S_AXI_ARLEN(5),
I3 => S_AXI_ARLEN(4),
I4 => S_AXI_ARLEN(3),
I5 => N01,
O => S_AXI_ARLEN_7_GND_8_o_equal_1_o
);
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_gaxi_full_sm_outstanding_read_c1 : STATE_LOGIC
generic map(
INIT => X"0020000002200200"
)
port map (
I0 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd1_13,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => N2,
O => gaxi_full_sm_outstanding_read_c
);
Mmux_gaxi_full_sm_ar_ready_c12 : STATE_LOGIC
generic map(
INIT => X"0000000000004555"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => '0',
I5 => '0',
O => Mmux_gaxi_full_sm_ar_ready_c11
);
Mmux_S_AXI_R_LAST11_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000EF"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
Mmux_S_AXI_R_LAST11 : STATE_LOGIC
generic map(
INIT => X"FCAAFC0A00AA000A"
)
port map (
I0 => S_AXI_ARVALID,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => N4,
I5 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
O => gaxi_full_sm_r_valid_c
);
S_AXI_MUX_SEL1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAAAA08"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => '0',
O => S_AXI_MUX_SEL
);
Mmux_S_AXI_RD_EN11 : STATE_LOGIC
generic map(
INIT => X"F3F3F755A2A2A200"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => gaxi_full_sm_outstanding_read_r_15,
I4 => present_state_FSM_FFd2_14,
I5 => S_AXI_ARVALID,
O => S_AXI_RD_EN
);
present_state_FSM_FFd1_In3 : beh_muxf7
port map (
I0 => N8,
I1 => N9,
S => present_state_FSM_FFd1_13,
O => present_state_FSM_FFd1_In
);
present_state_FSM_FFd1_In3_F : STATE_LOGIC
generic map(
INIT => X"000000005410F4F0"
)
port map (
I0 => S_AXI_RREADY,
I1 => present_state_FSM_FFd2_14,
I2 => S_AXI_ARVALID,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => '0',
O => N8
);
present_state_FSM_FFd1_In3_G : STATE_LOGIC
generic map(
INIT => X"0000000072FF7272"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N9
);
Mmux_gaxi_full_sm_ar_ready_c14 : beh_muxf7
port map (
I0 => N10,
I1 => N11,
S => present_state_FSM_FFd1_13,
O => gaxi_full_sm_ar_ready_c
);
Mmux_gaxi_full_sm_ar_ready_c14_F : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88A8"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => Mmux_gaxi_full_sm_ar_ready_c11,
I5 => '0',
O => N10
);
Mmux_gaxi_full_sm_ar_ready_c14_G : STATE_LOGIC
generic map(
INIT => X"000000008D008D8D"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N11
);
Mmux_S_AXI_R_LAST1 : beh_muxf7
port map (
I0 => N12,
I1 => N13,
S => present_state_FSM_FFd1_13,
O => NlwRenamedSig_OI_S_AXI_R_LAST
);
Mmux_S_AXI_R_LAST1_F : STATE_LOGIC
generic map(
INIT => X"0000000088088888"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N12
);
Mmux_S_AXI_R_LAST1_G : STATE_LOGIC
generic map(
INIT => X"00000000E400E4E4"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => S_AXI_R_LAST_INT,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N13
);
end STRUCTURE;
-------------------------------------------------------------------------------
-- Output Register Stage Entity
--
-- This module builds the output register stages of the memory. This module is
-- instantiated in the main memory module (blk_mem_gen_v8_3_1) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_output_stage IS
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_output_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6" and "virtex6l".
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
-- C_HAS_RST : Determines the presence of the RST port
-- C_RSTRAM : Determines if special reset behavior is used
-- C_RST_PRIORITY : Determines the priority between CE and SR
-- C_INIT_VAL : Initialization value
-- C_HAS_EN : Determines the presence of the EN port
-- C_HAS_REGCE : Determines the presence of the REGCE port
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
-- of the RAM primitive
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- NUM_STAGES : Determines the number of output stages
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE output_stage_behavioral OF blk_mem_gen_v8_3_1_output_stage IS
--*******************************************************
-- Functions used in the output stage ARCHITECTURE
--*******************************************************
-- Calculate num_reg_stages
FUNCTION get_num_reg_stages(NUM_STAGES: INTEGER) RETURN INTEGER IS
VARIABLE num_reg_stages : INTEGER := 0;
BEGIN
IF (NUM_STAGES = 0) THEN
num_reg_stages := 0;
ELSE
num_reg_stages := NUM_STAGES - 1;
END IF;
RETURN num_reg_stages;
END get_num_reg_stages;
-- Check if the INTEGER is zero or non-zero
FUNCTION int_to_bit(input: INTEGER) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = 0) THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END int_to_bit;
-- Constants
CONSTANT HAS_EN : STD_LOGIC := int_to_bit(C_HAS_EN);
CONSTANT HAS_REGCE : STD_LOGIC := int_to_bit(C_HAS_REGCE);
CONSTANT HAS_RST : STD_LOGIC := int_to_bit(C_HAS_RST);
CONSTANT REG_STAGES : INTEGER := get_num_reg_stages(NUM_STAGES);
-- Pipeline array
TYPE reg_data_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
TYPE reg_ecc_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC;
TYPE reg_eccaddr_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
CONSTANT REG_INIT : reg_data_array := (OTHERS => init_val);
SIGNAL out_regs : reg_data_array := REG_INIT;
SIGNAL sbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL dbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL rdaddrecc_regs: reg_eccaddr_array := (OTHERS => (OTHERS => '0'));
-- Internal signals
SIGNAL en_i : STD_LOGIC;
SIGNAL regce_i : STD_LOGIC;
SIGNAL rst_i : STD_LOGIC;
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := init_val;
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL DIN : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL RDADDRECC_IN : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ;
SIGNAL SBITERR_IN : STD_LOGIC := '0';
SIGNAL DBITERR_IN : STD_LOGIC := '0';
BEGIN
--***********************************************************************
-- Assign internal signals. This effectively wires off optional inputs.
--***********************************************************************
-- Internal enable for output registers is tied to user EN or '1' depending
-- on parameters
en_i <= EN OR (NOT HAS_EN);
-- Internal register enable for output registers is tied to user REGCE, EN
-- or '1' depending on parameters
regce_i <= (HAS_REGCE AND REGCE)
OR ((NOT HAS_REGCE) AND en_i);
-- Internal SRR is tied to user RST or '0' depending on parameters
rst_i <= RST AND HAS_RST;
--***************************************************************************
-- NUM_STAGES = 0 (No output registers. RAM only)
--***************************************************************************
zero_stages: IF (NUM_STAGES = 0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE zero_stages;
NO_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 0) GENERATE
DIN <= DIN_I;
RDADDRECC_IN <= RDADDRECC_IN_I;
SBITERR_IN <= SBITERR_IN_I;
DBITERR_IN <= DBITERR_IN_I;
END GENERATE NO_ECC_PIPE_REG;
WITH_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(ECCPIPECE = '1') THEN
DIN <= DIN_I AFTER FLOP_DELAY;
RDADDRECC_IN <= RDADDRECC_IN_I AFTER FLOP_DELAY;
SBITERR_IN <= SBITERR_IN_I AFTER FLOP_DELAY;
DBITERR_IN <= DBITERR_IN_I AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS;
END GENERATE WITH_ECC_PIPE_REG;
--***************************************************************************
-- NUM_STAGES = 1
-- (Mem Output Reg only or Mux Output Reg only)
--***************************************************************************
-- Possible valid combinations:
-- Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
-- +-----------------------------------------+
-- | C_RSTRAM_* | Reset Behavior |
-- +----------------+------------------------+
-- | 0 | Normal Behavior |
-- +----------------+------------------------+
-- | 1 | Special Behavior |
-- +----------------+------------------------+
--
-- Normal = REGCE gates reset, as in the case of all Virtex families and all
-- spartan families with the exception of S3ADSP and S6.
-- Special = EN gates reset, as in the case of S3ADSP and S6.
one_stage_norm: IF (NUM_STAGES = 1 AND
(C_RSTRAM=0 OR (C_RSTRAM=1 AND (C_XDEVICEFAMILY/="spartan3adsp" AND C_XDEVICEFAMILY/="aspartan3adsp")) OR
C_HAS_MEM_OUTPUT_REGS=0 OR C_HAS_RST=0)) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i = '1' AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
END IF;--CLK
END PROCESS;
END GENERATE one_stage_norm;
-- Special Reset Behavior for S6 and S3ADSP
one_stage_splbhv: IF (NUM_STAGES=1 AND C_RSTRAM=1 AND (C_XDEVICEFAMILY ="spartan3adsp" OR C_XDEVICEFAMILY ="aspartan3adsp"))
GENERATE
DOUT <= dout_i;
SBITERR <= '0';
DBITERR <= '0';
RDADDRECC <= (OTHERS => '0');
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (rst_i='1' AND en_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
ELSIF (regce_i='1' AND rst_i/='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE one_stage_splbhv;
--****************************************************************************
-- NUM_STAGES > 1
-- Mem Output Reg + Mux Output Reg
-- or
-- Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
-- or
-- Mux Pipeline Stages (>0) + Mux Output Reg
--****************************************************************************
multi_stage: IF (NUM_STAGES > 1) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i='1'AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
IF (en_i='1') THEN
-- Shift the data through the output stages
FOR i IN 1 TO REG_STAGES-1 LOOP
out_regs(i) <= out_regs(i-1) AFTER FLOP_DELAY;
sbiterr_regs(i) <= sbiterr_regs(i-1) AFTER FLOP_DELAY;
dbiterr_regs(i) <= dbiterr_regs(i-1) AFTER FLOP_DELAY;
rdaddrecc_regs(i) <= rdaddrecc_regs(i-1) AFTER FLOP_DELAY;
END LOOP;
out_regs(0) <= DIN;
sbiterr_regs(0) <= SBITERR_IN;
dbiterr_regs(0) <= DBITERR_IN;
rdaddrecc_regs(0) <= RDADDRECC_IN;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE multi_stage;
END output_stage_behavioral;
-------------------------------------------------------------------------------
-- SoftECC Output Register Stage Entity
-- This module builds the softecc output register stages. This module is
-- instantiated in the memory module (blk_mem_gen_v8_3_1_mem_module) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ;
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- of the RAM primitive
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE softecc_output_reg_stage_behavioral OF blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
-- Internal signals
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
--***************************************************************************
-- NO OUTPUT STAGES
--***************************************************************************
no_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE no_output_stage;
--****************************************************************************
-- WITH OUTPUT STAGE
--****************************************************************************
has_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END PROCESS;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
END GENERATE has_output_stage;
END softecc_output_reg_stage_behavioral;
--******************************************************************************
-- Main Memory module
--
-- This module is the behavioral model which implements the RAM
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
ENTITY blk_mem_gen_v8_3_1_mem_module IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_mem_module;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE mem_module_behavioral OF blk_mem_gen_v8_3_1_mem_module IS
--****************************************
-- min/max constant functions
--****************************************
-- get_max
----------
function SLV_TO_INT(SLV: in std_logic_vector
) return integer is
variable int : integer;
begin
int := 0;
for i in SLV'high downto SLV'low loop
int := int * 2;
if SLV(i) = '1' then
int := int + 1;
end if;
end loop;
return int;
end;
FUNCTION get_max(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a > b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-- get_min
----------
FUNCTION get_min(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
--***************************************************************
-- convert write_mode from STRING type for use in case statement
--***************************************************************
FUNCTION write_mode_to_vector(mode: STRING) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF (mode = "NO_CHANGE") THEN
RETURN "10";
ELSIF (mode = "READ_FIRST") THEN
RETURN "01";
ELSE
RETURN "00"; -- WRITE_FIRST
END IF;
END FUNCTION;
--***************************************************************
-- convert hex STRING to STD_LOGIC_VECTOR
--***************************************************************
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
--***************************************************************
-- locally derived constants to determine memory shape
--***************************************************************
CONSTANT MIN_WIDTH_A : INTEGER := get_min(C_WRITE_WIDTH_A, C_READ_WIDTH_A);
CONSTANT MIN_WIDTH_B : INTEGER := get_min(C_WRITE_WIDTH_B,C_READ_WIDTH_B);
CONSTANT MIN_WIDTH : INTEGER := get_min(MIN_WIDTH_A, MIN_WIDTH_B);
CONSTANT MAX_DEPTH_A : INTEGER := get_max(C_WRITE_DEPTH_A, C_READ_DEPTH_A);
CONSTANT MAX_DEPTH_B : INTEGER := get_max(C_WRITE_DEPTH_B, C_READ_DEPTH_B);
CONSTANT MAX_DEPTH : INTEGER := get_max(MAX_DEPTH_A, MAX_DEPTH_B);
TYPE int_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF std_logic_vector(C_WRITE_WIDTH_A-1 DOWNTO 0);
TYPE mem_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC_VECTOR(MIN_WIDTH-1 DOWNTO 0);
TYPE ecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
TYPE softecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
--***************************************************************
-- memory initialization function
--***************************************************************
IMPURE FUNCTION init_memory(DEFAULT_DATA :
STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
write_width_a : INTEGER;
depth : INTEGER;
width : INTEGER)
RETURN mem_array IS
VARIABLE init_return : mem_array := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(write_width_a-1 DOWNTO 0);
VARIABLE int_mem_vector : int_array:= (OTHERS => (OTHERS => '0'));
VARIABLE file_buffer : LINE;
VARIABLE i : INTEGER := 0;
VARIABLE j : INTEGER;
VARIABLE k : INTEGER;
VARIABLE ignore_line : BOOLEAN := false;
VARIABLE good_data : BOOLEAN := false;
VARIABLE char_tmp : CHARACTER;
VARIABLE index : INTEGER;
variable init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable data : std_logic_vector(255 downto 0) := (others => '0');
variable inside_init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable k_slv : std_logic_vector(31 downto 0) := (others => '0');
variable i_slv : std_logic_vector(31 downto 0) := (others => '0');
VARIABLE disp_line : line := null;
variable open_status : file_open_status;
variable input_initf_tmp : mem_array ;
variable input_initf : mem_array := (others => (others => '0'));
file int_infile : text;
variable data_line, data_line_tmp, out_data_line : line;
variable slv_width : integer;
VARIABLE d_l : LINE;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
index := 0;
FOR i IN 0 TO depth-1 LOOP
FOR j IN 0 TO width-1 LOOP
init_return(i)(j) := DEFAULT_DATA(index);
index := (index + 1) MOD C_WRITE_WIDTH_A;
END LOOP;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, file_buffer);
read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO write_width_a-1 LOOP
IF (j MOD width = 0 AND j /= 0) THEN
i := i + 1;
END IF;
init_return(i)(j MOD width) := bit_to_sl(mem_vector(j));
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
--Display output message indicating that the behavioral model is done
--initializing
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator data initialization complete." SEVERITY NOTE;
if (C_USE_BRAM_BLOCK = 1) then
--Display output message indicating that the behavioral model is being
--initialized
-- Read in the .mem file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_INIT_FILE /= "NONE") then
file_open(open_status, int_infile, C_INIT_FILE, read_mode);
while not endfile(int_infile) loop
readline(int_infile, data_line);
while (data_line /= null and data_line'length > 0) loop
if (data_line(data_line'low to data_line'low + 1) = "//") then
deallocate(data_line);
elsif ((data_line(data_line'low to data_line'low + 1) = "/*") and (data_line(data_line'high-1 to data_line'high) = "*/")) then
deallocate(data_line);
elsif (data_line(data_line'low to data_line'low + 1) = "/*") then
deallocate(data_line);
ignore_line := true;
elsif (ignore_line = true and data_line(data_line'high-1 to data_line'high) = "*/") then
deallocate(data_line);
ignore_line := false;
elsif (ignore_line = false and data_line(data_line'low) = '@') then
read(data_line, char_tmp);
hread(data_line, init_addr_slv, good_data);
i := SLV_TO_INT(init_addr_slv);
elsif (ignore_line = false) then
hread(data_line, input_initf_tmp(i), good_data);
init_return(i)(write_width_a - 1 downto 0) := input_initf_tmp(i)(write_width_a - 1 downto 0);
if (good_data = true) then
i := i + 1;
end if;
else
deallocate(data_line);
end if;
end loop;
end loop;
file_close(int_infile);
END IF;
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- memory type constants
--***************************************************************
CONSTANT MEM_TYPE_SP_RAM : INTEGER := 0;
CONSTANT MEM_TYPE_SDP_RAM : INTEGER := 1;
CONSTANT MEM_TYPE_TDP_RAM : INTEGER := 2;
CONSTANT MEM_TYPE_SP_ROM : INTEGER := 3;
CONSTANT MEM_TYPE_DP_ROM : INTEGER := 4;
--***************************************************************
-- memory configuration constant functions
--***************************************************************
--get_single_port
-----------------
FUNCTION get_single_port(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_RAM OR mem_type=MEM_TYPE_SP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_single_port;
--get_is_rom
--------------
FUNCTION get_is_rom(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_ROM OR mem_type=MEM_TYPE_DP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_is_rom;
--get_has_a_write
------------------
FUNCTION get_has_a_write(IS_ROM : INTEGER) RETURN INTEGER IS
BEGIN
IF (IS_ROM=0) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_a_write;
--get_has_b_write
------------------
FUNCTION get_has_b_write(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_TDP_RAM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_write;
--get_has_a_read
------------------
FUNCTION get_has_a_read(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SDP_RAM) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_a_read;
--get_has_b_read
------------------
FUNCTION get_has_b_read(SINGLE_PORT : INTEGER) RETURN INTEGER IS
BEGIN
IF (SINGLE_PORT=1) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_b_read;
--get_has_b_port
------------------
FUNCTION get_has_b_port(HAS_B_READ : INTEGER;
HAS_B_WRITE : INTEGER)
RETURN INTEGER IS
BEGIN
IF (HAS_B_READ=1 OR HAS_B_WRITE=1) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_port;
--get_num_output_stages
-----------------------
FUNCTION get_num_output_stages(has_mem_output_regs : INTEGER;
has_mux_output_regs : INTEGER;
mux_pipeline_stages : INTEGER)
RETURN INTEGER IS
VARIABLE actual_mux_pipeline_stages : INTEGER;
BEGIN
-- Mux pipeline stages can be non-zero only when there is a mux
-- output register.
IF (has_mux_output_regs=1) THEN
actual_mux_pipeline_stages := mux_pipeline_stages;
ELSE
actual_mux_pipeline_stages := 0;
END IF;
RETURN has_mem_output_regs+actual_mux_pipeline_stages+has_mux_output_regs;
END get_num_output_stages;
--***************************************************************************
-- Component declaration of the VARIABLE depth output register stage
--***************************************************************************
COMPONENT blk_mem_gen_v8_3_1_output_stage
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
EN : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
ECCPIPECE : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_output_stage;
COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************************************
-- locally derived constants to assist memory access
--******************************************************
CONSTANT WRITE_WIDTH_RATIO_A : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_A : INTEGER := C_READ_WIDTH_A/MIN_WIDTH;
CONSTANT WRITE_WIDTH_RATIO_B : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_B : INTEGER := C_READ_WIDTH_B/MIN_WIDTH;
--******************************************************
-- To modify the LSBs of the 'wider' data to the actual
-- address value
--******************************************************
CONSTANT WRITE_ADDR_A_DIV : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH_A;
CONSTANT READ_ADDR_A_DIV : INTEGER := C_READ_WIDTH_A/MIN_WIDTH_A;
CONSTANT WRITE_ADDR_B_DIV : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH_B;
CONSTANT READ_ADDR_B_DIV : INTEGER := C_READ_WIDTH_B/MIN_WIDTH_B;
--******************************************************
-- FUNCTION : log2roundup
--******************************************************
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
--******************************************************
-- Other constants and signals
--******************************************************
CONSTANT COLL_DELAY : TIME := 100 ps;
-- default data vector
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_DEFAULT_DATA,
C_WRITE_WIDTH_A);
CONSTANT CHKBIT_WIDTH : INTEGER := if_then_else(C_WRITE_WIDTH_A>57,8,if_then_else(C_WRITE_WIDTH_A>26,7,if_then_else(C_WRITE_WIDTH_A>11,6,if_then_else(C_WRITE_WIDTH_A>4,5,if_then_else(C_WRITE_WIDTH_A<5,4,0)))));
-- the init memory SIGNAL
SIGNAL memory_i : mem_array;
SIGNAL doublebit_error_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0);
SIGNAL current_contents_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
-- write mode constants
CONSTANT WRITE_MODE_A : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_A);
CONSTANT WRITE_MODE_B : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_B);
CONSTANT WRITE_MODES : STD_LOGIC_VECTOR(3 DOWNTO 0) :=
WRITE_MODE_A & WRITE_MODE_B;
-- reset values
CONSTANT INITA_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITA_VAL,
C_READ_WIDTH_A);
CONSTANT INITB_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITB_VAL,
C_READ_WIDTH_B);
-- memory output 'latches'
SIGNAL memory_out_a : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0) :=
INITA_VAL;
SIGNAL memory_out_b : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) :=
INITB_VAL;
SIGNAL sbiterr_in : STD_LOGIC := '0';
SIGNAL sbiterr_sdp : STD_LOGIC := '0';
SIGNAL dbiterr_in : STD_LOGIC := '0';
SIGNAL dbiterr_sdp : STD_LOGIC := '0';
SIGNAL rdaddrecc_in : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_sdp : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL doutb_i : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i : STD_LOGIC := '0';
SIGNAL dbiterr_i : STD_LOGIC := '0';
-- memory configuration constants
-----------------------------------------------
CONSTANT SINGLE_PORT : INTEGER := get_single_port(C_MEM_TYPE);
CONSTANT IS_ROM : INTEGER := get_is_rom(C_MEM_TYPE);
CONSTANT HAS_A_WRITE : INTEGER := get_has_a_write(IS_ROM);
CONSTANT HAS_B_WRITE : INTEGER := get_has_b_write(C_MEM_TYPE);
CONSTANT HAS_A_READ : INTEGER := get_has_a_read(C_MEM_TYPE);
CONSTANT HAS_B_READ : INTEGER := get_has_b_read(SINGLE_PORT);
CONSTANT HAS_B_PORT : INTEGER := get_has_b_port(HAS_B_READ, HAS_B_WRITE);
CONSTANT NUM_OUTPUT_STAGES_A : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_A,
C_MUX_PIPELINE_STAGES);
CONSTANT NUM_OUTPUT_STAGES_B : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES);
CONSTANT WEA0 : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT WEB0 : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-----------------------------------------------------------------------------
-- DEBUG CONTROL
-- DEBUG=0 : Debug output OFF
-- DEBUG=1 : Some debug info printed
-----------------------------------------------------------------------------
CONSTANT DEBUG : INTEGER := 0;
-- internal signals
-----------------------------------------------
SIGNAL ena_i : STD_LOGIC;
SIGNAL enb_i : STD_LOGIC;
SIGNAL reseta_i : STD_LOGIC;
SIGNAL resetb_i : STD_LOGIC;
SIGNAL wea_i : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL web_i : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL rea_i : STD_LOGIC;
SIGNAL reb_i : STD_LOGIC;
SIGNAL message_complete : BOOLEAN := false;
SIGNAL rsta_outp_stage : STD_LOGIC := '0';
SIGNAL rstb_outp_stage : STD_LOGIC := '0';
--*********************************************************
--FUNCTION : Collision check
--*********************************************************
FUNCTION collision_check (addr_a :
STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
iswrite_a : BOOLEAN;
addr_b :
STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
iswrite_b : BOOLEAN)
RETURN BOOLEAN IS
VARIABLE c_aw_bw : INTEGER;
VARIABLE c_aw_br : INTEGER;
VARIABLE c_ar_bw : INTEGER;
VARIABLE write_addr_a_width : INTEGER;
VARIABLE read_addr_a_width : INTEGER;
VARIABLE write_addr_b_width : INTEGER;
VARIABLE read_addr_b_width : INTEGER;
BEGIN
c_aw_bw := 0;
c_aw_br := 0;
c_ar_bw := 0;
-- Determine the effective address widths FOR each of the 4 ports
write_addr_a_width := C_ADDRA_WIDTH-log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width := C_ADDRA_WIDTH-log2roundup(READ_ADDR_A_DIV);
write_addr_b_width := C_ADDRB_WIDTH-log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width := C_ADDRB_WIDTH-log2roundup(READ_ADDR_B_DIV);
--Look FOR a write-write collision. In order FOR a write-write
--collision to exist, both ports must have a write transaction.
IF (iswrite_a AND iswrite_b) THEN
IF (write_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_a and iswrite_b
--If the B port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_a) THEN
IF (write_addr_a_width > read_addr_b_width) THEN
--read_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_b_width
--Once both are scaled to read_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
END IF; --width
END IF; --iswrite_a
--If the A port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_b) THEN
IF (read_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
ELSE
--read_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_a_width
--Once both are scaled to read_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_b
RETURN (c_aw_bw=1 OR c_aw_br=1 OR c_ar_bw=1);
END FUNCTION collision_check;
BEGIN -- Architecture
-----------------------------------------------------------------------------
-- SOFTECC and ECC SBITERR/DBITERR Outputs
-- The ECC Behavior is modeled by the behavioral models only for Virtex-6.
-- The SOFTECC Behavior is modeled by the behavioral models for Spartan-6.
-- For Virtex-5, these outputs will be tied to 0.
-----------------------------------------------------------------------------
SBITERR <= sbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_sdp WHEN (((C_FAMILY="virtex7") AND C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
-----------------------------------------------
-- This effectively wires off optional inputs
-----------------------------------------------
ena_i <= ENA WHEN (C_HAS_ENA=1) ELSE '1';
enb_i <= ENB WHEN (C_HAS_ENB=1 AND HAS_B_PORT=1) ELSE '1';
-- We are doing an "AND" operation of WEA and ENA and passing to Enbale pin of BRAM when built-in ECC is enabled,
-- what this means is that the write operation happens only when both WEA and ENA are high.
wea_i <= WEA WHEN (HAS_A_WRITE=1 AND ena_i='1') ELSE WEA0;
-- wea_i <= (OTHERS => '1') WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=1 AND ENA = '1') ELSE -- Use_ENA_pin
-- WEA WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=0) ELSE -- Always_enabled
-- WEA WHEN (HAS_A_WRITE=1 AND ena_i='1' AND C_USE_ECC = 0) ELSE
-- WEA0;
web_i <= WEB WHEN (HAS_B_WRITE=1 AND enb_i='1') ELSE WEB0;
rea_i <= ena_i WHEN (HAS_A_READ=1) ELSE '0';
reb_i <= enb_i WHEN (HAS_B_READ=1) ELSE '0';
-- these signals reset the memory latches
-- For the special reset behaviors in some of the families, the C_RSTRAM
-- attribute of the corresponding port is used to indicate if the latch is
-- reset or not.
reseta_i <= RSTA WHEN
((C_HAS_RSTA=1 AND NUM_OUTPUT_STAGES_A=0) OR
(C_HAS_RSTA=1 AND C_RSTRAM_A=1))
ELSE '0';
resetb_i <= RSTB WHEN
((C_HAS_RSTB=1 AND NUM_OUTPUT_STAGES_B=0) OR
(C_HAS_RSTB=1 AND C_RSTRAM_B=1) )
ELSE '0';
--***************************************************************************
-- This is the main PROCESS which includes the memory VARIABLE and the read
-- and write procedures. It also schedules read and write operations
--***************************************************************************
PROCESS (CLKA, CLKB,rea_i,reb_i,reseta_i,resetb_i)
-- Initialize the init memory array
------------------------------------
VARIABLE memory : mem_array := init_memory(DEFAULT_DATA,
C_WRITE_WIDTH_A,
MAX_DEPTH,
MIN_WIDTH);
-- Initialize the mem memory array
------------------------------------
VARIABLE softecc_sbiterr_arr : softecc_err_array;
VARIABLE softecc_dbiterr_arr : softecc_err_array;
VARIABLE sbiterr_arr : ecc_err_array;
VARIABLE dbiterr_arr : ecc_err_array;
CONSTANT doublebit_lsb : STD_LOGIC_VECTOR (1 DOWNTO 0):="11";
CONSTANT doublebit_msb : STD_LOGIC_VECTOR (C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 DOWNTO 0):= (OTHERS => '0');
VARIABLE doublebit_error : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0) := doublebit_msb & doublebit_lsb ;
VARIABLE current_contents_var : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
--***********************************
-- procedures to access the memory
--***********************************
-- write_a
----------
PROCEDURE write_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
inj_sbiterr : IN STD_LOGIC;
inj_dbiterr : IN STD_LOGIC) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
VARIABLE message : LINE;
VARIABLE errbit_current_contents : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
-- Block Memory Generator non-cycle-accurate message
ASSERT (message_complete) REPORT "Block Memory Generator module is using a behavioral model FOR simulation which will not precisely model memory collision behavior."
SEVERITY NOTE;
message_complete <= true;
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_A_DIV);
IF (address_i >= C_WRITE_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range FOR A Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEA = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_A + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEA_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Insert double bit errors:
IF (C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
current_contents(0) := NOT(current_contents(0));
current_contents(1) := NOT(current_contents(1));
--current_contents(0) := NOT(current_contents(30));
--current_contents(1) := NOT(current_contents(62));
END IF;
END IF;
-- Insert double bit errors:
IF (C_USE_SOFTECC=1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 downto 2) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 downto 0);
doublebit_error(0) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1);
doublebit_error(1) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-2);
current_contents := current_contents XOR doublebit_error(C_WRITE_WIDTH_A-1 DOWNTO 0);
END IF;
END IF;
IF(DEBUG=1) THEN
current_contents_var := current_contents; --for debugging current
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_A + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
-- Store address at which error is injected:
IF ((C_FAMILY = "virtex7") AND C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
sbiterr_arr(address_i) := '1';
ELSE
sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
dbiterr_arr(address_i) := '1';
ELSE
dbiterr_arr(address_i) := '0';
END IF;
END IF;
-- Store address at which softecc error is injected:
IF (C_USE_SOFTECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
softecc_sbiterr_arr(address_i) := '1';
ELSE
softecc_sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
softecc_dbiterr_arr(address_i) := '1';
ELSE
softecc_dbiterr_arr(address_i) := '0';
END IF;
END IF;
END IF;
END PROCEDURE;
-- write_b
----------
PROCEDURE write_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_B_DIV);
IF (address_i >= C_WRITE_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEB = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_B + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEB_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_B + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
END IF;
END PROCEDURE;
-- read_a
----------
PROCEDURE read_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_A_DIV);
IF (address_i >= C_READ_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for A Read"
SEVERITY WARNING;
END IF;
memory_out_a <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_A-1 LOOP
memory_out_a(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_A + i) AFTER FLOP_DELAY;
END LOOP;
END IF;
END IF;
END PROCEDURE;
-- read_b
----------
PROCEDURE read_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_B_DIV);
IF (address_i >= C_READ_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Read"
SEVERITY WARNING;
END IF;
memory_out_b <= (OTHERS => 'X') AFTER FLOP_DELAY;
sbiterr_in <= 'X' AFTER FLOP_DELAY;
dbiterr_in <= 'X' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_B-1 LOOP
memory_out_b(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_B + i) AFTER FLOP_DELAY;
END LOOP;
--assert sbiterr and dbiterr signals
IF ((C_FAMILY="virtex7") AND C_USE_ECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
--assert softecc sbiterr and dbiterr signals
ELSIF (C_USE_SOFTECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (softecc_sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (softecc_dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
END IF;
END IF;
END IF;
END PROCEDURE;
-- reset_a
----------
PROCEDURE reset_a
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
-- reset_b
----------
PROCEDURE reset_b
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
BEGIN -- begin the main PROCESS
--***************************************************************************
-- These are the main blocks which schedule read and write operations
-- Note that the reset priority feature at the latch stage is only supported
-- for Spartan-6. For other families, the default priority at the latch stage
-- is "CE"
--***************************************************************************
-- Synchronous clocks: schedule port operations with respect to both
-- write operating modes
IF (C_COMMON_CLK=1) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODES IS
WHEN "0000" => -- write_first write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "0100" => -- read_first write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "0001" => -- write_first read_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0101" => --read_first read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0010" => -- write_first no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0110" => -- read_first no_change
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1000" => -- no_change write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "1001" => -- no_change read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1010" => -- no_change no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Synchronous clocks
-- Asynchronous clocks: port operation is independent
IF (C_COMMON_CLK=0) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODE_A IS
WHEN "00" => -- write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN "01" => -- read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "10" => -- no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
IF (CLKB='1' AND CLKB'EVENT) THEN
CASE WRITE_MODE_B IS
WHEN "00" => -- write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "01" => -- read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "10" => -- no_change
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Asynchronous clocks
-- Assign the memory VARIABLE to the user_visible memory_i SIGNAL
IF(DEBUG=1) THEN
memory_i <= memory;
doublebit_error_i <= doublebit_error;
current_contents_i <= current_contents_var;
END IF;
END PROCESS;
--********************************************************************
-- Instantiate the VARIABLE depth output stage
--********************************************************************
-- Port A
rsta_outp_stage <= RSTA and not sleep;
rstb_outp_stage <= RSTB and not sleep;
reg_a : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTA,
C_RSTRAM => C_RSTRAM_A,
C_RST_PRIORITY => C_RST_PRIORITY_A,
init_val => INITA_VAL,
C_HAS_EN => C_HAS_ENA,
C_HAS_REGCE => C_HAS_REGCEA,
C_DATA_WIDTH => C_READ_WIDTH_A,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_A,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_A,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKA,
RST => rsta_outp_stage, --RSTA,
EN => ENA,
REGCE => REGCEA,
DIN_I => memory_out_a,
DOUT => DOUTA,
SBITERR_IN_I => '0',
DBITERR_IN_I => '0',
SBITERR => OPEN,
DBITERR => OPEN,
RDADDRECC_IN_I => (OTHERS => '0'),
ECCPIPECE => '0',
RDADDRECC => OPEN
);
-- Port B
reg_b : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTB,
C_RSTRAM => C_RSTRAM_B,
C_RST_PRIORITY => C_RST_PRIORITY_B,
init_val => INITB_VAL,
C_HAS_EN => C_HAS_ENB,
C_HAS_REGCE => C_HAS_REGCEB,
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_B,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKB,
RST => rstb_outp_stage,--RSTB,
EN => ENB,
REGCE => REGCEB,
DIN_I => memory_out_b,
DOUT => doutb_i,
SBITERR_IN_I => sbiterr_in,
DBITERR_IN_I => dbiterr_in,
SBITERR => sbiterr_i,
DBITERR => dbiterr_i,
RDADDRECC_IN_I => rdaddrecc_in,
ECCPIPECE => ECCPIPECE,
RDADDRECC => rdaddrecc_i
);
--********************************************************************
-- Instantiate the input / Output Register stages
--********************************************************************
output_reg_stage: blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC MAP(
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP(
CLK => CLKB,
DIN => doutb_i,
DOUT => DOUTB,
SBITERR_IN => sbiterr_i,
DBITERR_IN => dbiterr_i,
SBITERR => sbiterr_sdp,
DBITERR => dbiterr_sdp,
RDADDRECC_IN => rdaddrecc_i,
RDADDRECC => rdaddrecc_sdp
);
--*********************************
-- Synchronous collision checks
--*********************************
sync_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=1) GENERATE
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
-- collision detect
VARIABLE is_collision : BOOLEAN;
VARIABLE message : LINE;
BEGIN
IF (CLKA='1' AND CLKA'EVENT) THEN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision := false;
END IF;
-- If the write port is in READ_FIRST mode, there is no collision
IF (C_WRITE_MODE_A="READ_FIRST" AND wea_i/=WEA0 AND web_i=WEB0) THEN
is_collision := false;
END IF;
IF (C_WRITE_MODE_B="READ_FIRST" AND web_i/=WEB0 AND wea_i=WEA0) THEN
is_collision := false;
END IF;
-- Only flag if one of the accesses is a write
IF (is_collision AND (wea_i/=WEA0 OR web_i/=WEB0)) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END IF;
END PROCESS;
END GENERATE;
--*********************************
-- Asynchronous collision checks
--*********************************
async_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=0) GENERATE
SIGNAL addra_delay : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL wea_delay : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL ena_delay : STD_LOGIC;
SIGNAL addrb_delay : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
SIGNAL web_delay : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL enb_delay : STD_LOGIC;
BEGIN
-- Delay A and B addresses in order to mimic setup/hold times
PROCESS (ADDRA, wea_i, ena_i, ADDRB, web_i, enb_i)
BEGIN
addra_delay <= ADDRA AFTER COLL_DELAY;
wea_delay <= wea_i AFTER COLL_DELAY;
ena_delay <= ena_i AFTER COLL_DELAY;
addrb_delay <= ADDRB AFTER COLL_DELAY;
web_delay <= web_i AFTER COLL_DELAY;
enb_delay <= enb_i AFTER COLL_DELAY;
END PROCESS;
-- Do the checks w/rt A
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_a : BOOLEAN;
VARIABLE is_collision_delay_a : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_a := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_a := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_delay_a := collision_check(ADDRA,
wea_i/=WEA0,
addrb_delay,
web_delay/=WEB0);
ELSE
is_collision_delay_a := false;
END IF;
-- Only flag if B access is a write
IF (is_collision_a AND web_i/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_a AND web_delay/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, addrb_delay);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
-- Do the checks w/rt B
PROCESS (CLKB)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_b : BOOLEAN;
VARIABLE is_collision_delay_b : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA) /= 'X') THEN
is_collision_b := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_b := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(addra_delay) /= 'X') THEN
is_collision_delay_b := collision_check(addra_delay,
wea_delay/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_delay_b := false;
END IF;
-- Only flag if A access is a write
-- Modified condition checking (is_collision_b AND WEA0_i=/WEA0) to fix CR526228
IF (is_collision_b AND wea_i/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_b AND wea_delay/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, addra_delay);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
END GENERATE;
END mem_module_behavioral;
--******************************************************************************
-- Top module that wraps SoftECC Input register stage and the main memory module
--
-- This module is the top-level of behavioral model
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1 IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_CTRL_ECC_ALGO : STRING := "NONE";
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
--C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_SLEEP_PIN : INTEGER := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
PORT (
clka : IN STD_LOGIC := '0';
rsta : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '1';
regcea : IN STD_LOGIC := '1';
wea : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addra : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
dina : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
douta : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
clkb : IN STD_LOGIC := '0';
rstb : IN STD_LOGIC := '0';
enb : IN STD_LOGIC := '1';
regceb : IN STD_LOGIC := '1';
web : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addrb : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
dinb : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
doutb : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
injectsbiterr : IN STD_LOGIC := '0';
injectdbiterr : IN STD_LOGIC := '0';
sbiterr : OUT STD_LOGIC := '0';
dbiterr : OUT STD_LOGIC := '0';
rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : in std_logic := '0';
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic := '0';
rstb_busy : out std_logic := '0';
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
s_aclk : IN STD_LOGIC := '0';
s_aresetn : IN STD_LOGIC := '0';
-- axi full/lite slave Write (write side)
s_axi_awid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid : IN STD_LOGIC := '0';
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast : IN STD_LOGIC := '0';
s_axi_wvalid : IN STD_LOGIC := '0';
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC := '0';
-- axi full/lite slave Read (Write side)
s_axi_arid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid : IN STD_LOGIC := '0';
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_rdata : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC := '0';
-- axi full/lite sideband Signals
s_axi_injectsbiterr : IN STD_LOGIC := '0';
s_axi_injectdbiterr : IN STD_LOGIC := '0';
s_axi_sbiterr : OUT STD_LOGIC := '0';
s_axi_dbiterr : OUT STD_LOGIC := '0';
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END blk_mem_gen_v8_3_1;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE behavioral OF blk_mem_gen_v8_3_1 IS
COMPONENT blk_mem_gen_v8_3_1_mem_module
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_mem_module;
COMPONENT blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_axi_regs_fwd_v8_3;
COMPONENT blk_mem_axi_read_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT blk_mem_axi_read_wrapper_beh;
COMPONENT blk_mem_axi_write_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END COMPONENT blk_mem_axi_write_wrapper_beh;
CONSTANT FLOP_DELAY : TIME := 100 ps;
SIGNAL rsta_in : STD_LOGIC := '1';
SIGNAL ena_in : STD_LOGIC := '1';
SIGNAL regcea_in : STD_LOGIC := '1';
SIGNAL wea_in : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL addra_in : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL dina_in : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL injectsbiterr_in : STD_LOGIC := '0';
SIGNAL injectdbiterr_in : STD_LOGIC := '0';
-----------------------------------------------------------------------------
-- FUNCTION: toLowerCaseChar
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
-----------------------------------------------------------------------------
FUNCTION toLowerCaseChar(
char : character )
RETURN character IS
BEGIN
-- If char is not an upper case letter then return char
IF char<'A' OR char>'Z' THEN
RETURN char;
END IF;
-- Otherwise map char to its corresponding lower case character and
-- RETURN that
CASE char IS
WHEN 'A' => RETURN 'a';
WHEN 'B' => RETURN 'b';
WHEN 'C' => RETURN 'c';
WHEN 'D' => RETURN 'd';
WHEN 'E' => RETURN 'e';
WHEN 'F' => RETURN 'f';
WHEN 'G' => RETURN 'g';
WHEN 'H' => RETURN 'h';
WHEN 'I' => RETURN 'i';
WHEN 'J' => RETURN 'j';
WHEN 'K' => RETURN 'k';
WHEN 'L' => RETURN 'l';
WHEN 'M' => RETURN 'm';
WHEN 'N' => RETURN 'n';
WHEN 'O' => RETURN 'o';
WHEN 'P' => RETURN 'p';
WHEN 'Q' => RETURN 'q';
WHEN 'R' => RETURN 'r';
WHEN 'S' => RETURN 's';
WHEN 'T' => RETURN 't';
WHEN 'U' => RETURN 'u';
WHEN 'V' => RETURN 'v';
WHEN 'W' => RETURN 'w';
WHEN 'X' => RETURN 'x';
WHEN 'Y' => RETURN 'y';
WHEN 'Z' => RETURN 'z';
WHEN OTHERS => RETURN char;
END CASE;
END toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
FUNCTION equalIgnoreCase(
str1 : STRING;
str2 : STRING )
RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str2'left TO str1'right LOOP
IF NOT (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equalIgnoreCase;
-----------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
----------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
----------------------------------------------------------------------------
-- FUNCTION : log2roundup
----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
CONSTANT lower_limit : INTEGER := 1;
CONSTANT upper_limit : INTEGER := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
-----------------------------------------------------------------------------
-- FUNCTION : divroundup
-- Returns the ceiling value of the division
-- Data_value - the quantity to be divided, dividend
-- Divisor - the value to divide the data_value by
-----------------------------------------------------------------------------
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
SIGNAL s_axi_awaddr_out_c : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_araddr_out_c : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_wr_en_c : STD_LOGIC := '0';
SIGNAL s_axi_rd_en_c : STD_LOGIC := '0';
SIGNAL s_aresetn_a_c : STD_LOGIC := '0';
--**************************************************************************
-- AXI PARAMETERS
CONSTANT AXI_FULL_MEMORY_SLAVE : integer := if_then_else((C_AXI_SLAVE_TYPE = 0 AND C_AXI_TYPE = 1),1,0);
CONSTANT C_AXI_ADDR_WIDTH_MSB : integer := C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
CONSTANT C_AXI_ADDR_WIDTH : integer := C_AXI_ADDR_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT LOWER_BOUND_VAL : integer := if_then_else((log2roundup(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT C_AXI_ADDR_WIDTH_LSB : integer := if_then_else((AXI_FULL_MEMORY_SLAVE = 1),0,LOWER_BOUND_VAL);
CONSTANT C_AXI_OS_WR : integer := 2;
-- SAFETY LOGIC related Signals
SIGNAL RSTA_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_A : STD_LOGIC := '0';
SIGNAL RSTB_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_B : STD_LOGIC := '0';
SIGNAL ENA_dly : STD_LOGIC := '0';
SIGNAL ENA_dly_D : STD_LOGIC := '0';
SIGNAL ENB_dly : STD_LOGIC := '0';
SIGNAL ENB_dly_D : STD_LOGIC := '0';
SIGNAL RSTA_I_SAFE : STD_LOGIC := '0';
SIGNAL RSTB_I_SAFE : STD_LOGIC := '0';
SIGNAL ENA_I_SAFE : STD_LOGIC := '0';
SIGNAL ENB_I_SAFE : STD_LOGIC := '0';
SIGNAL ram_rstram_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstram_b_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_b_busy : STD_LOGIC := '0';
SIGNAL ENA_dly_reg : STD_LOGIC := '0';
SIGNAL ENB_dly_reg : STD_LOGIC := '0';
SIGNAL ENA_dly_reg_D : STD_LOGIC := '0';
SIGNAL ENB_dly_reg_D : STD_LOGIC := '0';
--**************************************************************************
BEGIN -- Architecture
--*************************************************************************
-- NO INPUT STAGE
--*************************************************************************
no_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=0) GENERATE
rsta_in <= RSTA;
ena_in <= ENA;
regcea_in <= REGCEA;
wea_in <= WEA;
addra_in <= ADDRA;
dina_in <= DINA;
injectsbiterr_in <= INJECTSBITERR;
injectdbiterr_in <= INJECTDBITERR;
END GENERATE no_input_stage;
--**************************************************************************
-- WITH INPUT STAGE
--**************************************************************************
has_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=1) GENERATE
PROCESS (CLKA)
BEGIN
IF (CLKA'EVENT AND CLKA = '1') THEN
rsta_in <= RSTA AFTER FLOP_DELAY;
ena_in <= ENA AFTER FLOP_DELAY;
regcea_in <= REGCEA AFTER FLOP_DELAY;
wea_in <= WEA AFTER FLOP_DELAY;
addra_in <= ADDRA AFTER FLOP_DELAY;
dina_in <= DINA AFTER FLOP_DELAY;
injectsbiterr_in <= INJECTSBITERR AFTER FLOP_DELAY;
injectdbiterr_in <= INJECTDBITERR AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE has_input_stage;
--**************************************************************************
-- NO SAFETY LOGIC
--**************************************************************************
NO_SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 0) GENERATE
ENA_I_SAFE <= ena_in;
ENB_I_SAFE <= ENB;
RSTA_I_SAFE <= rsta_in;
RSTB_I_SAFE <= RSTB;
END GENERATE NO_SAFETY_CKT_GEN;
--**************************************************************************
-- SAFETY LOGIC
--**************************************************************************
SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 1) GENERATE
-- RESET SAFETY LOGIC Generation
-- POR Generation
------------------------------------------------------------------------------
-- Power-ON Reset Generation
------------------------------------------------------------------------------
RST_SHFT_LOGIC_A : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
RSTA_SHFT_REG(4 DOWNTO 0) <= RSTA_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_A;
POR_RSTA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
POR_A <= RSTA_SHFT_REG(4) xor RSTA_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTA_GEN;
RST_SHFT_LOGIC_B : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
RSTB_SHFT_REG(4 DOWNTO 0) <= RSTB_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_B;
POR_RSTB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
POR_B <= RSTB_SHFT_REG(4) xor RSTB_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTB_GEN;
-----------------------------------------------------------------------------
-- Fix for the AR42571
-----------------------------------------------------------------------------
-- Reset Generation
-----------------------------------------------------------------------------
RSTA_I_SAFE <= rsta_in OR POR_A;
SPRAM_RST: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_I_SAFE <= '0';
END GENERATE SPRAM_RST;
nSPRAM_RST: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_I_SAFE <= RSTB OR POR_B;
END GENERATE nSPRAM_RST;
-----------------------------------------------------------------------------
-- RSTA/B_BUSY Generation
-----------------------------------------------------------------------------
RSTA_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
ram_rstram_a_busy <= rsta_in OR ENA_dly OR ENA_dly_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstram_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_NO_REG;
RSTA_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
ram_rstreg_a_busy <= rsta_in OR ENA_dly OR ENA_dly_reg_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstreg_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_WITH_REG;
SPRAM_RST_BUSY: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_BUSY <= '0';
END GENERATE SPRAM_RST_BUSY;
nSPRAM_RST_BUSY: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
ram_rstram_b_busy <= RSTB OR ENB_dly OR ENB_dly_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstram_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_NO_REG;
RSTB_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
ram_rstreg_b_busy <= RSTB OR ENB_dly OR ENB_dly_reg_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstreg_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_WITH_REG;
END GENERATE nSPRAM_RST_BUSY;
-----------------------------------------------------------------------------
-- ENA/ENB Generation
-----------------------------------------------------------------------------
ENA_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly <= rsta_in AFTER FLOP_DELAY;
ENA_dly_D <= ENA_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_D OR ena_in;
END GENERATE ENA_NO_REG;
ENA_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly_reg <= rsta_in AFTER FLOP_DELAY;
ENA_dly_reg_D <= ENA_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_reg_D OR ena_in;
END GENERATE ENA_WITH_REG;
SPRAM_ENB: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
ENB_I_SAFE <= '0';
END GENERATE SPRAM_ENB;
nSPRAM_ENB: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
ENB_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly <= RSTB AFTER FLOP_DELAY;
ENB_dly_D <= ENB_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_D OR ENB;
END GENERATE ENB_NO_REG;
ENB_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly_reg <= RSTB AFTER FLOP_DELAY;
ENB_dly_reg_D <= ENB_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_reg_D OR ENB;
END GENERATE ENB_WITH_REG;
END GENERATE nSPRAM_ENB;
END GENERATE SAFETY_CKT_GEN;
--**************************************************************************
-- NATIVE MEMORY MODULE INSTANCE
--**************************************************************************
native_mem_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 0) GENERATE
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,--rsta_in,
ENA => ENA_I_SAFE,--ena_in,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in,
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => RDADDRECC
);
END GENERATE native_mem_module;
--**************************************************************************
-- NATIVE MEMORY MAPPED MODULE INSTANCE
--**************************************************************************
native_mem_map_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 1) GENERATE
--**************************************************************************
-- NATIVE MEMORY MAPPED PARAMETERS
CONSTANT C_ADDRA_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_A);
CONSTANT C_ADDRB_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_B);
CONSTANT C_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
CONSTANT C_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
CONSTANT C_MEM_MAP_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_MSB;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT MEM_MAP_LOWER_BOUND_VAL_A : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT MEM_MAP_LOWER_BOUND_VAL_B : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_B,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_B,8)));
CONSTANT C_MEM_MAP_ADDRA_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_A;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_B;
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH_ACTUAL-1 DOWNTO 0) := (OTHERS => '0');
--**************************************************************************
BEGIN
RDADDRECC(C_ADDRB_WIDTH-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_MSB) <= (OTHERS => '0');
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB) <= rdaddrecc_i;
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_LSB-1 DOWNTO 0) <= (OTHERS => '0');
mem_map_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH_ACTUAL,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH_ACTUAL,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,
ENA => ENA_I_SAFE,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in(C_MEM_MAP_ADDRA_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRA_WIDTH_LSB),
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB),
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => rdaddrecc_i
);
END GENERATE native_mem_map_module;
--****************************************************************************
-- AXI MEMORY MODULE INSTANCE
--****************************************************************************
axi_mem_module: IF (C_INTERFACE_TYPE = 1) GENERATE
SIGNAL s_axi_rid_c : STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rdata_c : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rresp_c : STD_LOGIC_VECTOR(2-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rlast_c : STD_LOGIC := '0';
SIGNAL s_axi_rvalid_c : STD_LOGIC := '0';
SIGNAL s_axi_rready_c : STD_LOGIC := '0';
SIGNAL regceb_c : STD_LOGIC := '0';
BEGIN
s_aresetn_a_c <= NOT S_ARESETN;
S_AXI_BRESP <= (OTHERS => '0');
s_axi_rresp_c <= (OTHERS => '0');
no_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 0 AND C_HAS_MUX_OUTPUT_REGS_B = 0 ) GENERATE
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RLAST <= s_axi_rlast_c;
S_AXI_RVALID <= s_axi_rvalid_c;
S_AXI_RID <= s_axi_rid_c;
S_AXI_RRESP <= s_axi_rresp_c;
s_axi_rready_c <= S_AXI_RREADY;
END GENERATE no_regs;
has_regs_fwd: IF (C_HAS_MUX_OUTPUT_REGS_B = 1 OR C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
CONSTANT C_AXI_PAYLOAD : INTEGER := if_then_else((C_HAS_MUX_OUTPUT_REGS_B = 1),C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3,C_AXI_ID_WIDTH+3);
SIGNAL s_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
has_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
regceb_c <= s_axi_rvalid_c AND s_axi_rready_c;
END GENERATE has_regceb;
no_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 0) GENERATE
regceb_c <= REGCEB;
END GENERATE no_regceb;
only_core_op_regs: IF (C_HAS_MUX_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rdata_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RDATA <= m_axi_payload_c(C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_core_op_regs;
only_emb_op_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_emb_op_regs;
axi_regs_inst : blk_mem_axi_regs_fwd_v8_3
GENERIC MAP(
C_DATA_WIDTH => C_AXI_PAYLOAD
)
PORT MAP (
ACLK => S_ACLK,
ARESET => s_aresetn_a_c,
S_VALID => s_axi_rvalid_c,
S_READY => s_axi_rready_c,
S_PAYLOAD_DATA => s_axi_payload_c,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY,
M_PAYLOAD_DATA => m_axi_payload_c
);
END GENERATE has_regs_fwd;
axi_wr_fsm : blk_mem_axi_write_wrapper_beh
GENERIC MAP(
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_AXI_AWADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_WDATA_WIDTH => C_WRITE_WIDTH_A,
C_AXI_OS_WR => C_AXI_OS_WR
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Slave Write Interface
S_AXI_AWADDR => S_AXI_AWADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_AWLEN => S_AXI_AWLEN,
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BID => S_AXI_BID,
-- Signals for BRAM interface
S_AXI_AWADDR_OUT =>s_axi_awaddr_out_c,
S_AXI_WR_EN =>s_axi_wr_en_c
);
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => 1, -- For AXI, Read Enable is always C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => 1, -- For AXI C_USE_BYTE_WEA is always 1,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => 1, -- For AXI, Read Enable is always C_HAS_ENB,
C_HAS_REGCEB => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_BYTE_WEB => 1, -- For AXI C_USE_BYTE_WEB is always 1,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => 0, --For AXI, Primitive Registers A is not supported C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => 0,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
--Port A:
CLKA => S_AClk,
RSTA => s_aresetn_a_c,
ENA => s_axi_wr_en_c,
REGCEA => regcea_in,
WEA => S_AXI_WSTRB,
ADDRA => s_axi_awaddr_out_c,
DINA => S_AXI_WDATA,
DOUTA => DOUTA,
--Port B:
CLKB => S_AClk,
RSTB => s_aresetn_a_c,
ENB => s_axi_rd_en_c,
REGCEB => regceb_c,
WEB => (OTHERS => '0'),
ADDRB => s_axi_araddr_out_c,
DINB => DINB,
DOUTB => s_axi_rdata_c,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => '0',
SLEEP => '0',
RDADDRECC => RDADDRECC
);
axi_rd_sm : blk_mem_axi_read_wrapper_beh
GENERIC MAP (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_PIPELINE_STAGES => 1,
C_AXI_ARADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_AClk,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Read Side
S_AXI_ARADDR => S_AXI_ARADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARSIZE => S_AXI_ARSIZE,
S_AXI_ARBURST => S_AXI_ARBURST,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => s_axi_rlast_c,
S_AXI_RVALID => s_axi_rvalid_c,
S_AXI_RREADY => s_axi_rready_c,
S_AXI_ARID => S_AXI_ARID,
S_AXI_RID => s_axi_rid_c,
-- AXI Full/Lite Read FSM Outputs
S_AXI_ARADDR_OUT => s_axi_araddr_out_c,
S_AXI_RD_EN => s_axi_rd_en_c
);
END GENERATE axi_mem_module;
END behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_clr is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_clr;
architecture beh_ff_clr_arch of beh_ff_clr is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(CLR, C)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_clr_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_ce is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_ce;
architecture beh_ff_ce_arch of beh_ff_ce is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, CLR)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
if (CE = '1') then
q_o <= D after 100 ps;
end if;
end if;
end process;
end beh_ff_ce_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_pre is
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end beh_ff_pre;
architecture beh_ff_pre_arch of beh_ff_pre is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, PRE)
begin
if (PRE = '1') then
q_o <= '1';
elsif (C' event and C = '1') then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_pre_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_muxf7 is
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end beh_muxf7;
architecture beh_muxf7_arch of beh_muxf7 is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
else
O <= I1;
end if;
end process;
end beh_muxf7_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity STATE_LOGIC is
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic := '0';
I0 : in std_logic := '0';
I1 : in std_logic := '0';
I2 : in std_logic := '0';
I3 : in std_logic := '0';
I4 : in std_logic := '0';
I5 : in std_logic := '0'
);
end STATE_LOGIC;
architecture STATE_LOGIC_arch of STATE_LOGIC is
constant INIT_reg : std_logic_vector(63 downto 0) := INIT;
begin
LUT_beh:process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
begin
I_reg := I5 & I4 & I3 & I2 & I1 & I0;
O <= INIT_reg(conv_integer(I_reg));
end process;
end STATE_LOGIC_arch;
|
-------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v8_3_1.vhd
--
-- Description:
-- This file is the VHDL behvarial model for the
-- Block Memory Generator Core.
--
-------------------------------------------------------------------------------
-- Author: Xilinx
--
-- History: January 11, 2006: Initial revision
-- June 11, 2007 : Added independent register stages for
-- Port A and Port B (IP1_Jm/v2.5)
-- August 28, 2007 : Added mux pipeline stages feature (IP2_Jm/v2.6)
-- April 07, 2009 : Added support for Spartan-6 and Virtex-6
-- features, including the following:
-- (i) error injection, detection and/or correction
-- (ii) reset priority
-- (iii) special reset behavior
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
ENTITY blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END ENTITY blk_mem_axi_regs_fwd_v8_3;
ARCHITECTURE axi_regs_fwd_arch OF blk_mem_axi_regs_fwd_v8_3 IS
SIGNAL STORAGE_DATA : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_READY_I : STD_LOGIC := '0';
SIGNAL M_VALID_I : STD_LOGIC := '0';
SIGNAL ARESET_D : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');-- Reset delay register
BEGIN
--assign local signal to its output signal
S_READY <= S_READY_I;
M_VALID <= M_VALID_I;
PROCESS(ACLK)
BEGIN
IF(ACLK'event AND ACLK = '1') THEN
ARESET_D <= ARESET_D(0) & ARESET;
END IF;
END PROCESS;
--Save payload data whenever we have a transaction on the slave side
PROCESS(ACLK, ARESET)
BEGIN
IF (ARESET = '1') THEN
STORAGE_DATA <= (OTHERS => '0');
ELSIF(ACLK'event AND ACLK = '1') THEN
IF(S_VALID = '1' AND S_READY_I = '1') THEN
STORAGE_DATA <= S_PAYLOAD_DATA;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= STORAGE_DATA;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
PROCESS(ACLK,ARESET)
BEGIN
IF (ARESET_D /= "00") THEN
M_VALID_I <= '0';
ELSIF(ACLK'event AND ACLK = '1') THEN
IF (S_VALID = '1') THEN
--Always set M_VALID_I when slave side is valid
M_VALID_I <= '1';
ELSIF (M_READY = '1') THEN
--Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= '0';
END IF;
END IF;
END PROCESS;
--Slave Ready is either when Master side drives M_READY or we have space in our storage data
S_READY_I <= (M_READY OR (NOT M_VALID_I)) AND NOT(OR_REDUCE(ARESET_D));
END axi_regs_fwd_arch;
-------------------------------------------------------------------------------
-- Description:
-- This is the behavioral model of write_wrapper for the
-- Block Memory Generator Core.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_axi_write_wrapper_beh IS
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END blk_mem_axi_write_wrapper_beh;
ARCHITECTURE axi_write_wrap_arch OF blk_mem_axi_write_wrapper_beh IS
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_AXI_WDATA_WIDTH=8,0,
if_then_else((C_AXI_WDATA_WIDTH=16),1,
if_then_else((C_AXI_WDATA_WIDTH=32),2,
if_then_else((C_AXI_WDATA_WIDTH=64),3,
if_then_else((C_AXI_WDATA_WIDTH=128),4,
if_then_else((C_AXI_WDATA_WIDTH=256),5,0))))));
SIGNAL bvalid_c : std_logic := '0';
SIGNAL bready_timeout_c : std_logic := '0';
SIGNAL bvalid_rd_cnt_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_r : std_logic := '0';
SIGNAL bvalid_count_r : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL awaddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
C_AXI_AWADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL bvalid_wr_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_rd_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_last_c : std_logic := '0';
SIGNAL addr_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL aw_ready_r : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL awlen_cntr_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1');
SIGNAL awlen_int : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL awburst_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes : integer := 0;
SIGNAL wrap_boundary : integer := 0;
SIGNAL wrap_base_addr : integer := 0;
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
-- Array to store BIDs
TYPE id_array IS ARRAY (3 DOWNTO 0) OF std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
SIGNAL axi_bid_array : id_array := (others => (others => '0'));
COMPONENT write_netlist
GENERIC(
C_AXI_TYPE : integer
);
PORT(
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
S_AXI_AWVALID : IN std_logic;
aw_ready_r : OUT std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN std_logic;
S_AXI_WR_EN : OUT std_logic;
w_last_c : IN std_logic;
bready_timeout_c : IN std_logic;
addr_en_c : OUT std_logic;
incr_addr_c : OUT std_logic;
bvalid_c : OUT std_logic
);
END COMPONENT write_netlist;
BEGIN
---------------------------------------
--AXI WRITE FSM COMPONENT INSTANTIATION
---------------------------------------
axi_wr_fsm : write_netlist
GENERIC MAP (
C_AXI_TYPE => C_AXI_TYPE
)
PORT MAP (
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
S_AXI_AWVALID => S_AXI_AWVALID,
aw_ready_r => aw_ready_r,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BVALID => OPEN,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_WR_EN => S_AXI_WR_EN,
w_last_c => w_last_c,
bready_timeout_c => bready_timeout_c,
addr_en_c => addr_en_c,
incr_addr_c => incr_addr_c,
bvalid_c => bvalid_c
);
--Wrap Address boundary calculation
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWSIZE,"000"));
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(awlen_int)+1);
wrap_base_addr <= (conv_integer(awaddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary <= wrap_base_addr+total_bytes;
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awaddr_reg <= (OTHERS => '0');
num_of_bytes_r <= 0;
awburst_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awaddr_reg <= S_AXI_AWADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWBURST,"01");
ELSIF (incr_addr_c = '1') THEN
IF (awburst_int = "10") THEN
IF(conv_integer(awaddr_reg) = (wrap_boundary-num_of_bytes_r)) THEN
awaddr_reg <= conv_std_logic_vector(wrap_base_addr,C_AXI_AWADDR_WIDTH);
ELSE
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
ELSIF (awburst_int = "01" OR awburst_int = "11") THEN
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
S_AXI_AWADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
awaddr_reg(C_AXI_AWADDR_WIDTH-1 DOWNTO C_RANGE),awaddr_reg);
---------------------------------------------------------------------------
-- AXI wlast generation
---------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awlen_cntr_r <= (OTHERS => '1');
awlen_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awlen_int <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
awlen_cntr_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
ELSIF (dec_alen_c = '1') THEN
awlen_cntr_r <= awlen_cntr_r - ONE AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
w_last_c <= '1' WHEN (awlen_cntr_r = "00000000" AND S_AXI_WVALID = '1') ELSE '0';
dec_alen_c <= (incr_addr_c OR w_last_c);
---------------------------------------------------------------------------
-- Generation of bvalid counter for outstanding transactions
---------------------------------------------------------------------------
P_b_valid_os_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_count_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- bvalid_count_r generation
IF (bvalid_c = '1' AND bvalid_r = '1' AND S_AXI_BREADY = '1') THEN
bvalid_count_r <= bvalid_count_r AFTER FLOP_DELAY;
ELSIF (bvalid_c = '1') THEN
bvalid_count_r <= bvalid_count_r + "01" AFTER FLOP_DELAY;
ELSIF (bvalid_r = '1' AND S_AXI_BREADY = '1' AND bvalid_count_r /= "0") THEN
bvalid_count_r <= bvalid_count_r - "01" AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_os_r ;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is used
---------------------------------------------------------------------------
gaxi_bvalid_id_r:IF (C_HAS_AXI_ID = 1) GENERATE
SIGNAL bvalid_d1_c : std_logic := '0';
BEGIN
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
bvalid_d1_c <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
--external bvalid signal generation
IF (bvalid_d1_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_id_r;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is not used
---------------------------------------------------------------------------
gaxi_bvalid_noid_r:IF (C_HAS_AXI_ID = 0) GENERATE
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
--external bvalid signal generation
IF (bvalid_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_noid_r;
---------------------------------------------------------------------------
-- Generation of Bready timeout
---------------------------------------------------------------------------
P_brdy_tout_c: PROCESS (bvalid_count_r)
BEGIN
-- bready_timeout_c generation
IF(conv_integer(bvalid_count_r) = C_AXI_OS_WR-1) THEN
bready_timeout_c <= '1';
ELSE
bready_timeout_c <= '0';
END IF;
END PROCESS P_brdy_tout_c;
---------------------------------------------------------------------------
-- Generation of BID
---------------------------------------------------------------------------
gaxi_bid_gen:IF (C_HAS_AXI_ID = 1) GENERATE
P_bid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
bvalid_wr_cnt_r <= (OTHERS => '0');
bvalid_rd_cnt_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- STORE AWID IN AN ARRAY
IF(bvalid_c = '1') THEN
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + "01";
END IF;
-- GENERATE BID FROM AWID ARRAY
bvalid_rd_cnt_r <= bvalid_rd_cnt_c AFTER FLOP_DELAY;
S_AXI_BID <= axi_bid_array(conv_integer(bvalid_rd_cnt_c));
END IF;
END PROCESS P_bid_gen;
bvalid_rd_cnt_c <= bvalid_rd_cnt_r + "01" WHEN (bvalid_r = '1' AND S_AXI_BREADY = '1') ELSE bvalid_rd_cnt_r;
---------------------------------------------------------------------------
-- Storing AWID for generation of BID
---------------------------------------------------------------------------
P_awid_reg:PROCESS (S_ACLK)
BEGIN
IF (S_ACLK'event AND S_ACLK='1') THEN
IF(aw_ready_r = '1' AND S_AXI_AWVALID = '1') THEN
axi_bid_array(conv_integer(bvalid_wr_cnt_r)) <= S_AXI_AWID;
END IF;
END IF;
END PROCESS P_awid_reg;
END GENERATE gaxi_bid_gen;
S_AXI_BVALID <= bvalid_r;
S_AXI_AWREADY <= aw_ready_r;
END axi_write_wrap_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity write_netlist is
GENERIC(
C_AXI_TYPE : integer
);
port (
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_AWVALID : in STD_LOGIC := '0';
S_AXI_WVALID : in STD_LOGIC := '0';
S_AXI_BREADY : in STD_LOGIC := '0';
w_last_c : in STD_LOGIC := '0';
bready_timeout_c : in STD_LOGIC := '0';
aw_ready_r : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_WR_EN : out STD_LOGIC;
addr_en_c : out STD_LOGIC;
incr_addr_c : out STD_LOGIC;
bvalid_c : out STD_LOGIC
);
end write_netlist;
architecture STRUCTURE of write_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
BEGIN
---------------------------------------------------------------------------
-- AXI LITE
---------------------------------------------------------------------------
gbeh_axi_lite_sm: IF (C_AXI_TYPE = 0 ) GENERATE
signal w_ready_r_7 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSignal_bvalid_c : STD_LOGIC;
signal NlwRenamedSignal_incr_addr_c : STD_LOGIC;
signal present_state_FSM_FFd3_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal present_state_FSM_FFd1_15 : STD_LOGIC;
signal present_state_FSM_FFd4_16 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd4_In1_21 : STD_LOGIC;
signal Mmux_aw_ready_c : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
S_AXI_WREADY <= w_ready_r_7;
S_AXI_BVALID <= NlwRenamedSignal_incr_addr_c;
S_AXI_WR_EN <= NlwRenamedSignal_bvalid_c;
incr_addr_c <= NlwRenamedSignal_incr_addr_c;
bvalid_c <= NlwRenamedSignal_bvalid_c;
NlwRenamedSignal_incr_addr_c <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_7
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_16
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_13
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_15
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000055554440"
)
port map (
I0 => S_AXI_WVALID,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => '0',
O => present_state_FSM_FFd3_In
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"0000000088880800"
)
port map (
I0 => S_AXI_AWVALID,
I1 => S_AXI_WVALID,
I2 => bready_timeout_c,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => present_state_FSM_FFd2_In
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAA2000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_WVALID,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => addr_en_c
);
Mmux_w_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"F5F07570F5F05500"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => w_ready_c
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd3_13,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd1_15,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_14,
I2 => present_state_FSM_FFd3_13,
I3 => '0',
I4 => '0',
I5 => '0',
O => NlwRenamedSignal_bvalid_c
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"2F0F27072F0F2200"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => present_state_FSM_FFd4_In1_21
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_In1_21,
I3 => '0',
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_aw_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"7535753575305500"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => S_AXI_WVALID,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => present_state_FSM_FFd2_14,
O => Mmux_aw_ready_c(0)
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => Mmux_aw_ready_c(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => aw_ready_c
);
END GENERATE gbeh_axi_lite_sm;
---------------------------------------------------------------------------
-- AXI FULL
---------------------------------------------------------------------------
gbeh_axi_full_sm: IF (C_AXI_TYPE = 1 ) GENERATE
signal w_ready_r_8 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSig_OI_bvalid_c : STD_LOGIC;
signal present_state_FSM_FFd1_16 : STD_LOGIC;
signal present_state_FSM_FFd4_17 : STD_LOGIC;
signal present_state_FSM_FFd3_18 : STD_LOGIC;
signal present_state_FSM_FFd2_19 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd2_In1_24 : STD_LOGIC;
signal present_state_FSM_FFd4_In1_25 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal N4 : STD_LOGIC;
begin
S_AXI_WREADY <= w_ready_r_8;
bvalid_c <= NlwRenamedSig_OI_bvalid_c;
S_AXI_BVALID <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_8
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_17
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_18
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_19
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_16
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000000005540"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd4_17,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd3_In
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"BF3FBB33AF0FAA00"
)
port map (
I0 => S_AXI_BREADY,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd1_16,
I4 => present_state_FSM_FFd4_17,
I5 => NlwRenamedSig_OI_bvalid_c,
O => aw_ready_c
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"AAAAAAAA20000000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_19,
I3 => S_AXI_WVALID,
I4 => w_last_c,
I5 => present_state_FSM_FFd4_17,
O => addr_en_c
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_19,
I2 => present_state_FSM_FFd3_18,
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_WR_EN
);
Mmux_incr_addr_c_0_1 : STATE_LOGIC
generic map(
INIT => X"0000000000002220"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => incr_addr_c
);
Mmux_aw_ready_c_0_11 : STATE_LOGIC
generic map(
INIT => X"0000000000008880"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => NlwRenamedSig_OI_bvalid_c
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"000000000000D5C0"
)
port map (
I0 => w_last_c,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd4_17,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd2_In1_24
);
present_state_FSM_FFd2_In2 : STATE_LOGIC
generic map(
INIT => X"FFFFAAAA08AAAAAA"
)
port map (
I0 => present_state_FSM_FFd2_19,
I1 => S_AXI_AWVALID,
I2 => bready_timeout_c,
I3 => w_last_c,
I4 => S_AXI_WVALID,
I5 => present_state_FSM_FFd2_In1_24,
O => present_state_FSM_FFd2_In
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"00C0004000C00000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => w_last_c,
I2 => S_AXI_WVALID,
I3 => bready_timeout_c,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => present_state_FSM_FFd4_In1_25
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88F8"
)
port map (
I0 => present_state_FSM_FFd1_16,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_17,
I3 => S_AXI_AWVALID,
I4 => present_state_FSM_FFd4_In1_25,
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_w_ready_c_0_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => w_last_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_w_ready_c_0_Q : STATE_LOGIC
generic map(
INIT => X"FABAFABAFAAAF000"
)
port map (
I0 => N2,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd4_17,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => w_ready_c
);
Mmux_aw_ready_c_0_11_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => bready_timeout_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => w_last_c,
I1 => N4,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => present_state_FSM_FFd1_16,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
END GENERATE gbeh_axi_full_sm;
end STRUCTURE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--AXI Behavioral Model entities
ENTITY blk_mem_axi_read_wrapper_beh is
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
port (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END blk_mem_axi_read_wrapper_beh;
architecture blk_mem_axi_read_wrapper_beh_arch of blk_mem_axi_read_wrapper_beh is
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_WRITE_WIDTH_A=8,0,
if_then_else((C_WRITE_WIDTH_A=16),1,
if_then_else((C_WRITE_WIDTH_A=32),2,
if_then_else((C_WRITE_WIDTH_A=64),3,
if_then_else((C_WRITE_WIDTH_A=128),4,
if_then_else((C_WRITE_WIDTH_A=256),5,0))))));
SIGNAL ar_id_r : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
SIGNAL addr_en_c : std_logic := '0';
SIGNAL rd_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL single_trans_c : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL mux_sel_c : std_logic := '0';
SIGNAL r_last_c : std_logic := '0';
SIGNAL r_last_int_c : std_logic := '0';
SIGNAL arlen_int_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL arlen_cntr : std_logic_vector(7 DOWNTO 0) := ONE;
SIGNAL arburst_int_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL arburst_int_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL araddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),C_AXI_ARADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL total_bytes : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
SIGNAL wrap_base_addr_r : integer := 0;
SIGNAL wrap_boundary_r : integer := 0;
SIGNAL arlen_int_c : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes_c : integer := 0;
SIGNAL wrap_base_addr_c : integer := 0;
SIGNAL wrap_boundary_c : integer := 0;
SIGNAL araddr_out : std_logic_vector(C_ADDRB_WIDTH-1 downto 0) := (OTHERS => '0');
COMPONENT read_netlist
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_INCR_ADDR : OUT std_logic := '0';
S_AXI_ADDR_EN : OUT std_logic := '0';
S_AXI_SINGLE_TRANS : OUT std_logic := '0';
S_AXI_MUX_SEL : OUT std_logic := '0';
S_AXI_R_LAST : OUT std_logic := '0';
S_AXI_R_LAST_INT : IN std_logic := '0';
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT read_netlist;
BEGIN
dec_alen_c <= incr_addr_c OR r_last_int_c;
axi_read_fsm : read_netlist
GENERIC MAP(
C_AXI_TYPE => 1,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
S_AXI_INCR_ADDR => incr_addr_c,
S_AXI_ADDR_EN => addr_en_c,
S_AXI_SINGLE_TRANS => single_trans_c,
S_AXI_MUX_SEL => mux_sel_c,
S_AXI_R_LAST => r_last_c,
S_AXI_R_LAST_INT => r_last_int_c,
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN => rd_en_c
);
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(arlen_int_r)+1);
wrap_base_addr_r <= (conv_integer(araddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary_r <= wrap_base_addr_r+total_bytes;
---- combinatorial from interface
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARSIZE,"000"));
arlen_int_c <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
total_bytes_c <= conv_integer(num_of_bytes_c)*(conv_integer(arlen_int_c)+1);
wrap_base_addr_c <= (conv_integer(S_AXI_ARADDR)/if_then_else(total_bytes_c=0,1,total_bytes_c))*(total_bytes_c);
wrap_boundary_c <= wrap_base_addr_c+total_bytes_c;
arburst_int_c <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARBURST,"01");
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
araddr_reg <= (OTHERS => '0');
arburst_int_r <= (OTHERS => '0');
num_of_bytes_r <= 0;
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (incr_addr_c = '1' AND addr_en_c = '1' AND single_trans_c = '0') THEN
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
IF (arburst_int_c = "10") THEN
IF(conv_integer(S_AXI_ARADDR) = (wrap_boundary_c-num_of_bytes_c)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_c,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (arburst_int_c = "01" OR arburst_int_c = "11") THEN
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (addr_en_c = '1') THEN
araddr_reg <= S_AXI_ARADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
ELSIF (incr_addr_c = '1') THEN
IF (arburst_int_r = "10") THEN
IF(conv_integer(araddr_reg) = (wrap_boundary_r-num_of_bytes_r)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_r,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
ELSIF (arburst_int_r = "01" OR arburst_int_r = "11") THEN
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
araddr_out <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),araddr_reg(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),araddr_reg);
--------------------------------------------------------------------------
-- Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
--------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF S_ARESETN = '1' THEN
arlen_cntr <= ONE;
arlen_int_r <= (OTHERS => '0');
ELSIF S_ACLK'event AND S_ACLK = '1' THEN
IF (addr_en_c = '1' AND dec_alen_c = '1' AND single_trans_c = '0') THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= S_AXI_ARLEN - ONE AFTER FLOP_DELAY;
ELSIF addr_en_c = '1' THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
ELSIF dec_alen_c = '1' THEN
arlen_cntr <= arlen_cntr - ONE AFTER FLOP_DELAY;
ELSE
arlen_cntr <= arlen_cntr AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
r_last_int_c <= '1' WHEN (arlen_cntr = "00000000" AND S_AXI_RREADY = '1') ELSE '0' ;
--------------------------------------------------------------------------
-- AXI FULL FSM
-- Mux Selection of ARADDR
-- ARADDR is driven out from the read fsm based on the mux_sel_c
-- Based on mux_sel either ARADDR is given out or the latched ARADDR is
-- given out to BRAM
--------------------------------------------------------------------------
P_araddr_mux: PROCESS (mux_sel_c,S_AXI_ARADDR,araddr_out)
BEGIN
IF (mux_sel_c = '0') THEN
S_AXI_ARADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARADDR(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),S_AXI_ARADDR);
ELSE
S_AXI_ARADDR_OUT <= araddr_out;
END IF;
END PROCESS P_araddr_mux;
--------------------------------------------------------------------------
-- Assign output signals - AXI FULL FSM
--------------------------------------------------------------------------
S_AXI_RD_EN <= rd_en_c;
grid: IF (C_HAS_AXI_ID = 1) GENERATE
P_rid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
S_AXI_RID <= (OTHERS => '0');
ar_id_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
IF (addr_en_c = '1' AND rd_en_c = '1') THEN
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
ELSIF (addr_en_c = '1' AND rd_en_c = '0') THEN
ar_id_r <= S_AXI_ARID;
ELSIF (rd_en_c = '1') THEN
S_AXI_RID <= ar_id_r;
END IF;
END IF;
END PROCESS P_rid_gen;
END GENERATE grid;
END blk_mem_axi_read_wrapper_beh_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity read_netlist is
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_R_LAST_INT : in STD_LOGIC := '0';
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_ARVALID : in STD_LOGIC := '0';
S_AXI_RREADY : in STD_LOGIC := '0';
S_AXI_INCR_ADDR : out STD_LOGIC;
S_AXI_ADDR_EN : out STD_LOGIC;
S_AXI_SINGLE_TRANS : out STD_LOGIC;
S_AXI_MUX_SEL : out STD_LOGIC;
S_AXI_R_LAST : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RLAST : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RD_EN : out STD_LOGIC;
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end read_netlist;
architecture STRUCTURE of read_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
signal present_state_FSM_FFd1_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_r_15 : STD_LOGIC;
signal gaxi_full_sm_ar_ready_r_16 : STD_LOGIC;
signal gaxi_full_sm_r_last_r_17 : STD_LOGIC;
signal NlwRenamedSig_OI_gaxi_full_sm_r_valid_r : STD_LOGIC;
signal gaxi_full_sm_r_valid_c : STD_LOGIC;
signal S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o : STD_LOGIC;
signal gaxi_full_sm_ar_ready_c : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_c : STD_LOGIC;
signal NlwRenamedSig_OI_S_AXI_R_LAST : STD_LOGIC;
signal S_AXI_ARLEN_7_GND_8_o_equal_1_o : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal Mmux_S_AXI_R_LAST13 : STD_LOGIC;
signal N01 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal Mmux_gaxi_full_sm_ar_ready_c11 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N8 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N13 : STD_LOGIC;
begin
S_AXI_R_LAST <= NlwRenamedSig_OI_S_AXI_R_LAST;
S_AXI_ARREADY <= gaxi_full_sm_ar_ready_r_16;
S_AXI_RLAST <= gaxi_full_sm_r_last_r_17;
S_AXI_RVALID <= NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
gaxi_full_sm_outstanding_read_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_outstanding_read_c,
Q => gaxi_full_sm_outstanding_read_r_15
);
gaxi_full_sm_r_valid_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => gaxi_full_sm_r_valid_c,
Q => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r
);
gaxi_full_sm_ar_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_ar_ready_c,
Q => gaxi_full_sm_ar_ready_r_16
);
gaxi_full_sm_r_last_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => NlwRenamedSig_OI_S_AXI_R_LAST,
Q => gaxi_full_sm_r_last_r_17
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_13
);
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 : STATE_LOGIC
generic map(
INIT => X"000000000000000B"
)
port map (
I0 => S_AXI_RREADY,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o
);
Mmux_S_AXI_SINGLE_TRANS11 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_SINGLE_TRANS
);
Mmux_S_AXI_ADDR_EN11 : STATE_LOGIC
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_ADDR_EN
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"ECEE2022EEEE2022"
)
port map (
I0 => S_AXI_ARVALID,
I1 => present_state_FSM_FFd1_13,
I2 => S_AXI_RREADY,
I3 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I4 => present_state_FSM_FFd2_14,
I5 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
O => present_state_FSM_FFd2_In
);
Mmux_S_AXI_R_LAST131 : STATE_LOGIC
generic map(
INIT => X"0000000044440444"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_RREADY,
I5 => '0',
O => Mmux_S_AXI_R_LAST13
);
Mmux_S_AXI_INCR_ADDR11 : STATE_LOGIC
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => S_AXI_R_LAST_INT,
I1 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => Mmux_S_AXI_R_LAST13,
O => S_AXI_INCR_ADDR
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000FE"
)
port map (
I0 => S_AXI_ARLEN(2),
I1 => S_AXI_ARLEN(1),
I2 => S_AXI_ARLEN(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => N01
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q : STATE_LOGIC
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => S_AXI_ARLEN(7),
I1 => S_AXI_ARLEN(6),
I2 => S_AXI_ARLEN(5),
I3 => S_AXI_ARLEN(4),
I4 => S_AXI_ARLEN(3),
I5 => N01,
O => S_AXI_ARLEN_7_GND_8_o_equal_1_o
);
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_gaxi_full_sm_outstanding_read_c1 : STATE_LOGIC
generic map(
INIT => X"0020000002200200"
)
port map (
I0 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd1_13,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => N2,
O => gaxi_full_sm_outstanding_read_c
);
Mmux_gaxi_full_sm_ar_ready_c12 : STATE_LOGIC
generic map(
INIT => X"0000000000004555"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => '0',
I5 => '0',
O => Mmux_gaxi_full_sm_ar_ready_c11
);
Mmux_S_AXI_R_LAST11_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000EF"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
Mmux_S_AXI_R_LAST11 : STATE_LOGIC
generic map(
INIT => X"FCAAFC0A00AA000A"
)
port map (
I0 => S_AXI_ARVALID,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => N4,
I5 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
O => gaxi_full_sm_r_valid_c
);
S_AXI_MUX_SEL1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAAAA08"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => '0',
O => S_AXI_MUX_SEL
);
Mmux_S_AXI_RD_EN11 : STATE_LOGIC
generic map(
INIT => X"F3F3F755A2A2A200"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => gaxi_full_sm_outstanding_read_r_15,
I4 => present_state_FSM_FFd2_14,
I5 => S_AXI_ARVALID,
O => S_AXI_RD_EN
);
present_state_FSM_FFd1_In3 : beh_muxf7
port map (
I0 => N8,
I1 => N9,
S => present_state_FSM_FFd1_13,
O => present_state_FSM_FFd1_In
);
present_state_FSM_FFd1_In3_F : STATE_LOGIC
generic map(
INIT => X"000000005410F4F0"
)
port map (
I0 => S_AXI_RREADY,
I1 => present_state_FSM_FFd2_14,
I2 => S_AXI_ARVALID,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => '0',
O => N8
);
present_state_FSM_FFd1_In3_G : STATE_LOGIC
generic map(
INIT => X"0000000072FF7272"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N9
);
Mmux_gaxi_full_sm_ar_ready_c14 : beh_muxf7
port map (
I0 => N10,
I1 => N11,
S => present_state_FSM_FFd1_13,
O => gaxi_full_sm_ar_ready_c
);
Mmux_gaxi_full_sm_ar_ready_c14_F : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88A8"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => Mmux_gaxi_full_sm_ar_ready_c11,
I5 => '0',
O => N10
);
Mmux_gaxi_full_sm_ar_ready_c14_G : STATE_LOGIC
generic map(
INIT => X"000000008D008D8D"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N11
);
Mmux_S_AXI_R_LAST1 : beh_muxf7
port map (
I0 => N12,
I1 => N13,
S => present_state_FSM_FFd1_13,
O => NlwRenamedSig_OI_S_AXI_R_LAST
);
Mmux_S_AXI_R_LAST1_F : STATE_LOGIC
generic map(
INIT => X"0000000088088888"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N12
);
Mmux_S_AXI_R_LAST1_G : STATE_LOGIC
generic map(
INIT => X"00000000E400E4E4"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => S_AXI_R_LAST_INT,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N13
);
end STRUCTURE;
-------------------------------------------------------------------------------
-- Output Register Stage Entity
--
-- This module builds the output register stages of the memory. This module is
-- instantiated in the main memory module (blk_mem_gen_v8_3_1) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_output_stage IS
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_output_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6" and "virtex6l".
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
-- C_HAS_RST : Determines the presence of the RST port
-- C_RSTRAM : Determines if special reset behavior is used
-- C_RST_PRIORITY : Determines the priority between CE and SR
-- C_INIT_VAL : Initialization value
-- C_HAS_EN : Determines the presence of the EN port
-- C_HAS_REGCE : Determines the presence of the REGCE port
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
-- of the RAM primitive
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- NUM_STAGES : Determines the number of output stages
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE output_stage_behavioral OF blk_mem_gen_v8_3_1_output_stage IS
--*******************************************************
-- Functions used in the output stage ARCHITECTURE
--*******************************************************
-- Calculate num_reg_stages
FUNCTION get_num_reg_stages(NUM_STAGES: INTEGER) RETURN INTEGER IS
VARIABLE num_reg_stages : INTEGER := 0;
BEGIN
IF (NUM_STAGES = 0) THEN
num_reg_stages := 0;
ELSE
num_reg_stages := NUM_STAGES - 1;
END IF;
RETURN num_reg_stages;
END get_num_reg_stages;
-- Check if the INTEGER is zero or non-zero
FUNCTION int_to_bit(input: INTEGER) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = 0) THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END int_to_bit;
-- Constants
CONSTANT HAS_EN : STD_LOGIC := int_to_bit(C_HAS_EN);
CONSTANT HAS_REGCE : STD_LOGIC := int_to_bit(C_HAS_REGCE);
CONSTANT HAS_RST : STD_LOGIC := int_to_bit(C_HAS_RST);
CONSTANT REG_STAGES : INTEGER := get_num_reg_stages(NUM_STAGES);
-- Pipeline array
TYPE reg_data_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
TYPE reg_ecc_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC;
TYPE reg_eccaddr_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
CONSTANT REG_INIT : reg_data_array := (OTHERS => init_val);
SIGNAL out_regs : reg_data_array := REG_INIT;
SIGNAL sbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL dbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL rdaddrecc_regs: reg_eccaddr_array := (OTHERS => (OTHERS => '0'));
-- Internal signals
SIGNAL en_i : STD_LOGIC;
SIGNAL regce_i : STD_LOGIC;
SIGNAL rst_i : STD_LOGIC;
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := init_val;
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL DIN : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL RDADDRECC_IN : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ;
SIGNAL SBITERR_IN : STD_LOGIC := '0';
SIGNAL DBITERR_IN : STD_LOGIC := '0';
BEGIN
--***********************************************************************
-- Assign internal signals. This effectively wires off optional inputs.
--***********************************************************************
-- Internal enable for output registers is tied to user EN or '1' depending
-- on parameters
en_i <= EN OR (NOT HAS_EN);
-- Internal register enable for output registers is tied to user REGCE, EN
-- or '1' depending on parameters
regce_i <= (HAS_REGCE AND REGCE)
OR ((NOT HAS_REGCE) AND en_i);
-- Internal SRR is tied to user RST or '0' depending on parameters
rst_i <= RST AND HAS_RST;
--***************************************************************************
-- NUM_STAGES = 0 (No output registers. RAM only)
--***************************************************************************
zero_stages: IF (NUM_STAGES = 0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE zero_stages;
NO_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 0) GENERATE
DIN <= DIN_I;
RDADDRECC_IN <= RDADDRECC_IN_I;
SBITERR_IN <= SBITERR_IN_I;
DBITERR_IN <= DBITERR_IN_I;
END GENERATE NO_ECC_PIPE_REG;
WITH_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(ECCPIPECE = '1') THEN
DIN <= DIN_I AFTER FLOP_DELAY;
RDADDRECC_IN <= RDADDRECC_IN_I AFTER FLOP_DELAY;
SBITERR_IN <= SBITERR_IN_I AFTER FLOP_DELAY;
DBITERR_IN <= DBITERR_IN_I AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS;
END GENERATE WITH_ECC_PIPE_REG;
--***************************************************************************
-- NUM_STAGES = 1
-- (Mem Output Reg only or Mux Output Reg only)
--***************************************************************************
-- Possible valid combinations:
-- Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
-- +-----------------------------------------+
-- | C_RSTRAM_* | Reset Behavior |
-- +----------------+------------------------+
-- | 0 | Normal Behavior |
-- +----------------+------------------------+
-- | 1 | Special Behavior |
-- +----------------+------------------------+
--
-- Normal = REGCE gates reset, as in the case of all Virtex families and all
-- spartan families with the exception of S3ADSP and S6.
-- Special = EN gates reset, as in the case of S3ADSP and S6.
one_stage_norm: IF (NUM_STAGES = 1 AND
(C_RSTRAM=0 OR (C_RSTRAM=1 AND (C_XDEVICEFAMILY/="spartan3adsp" AND C_XDEVICEFAMILY/="aspartan3adsp")) OR
C_HAS_MEM_OUTPUT_REGS=0 OR C_HAS_RST=0)) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i = '1' AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
END IF;--CLK
END PROCESS;
END GENERATE one_stage_norm;
-- Special Reset Behavior for S6 and S3ADSP
one_stage_splbhv: IF (NUM_STAGES=1 AND C_RSTRAM=1 AND (C_XDEVICEFAMILY ="spartan3adsp" OR C_XDEVICEFAMILY ="aspartan3adsp"))
GENERATE
DOUT <= dout_i;
SBITERR <= '0';
DBITERR <= '0';
RDADDRECC <= (OTHERS => '0');
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (rst_i='1' AND en_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
ELSIF (regce_i='1' AND rst_i/='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE one_stage_splbhv;
--****************************************************************************
-- NUM_STAGES > 1
-- Mem Output Reg + Mux Output Reg
-- or
-- Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
-- or
-- Mux Pipeline Stages (>0) + Mux Output Reg
--****************************************************************************
multi_stage: IF (NUM_STAGES > 1) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i='1'AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
IF (en_i='1') THEN
-- Shift the data through the output stages
FOR i IN 1 TO REG_STAGES-1 LOOP
out_regs(i) <= out_regs(i-1) AFTER FLOP_DELAY;
sbiterr_regs(i) <= sbiterr_regs(i-1) AFTER FLOP_DELAY;
dbiterr_regs(i) <= dbiterr_regs(i-1) AFTER FLOP_DELAY;
rdaddrecc_regs(i) <= rdaddrecc_regs(i-1) AFTER FLOP_DELAY;
END LOOP;
out_regs(0) <= DIN;
sbiterr_regs(0) <= SBITERR_IN;
dbiterr_regs(0) <= DBITERR_IN;
rdaddrecc_regs(0) <= RDADDRECC_IN;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE multi_stage;
END output_stage_behavioral;
-------------------------------------------------------------------------------
-- SoftECC Output Register Stage Entity
-- This module builds the softecc output register stages. This module is
-- instantiated in the memory module (blk_mem_gen_v8_3_1_mem_module) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ;
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- of the RAM primitive
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE softecc_output_reg_stage_behavioral OF blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
-- Internal signals
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
--***************************************************************************
-- NO OUTPUT STAGES
--***************************************************************************
no_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE no_output_stage;
--****************************************************************************
-- WITH OUTPUT STAGE
--****************************************************************************
has_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END PROCESS;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
END GENERATE has_output_stage;
END softecc_output_reg_stage_behavioral;
--******************************************************************************
-- Main Memory module
--
-- This module is the behavioral model which implements the RAM
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
ENTITY blk_mem_gen_v8_3_1_mem_module IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_mem_module;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE mem_module_behavioral OF blk_mem_gen_v8_3_1_mem_module IS
--****************************************
-- min/max constant functions
--****************************************
-- get_max
----------
function SLV_TO_INT(SLV: in std_logic_vector
) return integer is
variable int : integer;
begin
int := 0;
for i in SLV'high downto SLV'low loop
int := int * 2;
if SLV(i) = '1' then
int := int + 1;
end if;
end loop;
return int;
end;
FUNCTION get_max(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a > b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-- get_min
----------
FUNCTION get_min(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
--***************************************************************
-- convert write_mode from STRING type for use in case statement
--***************************************************************
FUNCTION write_mode_to_vector(mode: STRING) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF (mode = "NO_CHANGE") THEN
RETURN "10";
ELSIF (mode = "READ_FIRST") THEN
RETURN "01";
ELSE
RETURN "00"; -- WRITE_FIRST
END IF;
END FUNCTION;
--***************************************************************
-- convert hex STRING to STD_LOGIC_VECTOR
--***************************************************************
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
--***************************************************************
-- locally derived constants to determine memory shape
--***************************************************************
CONSTANT MIN_WIDTH_A : INTEGER := get_min(C_WRITE_WIDTH_A, C_READ_WIDTH_A);
CONSTANT MIN_WIDTH_B : INTEGER := get_min(C_WRITE_WIDTH_B,C_READ_WIDTH_B);
CONSTANT MIN_WIDTH : INTEGER := get_min(MIN_WIDTH_A, MIN_WIDTH_B);
CONSTANT MAX_DEPTH_A : INTEGER := get_max(C_WRITE_DEPTH_A, C_READ_DEPTH_A);
CONSTANT MAX_DEPTH_B : INTEGER := get_max(C_WRITE_DEPTH_B, C_READ_DEPTH_B);
CONSTANT MAX_DEPTH : INTEGER := get_max(MAX_DEPTH_A, MAX_DEPTH_B);
TYPE int_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF std_logic_vector(C_WRITE_WIDTH_A-1 DOWNTO 0);
TYPE mem_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC_VECTOR(MIN_WIDTH-1 DOWNTO 0);
TYPE ecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
TYPE softecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
--***************************************************************
-- memory initialization function
--***************************************************************
IMPURE FUNCTION init_memory(DEFAULT_DATA :
STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
write_width_a : INTEGER;
depth : INTEGER;
width : INTEGER)
RETURN mem_array IS
VARIABLE init_return : mem_array := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(write_width_a-1 DOWNTO 0);
VARIABLE int_mem_vector : int_array:= (OTHERS => (OTHERS => '0'));
VARIABLE file_buffer : LINE;
VARIABLE i : INTEGER := 0;
VARIABLE j : INTEGER;
VARIABLE k : INTEGER;
VARIABLE ignore_line : BOOLEAN := false;
VARIABLE good_data : BOOLEAN := false;
VARIABLE char_tmp : CHARACTER;
VARIABLE index : INTEGER;
variable init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable data : std_logic_vector(255 downto 0) := (others => '0');
variable inside_init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable k_slv : std_logic_vector(31 downto 0) := (others => '0');
variable i_slv : std_logic_vector(31 downto 0) := (others => '0');
VARIABLE disp_line : line := null;
variable open_status : file_open_status;
variable input_initf_tmp : mem_array ;
variable input_initf : mem_array := (others => (others => '0'));
file int_infile : text;
variable data_line, data_line_tmp, out_data_line : line;
variable slv_width : integer;
VARIABLE d_l : LINE;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
index := 0;
FOR i IN 0 TO depth-1 LOOP
FOR j IN 0 TO width-1 LOOP
init_return(i)(j) := DEFAULT_DATA(index);
index := (index + 1) MOD C_WRITE_WIDTH_A;
END LOOP;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, file_buffer);
read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO write_width_a-1 LOOP
IF (j MOD width = 0 AND j /= 0) THEN
i := i + 1;
END IF;
init_return(i)(j MOD width) := bit_to_sl(mem_vector(j));
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
--Display output message indicating that the behavioral model is done
--initializing
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator data initialization complete." SEVERITY NOTE;
if (C_USE_BRAM_BLOCK = 1) then
--Display output message indicating that the behavioral model is being
--initialized
-- Read in the .mem file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_INIT_FILE /= "NONE") then
file_open(open_status, int_infile, C_INIT_FILE, read_mode);
while not endfile(int_infile) loop
readline(int_infile, data_line);
while (data_line /= null and data_line'length > 0) loop
if (data_line(data_line'low to data_line'low + 1) = "//") then
deallocate(data_line);
elsif ((data_line(data_line'low to data_line'low + 1) = "/*") and (data_line(data_line'high-1 to data_line'high) = "*/")) then
deallocate(data_line);
elsif (data_line(data_line'low to data_line'low + 1) = "/*") then
deallocate(data_line);
ignore_line := true;
elsif (ignore_line = true and data_line(data_line'high-1 to data_line'high) = "*/") then
deallocate(data_line);
ignore_line := false;
elsif (ignore_line = false and data_line(data_line'low) = '@') then
read(data_line, char_tmp);
hread(data_line, init_addr_slv, good_data);
i := SLV_TO_INT(init_addr_slv);
elsif (ignore_line = false) then
hread(data_line, input_initf_tmp(i), good_data);
init_return(i)(write_width_a - 1 downto 0) := input_initf_tmp(i)(write_width_a - 1 downto 0);
if (good_data = true) then
i := i + 1;
end if;
else
deallocate(data_line);
end if;
end loop;
end loop;
file_close(int_infile);
END IF;
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- memory type constants
--***************************************************************
CONSTANT MEM_TYPE_SP_RAM : INTEGER := 0;
CONSTANT MEM_TYPE_SDP_RAM : INTEGER := 1;
CONSTANT MEM_TYPE_TDP_RAM : INTEGER := 2;
CONSTANT MEM_TYPE_SP_ROM : INTEGER := 3;
CONSTANT MEM_TYPE_DP_ROM : INTEGER := 4;
--***************************************************************
-- memory configuration constant functions
--***************************************************************
--get_single_port
-----------------
FUNCTION get_single_port(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_RAM OR mem_type=MEM_TYPE_SP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_single_port;
--get_is_rom
--------------
FUNCTION get_is_rom(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_ROM OR mem_type=MEM_TYPE_DP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_is_rom;
--get_has_a_write
------------------
FUNCTION get_has_a_write(IS_ROM : INTEGER) RETURN INTEGER IS
BEGIN
IF (IS_ROM=0) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_a_write;
--get_has_b_write
------------------
FUNCTION get_has_b_write(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_TDP_RAM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_write;
--get_has_a_read
------------------
FUNCTION get_has_a_read(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SDP_RAM) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_a_read;
--get_has_b_read
------------------
FUNCTION get_has_b_read(SINGLE_PORT : INTEGER) RETURN INTEGER IS
BEGIN
IF (SINGLE_PORT=1) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_b_read;
--get_has_b_port
------------------
FUNCTION get_has_b_port(HAS_B_READ : INTEGER;
HAS_B_WRITE : INTEGER)
RETURN INTEGER IS
BEGIN
IF (HAS_B_READ=1 OR HAS_B_WRITE=1) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_port;
--get_num_output_stages
-----------------------
FUNCTION get_num_output_stages(has_mem_output_regs : INTEGER;
has_mux_output_regs : INTEGER;
mux_pipeline_stages : INTEGER)
RETURN INTEGER IS
VARIABLE actual_mux_pipeline_stages : INTEGER;
BEGIN
-- Mux pipeline stages can be non-zero only when there is a mux
-- output register.
IF (has_mux_output_regs=1) THEN
actual_mux_pipeline_stages := mux_pipeline_stages;
ELSE
actual_mux_pipeline_stages := 0;
END IF;
RETURN has_mem_output_regs+actual_mux_pipeline_stages+has_mux_output_regs;
END get_num_output_stages;
--***************************************************************************
-- Component declaration of the VARIABLE depth output register stage
--***************************************************************************
COMPONENT blk_mem_gen_v8_3_1_output_stage
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
EN : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
ECCPIPECE : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_output_stage;
COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************************************
-- locally derived constants to assist memory access
--******************************************************
CONSTANT WRITE_WIDTH_RATIO_A : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_A : INTEGER := C_READ_WIDTH_A/MIN_WIDTH;
CONSTANT WRITE_WIDTH_RATIO_B : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_B : INTEGER := C_READ_WIDTH_B/MIN_WIDTH;
--******************************************************
-- To modify the LSBs of the 'wider' data to the actual
-- address value
--******************************************************
CONSTANT WRITE_ADDR_A_DIV : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH_A;
CONSTANT READ_ADDR_A_DIV : INTEGER := C_READ_WIDTH_A/MIN_WIDTH_A;
CONSTANT WRITE_ADDR_B_DIV : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH_B;
CONSTANT READ_ADDR_B_DIV : INTEGER := C_READ_WIDTH_B/MIN_WIDTH_B;
--******************************************************
-- FUNCTION : log2roundup
--******************************************************
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
--******************************************************
-- Other constants and signals
--******************************************************
CONSTANT COLL_DELAY : TIME := 100 ps;
-- default data vector
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_DEFAULT_DATA,
C_WRITE_WIDTH_A);
CONSTANT CHKBIT_WIDTH : INTEGER := if_then_else(C_WRITE_WIDTH_A>57,8,if_then_else(C_WRITE_WIDTH_A>26,7,if_then_else(C_WRITE_WIDTH_A>11,6,if_then_else(C_WRITE_WIDTH_A>4,5,if_then_else(C_WRITE_WIDTH_A<5,4,0)))));
-- the init memory SIGNAL
SIGNAL memory_i : mem_array;
SIGNAL doublebit_error_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0);
SIGNAL current_contents_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
-- write mode constants
CONSTANT WRITE_MODE_A : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_A);
CONSTANT WRITE_MODE_B : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_B);
CONSTANT WRITE_MODES : STD_LOGIC_VECTOR(3 DOWNTO 0) :=
WRITE_MODE_A & WRITE_MODE_B;
-- reset values
CONSTANT INITA_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITA_VAL,
C_READ_WIDTH_A);
CONSTANT INITB_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITB_VAL,
C_READ_WIDTH_B);
-- memory output 'latches'
SIGNAL memory_out_a : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0) :=
INITA_VAL;
SIGNAL memory_out_b : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) :=
INITB_VAL;
SIGNAL sbiterr_in : STD_LOGIC := '0';
SIGNAL sbiterr_sdp : STD_LOGIC := '0';
SIGNAL dbiterr_in : STD_LOGIC := '0';
SIGNAL dbiterr_sdp : STD_LOGIC := '0';
SIGNAL rdaddrecc_in : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_sdp : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL doutb_i : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i : STD_LOGIC := '0';
SIGNAL dbiterr_i : STD_LOGIC := '0';
-- memory configuration constants
-----------------------------------------------
CONSTANT SINGLE_PORT : INTEGER := get_single_port(C_MEM_TYPE);
CONSTANT IS_ROM : INTEGER := get_is_rom(C_MEM_TYPE);
CONSTANT HAS_A_WRITE : INTEGER := get_has_a_write(IS_ROM);
CONSTANT HAS_B_WRITE : INTEGER := get_has_b_write(C_MEM_TYPE);
CONSTANT HAS_A_READ : INTEGER := get_has_a_read(C_MEM_TYPE);
CONSTANT HAS_B_READ : INTEGER := get_has_b_read(SINGLE_PORT);
CONSTANT HAS_B_PORT : INTEGER := get_has_b_port(HAS_B_READ, HAS_B_WRITE);
CONSTANT NUM_OUTPUT_STAGES_A : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_A,
C_MUX_PIPELINE_STAGES);
CONSTANT NUM_OUTPUT_STAGES_B : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES);
CONSTANT WEA0 : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT WEB0 : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-----------------------------------------------------------------------------
-- DEBUG CONTROL
-- DEBUG=0 : Debug output OFF
-- DEBUG=1 : Some debug info printed
-----------------------------------------------------------------------------
CONSTANT DEBUG : INTEGER := 0;
-- internal signals
-----------------------------------------------
SIGNAL ena_i : STD_LOGIC;
SIGNAL enb_i : STD_LOGIC;
SIGNAL reseta_i : STD_LOGIC;
SIGNAL resetb_i : STD_LOGIC;
SIGNAL wea_i : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL web_i : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL rea_i : STD_LOGIC;
SIGNAL reb_i : STD_LOGIC;
SIGNAL message_complete : BOOLEAN := false;
SIGNAL rsta_outp_stage : STD_LOGIC := '0';
SIGNAL rstb_outp_stage : STD_LOGIC := '0';
--*********************************************************
--FUNCTION : Collision check
--*********************************************************
FUNCTION collision_check (addr_a :
STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
iswrite_a : BOOLEAN;
addr_b :
STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
iswrite_b : BOOLEAN)
RETURN BOOLEAN IS
VARIABLE c_aw_bw : INTEGER;
VARIABLE c_aw_br : INTEGER;
VARIABLE c_ar_bw : INTEGER;
VARIABLE write_addr_a_width : INTEGER;
VARIABLE read_addr_a_width : INTEGER;
VARIABLE write_addr_b_width : INTEGER;
VARIABLE read_addr_b_width : INTEGER;
BEGIN
c_aw_bw := 0;
c_aw_br := 0;
c_ar_bw := 0;
-- Determine the effective address widths FOR each of the 4 ports
write_addr_a_width := C_ADDRA_WIDTH-log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width := C_ADDRA_WIDTH-log2roundup(READ_ADDR_A_DIV);
write_addr_b_width := C_ADDRB_WIDTH-log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width := C_ADDRB_WIDTH-log2roundup(READ_ADDR_B_DIV);
--Look FOR a write-write collision. In order FOR a write-write
--collision to exist, both ports must have a write transaction.
IF (iswrite_a AND iswrite_b) THEN
IF (write_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_a and iswrite_b
--If the B port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_a) THEN
IF (write_addr_a_width > read_addr_b_width) THEN
--read_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_b_width
--Once both are scaled to read_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
END IF; --width
END IF; --iswrite_a
--If the A port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_b) THEN
IF (read_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
ELSE
--read_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_a_width
--Once both are scaled to read_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_b
RETURN (c_aw_bw=1 OR c_aw_br=1 OR c_ar_bw=1);
END FUNCTION collision_check;
BEGIN -- Architecture
-----------------------------------------------------------------------------
-- SOFTECC and ECC SBITERR/DBITERR Outputs
-- The ECC Behavior is modeled by the behavioral models only for Virtex-6.
-- The SOFTECC Behavior is modeled by the behavioral models for Spartan-6.
-- For Virtex-5, these outputs will be tied to 0.
-----------------------------------------------------------------------------
SBITERR <= sbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_sdp WHEN (((C_FAMILY="virtex7") AND C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
-----------------------------------------------
-- This effectively wires off optional inputs
-----------------------------------------------
ena_i <= ENA WHEN (C_HAS_ENA=1) ELSE '1';
enb_i <= ENB WHEN (C_HAS_ENB=1 AND HAS_B_PORT=1) ELSE '1';
-- We are doing an "AND" operation of WEA and ENA and passing to Enbale pin of BRAM when built-in ECC is enabled,
-- what this means is that the write operation happens only when both WEA and ENA are high.
wea_i <= WEA WHEN (HAS_A_WRITE=1 AND ena_i='1') ELSE WEA0;
-- wea_i <= (OTHERS => '1') WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=1 AND ENA = '1') ELSE -- Use_ENA_pin
-- WEA WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=0) ELSE -- Always_enabled
-- WEA WHEN (HAS_A_WRITE=1 AND ena_i='1' AND C_USE_ECC = 0) ELSE
-- WEA0;
web_i <= WEB WHEN (HAS_B_WRITE=1 AND enb_i='1') ELSE WEB0;
rea_i <= ena_i WHEN (HAS_A_READ=1) ELSE '0';
reb_i <= enb_i WHEN (HAS_B_READ=1) ELSE '0';
-- these signals reset the memory latches
-- For the special reset behaviors in some of the families, the C_RSTRAM
-- attribute of the corresponding port is used to indicate if the latch is
-- reset or not.
reseta_i <= RSTA WHEN
((C_HAS_RSTA=1 AND NUM_OUTPUT_STAGES_A=0) OR
(C_HAS_RSTA=1 AND C_RSTRAM_A=1))
ELSE '0';
resetb_i <= RSTB WHEN
((C_HAS_RSTB=1 AND NUM_OUTPUT_STAGES_B=0) OR
(C_HAS_RSTB=1 AND C_RSTRAM_B=1) )
ELSE '0';
--***************************************************************************
-- This is the main PROCESS which includes the memory VARIABLE and the read
-- and write procedures. It also schedules read and write operations
--***************************************************************************
PROCESS (CLKA, CLKB,rea_i,reb_i,reseta_i,resetb_i)
-- Initialize the init memory array
------------------------------------
VARIABLE memory : mem_array := init_memory(DEFAULT_DATA,
C_WRITE_WIDTH_A,
MAX_DEPTH,
MIN_WIDTH);
-- Initialize the mem memory array
------------------------------------
VARIABLE softecc_sbiterr_arr : softecc_err_array;
VARIABLE softecc_dbiterr_arr : softecc_err_array;
VARIABLE sbiterr_arr : ecc_err_array;
VARIABLE dbiterr_arr : ecc_err_array;
CONSTANT doublebit_lsb : STD_LOGIC_VECTOR (1 DOWNTO 0):="11";
CONSTANT doublebit_msb : STD_LOGIC_VECTOR (C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 DOWNTO 0):= (OTHERS => '0');
VARIABLE doublebit_error : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0) := doublebit_msb & doublebit_lsb ;
VARIABLE current_contents_var : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
--***********************************
-- procedures to access the memory
--***********************************
-- write_a
----------
PROCEDURE write_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
inj_sbiterr : IN STD_LOGIC;
inj_dbiterr : IN STD_LOGIC) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
VARIABLE message : LINE;
VARIABLE errbit_current_contents : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
-- Block Memory Generator non-cycle-accurate message
ASSERT (message_complete) REPORT "Block Memory Generator module is using a behavioral model FOR simulation which will not precisely model memory collision behavior."
SEVERITY NOTE;
message_complete <= true;
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_A_DIV);
IF (address_i >= C_WRITE_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range FOR A Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEA = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_A + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEA_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Insert double bit errors:
IF (C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
current_contents(0) := NOT(current_contents(0));
current_contents(1) := NOT(current_contents(1));
--current_contents(0) := NOT(current_contents(30));
--current_contents(1) := NOT(current_contents(62));
END IF;
END IF;
-- Insert double bit errors:
IF (C_USE_SOFTECC=1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 downto 2) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 downto 0);
doublebit_error(0) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1);
doublebit_error(1) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-2);
current_contents := current_contents XOR doublebit_error(C_WRITE_WIDTH_A-1 DOWNTO 0);
END IF;
END IF;
IF(DEBUG=1) THEN
current_contents_var := current_contents; --for debugging current
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_A + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
-- Store address at which error is injected:
IF ((C_FAMILY = "virtex7") AND C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
sbiterr_arr(address_i) := '1';
ELSE
sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
dbiterr_arr(address_i) := '1';
ELSE
dbiterr_arr(address_i) := '0';
END IF;
END IF;
-- Store address at which softecc error is injected:
IF (C_USE_SOFTECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
softecc_sbiterr_arr(address_i) := '1';
ELSE
softecc_sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
softecc_dbiterr_arr(address_i) := '1';
ELSE
softecc_dbiterr_arr(address_i) := '0';
END IF;
END IF;
END IF;
END PROCEDURE;
-- write_b
----------
PROCEDURE write_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_B_DIV);
IF (address_i >= C_WRITE_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEB = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_B + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEB_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_B + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
END IF;
END PROCEDURE;
-- read_a
----------
PROCEDURE read_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_A_DIV);
IF (address_i >= C_READ_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for A Read"
SEVERITY WARNING;
END IF;
memory_out_a <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_A-1 LOOP
memory_out_a(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_A + i) AFTER FLOP_DELAY;
END LOOP;
END IF;
END IF;
END PROCEDURE;
-- read_b
----------
PROCEDURE read_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_B_DIV);
IF (address_i >= C_READ_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Read"
SEVERITY WARNING;
END IF;
memory_out_b <= (OTHERS => 'X') AFTER FLOP_DELAY;
sbiterr_in <= 'X' AFTER FLOP_DELAY;
dbiterr_in <= 'X' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_B-1 LOOP
memory_out_b(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_B + i) AFTER FLOP_DELAY;
END LOOP;
--assert sbiterr and dbiterr signals
IF ((C_FAMILY="virtex7") AND C_USE_ECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
--assert softecc sbiterr and dbiterr signals
ELSIF (C_USE_SOFTECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (softecc_sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (softecc_dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
END IF;
END IF;
END IF;
END PROCEDURE;
-- reset_a
----------
PROCEDURE reset_a
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
-- reset_b
----------
PROCEDURE reset_b
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
BEGIN -- begin the main PROCESS
--***************************************************************************
-- These are the main blocks which schedule read and write operations
-- Note that the reset priority feature at the latch stage is only supported
-- for Spartan-6. For other families, the default priority at the latch stage
-- is "CE"
--***************************************************************************
-- Synchronous clocks: schedule port operations with respect to both
-- write operating modes
IF (C_COMMON_CLK=1) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODES IS
WHEN "0000" => -- write_first write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "0100" => -- read_first write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "0001" => -- write_first read_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0101" => --read_first read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0010" => -- write_first no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0110" => -- read_first no_change
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1000" => -- no_change write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "1001" => -- no_change read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1010" => -- no_change no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Synchronous clocks
-- Asynchronous clocks: port operation is independent
IF (C_COMMON_CLK=0) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODE_A IS
WHEN "00" => -- write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN "01" => -- read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "10" => -- no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
IF (CLKB='1' AND CLKB'EVENT) THEN
CASE WRITE_MODE_B IS
WHEN "00" => -- write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "01" => -- read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "10" => -- no_change
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Asynchronous clocks
-- Assign the memory VARIABLE to the user_visible memory_i SIGNAL
IF(DEBUG=1) THEN
memory_i <= memory;
doublebit_error_i <= doublebit_error;
current_contents_i <= current_contents_var;
END IF;
END PROCESS;
--********************************************************************
-- Instantiate the VARIABLE depth output stage
--********************************************************************
-- Port A
rsta_outp_stage <= RSTA and not sleep;
rstb_outp_stage <= RSTB and not sleep;
reg_a : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTA,
C_RSTRAM => C_RSTRAM_A,
C_RST_PRIORITY => C_RST_PRIORITY_A,
init_val => INITA_VAL,
C_HAS_EN => C_HAS_ENA,
C_HAS_REGCE => C_HAS_REGCEA,
C_DATA_WIDTH => C_READ_WIDTH_A,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_A,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_A,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKA,
RST => rsta_outp_stage, --RSTA,
EN => ENA,
REGCE => REGCEA,
DIN_I => memory_out_a,
DOUT => DOUTA,
SBITERR_IN_I => '0',
DBITERR_IN_I => '0',
SBITERR => OPEN,
DBITERR => OPEN,
RDADDRECC_IN_I => (OTHERS => '0'),
ECCPIPECE => '0',
RDADDRECC => OPEN
);
-- Port B
reg_b : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTB,
C_RSTRAM => C_RSTRAM_B,
C_RST_PRIORITY => C_RST_PRIORITY_B,
init_val => INITB_VAL,
C_HAS_EN => C_HAS_ENB,
C_HAS_REGCE => C_HAS_REGCEB,
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_B,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKB,
RST => rstb_outp_stage,--RSTB,
EN => ENB,
REGCE => REGCEB,
DIN_I => memory_out_b,
DOUT => doutb_i,
SBITERR_IN_I => sbiterr_in,
DBITERR_IN_I => dbiterr_in,
SBITERR => sbiterr_i,
DBITERR => dbiterr_i,
RDADDRECC_IN_I => rdaddrecc_in,
ECCPIPECE => ECCPIPECE,
RDADDRECC => rdaddrecc_i
);
--********************************************************************
-- Instantiate the input / Output Register stages
--********************************************************************
output_reg_stage: blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC MAP(
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP(
CLK => CLKB,
DIN => doutb_i,
DOUT => DOUTB,
SBITERR_IN => sbiterr_i,
DBITERR_IN => dbiterr_i,
SBITERR => sbiterr_sdp,
DBITERR => dbiterr_sdp,
RDADDRECC_IN => rdaddrecc_i,
RDADDRECC => rdaddrecc_sdp
);
--*********************************
-- Synchronous collision checks
--*********************************
sync_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=1) GENERATE
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
-- collision detect
VARIABLE is_collision : BOOLEAN;
VARIABLE message : LINE;
BEGIN
IF (CLKA='1' AND CLKA'EVENT) THEN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision := false;
END IF;
-- If the write port is in READ_FIRST mode, there is no collision
IF (C_WRITE_MODE_A="READ_FIRST" AND wea_i/=WEA0 AND web_i=WEB0) THEN
is_collision := false;
END IF;
IF (C_WRITE_MODE_B="READ_FIRST" AND web_i/=WEB0 AND wea_i=WEA0) THEN
is_collision := false;
END IF;
-- Only flag if one of the accesses is a write
IF (is_collision AND (wea_i/=WEA0 OR web_i/=WEB0)) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END IF;
END PROCESS;
END GENERATE;
--*********************************
-- Asynchronous collision checks
--*********************************
async_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=0) GENERATE
SIGNAL addra_delay : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL wea_delay : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL ena_delay : STD_LOGIC;
SIGNAL addrb_delay : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
SIGNAL web_delay : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL enb_delay : STD_LOGIC;
BEGIN
-- Delay A and B addresses in order to mimic setup/hold times
PROCESS (ADDRA, wea_i, ena_i, ADDRB, web_i, enb_i)
BEGIN
addra_delay <= ADDRA AFTER COLL_DELAY;
wea_delay <= wea_i AFTER COLL_DELAY;
ena_delay <= ena_i AFTER COLL_DELAY;
addrb_delay <= ADDRB AFTER COLL_DELAY;
web_delay <= web_i AFTER COLL_DELAY;
enb_delay <= enb_i AFTER COLL_DELAY;
END PROCESS;
-- Do the checks w/rt A
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_a : BOOLEAN;
VARIABLE is_collision_delay_a : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_a := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_a := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_delay_a := collision_check(ADDRA,
wea_i/=WEA0,
addrb_delay,
web_delay/=WEB0);
ELSE
is_collision_delay_a := false;
END IF;
-- Only flag if B access is a write
IF (is_collision_a AND web_i/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_a AND web_delay/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, addrb_delay);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
-- Do the checks w/rt B
PROCESS (CLKB)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_b : BOOLEAN;
VARIABLE is_collision_delay_b : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA) /= 'X') THEN
is_collision_b := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_b := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(addra_delay) /= 'X') THEN
is_collision_delay_b := collision_check(addra_delay,
wea_delay/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_delay_b := false;
END IF;
-- Only flag if A access is a write
-- Modified condition checking (is_collision_b AND WEA0_i=/WEA0) to fix CR526228
IF (is_collision_b AND wea_i/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_b AND wea_delay/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, addra_delay);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
END GENERATE;
END mem_module_behavioral;
--******************************************************************************
-- Top module that wraps SoftECC Input register stage and the main memory module
--
-- This module is the top-level of behavioral model
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1 IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_CTRL_ECC_ALGO : STRING := "NONE";
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
--C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_SLEEP_PIN : INTEGER := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
PORT (
clka : IN STD_LOGIC := '0';
rsta : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '1';
regcea : IN STD_LOGIC := '1';
wea : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addra : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
dina : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
douta : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
clkb : IN STD_LOGIC := '0';
rstb : IN STD_LOGIC := '0';
enb : IN STD_LOGIC := '1';
regceb : IN STD_LOGIC := '1';
web : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addrb : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
dinb : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
doutb : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
injectsbiterr : IN STD_LOGIC := '0';
injectdbiterr : IN STD_LOGIC := '0';
sbiterr : OUT STD_LOGIC := '0';
dbiterr : OUT STD_LOGIC := '0';
rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : in std_logic := '0';
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic := '0';
rstb_busy : out std_logic := '0';
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
s_aclk : IN STD_LOGIC := '0';
s_aresetn : IN STD_LOGIC := '0';
-- axi full/lite slave Write (write side)
s_axi_awid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid : IN STD_LOGIC := '0';
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast : IN STD_LOGIC := '0';
s_axi_wvalid : IN STD_LOGIC := '0';
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC := '0';
-- axi full/lite slave Read (Write side)
s_axi_arid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid : IN STD_LOGIC := '0';
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_rdata : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC := '0';
-- axi full/lite sideband Signals
s_axi_injectsbiterr : IN STD_LOGIC := '0';
s_axi_injectdbiterr : IN STD_LOGIC := '0';
s_axi_sbiterr : OUT STD_LOGIC := '0';
s_axi_dbiterr : OUT STD_LOGIC := '0';
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END blk_mem_gen_v8_3_1;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE behavioral OF blk_mem_gen_v8_3_1 IS
COMPONENT blk_mem_gen_v8_3_1_mem_module
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_mem_module;
COMPONENT blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_axi_regs_fwd_v8_3;
COMPONENT blk_mem_axi_read_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT blk_mem_axi_read_wrapper_beh;
COMPONENT blk_mem_axi_write_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END COMPONENT blk_mem_axi_write_wrapper_beh;
CONSTANT FLOP_DELAY : TIME := 100 ps;
SIGNAL rsta_in : STD_LOGIC := '1';
SIGNAL ena_in : STD_LOGIC := '1';
SIGNAL regcea_in : STD_LOGIC := '1';
SIGNAL wea_in : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL addra_in : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL dina_in : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL injectsbiterr_in : STD_LOGIC := '0';
SIGNAL injectdbiterr_in : STD_LOGIC := '0';
-----------------------------------------------------------------------------
-- FUNCTION: toLowerCaseChar
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
-----------------------------------------------------------------------------
FUNCTION toLowerCaseChar(
char : character )
RETURN character IS
BEGIN
-- If char is not an upper case letter then return char
IF char<'A' OR char>'Z' THEN
RETURN char;
END IF;
-- Otherwise map char to its corresponding lower case character and
-- RETURN that
CASE char IS
WHEN 'A' => RETURN 'a';
WHEN 'B' => RETURN 'b';
WHEN 'C' => RETURN 'c';
WHEN 'D' => RETURN 'd';
WHEN 'E' => RETURN 'e';
WHEN 'F' => RETURN 'f';
WHEN 'G' => RETURN 'g';
WHEN 'H' => RETURN 'h';
WHEN 'I' => RETURN 'i';
WHEN 'J' => RETURN 'j';
WHEN 'K' => RETURN 'k';
WHEN 'L' => RETURN 'l';
WHEN 'M' => RETURN 'm';
WHEN 'N' => RETURN 'n';
WHEN 'O' => RETURN 'o';
WHEN 'P' => RETURN 'p';
WHEN 'Q' => RETURN 'q';
WHEN 'R' => RETURN 'r';
WHEN 'S' => RETURN 's';
WHEN 'T' => RETURN 't';
WHEN 'U' => RETURN 'u';
WHEN 'V' => RETURN 'v';
WHEN 'W' => RETURN 'w';
WHEN 'X' => RETURN 'x';
WHEN 'Y' => RETURN 'y';
WHEN 'Z' => RETURN 'z';
WHEN OTHERS => RETURN char;
END CASE;
END toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
FUNCTION equalIgnoreCase(
str1 : STRING;
str2 : STRING )
RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str2'left TO str1'right LOOP
IF NOT (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equalIgnoreCase;
-----------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
----------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
----------------------------------------------------------------------------
-- FUNCTION : log2roundup
----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
CONSTANT lower_limit : INTEGER := 1;
CONSTANT upper_limit : INTEGER := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
-----------------------------------------------------------------------------
-- FUNCTION : divroundup
-- Returns the ceiling value of the division
-- Data_value - the quantity to be divided, dividend
-- Divisor - the value to divide the data_value by
-----------------------------------------------------------------------------
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
SIGNAL s_axi_awaddr_out_c : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_araddr_out_c : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_wr_en_c : STD_LOGIC := '0';
SIGNAL s_axi_rd_en_c : STD_LOGIC := '0';
SIGNAL s_aresetn_a_c : STD_LOGIC := '0';
--**************************************************************************
-- AXI PARAMETERS
CONSTANT AXI_FULL_MEMORY_SLAVE : integer := if_then_else((C_AXI_SLAVE_TYPE = 0 AND C_AXI_TYPE = 1),1,0);
CONSTANT C_AXI_ADDR_WIDTH_MSB : integer := C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
CONSTANT C_AXI_ADDR_WIDTH : integer := C_AXI_ADDR_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT LOWER_BOUND_VAL : integer := if_then_else((log2roundup(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT C_AXI_ADDR_WIDTH_LSB : integer := if_then_else((AXI_FULL_MEMORY_SLAVE = 1),0,LOWER_BOUND_VAL);
CONSTANT C_AXI_OS_WR : integer := 2;
-- SAFETY LOGIC related Signals
SIGNAL RSTA_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_A : STD_LOGIC := '0';
SIGNAL RSTB_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_B : STD_LOGIC := '0';
SIGNAL ENA_dly : STD_LOGIC := '0';
SIGNAL ENA_dly_D : STD_LOGIC := '0';
SIGNAL ENB_dly : STD_LOGIC := '0';
SIGNAL ENB_dly_D : STD_LOGIC := '0';
SIGNAL RSTA_I_SAFE : STD_LOGIC := '0';
SIGNAL RSTB_I_SAFE : STD_LOGIC := '0';
SIGNAL ENA_I_SAFE : STD_LOGIC := '0';
SIGNAL ENB_I_SAFE : STD_LOGIC := '0';
SIGNAL ram_rstram_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstram_b_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_b_busy : STD_LOGIC := '0';
SIGNAL ENA_dly_reg : STD_LOGIC := '0';
SIGNAL ENB_dly_reg : STD_LOGIC := '0';
SIGNAL ENA_dly_reg_D : STD_LOGIC := '0';
SIGNAL ENB_dly_reg_D : STD_LOGIC := '0';
--**************************************************************************
BEGIN -- Architecture
--*************************************************************************
-- NO INPUT STAGE
--*************************************************************************
no_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=0) GENERATE
rsta_in <= RSTA;
ena_in <= ENA;
regcea_in <= REGCEA;
wea_in <= WEA;
addra_in <= ADDRA;
dina_in <= DINA;
injectsbiterr_in <= INJECTSBITERR;
injectdbiterr_in <= INJECTDBITERR;
END GENERATE no_input_stage;
--**************************************************************************
-- WITH INPUT STAGE
--**************************************************************************
has_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=1) GENERATE
PROCESS (CLKA)
BEGIN
IF (CLKA'EVENT AND CLKA = '1') THEN
rsta_in <= RSTA AFTER FLOP_DELAY;
ena_in <= ENA AFTER FLOP_DELAY;
regcea_in <= REGCEA AFTER FLOP_DELAY;
wea_in <= WEA AFTER FLOP_DELAY;
addra_in <= ADDRA AFTER FLOP_DELAY;
dina_in <= DINA AFTER FLOP_DELAY;
injectsbiterr_in <= INJECTSBITERR AFTER FLOP_DELAY;
injectdbiterr_in <= INJECTDBITERR AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE has_input_stage;
--**************************************************************************
-- NO SAFETY LOGIC
--**************************************************************************
NO_SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 0) GENERATE
ENA_I_SAFE <= ena_in;
ENB_I_SAFE <= ENB;
RSTA_I_SAFE <= rsta_in;
RSTB_I_SAFE <= RSTB;
END GENERATE NO_SAFETY_CKT_GEN;
--**************************************************************************
-- SAFETY LOGIC
--**************************************************************************
SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 1) GENERATE
-- RESET SAFETY LOGIC Generation
-- POR Generation
------------------------------------------------------------------------------
-- Power-ON Reset Generation
------------------------------------------------------------------------------
RST_SHFT_LOGIC_A : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
RSTA_SHFT_REG(4 DOWNTO 0) <= RSTA_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_A;
POR_RSTA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
POR_A <= RSTA_SHFT_REG(4) xor RSTA_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTA_GEN;
RST_SHFT_LOGIC_B : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
RSTB_SHFT_REG(4 DOWNTO 0) <= RSTB_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_B;
POR_RSTB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
POR_B <= RSTB_SHFT_REG(4) xor RSTB_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTB_GEN;
-----------------------------------------------------------------------------
-- Fix for the AR42571
-----------------------------------------------------------------------------
-- Reset Generation
-----------------------------------------------------------------------------
RSTA_I_SAFE <= rsta_in OR POR_A;
SPRAM_RST: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_I_SAFE <= '0';
END GENERATE SPRAM_RST;
nSPRAM_RST: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_I_SAFE <= RSTB OR POR_B;
END GENERATE nSPRAM_RST;
-----------------------------------------------------------------------------
-- RSTA/B_BUSY Generation
-----------------------------------------------------------------------------
RSTA_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
ram_rstram_a_busy <= rsta_in OR ENA_dly OR ENA_dly_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstram_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_NO_REG;
RSTA_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
ram_rstreg_a_busy <= rsta_in OR ENA_dly OR ENA_dly_reg_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstreg_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_WITH_REG;
SPRAM_RST_BUSY: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_BUSY <= '0';
END GENERATE SPRAM_RST_BUSY;
nSPRAM_RST_BUSY: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
ram_rstram_b_busy <= RSTB OR ENB_dly OR ENB_dly_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstram_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_NO_REG;
RSTB_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
ram_rstreg_b_busy <= RSTB OR ENB_dly OR ENB_dly_reg_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstreg_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_WITH_REG;
END GENERATE nSPRAM_RST_BUSY;
-----------------------------------------------------------------------------
-- ENA/ENB Generation
-----------------------------------------------------------------------------
ENA_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly <= rsta_in AFTER FLOP_DELAY;
ENA_dly_D <= ENA_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_D OR ena_in;
END GENERATE ENA_NO_REG;
ENA_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly_reg <= rsta_in AFTER FLOP_DELAY;
ENA_dly_reg_D <= ENA_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_reg_D OR ena_in;
END GENERATE ENA_WITH_REG;
SPRAM_ENB: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
ENB_I_SAFE <= '0';
END GENERATE SPRAM_ENB;
nSPRAM_ENB: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
ENB_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly <= RSTB AFTER FLOP_DELAY;
ENB_dly_D <= ENB_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_D OR ENB;
END GENERATE ENB_NO_REG;
ENB_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly_reg <= RSTB AFTER FLOP_DELAY;
ENB_dly_reg_D <= ENB_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_reg_D OR ENB;
END GENERATE ENB_WITH_REG;
END GENERATE nSPRAM_ENB;
END GENERATE SAFETY_CKT_GEN;
--**************************************************************************
-- NATIVE MEMORY MODULE INSTANCE
--**************************************************************************
native_mem_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 0) GENERATE
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,--rsta_in,
ENA => ENA_I_SAFE,--ena_in,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in,
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => RDADDRECC
);
END GENERATE native_mem_module;
--**************************************************************************
-- NATIVE MEMORY MAPPED MODULE INSTANCE
--**************************************************************************
native_mem_map_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 1) GENERATE
--**************************************************************************
-- NATIVE MEMORY MAPPED PARAMETERS
CONSTANT C_ADDRA_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_A);
CONSTANT C_ADDRB_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_B);
CONSTANT C_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
CONSTANT C_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
CONSTANT C_MEM_MAP_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_MSB;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT MEM_MAP_LOWER_BOUND_VAL_A : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT MEM_MAP_LOWER_BOUND_VAL_B : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_B,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_B,8)));
CONSTANT C_MEM_MAP_ADDRA_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_A;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_B;
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH_ACTUAL-1 DOWNTO 0) := (OTHERS => '0');
--**************************************************************************
BEGIN
RDADDRECC(C_ADDRB_WIDTH-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_MSB) <= (OTHERS => '0');
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB) <= rdaddrecc_i;
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_LSB-1 DOWNTO 0) <= (OTHERS => '0');
mem_map_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH_ACTUAL,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH_ACTUAL,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,
ENA => ENA_I_SAFE,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in(C_MEM_MAP_ADDRA_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRA_WIDTH_LSB),
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB),
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => rdaddrecc_i
);
END GENERATE native_mem_map_module;
--****************************************************************************
-- AXI MEMORY MODULE INSTANCE
--****************************************************************************
axi_mem_module: IF (C_INTERFACE_TYPE = 1) GENERATE
SIGNAL s_axi_rid_c : STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rdata_c : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rresp_c : STD_LOGIC_VECTOR(2-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rlast_c : STD_LOGIC := '0';
SIGNAL s_axi_rvalid_c : STD_LOGIC := '0';
SIGNAL s_axi_rready_c : STD_LOGIC := '0';
SIGNAL regceb_c : STD_LOGIC := '0';
BEGIN
s_aresetn_a_c <= NOT S_ARESETN;
S_AXI_BRESP <= (OTHERS => '0');
s_axi_rresp_c <= (OTHERS => '0');
no_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 0 AND C_HAS_MUX_OUTPUT_REGS_B = 0 ) GENERATE
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RLAST <= s_axi_rlast_c;
S_AXI_RVALID <= s_axi_rvalid_c;
S_AXI_RID <= s_axi_rid_c;
S_AXI_RRESP <= s_axi_rresp_c;
s_axi_rready_c <= S_AXI_RREADY;
END GENERATE no_regs;
has_regs_fwd: IF (C_HAS_MUX_OUTPUT_REGS_B = 1 OR C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
CONSTANT C_AXI_PAYLOAD : INTEGER := if_then_else((C_HAS_MUX_OUTPUT_REGS_B = 1),C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3,C_AXI_ID_WIDTH+3);
SIGNAL s_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
has_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
regceb_c <= s_axi_rvalid_c AND s_axi_rready_c;
END GENERATE has_regceb;
no_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 0) GENERATE
regceb_c <= REGCEB;
END GENERATE no_regceb;
only_core_op_regs: IF (C_HAS_MUX_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rdata_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RDATA <= m_axi_payload_c(C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_core_op_regs;
only_emb_op_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_emb_op_regs;
axi_regs_inst : blk_mem_axi_regs_fwd_v8_3
GENERIC MAP(
C_DATA_WIDTH => C_AXI_PAYLOAD
)
PORT MAP (
ACLK => S_ACLK,
ARESET => s_aresetn_a_c,
S_VALID => s_axi_rvalid_c,
S_READY => s_axi_rready_c,
S_PAYLOAD_DATA => s_axi_payload_c,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY,
M_PAYLOAD_DATA => m_axi_payload_c
);
END GENERATE has_regs_fwd;
axi_wr_fsm : blk_mem_axi_write_wrapper_beh
GENERIC MAP(
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_AXI_AWADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_WDATA_WIDTH => C_WRITE_WIDTH_A,
C_AXI_OS_WR => C_AXI_OS_WR
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Slave Write Interface
S_AXI_AWADDR => S_AXI_AWADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_AWLEN => S_AXI_AWLEN,
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BID => S_AXI_BID,
-- Signals for BRAM interface
S_AXI_AWADDR_OUT =>s_axi_awaddr_out_c,
S_AXI_WR_EN =>s_axi_wr_en_c
);
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => 1, -- For AXI, Read Enable is always C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => 1, -- For AXI C_USE_BYTE_WEA is always 1,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => 1, -- For AXI, Read Enable is always C_HAS_ENB,
C_HAS_REGCEB => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_BYTE_WEB => 1, -- For AXI C_USE_BYTE_WEB is always 1,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => 0, --For AXI, Primitive Registers A is not supported C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => 0,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
--Port A:
CLKA => S_AClk,
RSTA => s_aresetn_a_c,
ENA => s_axi_wr_en_c,
REGCEA => regcea_in,
WEA => S_AXI_WSTRB,
ADDRA => s_axi_awaddr_out_c,
DINA => S_AXI_WDATA,
DOUTA => DOUTA,
--Port B:
CLKB => S_AClk,
RSTB => s_aresetn_a_c,
ENB => s_axi_rd_en_c,
REGCEB => regceb_c,
WEB => (OTHERS => '0'),
ADDRB => s_axi_araddr_out_c,
DINB => DINB,
DOUTB => s_axi_rdata_c,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => '0',
SLEEP => '0',
RDADDRECC => RDADDRECC
);
axi_rd_sm : blk_mem_axi_read_wrapper_beh
GENERIC MAP (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_PIPELINE_STAGES => 1,
C_AXI_ARADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_AClk,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Read Side
S_AXI_ARADDR => S_AXI_ARADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARSIZE => S_AXI_ARSIZE,
S_AXI_ARBURST => S_AXI_ARBURST,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => s_axi_rlast_c,
S_AXI_RVALID => s_axi_rvalid_c,
S_AXI_RREADY => s_axi_rready_c,
S_AXI_ARID => S_AXI_ARID,
S_AXI_RID => s_axi_rid_c,
-- AXI Full/Lite Read FSM Outputs
S_AXI_ARADDR_OUT => s_axi_araddr_out_c,
S_AXI_RD_EN => s_axi_rd_en_c
);
END GENERATE axi_mem_module;
END behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_clr is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_clr;
architecture beh_ff_clr_arch of beh_ff_clr is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(CLR, C)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_clr_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_ce is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_ce;
architecture beh_ff_ce_arch of beh_ff_ce is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, CLR)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
if (CE = '1') then
q_o <= D after 100 ps;
end if;
end if;
end process;
end beh_ff_ce_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_pre is
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end beh_ff_pre;
architecture beh_ff_pre_arch of beh_ff_pre is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, PRE)
begin
if (PRE = '1') then
q_o <= '1';
elsif (C' event and C = '1') then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_pre_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_muxf7 is
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end beh_muxf7;
architecture beh_muxf7_arch of beh_muxf7 is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
else
O <= I1;
end if;
end process;
end beh_muxf7_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity STATE_LOGIC is
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic := '0';
I0 : in std_logic := '0';
I1 : in std_logic := '0';
I2 : in std_logic := '0';
I3 : in std_logic := '0';
I4 : in std_logic := '0';
I5 : in std_logic := '0'
);
end STATE_LOGIC;
architecture STATE_LOGIC_arch of STATE_LOGIC is
constant INIT_reg : std_logic_vector(63 downto 0) := INIT;
begin
LUT_beh:process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
begin
I_reg := I5 & I4 & I3 & I2 & I1 & I0;
O <= INIT_reg(conv_integer(I_reg));
end process;
end STATE_LOGIC_arch;
|
-------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v8_3_1.vhd
--
-- Description:
-- This file is the VHDL behvarial model for the
-- Block Memory Generator Core.
--
-------------------------------------------------------------------------------
-- Author: Xilinx
--
-- History: January 11, 2006: Initial revision
-- June 11, 2007 : Added independent register stages for
-- Port A and Port B (IP1_Jm/v2.5)
-- August 28, 2007 : Added mux pipeline stages feature (IP2_Jm/v2.6)
-- April 07, 2009 : Added support for Spartan-6 and Virtex-6
-- features, including the following:
-- (i) error injection, detection and/or correction
-- (ii) reset priority
-- (iii) special reset behavior
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
ENTITY blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END ENTITY blk_mem_axi_regs_fwd_v8_3;
ARCHITECTURE axi_regs_fwd_arch OF blk_mem_axi_regs_fwd_v8_3 IS
SIGNAL STORAGE_DATA : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_READY_I : STD_LOGIC := '0';
SIGNAL M_VALID_I : STD_LOGIC := '0';
SIGNAL ARESET_D : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');-- Reset delay register
BEGIN
--assign local signal to its output signal
S_READY <= S_READY_I;
M_VALID <= M_VALID_I;
PROCESS(ACLK)
BEGIN
IF(ACLK'event AND ACLK = '1') THEN
ARESET_D <= ARESET_D(0) & ARESET;
END IF;
END PROCESS;
--Save payload data whenever we have a transaction on the slave side
PROCESS(ACLK, ARESET)
BEGIN
IF (ARESET = '1') THEN
STORAGE_DATA <= (OTHERS => '0');
ELSIF(ACLK'event AND ACLK = '1') THEN
IF(S_VALID = '1' AND S_READY_I = '1') THEN
STORAGE_DATA <= S_PAYLOAD_DATA;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= STORAGE_DATA;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
PROCESS(ACLK,ARESET)
BEGIN
IF (ARESET_D /= "00") THEN
M_VALID_I <= '0';
ELSIF(ACLK'event AND ACLK = '1') THEN
IF (S_VALID = '1') THEN
--Always set M_VALID_I when slave side is valid
M_VALID_I <= '1';
ELSIF (M_READY = '1') THEN
--Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= '0';
END IF;
END IF;
END PROCESS;
--Slave Ready is either when Master side drives M_READY or we have space in our storage data
S_READY_I <= (M_READY OR (NOT M_VALID_I)) AND NOT(OR_REDUCE(ARESET_D));
END axi_regs_fwd_arch;
-------------------------------------------------------------------------------
-- Description:
-- This is the behavioral model of write_wrapper for the
-- Block Memory Generator Core.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_axi_write_wrapper_beh IS
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END blk_mem_axi_write_wrapper_beh;
ARCHITECTURE axi_write_wrap_arch OF blk_mem_axi_write_wrapper_beh IS
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_AXI_WDATA_WIDTH=8,0,
if_then_else((C_AXI_WDATA_WIDTH=16),1,
if_then_else((C_AXI_WDATA_WIDTH=32),2,
if_then_else((C_AXI_WDATA_WIDTH=64),3,
if_then_else((C_AXI_WDATA_WIDTH=128),4,
if_then_else((C_AXI_WDATA_WIDTH=256),5,0))))));
SIGNAL bvalid_c : std_logic := '0';
SIGNAL bready_timeout_c : std_logic := '0';
SIGNAL bvalid_rd_cnt_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_r : std_logic := '0';
SIGNAL bvalid_count_r : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL awaddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
C_AXI_AWADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL bvalid_wr_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_rd_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_last_c : std_logic := '0';
SIGNAL addr_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL aw_ready_r : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL awlen_cntr_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1');
SIGNAL awlen_int : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL awburst_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes : integer := 0;
SIGNAL wrap_boundary : integer := 0;
SIGNAL wrap_base_addr : integer := 0;
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
-- Array to store BIDs
TYPE id_array IS ARRAY (3 DOWNTO 0) OF std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
SIGNAL axi_bid_array : id_array := (others => (others => '0'));
COMPONENT write_netlist
GENERIC(
C_AXI_TYPE : integer
);
PORT(
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
S_AXI_AWVALID : IN std_logic;
aw_ready_r : OUT std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN std_logic;
S_AXI_WR_EN : OUT std_logic;
w_last_c : IN std_logic;
bready_timeout_c : IN std_logic;
addr_en_c : OUT std_logic;
incr_addr_c : OUT std_logic;
bvalid_c : OUT std_logic
);
END COMPONENT write_netlist;
BEGIN
---------------------------------------
--AXI WRITE FSM COMPONENT INSTANTIATION
---------------------------------------
axi_wr_fsm : write_netlist
GENERIC MAP (
C_AXI_TYPE => C_AXI_TYPE
)
PORT MAP (
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
S_AXI_AWVALID => S_AXI_AWVALID,
aw_ready_r => aw_ready_r,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BVALID => OPEN,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_WR_EN => S_AXI_WR_EN,
w_last_c => w_last_c,
bready_timeout_c => bready_timeout_c,
addr_en_c => addr_en_c,
incr_addr_c => incr_addr_c,
bvalid_c => bvalid_c
);
--Wrap Address boundary calculation
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWSIZE,"000"));
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(awlen_int)+1);
wrap_base_addr <= (conv_integer(awaddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary <= wrap_base_addr+total_bytes;
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awaddr_reg <= (OTHERS => '0');
num_of_bytes_r <= 0;
awburst_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awaddr_reg <= S_AXI_AWADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWBURST,"01");
ELSIF (incr_addr_c = '1') THEN
IF (awburst_int = "10") THEN
IF(conv_integer(awaddr_reg) = (wrap_boundary-num_of_bytes_r)) THEN
awaddr_reg <= conv_std_logic_vector(wrap_base_addr,C_AXI_AWADDR_WIDTH);
ELSE
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
ELSIF (awburst_int = "01" OR awburst_int = "11") THEN
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
S_AXI_AWADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
awaddr_reg(C_AXI_AWADDR_WIDTH-1 DOWNTO C_RANGE),awaddr_reg);
---------------------------------------------------------------------------
-- AXI wlast generation
---------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awlen_cntr_r <= (OTHERS => '1');
awlen_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awlen_int <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
awlen_cntr_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
ELSIF (dec_alen_c = '1') THEN
awlen_cntr_r <= awlen_cntr_r - ONE AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
w_last_c <= '1' WHEN (awlen_cntr_r = "00000000" AND S_AXI_WVALID = '1') ELSE '0';
dec_alen_c <= (incr_addr_c OR w_last_c);
---------------------------------------------------------------------------
-- Generation of bvalid counter for outstanding transactions
---------------------------------------------------------------------------
P_b_valid_os_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_count_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- bvalid_count_r generation
IF (bvalid_c = '1' AND bvalid_r = '1' AND S_AXI_BREADY = '1') THEN
bvalid_count_r <= bvalid_count_r AFTER FLOP_DELAY;
ELSIF (bvalid_c = '1') THEN
bvalid_count_r <= bvalid_count_r + "01" AFTER FLOP_DELAY;
ELSIF (bvalid_r = '1' AND S_AXI_BREADY = '1' AND bvalid_count_r /= "0") THEN
bvalid_count_r <= bvalid_count_r - "01" AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_os_r ;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is used
---------------------------------------------------------------------------
gaxi_bvalid_id_r:IF (C_HAS_AXI_ID = 1) GENERATE
SIGNAL bvalid_d1_c : std_logic := '0';
BEGIN
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
bvalid_d1_c <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
--external bvalid signal generation
IF (bvalid_d1_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_id_r;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is not used
---------------------------------------------------------------------------
gaxi_bvalid_noid_r:IF (C_HAS_AXI_ID = 0) GENERATE
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
--external bvalid signal generation
IF (bvalid_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_noid_r;
---------------------------------------------------------------------------
-- Generation of Bready timeout
---------------------------------------------------------------------------
P_brdy_tout_c: PROCESS (bvalid_count_r)
BEGIN
-- bready_timeout_c generation
IF(conv_integer(bvalid_count_r) = C_AXI_OS_WR-1) THEN
bready_timeout_c <= '1';
ELSE
bready_timeout_c <= '0';
END IF;
END PROCESS P_brdy_tout_c;
---------------------------------------------------------------------------
-- Generation of BID
---------------------------------------------------------------------------
gaxi_bid_gen:IF (C_HAS_AXI_ID = 1) GENERATE
P_bid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
bvalid_wr_cnt_r <= (OTHERS => '0');
bvalid_rd_cnt_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- STORE AWID IN AN ARRAY
IF(bvalid_c = '1') THEN
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + "01";
END IF;
-- GENERATE BID FROM AWID ARRAY
bvalid_rd_cnt_r <= bvalid_rd_cnt_c AFTER FLOP_DELAY;
S_AXI_BID <= axi_bid_array(conv_integer(bvalid_rd_cnt_c));
END IF;
END PROCESS P_bid_gen;
bvalid_rd_cnt_c <= bvalid_rd_cnt_r + "01" WHEN (bvalid_r = '1' AND S_AXI_BREADY = '1') ELSE bvalid_rd_cnt_r;
---------------------------------------------------------------------------
-- Storing AWID for generation of BID
---------------------------------------------------------------------------
P_awid_reg:PROCESS (S_ACLK)
BEGIN
IF (S_ACLK'event AND S_ACLK='1') THEN
IF(aw_ready_r = '1' AND S_AXI_AWVALID = '1') THEN
axi_bid_array(conv_integer(bvalid_wr_cnt_r)) <= S_AXI_AWID;
END IF;
END IF;
END PROCESS P_awid_reg;
END GENERATE gaxi_bid_gen;
S_AXI_BVALID <= bvalid_r;
S_AXI_AWREADY <= aw_ready_r;
END axi_write_wrap_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity write_netlist is
GENERIC(
C_AXI_TYPE : integer
);
port (
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_AWVALID : in STD_LOGIC := '0';
S_AXI_WVALID : in STD_LOGIC := '0';
S_AXI_BREADY : in STD_LOGIC := '0';
w_last_c : in STD_LOGIC := '0';
bready_timeout_c : in STD_LOGIC := '0';
aw_ready_r : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_WR_EN : out STD_LOGIC;
addr_en_c : out STD_LOGIC;
incr_addr_c : out STD_LOGIC;
bvalid_c : out STD_LOGIC
);
end write_netlist;
architecture STRUCTURE of write_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
BEGIN
---------------------------------------------------------------------------
-- AXI LITE
---------------------------------------------------------------------------
gbeh_axi_lite_sm: IF (C_AXI_TYPE = 0 ) GENERATE
signal w_ready_r_7 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSignal_bvalid_c : STD_LOGIC;
signal NlwRenamedSignal_incr_addr_c : STD_LOGIC;
signal present_state_FSM_FFd3_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal present_state_FSM_FFd1_15 : STD_LOGIC;
signal present_state_FSM_FFd4_16 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd4_In1_21 : STD_LOGIC;
signal Mmux_aw_ready_c : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
S_AXI_WREADY <= w_ready_r_7;
S_AXI_BVALID <= NlwRenamedSignal_incr_addr_c;
S_AXI_WR_EN <= NlwRenamedSignal_bvalid_c;
incr_addr_c <= NlwRenamedSignal_incr_addr_c;
bvalid_c <= NlwRenamedSignal_bvalid_c;
NlwRenamedSignal_incr_addr_c <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_7
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_16
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_13
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_15
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000055554440"
)
port map (
I0 => S_AXI_WVALID,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => '0',
O => present_state_FSM_FFd3_In
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"0000000088880800"
)
port map (
I0 => S_AXI_AWVALID,
I1 => S_AXI_WVALID,
I2 => bready_timeout_c,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => present_state_FSM_FFd2_In
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAA2000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_WVALID,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => addr_en_c
);
Mmux_w_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"F5F07570F5F05500"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => w_ready_c
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd3_13,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd1_15,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_14,
I2 => present_state_FSM_FFd3_13,
I3 => '0',
I4 => '0',
I5 => '0',
O => NlwRenamedSignal_bvalid_c
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"2F0F27072F0F2200"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => present_state_FSM_FFd4_In1_21
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_In1_21,
I3 => '0',
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_aw_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"7535753575305500"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => S_AXI_WVALID,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => present_state_FSM_FFd2_14,
O => Mmux_aw_ready_c(0)
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => Mmux_aw_ready_c(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => aw_ready_c
);
END GENERATE gbeh_axi_lite_sm;
---------------------------------------------------------------------------
-- AXI FULL
---------------------------------------------------------------------------
gbeh_axi_full_sm: IF (C_AXI_TYPE = 1 ) GENERATE
signal w_ready_r_8 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSig_OI_bvalid_c : STD_LOGIC;
signal present_state_FSM_FFd1_16 : STD_LOGIC;
signal present_state_FSM_FFd4_17 : STD_LOGIC;
signal present_state_FSM_FFd3_18 : STD_LOGIC;
signal present_state_FSM_FFd2_19 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd2_In1_24 : STD_LOGIC;
signal present_state_FSM_FFd4_In1_25 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal N4 : STD_LOGIC;
begin
S_AXI_WREADY <= w_ready_r_8;
bvalid_c <= NlwRenamedSig_OI_bvalid_c;
S_AXI_BVALID <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_8
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_17
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_18
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_19
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_16
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000000005540"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd4_17,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd3_In
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"BF3FBB33AF0FAA00"
)
port map (
I0 => S_AXI_BREADY,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd1_16,
I4 => present_state_FSM_FFd4_17,
I5 => NlwRenamedSig_OI_bvalid_c,
O => aw_ready_c
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"AAAAAAAA20000000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_19,
I3 => S_AXI_WVALID,
I4 => w_last_c,
I5 => present_state_FSM_FFd4_17,
O => addr_en_c
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_19,
I2 => present_state_FSM_FFd3_18,
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_WR_EN
);
Mmux_incr_addr_c_0_1 : STATE_LOGIC
generic map(
INIT => X"0000000000002220"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => incr_addr_c
);
Mmux_aw_ready_c_0_11 : STATE_LOGIC
generic map(
INIT => X"0000000000008880"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => NlwRenamedSig_OI_bvalid_c
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"000000000000D5C0"
)
port map (
I0 => w_last_c,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd4_17,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd2_In1_24
);
present_state_FSM_FFd2_In2 : STATE_LOGIC
generic map(
INIT => X"FFFFAAAA08AAAAAA"
)
port map (
I0 => present_state_FSM_FFd2_19,
I1 => S_AXI_AWVALID,
I2 => bready_timeout_c,
I3 => w_last_c,
I4 => S_AXI_WVALID,
I5 => present_state_FSM_FFd2_In1_24,
O => present_state_FSM_FFd2_In
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"00C0004000C00000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => w_last_c,
I2 => S_AXI_WVALID,
I3 => bready_timeout_c,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => present_state_FSM_FFd4_In1_25
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88F8"
)
port map (
I0 => present_state_FSM_FFd1_16,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_17,
I3 => S_AXI_AWVALID,
I4 => present_state_FSM_FFd4_In1_25,
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_w_ready_c_0_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => w_last_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_w_ready_c_0_Q : STATE_LOGIC
generic map(
INIT => X"FABAFABAFAAAF000"
)
port map (
I0 => N2,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd4_17,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => w_ready_c
);
Mmux_aw_ready_c_0_11_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => bready_timeout_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => w_last_c,
I1 => N4,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => present_state_FSM_FFd1_16,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
END GENERATE gbeh_axi_full_sm;
end STRUCTURE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--AXI Behavioral Model entities
ENTITY blk_mem_axi_read_wrapper_beh is
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
port (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END blk_mem_axi_read_wrapper_beh;
architecture blk_mem_axi_read_wrapper_beh_arch of blk_mem_axi_read_wrapper_beh is
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_WRITE_WIDTH_A=8,0,
if_then_else((C_WRITE_WIDTH_A=16),1,
if_then_else((C_WRITE_WIDTH_A=32),2,
if_then_else((C_WRITE_WIDTH_A=64),3,
if_then_else((C_WRITE_WIDTH_A=128),4,
if_then_else((C_WRITE_WIDTH_A=256),5,0))))));
SIGNAL ar_id_r : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
SIGNAL addr_en_c : std_logic := '0';
SIGNAL rd_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL single_trans_c : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL mux_sel_c : std_logic := '0';
SIGNAL r_last_c : std_logic := '0';
SIGNAL r_last_int_c : std_logic := '0';
SIGNAL arlen_int_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL arlen_cntr : std_logic_vector(7 DOWNTO 0) := ONE;
SIGNAL arburst_int_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL arburst_int_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL araddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),C_AXI_ARADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL total_bytes : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
SIGNAL wrap_base_addr_r : integer := 0;
SIGNAL wrap_boundary_r : integer := 0;
SIGNAL arlen_int_c : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes_c : integer := 0;
SIGNAL wrap_base_addr_c : integer := 0;
SIGNAL wrap_boundary_c : integer := 0;
SIGNAL araddr_out : std_logic_vector(C_ADDRB_WIDTH-1 downto 0) := (OTHERS => '0');
COMPONENT read_netlist
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_INCR_ADDR : OUT std_logic := '0';
S_AXI_ADDR_EN : OUT std_logic := '0';
S_AXI_SINGLE_TRANS : OUT std_logic := '0';
S_AXI_MUX_SEL : OUT std_logic := '0';
S_AXI_R_LAST : OUT std_logic := '0';
S_AXI_R_LAST_INT : IN std_logic := '0';
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT read_netlist;
BEGIN
dec_alen_c <= incr_addr_c OR r_last_int_c;
axi_read_fsm : read_netlist
GENERIC MAP(
C_AXI_TYPE => 1,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
S_AXI_INCR_ADDR => incr_addr_c,
S_AXI_ADDR_EN => addr_en_c,
S_AXI_SINGLE_TRANS => single_trans_c,
S_AXI_MUX_SEL => mux_sel_c,
S_AXI_R_LAST => r_last_c,
S_AXI_R_LAST_INT => r_last_int_c,
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN => rd_en_c
);
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(arlen_int_r)+1);
wrap_base_addr_r <= (conv_integer(araddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary_r <= wrap_base_addr_r+total_bytes;
---- combinatorial from interface
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARSIZE,"000"));
arlen_int_c <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
total_bytes_c <= conv_integer(num_of_bytes_c)*(conv_integer(arlen_int_c)+1);
wrap_base_addr_c <= (conv_integer(S_AXI_ARADDR)/if_then_else(total_bytes_c=0,1,total_bytes_c))*(total_bytes_c);
wrap_boundary_c <= wrap_base_addr_c+total_bytes_c;
arburst_int_c <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARBURST,"01");
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
araddr_reg <= (OTHERS => '0');
arburst_int_r <= (OTHERS => '0');
num_of_bytes_r <= 0;
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (incr_addr_c = '1' AND addr_en_c = '1' AND single_trans_c = '0') THEN
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
IF (arburst_int_c = "10") THEN
IF(conv_integer(S_AXI_ARADDR) = (wrap_boundary_c-num_of_bytes_c)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_c,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (arburst_int_c = "01" OR arburst_int_c = "11") THEN
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (addr_en_c = '1') THEN
araddr_reg <= S_AXI_ARADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
ELSIF (incr_addr_c = '1') THEN
IF (arburst_int_r = "10") THEN
IF(conv_integer(araddr_reg) = (wrap_boundary_r-num_of_bytes_r)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_r,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
ELSIF (arburst_int_r = "01" OR arburst_int_r = "11") THEN
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
araddr_out <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),araddr_reg(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),araddr_reg);
--------------------------------------------------------------------------
-- Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
--------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF S_ARESETN = '1' THEN
arlen_cntr <= ONE;
arlen_int_r <= (OTHERS => '0');
ELSIF S_ACLK'event AND S_ACLK = '1' THEN
IF (addr_en_c = '1' AND dec_alen_c = '1' AND single_trans_c = '0') THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= S_AXI_ARLEN - ONE AFTER FLOP_DELAY;
ELSIF addr_en_c = '1' THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
ELSIF dec_alen_c = '1' THEN
arlen_cntr <= arlen_cntr - ONE AFTER FLOP_DELAY;
ELSE
arlen_cntr <= arlen_cntr AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
r_last_int_c <= '1' WHEN (arlen_cntr = "00000000" AND S_AXI_RREADY = '1') ELSE '0' ;
--------------------------------------------------------------------------
-- AXI FULL FSM
-- Mux Selection of ARADDR
-- ARADDR is driven out from the read fsm based on the mux_sel_c
-- Based on mux_sel either ARADDR is given out or the latched ARADDR is
-- given out to BRAM
--------------------------------------------------------------------------
P_araddr_mux: PROCESS (mux_sel_c,S_AXI_ARADDR,araddr_out)
BEGIN
IF (mux_sel_c = '0') THEN
S_AXI_ARADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARADDR(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),S_AXI_ARADDR);
ELSE
S_AXI_ARADDR_OUT <= araddr_out;
END IF;
END PROCESS P_araddr_mux;
--------------------------------------------------------------------------
-- Assign output signals - AXI FULL FSM
--------------------------------------------------------------------------
S_AXI_RD_EN <= rd_en_c;
grid: IF (C_HAS_AXI_ID = 1) GENERATE
P_rid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
S_AXI_RID <= (OTHERS => '0');
ar_id_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
IF (addr_en_c = '1' AND rd_en_c = '1') THEN
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
ELSIF (addr_en_c = '1' AND rd_en_c = '0') THEN
ar_id_r <= S_AXI_ARID;
ELSIF (rd_en_c = '1') THEN
S_AXI_RID <= ar_id_r;
END IF;
END IF;
END PROCESS P_rid_gen;
END GENERATE grid;
END blk_mem_axi_read_wrapper_beh_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity read_netlist is
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_R_LAST_INT : in STD_LOGIC := '0';
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_ARVALID : in STD_LOGIC := '0';
S_AXI_RREADY : in STD_LOGIC := '0';
S_AXI_INCR_ADDR : out STD_LOGIC;
S_AXI_ADDR_EN : out STD_LOGIC;
S_AXI_SINGLE_TRANS : out STD_LOGIC;
S_AXI_MUX_SEL : out STD_LOGIC;
S_AXI_R_LAST : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RLAST : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RD_EN : out STD_LOGIC;
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end read_netlist;
architecture STRUCTURE of read_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
signal present_state_FSM_FFd1_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_r_15 : STD_LOGIC;
signal gaxi_full_sm_ar_ready_r_16 : STD_LOGIC;
signal gaxi_full_sm_r_last_r_17 : STD_LOGIC;
signal NlwRenamedSig_OI_gaxi_full_sm_r_valid_r : STD_LOGIC;
signal gaxi_full_sm_r_valid_c : STD_LOGIC;
signal S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o : STD_LOGIC;
signal gaxi_full_sm_ar_ready_c : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_c : STD_LOGIC;
signal NlwRenamedSig_OI_S_AXI_R_LAST : STD_LOGIC;
signal S_AXI_ARLEN_7_GND_8_o_equal_1_o : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal Mmux_S_AXI_R_LAST13 : STD_LOGIC;
signal N01 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal Mmux_gaxi_full_sm_ar_ready_c11 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N8 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N13 : STD_LOGIC;
begin
S_AXI_R_LAST <= NlwRenamedSig_OI_S_AXI_R_LAST;
S_AXI_ARREADY <= gaxi_full_sm_ar_ready_r_16;
S_AXI_RLAST <= gaxi_full_sm_r_last_r_17;
S_AXI_RVALID <= NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
gaxi_full_sm_outstanding_read_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_outstanding_read_c,
Q => gaxi_full_sm_outstanding_read_r_15
);
gaxi_full_sm_r_valid_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => gaxi_full_sm_r_valid_c,
Q => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r
);
gaxi_full_sm_ar_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_ar_ready_c,
Q => gaxi_full_sm_ar_ready_r_16
);
gaxi_full_sm_r_last_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => NlwRenamedSig_OI_S_AXI_R_LAST,
Q => gaxi_full_sm_r_last_r_17
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_13
);
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 : STATE_LOGIC
generic map(
INIT => X"000000000000000B"
)
port map (
I0 => S_AXI_RREADY,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o
);
Mmux_S_AXI_SINGLE_TRANS11 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_SINGLE_TRANS
);
Mmux_S_AXI_ADDR_EN11 : STATE_LOGIC
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_ADDR_EN
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"ECEE2022EEEE2022"
)
port map (
I0 => S_AXI_ARVALID,
I1 => present_state_FSM_FFd1_13,
I2 => S_AXI_RREADY,
I3 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I4 => present_state_FSM_FFd2_14,
I5 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
O => present_state_FSM_FFd2_In
);
Mmux_S_AXI_R_LAST131 : STATE_LOGIC
generic map(
INIT => X"0000000044440444"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_RREADY,
I5 => '0',
O => Mmux_S_AXI_R_LAST13
);
Mmux_S_AXI_INCR_ADDR11 : STATE_LOGIC
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => S_AXI_R_LAST_INT,
I1 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => Mmux_S_AXI_R_LAST13,
O => S_AXI_INCR_ADDR
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000FE"
)
port map (
I0 => S_AXI_ARLEN(2),
I1 => S_AXI_ARLEN(1),
I2 => S_AXI_ARLEN(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => N01
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q : STATE_LOGIC
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => S_AXI_ARLEN(7),
I1 => S_AXI_ARLEN(6),
I2 => S_AXI_ARLEN(5),
I3 => S_AXI_ARLEN(4),
I4 => S_AXI_ARLEN(3),
I5 => N01,
O => S_AXI_ARLEN_7_GND_8_o_equal_1_o
);
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_gaxi_full_sm_outstanding_read_c1 : STATE_LOGIC
generic map(
INIT => X"0020000002200200"
)
port map (
I0 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd1_13,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => N2,
O => gaxi_full_sm_outstanding_read_c
);
Mmux_gaxi_full_sm_ar_ready_c12 : STATE_LOGIC
generic map(
INIT => X"0000000000004555"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => '0',
I5 => '0',
O => Mmux_gaxi_full_sm_ar_ready_c11
);
Mmux_S_AXI_R_LAST11_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000EF"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
Mmux_S_AXI_R_LAST11 : STATE_LOGIC
generic map(
INIT => X"FCAAFC0A00AA000A"
)
port map (
I0 => S_AXI_ARVALID,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => N4,
I5 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
O => gaxi_full_sm_r_valid_c
);
S_AXI_MUX_SEL1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAAAA08"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => '0',
O => S_AXI_MUX_SEL
);
Mmux_S_AXI_RD_EN11 : STATE_LOGIC
generic map(
INIT => X"F3F3F755A2A2A200"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => gaxi_full_sm_outstanding_read_r_15,
I4 => present_state_FSM_FFd2_14,
I5 => S_AXI_ARVALID,
O => S_AXI_RD_EN
);
present_state_FSM_FFd1_In3 : beh_muxf7
port map (
I0 => N8,
I1 => N9,
S => present_state_FSM_FFd1_13,
O => present_state_FSM_FFd1_In
);
present_state_FSM_FFd1_In3_F : STATE_LOGIC
generic map(
INIT => X"000000005410F4F0"
)
port map (
I0 => S_AXI_RREADY,
I1 => present_state_FSM_FFd2_14,
I2 => S_AXI_ARVALID,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => '0',
O => N8
);
present_state_FSM_FFd1_In3_G : STATE_LOGIC
generic map(
INIT => X"0000000072FF7272"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N9
);
Mmux_gaxi_full_sm_ar_ready_c14 : beh_muxf7
port map (
I0 => N10,
I1 => N11,
S => present_state_FSM_FFd1_13,
O => gaxi_full_sm_ar_ready_c
);
Mmux_gaxi_full_sm_ar_ready_c14_F : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88A8"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => Mmux_gaxi_full_sm_ar_ready_c11,
I5 => '0',
O => N10
);
Mmux_gaxi_full_sm_ar_ready_c14_G : STATE_LOGIC
generic map(
INIT => X"000000008D008D8D"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N11
);
Mmux_S_AXI_R_LAST1 : beh_muxf7
port map (
I0 => N12,
I1 => N13,
S => present_state_FSM_FFd1_13,
O => NlwRenamedSig_OI_S_AXI_R_LAST
);
Mmux_S_AXI_R_LAST1_F : STATE_LOGIC
generic map(
INIT => X"0000000088088888"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N12
);
Mmux_S_AXI_R_LAST1_G : STATE_LOGIC
generic map(
INIT => X"00000000E400E4E4"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => S_AXI_R_LAST_INT,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N13
);
end STRUCTURE;
-------------------------------------------------------------------------------
-- Output Register Stage Entity
--
-- This module builds the output register stages of the memory. This module is
-- instantiated in the main memory module (blk_mem_gen_v8_3_1) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_output_stage IS
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_output_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6" and "virtex6l".
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
-- C_HAS_RST : Determines the presence of the RST port
-- C_RSTRAM : Determines if special reset behavior is used
-- C_RST_PRIORITY : Determines the priority between CE and SR
-- C_INIT_VAL : Initialization value
-- C_HAS_EN : Determines the presence of the EN port
-- C_HAS_REGCE : Determines the presence of the REGCE port
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
-- of the RAM primitive
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- NUM_STAGES : Determines the number of output stages
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE output_stage_behavioral OF blk_mem_gen_v8_3_1_output_stage IS
--*******************************************************
-- Functions used in the output stage ARCHITECTURE
--*******************************************************
-- Calculate num_reg_stages
FUNCTION get_num_reg_stages(NUM_STAGES: INTEGER) RETURN INTEGER IS
VARIABLE num_reg_stages : INTEGER := 0;
BEGIN
IF (NUM_STAGES = 0) THEN
num_reg_stages := 0;
ELSE
num_reg_stages := NUM_STAGES - 1;
END IF;
RETURN num_reg_stages;
END get_num_reg_stages;
-- Check if the INTEGER is zero or non-zero
FUNCTION int_to_bit(input: INTEGER) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = 0) THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END int_to_bit;
-- Constants
CONSTANT HAS_EN : STD_LOGIC := int_to_bit(C_HAS_EN);
CONSTANT HAS_REGCE : STD_LOGIC := int_to_bit(C_HAS_REGCE);
CONSTANT HAS_RST : STD_LOGIC := int_to_bit(C_HAS_RST);
CONSTANT REG_STAGES : INTEGER := get_num_reg_stages(NUM_STAGES);
-- Pipeline array
TYPE reg_data_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
TYPE reg_ecc_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC;
TYPE reg_eccaddr_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
CONSTANT REG_INIT : reg_data_array := (OTHERS => init_val);
SIGNAL out_regs : reg_data_array := REG_INIT;
SIGNAL sbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL dbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL rdaddrecc_regs: reg_eccaddr_array := (OTHERS => (OTHERS => '0'));
-- Internal signals
SIGNAL en_i : STD_LOGIC;
SIGNAL regce_i : STD_LOGIC;
SIGNAL rst_i : STD_LOGIC;
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := init_val;
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL DIN : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL RDADDRECC_IN : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ;
SIGNAL SBITERR_IN : STD_LOGIC := '0';
SIGNAL DBITERR_IN : STD_LOGIC := '0';
BEGIN
--***********************************************************************
-- Assign internal signals. This effectively wires off optional inputs.
--***********************************************************************
-- Internal enable for output registers is tied to user EN or '1' depending
-- on parameters
en_i <= EN OR (NOT HAS_EN);
-- Internal register enable for output registers is tied to user REGCE, EN
-- or '1' depending on parameters
regce_i <= (HAS_REGCE AND REGCE)
OR ((NOT HAS_REGCE) AND en_i);
-- Internal SRR is tied to user RST or '0' depending on parameters
rst_i <= RST AND HAS_RST;
--***************************************************************************
-- NUM_STAGES = 0 (No output registers. RAM only)
--***************************************************************************
zero_stages: IF (NUM_STAGES = 0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE zero_stages;
NO_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 0) GENERATE
DIN <= DIN_I;
RDADDRECC_IN <= RDADDRECC_IN_I;
SBITERR_IN <= SBITERR_IN_I;
DBITERR_IN <= DBITERR_IN_I;
END GENERATE NO_ECC_PIPE_REG;
WITH_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(ECCPIPECE = '1') THEN
DIN <= DIN_I AFTER FLOP_DELAY;
RDADDRECC_IN <= RDADDRECC_IN_I AFTER FLOP_DELAY;
SBITERR_IN <= SBITERR_IN_I AFTER FLOP_DELAY;
DBITERR_IN <= DBITERR_IN_I AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS;
END GENERATE WITH_ECC_PIPE_REG;
--***************************************************************************
-- NUM_STAGES = 1
-- (Mem Output Reg only or Mux Output Reg only)
--***************************************************************************
-- Possible valid combinations:
-- Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
-- +-----------------------------------------+
-- | C_RSTRAM_* | Reset Behavior |
-- +----------------+------------------------+
-- | 0 | Normal Behavior |
-- +----------------+------------------------+
-- | 1 | Special Behavior |
-- +----------------+------------------------+
--
-- Normal = REGCE gates reset, as in the case of all Virtex families and all
-- spartan families with the exception of S3ADSP and S6.
-- Special = EN gates reset, as in the case of S3ADSP and S6.
one_stage_norm: IF (NUM_STAGES = 1 AND
(C_RSTRAM=0 OR (C_RSTRAM=1 AND (C_XDEVICEFAMILY/="spartan3adsp" AND C_XDEVICEFAMILY/="aspartan3adsp")) OR
C_HAS_MEM_OUTPUT_REGS=0 OR C_HAS_RST=0)) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i = '1' AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
END IF;--CLK
END PROCESS;
END GENERATE one_stage_norm;
-- Special Reset Behavior for S6 and S3ADSP
one_stage_splbhv: IF (NUM_STAGES=1 AND C_RSTRAM=1 AND (C_XDEVICEFAMILY ="spartan3adsp" OR C_XDEVICEFAMILY ="aspartan3adsp"))
GENERATE
DOUT <= dout_i;
SBITERR <= '0';
DBITERR <= '0';
RDADDRECC <= (OTHERS => '0');
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (rst_i='1' AND en_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
ELSIF (regce_i='1' AND rst_i/='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE one_stage_splbhv;
--****************************************************************************
-- NUM_STAGES > 1
-- Mem Output Reg + Mux Output Reg
-- or
-- Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
-- or
-- Mux Pipeline Stages (>0) + Mux Output Reg
--****************************************************************************
multi_stage: IF (NUM_STAGES > 1) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i='1'AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
IF (en_i='1') THEN
-- Shift the data through the output stages
FOR i IN 1 TO REG_STAGES-1 LOOP
out_regs(i) <= out_regs(i-1) AFTER FLOP_DELAY;
sbiterr_regs(i) <= sbiterr_regs(i-1) AFTER FLOP_DELAY;
dbiterr_regs(i) <= dbiterr_regs(i-1) AFTER FLOP_DELAY;
rdaddrecc_regs(i) <= rdaddrecc_regs(i-1) AFTER FLOP_DELAY;
END LOOP;
out_regs(0) <= DIN;
sbiterr_regs(0) <= SBITERR_IN;
dbiterr_regs(0) <= DBITERR_IN;
rdaddrecc_regs(0) <= RDADDRECC_IN;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE multi_stage;
END output_stage_behavioral;
-------------------------------------------------------------------------------
-- SoftECC Output Register Stage Entity
-- This module builds the softecc output register stages. This module is
-- instantiated in the memory module (blk_mem_gen_v8_3_1_mem_module) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ;
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- of the RAM primitive
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE softecc_output_reg_stage_behavioral OF blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
-- Internal signals
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
--***************************************************************************
-- NO OUTPUT STAGES
--***************************************************************************
no_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE no_output_stage;
--****************************************************************************
-- WITH OUTPUT STAGE
--****************************************************************************
has_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END PROCESS;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
END GENERATE has_output_stage;
END softecc_output_reg_stage_behavioral;
--******************************************************************************
-- Main Memory module
--
-- This module is the behavioral model which implements the RAM
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
ENTITY blk_mem_gen_v8_3_1_mem_module IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_mem_module;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE mem_module_behavioral OF blk_mem_gen_v8_3_1_mem_module IS
--****************************************
-- min/max constant functions
--****************************************
-- get_max
----------
function SLV_TO_INT(SLV: in std_logic_vector
) return integer is
variable int : integer;
begin
int := 0;
for i in SLV'high downto SLV'low loop
int := int * 2;
if SLV(i) = '1' then
int := int + 1;
end if;
end loop;
return int;
end;
FUNCTION get_max(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a > b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-- get_min
----------
FUNCTION get_min(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
--***************************************************************
-- convert write_mode from STRING type for use in case statement
--***************************************************************
FUNCTION write_mode_to_vector(mode: STRING) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF (mode = "NO_CHANGE") THEN
RETURN "10";
ELSIF (mode = "READ_FIRST") THEN
RETURN "01";
ELSE
RETURN "00"; -- WRITE_FIRST
END IF;
END FUNCTION;
--***************************************************************
-- convert hex STRING to STD_LOGIC_VECTOR
--***************************************************************
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
--***************************************************************
-- locally derived constants to determine memory shape
--***************************************************************
CONSTANT MIN_WIDTH_A : INTEGER := get_min(C_WRITE_WIDTH_A, C_READ_WIDTH_A);
CONSTANT MIN_WIDTH_B : INTEGER := get_min(C_WRITE_WIDTH_B,C_READ_WIDTH_B);
CONSTANT MIN_WIDTH : INTEGER := get_min(MIN_WIDTH_A, MIN_WIDTH_B);
CONSTANT MAX_DEPTH_A : INTEGER := get_max(C_WRITE_DEPTH_A, C_READ_DEPTH_A);
CONSTANT MAX_DEPTH_B : INTEGER := get_max(C_WRITE_DEPTH_B, C_READ_DEPTH_B);
CONSTANT MAX_DEPTH : INTEGER := get_max(MAX_DEPTH_A, MAX_DEPTH_B);
TYPE int_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF std_logic_vector(C_WRITE_WIDTH_A-1 DOWNTO 0);
TYPE mem_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC_VECTOR(MIN_WIDTH-1 DOWNTO 0);
TYPE ecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
TYPE softecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
--***************************************************************
-- memory initialization function
--***************************************************************
IMPURE FUNCTION init_memory(DEFAULT_DATA :
STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
write_width_a : INTEGER;
depth : INTEGER;
width : INTEGER)
RETURN mem_array IS
VARIABLE init_return : mem_array := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(write_width_a-1 DOWNTO 0);
VARIABLE int_mem_vector : int_array:= (OTHERS => (OTHERS => '0'));
VARIABLE file_buffer : LINE;
VARIABLE i : INTEGER := 0;
VARIABLE j : INTEGER;
VARIABLE k : INTEGER;
VARIABLE ignore_line : BOOLEAN := false;
VARIABLE good_data : BOOLEAN := false;
VARIABLE char_tmp : CHARACTER;
VARIABLE index : INTEGER;
variable init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable data : std_logic_vector(255 downto 0) := (others => '0');
variable inside_init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable k_slv : std_logic_vector(31 downto 0) := (others => '0');
variable i_slv : std_logic_vector(31 downto 0) := (others => '0');
VARIABLE disp_line : line := null;
variable open_status : file_open_status;
variable input_initf_tmp : mem_array ;
variable input_initf : mem_array := (others => (others => '0'));
file int_infile : text;
variable data_line, data_line_tmp, out_data_line : line;
variable slv_width : integer;
VARIABLE d_l : LINE;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
index := 0;
FOR i IN 0 TO depth-1 LOOP
FOR j IN 0 TO width-1 LOOP
init_return(i)(j) := DEFAULT_DATA(index);
index := (index + 1) MOD C_WRITE_WIDTH_A;
END LOOP;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, file_buffer);
read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO write_width_a-1 LOOP
IF (j MOD width = 0 AND j /= 0) THEN
i := i + 1;
END IF;
init_return(i)(j MOD width) := bit_to_sl(mem_vector(j));
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
--Display output message indicating that the behavioral model is done
--initializing
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator data initialization complete." SEVERITY NOTE;
if (C_USE_BRAM_BLOCK = 1) then
--Display output message indicating that the behavioral model is being
--initialized
-- Read in the .mem file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_INIT_FILE /= "NONE") then
file_open(open_status, int_infile, C_INIT_FILE, read_mode);
while not endfile(int_infile) loop
readline(int_infile, data_line);
while (data_line /= null and data_line'length > 0) loop
if (data_line(data_line'low to data_line'low + 1) = "//") then
deallocate(data_line);
elsif ((data_line(data_line'low to data_line'low + 1) = "/*") and (data_line(data_line'high-1 to data_line'high) = "*/")) then
deallocate(data_line);
elsif (data_line(data_line'low to data_line'low + 1) = "/*") then
deallocate(data_line);
ignore_line := true;
elsif (ignore_line = true and data_line(data_line'high-1 to data_line'high) = "*/") then
deallocate(data_line);
ignore_line := false;
elsif (ignore_line = false and data_line(data_line'low) = '@') then
read(data_line, char_tmp);
hread(data_line, init_addr_slv, good_data);
i := SLV_TO_INT(init_addr_slv);
elsif (ignore_line = false) then
hread(data_line, input_initf_tmp(i), good_data);
init_return(i)(write_width_a - 1 downto 0) := input_initf_tmp(i)(write_width_a - 1 downto 0);
if (good_data = true) then
i := i + 1;
end if;
else
deallocate(data_line);
end if;
end loop;
end loop;
file_close(int_infile);
END IF;
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- memory type constants
--***************************************************************
CONSTANT MEM_TYPE_SP_RAM : INTEGER := 0;
CONSTANT MEM_TYPE_SDP_RAM : INTEGER := 1;
CONSTANT MEM_TYPE_TDP_RAM : INTEGER := 2;
CONSTANT MEM_TYPE_SP_ROM : INTEGER := 3;
CONSTANT MEM_TYPE_DP_ROM : INTEGER := 4;
--***************************************************************
-- memory configuration constant functions
--***************************************************************
--get_single_port
-----------------
FUNCTION get_single_port(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_RAM OR mem_type=MEM_TYPE_SP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_single_port;
--get_is_rom
--------------
FUNCTION get_is_rom(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_ROM OR mem_type=MEM_TYPE_DP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_is_rom;
--get_has_a_write
------------------
FUNCTION get_has_a_write(IS_ROM : INTEGER) RETURN INTEGER IS
BEGIN
IF (IS_ROM=0) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_a_write;
--get_has_b_write
------------------
FUNCTION get_has_b_write(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_TDP_RAM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_write;
--get_has_a_read
------------------
FUNCTION get_has_a_read(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SDP_RAM) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_a_read;
--get_has_b_read
------------------
FUNCTION get_has_b_read(SINGLE_PORT : INTEGER) RETURN INTEGER IS
BEGIN
IF (SINGLE_PORT=1) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_b_read;
--get_has_b_port
------------------
FUNCTION get_has_b_port(HAS_B_READ : INTEGER;
HAS_B_WRITE : INTEGER)
RETURN INTEGER IS
BEGIN
IF (HAS_B_READ=1 OR HAS_B_WRITE=1) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_port;
--get_num_output_stages
-----------------------
FUNCTION get_num_output_stages(has_mem_output_regs : INTEGER;
has_mux_output_regs : INTEGER;
mux_pipeline_stages : INTEGER)
RETURN INTEGER IS
VARIABLE actual_mux_pipeline_stages : INTEGER;
BEGIN
-- Mux pipeline stages can be non-zero only when there is a mux
-- output register.
IF (has_mux_output_regs=1) THEN
actual_mux_pipeline_stages := mux_pipeline_stages;
ELSE
actual_mux_pipeline_stages := 0;
END IF;
RETURN has_mem_output_regs+actual_mux_pipeline_stages+has_mux_output_regs;
END get_num_output_stages;
--***************************************************************************
-- Component declaration of the VARIABLE depth output register stage
--***************************************************************************
COMPONENT blk_mem_gen_v8_3_1_output_stage
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
EN : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
ECCPIPECE : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_output_stage;
COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************************************
-- locally derived constants to assist memory access
--******************************************************
CONSTANT WRITE_WIDTH_RATIO_A : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_A : INTEGER := C_READ_WIDTH_A/MIN_WIDTH;
CONSTANT WRITE_WIDTH_RATIO_B : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_B : INTEGER := C_READ_WIDTH_B/MIN_WIDTH;
--******************************************************
-- To modify the LSBs of the 'wider' data to the actual
-- address value
--******************************************************
CONSTANT WRITE_ADDR_A_DIV : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH_A;
CONSTANT READ_ADDR_A_DIV : INTEGER := C_READ_WIDTH_A/MIN_WIDTH_A;
CONSTANT WRITE_ADDR_B_DIV : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH_B;
CONSTANT READ_ADDR_B_DIV : INTEGER := C_READ_WIDTH_B/MIN_WIDTH_B;
--******************************************************
-- FUNCTION : log2roundup
--******************************************************
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
--******************************************************
-- Other constants and signals
--******************************************************
CONSTANT COLL_DELAY : TIME := 100 ps;
-- default data vector
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_DEFAULT_DATA,
C_WRITE_WIDTH_A);
CONSTANT CHKBIT_WIDTH : INTEGER := if_then_else(C_WRITE_WIDTH_A>57,8,if_then_else(C_WRITE_WIDTH_A>26,7,if_then_else(C_WRITE_WIDTH_A>11,6,if_then_else(C_WRITE_WIDTH_A>4,5,if_then_else(C_WRITE_WIDTH_A<5,4,0)))));
-- the init memory SIGNAL
SIGNAL memory_i : mem_array;
SIGNAL doublebit_error_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0);
SIGNAL current_contents_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
-- write mode constants
CONSTANT WRITE_MODE_A : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_A);
CONSTANT WRITE_MODE_B : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_B);
CONSTANT WRITE_MODES : STD_LOGIC_VECTOR(3 DOWNTO 0) :=
WRITE_MODE_A & WRITE_MODE_B;
-- reset values
CONSTANT INITA_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITA_VAL,
C_READ_WIDTH_A);
CONSTANT INITB_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITB_VAL,
C_READ_WIDTH_B);
-- memory output 'latches'
SIGNAL memory_out_a : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0) :=
INITA_VAL;
SIGNAL memory_out_b : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) :=
INITB_VAL;
SIGNAL sbiterr_in : STD_LOGIC := '0';
SIGNAL sbiterr_sdp : STD_LOGIC := '0';
SIGNAL dbiterr_in : STD_LOGIC := '0';
SIGNAL dbiterr_sdp : STD_LOGIC := '0';
SIGNAL rdaddrecc_in : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_sdp : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL doutb_i : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i : STD_LOGIC := '0';
SIGNAL dbiterr_i : STD_LOGIC := '0';
-- memory configuration constants
-----------------------------------------------
CONSTANT SINGLE_PORT : INTEGER := get_single_port(C_MEM_TYPE);
CONSTANT IS_ROM : INTEGER := get_is_rom(C_MEM_TYPE);
CONSTANT HAS_A_WRITE : INTEGER := get_has_a_write(IS_ROM);
CONSTANT HAS_B_WRITE : INTEGER := get_has_b_write(C_MEM_TYPE);
CONSTANT HAS_A_READ : INTEGER := get_has_a_read(C_MEM_TYPE);
CONSTANT HAS_B_READ : INTEGER := get_has_b_read(SINGLE_PORT);
CONSTANT HAS_B_PORT : INTEGER := get_has_b_port(HAS_B_READ, HAS_B_WRITE);
CONSTANT NUM_OUTPUT_STAGES_A : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_A,
C_MUX_PIPELINE_STAGES);
CONSTANT NUM_OUTPUT_STAGES_B : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES);
CONSTANT WEA0 : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT WEB0 : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-----------------------------------------------------------------------------
-- DEBUG CONTROL
-- DEBUG=0 : Debug output OFF
-- DEBUG=1 : Some debug info printed
-----------------------------------------------------------------------------
CONSTANT DEBUG : INTEGER := 0;
-- internal signals
-----------------------------------------------
SIGNAL ena_i : STD_LOGIC;
SIGNAL enb_i : STD_LOGIC;
SIGNAL reseta_i : STD_LOGIC;
SIGNAL resetb_i : STD_LOGIC;
SIGNAL wea_i : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL web_i : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL rea_i : STD_LOGIC;
SIGNAL reb_i : STD_LOGIC;
SIGNAL message_complete : BOOLEAN := false;
SIGNAL rsta_outp_stage : STD_LOGIC := '0';
SIGNAL rstb_outp_stage : STD_LOGIC := '0';
--*********************************************************
--FUNCTION : Collision check
--*********************************************************
FUNCTION collision_check (addr_a :
STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
iswrite_a : BOOLEAN;
addr_b :
STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
iswrite_b : BOOLEAN)
RETURN BOOLEAN IS
VARIABLE c_aw_bw : INTEGER;
VARIABLE c_aw_br : INTEGER;
VARIABLE c_ar_bw : INTEGER;
VARIABLE write_addr_a_width : INTEGER;
VARIABLE read_addr_a_width : INTEGER;
VARIABLE write_addr_b_width : INTEGER;
VARIABLE read_addr_b_width : INTEGER;
BEGIN
c_aw_bw := 0;
c_aw_br := 0;
c_ar_bw := 0;
-- Determine the effective address widths FOR each of the 4 ports
write_addr_a_width := C_ADDRA_WIDTH-log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width := C_ADDRA_WIDTH-log2roundup(READ_ADDR_A_DIV);
write_addr_b_width := C_ADDRB_WIDTH-log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width := C_ADDRB_WIDTH-log2roundup(READ_ADDR_B_DIV);
--Look FOR a write-write collision. In order FOR a write-write
--collision to exist, both ports must have a write transaction.
IF (iswrite_a AND iswrite_b) THEN
IF (write_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_a and iswrite_b
--If the B port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_a) THEN
IF (write_addr_a_width > read_addr_b_width) THEN
--read_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_b_width
--Once both are scaled to read_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
END IF; --width
END IF; --iswrite_a
--If the A port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_b) THEN
IF (read_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
ELSE
--read_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_a_width
--Once both are scaled to read_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_b
RETURN (c_aw_bw=1 OR c_aw_br=1 OR c_ar_bw=1);
END FUNCTION collision_check;
BEGIN -- Architecture
-----------------------------------------------------------------------------
-- SOFTECC and ECC SBITERR/DBITERR Outputs
-- The ECC Behavior is modeled by the behavioral models only for Virtex-6.
-- The SOFTECC Behavior is modeled by the behavioral models for Spartan-6.
-- For Virtex-5, these outputs will be tied to 0.
-----------------------------------------------------------------------------
SBITERR <= sbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_sdp WHEN (((C_FAMILY="virtex7") AND C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
-----------------------------------------------
-- This effectively wires off optional inputs
-----------------------------------------------
ena_i <= ENA WHEN (C_HAS_ENA=1) ELSE '1';
enb_i <= ENB WHEN (C_HAS_ENB=1 AND HAS_B_PORT=1) ELSE '1';
-- We are doing an "AND" operation of WEA and ENA and passing to Enbale pin of BRAM when built-in ECC is enabled,
-- what this means is that the write operation happens only when both WEA and ENA are high.
wea_i <= WEA WHEN (HAS_A_WRITE=1 AND ena_i='1') ELSE WEA0;
-- wea_i <= (OTHERS => '1') WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=1 AND ENA = '1') ELSE -- Use_ENA_pin
-- WEA WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=0) ELSE -- Always_enabled
-- WEA WHEN (HAS_A_WRITE=1 AND ena_i='1' AND C_USE_ECC = 0) ELSE
-- WEA0;
web_i <= WEB WHEN (HAS_B_WRITE=1 AND enb_i='1') ELSE WEB0;
rea_i <= ena_i WHEN (HAS_A_READ=1) ELSE '0';
reb_i <= enb_i WHEN (HAS_B_READ=1) ELSE '0';
-- these signals reset the memory latches
-- For the special reset behaviors in some of the families, the C_RSTRAM
-- attribute of the corresponding port is used to indicate if the latch is
-- reset or not.
reseta_i <= RSTA WHEN
((C_HAS_RSTA=1 AND NUM_OUTPUT_STAGES_A=0) OR
(C_HAS_RSTA=1 AND C_RSTRAM_A=1))
ELSE '0';
resetb_i <= RSTB WHEN
((C_HAS_RSTB=1 AND NUM_OUTPUT_STAGES_B=0) OR
(C_HAS_RSTB=1 AND C_RSTRAM_B=1) )
ELSE '0';
--***************************************************************************
-- This is the main PROCESS which includes the memory VARIABLE and the read
-- and write procedures. It also schedules read and write operations
--***************************************************************************
PROCESS (CLKA, CLKB,rea_i,reb_i,reseta_i,resetb_i)
-- Initialize the init memory array
------------------------------------
VARIABLE memory : mem_array := init_memory(DEFAULT_DATA,
C_WRITE_WIDTH_A,
MAX_DEPTH,
MIN_WIDTH);
-- Initialize the mem memory array
------------------------------------
VARIABLE softecc_sbiterr_arr : softecc_err_array;
VARIABLE softecc_dbiterr_arr : softecc_err_array;
VARIABLE sbiterr_arr : ecc_err_array;
VARIABLE dbiterr_arr : ecc_err_array;
CONSTANT doublebit_lsb : STD_LOGIC_VECTOR (1 DOWNTO 0):="11";
CONSTANT doublebit_msb : STD_LOGIC_VECTOR (C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 DOWNTO 0):= (OTHERS => '0');
VARIABLE doublebit_error : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0) := doublebit_msb & doublebit_lsb ;
VARIABLE current_contents_var : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
--***********************************
-- procedures to access the memory
--***********************************
-- write_a
----------
PROCEDURE write_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
inj_sbiterr : IN STD_LOGIC;
inj_dbiterr : IN STD_LOGIC) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
VARIABLE message : LINE;
VARIABLE errbit_current_contents : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
-- Block Memory Generator non-cycle-accurate message
ASSERT (message_complete) REPORT "Block Memory Generator module is using a behavioral model FOR simulation which will not precisely model memory collision behavior."
SEVERITY NOTE;
message_complete <= true;
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_A_DIV);
IF (address_i >= C_WRITE_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range FOR A Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEA = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_A + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEA_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Insert double bit errors:
IF (C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
current_contents(0) := NOT(current_contents(0));
current_contents(1) := NOT(current_contents(1));
--current_contents(0) := NOT(current_contents(30));
--current_contents(1) := NOT(current_contents(62));
END IF;
END IF;
-- Insert double bit errors:
IF (C_USE_SOFTECC=1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 downto 2) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 downto 0);
doublebit_error(0) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1);
doublebit_error(1) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-2);
current_contents := current_contents XOR doublebit_error(C_WRITE_WIDTH_A-1 DOWNTO 0);
END IF;
END IF;
IF(DEBUG=1) THEN
current_contents_var := current_contents; --for debugging current
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_A + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
-- Store address at which error is injected:
IF ((C_FAMILY = "virtex7") AND C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
sbiterr_arr(address_i) := '1';
ELSE
sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
dbiterr_arr(address_i) := '1';
ELSE
dbiterr_arr(address_i) := '0';
END IF;
END IF;
-- Store address at which softecc error is injected:
IF (C_USE_SOFTECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
softecc_sbiterr_arr(address_i) := '1';
ELSE
softecc_sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
softecc_dbiterr_arr(address_i) := '1';
ELSE
softecc_dbiterr_arr(address_i) := '0';
END IF;
END IF;
END IF;
END PROCEDURE;
-- write_b
----------
PROCEDURE write_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_B_DIV);
IF (address_i >= C_WRITE_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEB = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_B + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEB_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_B + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
END IF;
END PROCEDURE;
-- read_a
----------
PROCEDURE read_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_A_DIV);
IF (address_i >= C_READ_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for A Read"
SEVERITY WARNING;
END IF;
memory_out_a <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_A-1 LOOP
memory_out_a(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_A + i) AFTER FLOP_DELAY;
END LOOP;
END IF;
END IF;
END PROCEDURE;
-- read_b
----------
PROCEDURE read_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_B_DIV);
IF (address_i >= C_READ_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Read"
SEVERITY WARNING;
END IF;
memory_out_b <= (OTHERS => 'X') AFTER FLOP_DELAY;
sbiterr_in <= 'X' AFTER FLOP_DELAY;
dbiterr_in <= 'X' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_B-1 LOOP
memory_out_b(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_B + i) AFTER FLOP_DELAY;
END LOOP;
--assert sbiterr and dbiterr signals
IF ((C_FAMILY="virtex7") AND C_USE_ECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
--assert softecc sbiterr and dbiterr signals
ELSIF (C_USE_SOFTECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (softecc_sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (softecc_dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
END IF;
END IF;
END IF;
END PROCEDURE;
-- reset_a
----------
PROCEDURE reset_a
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
-- reset_b
----------
PROCEDURE reset_b
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
BEGIN -- begin the main PROCESS
--***************************************************************************
-- These are the main blocks which schedule read and write operations
-- Note that the reset priority feature at the latch stage is only supported
-- for Spartan-6. For other families, the default priority at the latch stage
-- is "CE"
--***************************************************************************
-- Synchronous clocks: schedule port operations with respect to both
-- write operating modes
IF (C_COMMON_CLK=1) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODES IS
WHEN "0000" => -- write_first write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "0100" => -- read_first write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "0001" => -- write_first read_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0101" => --read_first read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0010" => -- write_first no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0110" => -- read_first no_change
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1000" => -- no_change write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "1001" => -- no_change read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1010" => -- no_change no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Synchronous clocks
-- Asynchronous clocks: port operation is independent
IF (C_COMMON_CLK=0) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODE_A IS
WHEN "00" => -- write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN "01" => -- read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "10" => -- no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
IF (CLKB='1' AND CLKB'EVENT) THEN
CASE WRITE_MODE_B IS
WHEN "00" => -- write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "01" => -- read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "10" => -- no_change
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Asynchronous clocks
-- Assign the memory VARIABLE to the user_visible memory_i SIGNAL
IF(DEBUG=1) THEN
memory_i <= memory;
doublebit_error_i <= doublebit_error;
current_contents_i <= current_contents_var;
END IF;
END PROCESS;
--********************************************************************
-- Instantiate the VARIABLE depth output stage
--********************************************************************
-- Port A
rsta_outp_stage <= RSTA and not sleep;
rstb_outp_stage <= RSTB and not sleep;
reg_a : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTA,
C_RSTRAM => C_RSTRAM_A,
C_RST_PRIORITY => C_RST_PRIORITY_A,
init_val => INITA_VAL,
C_HAS_EN => C_HAS_ENA,
C_HAS_REGCE => C_HAS_REGCEA,
C_DATA_WIDTH => C_READ_WIDTH_A,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_A,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_A,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKA,
RST => rsta_outp_stage, --RSTA,
EN => ENA,
REGCE => REGCEA,
DIN_I => memory_out_a,
DOUT => DOUTA,
SBITERR_IN_I => '0',
DBITERR_IN_I => '0',
SBITERR => OPEN,
DBITERR => OPEN,
RDADDRECC_IN_I => (OTHERS => '0'),
ECCPIPECE => '0',
RDADDRECC => OPEN
);
-- Port B
reg_b : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTB,
C_RSTRAM => C_RSTRAM_B,
C_RST_PRIORITY => C_RST_PRIORITY_B,
init_val => INITB_VAL,
C_HAS_EN => C_HAS_ENB,
C_HAS_REGCE => C_HAS_REGCEB,
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_B,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKB,
RST => rstb_outp_stage,--RSTB,
EN => ENB,
REGCE => REGCEB,
DIN_I => memory_out_b,
DOUT => doutb_i,
SBITERR_IN_I => sbiterr_in,
DBITERR_IN_I => dbiterr_in,
SBITERR => sbiterr_i,
DBITERR => dbiterr_i,
RDADDRECC_IN_I => rdaddrecc_in,
ECCPIPECE => ECCPIPECE,
RDADDRECC => rdaddrecc_i
);
--********************************************************************
-- Instantiate the input / Output Register stages
--********************************************************************
output_reg_stage: blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC MAP(
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP(
CLK => CLKB,
DIN => doutb_i,
DOUT => DOUTB,
SBITERR_IN => sbiterr_i,
DBITERR_IN => dbiterr_i,
SBITERR => sbiterr_sdp,
DBITERR => dbiterr_sdp,
RDADDRECC_IN => rdaddrecc_i,
RDADDRECC => rdaddrecc_sdp
);
--*********************************
-- Synchronous collision checks
--*********************************
sync_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=1) GENERATE
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
-- collision detect
VARIABLE is_collision : BOOLEAN;
VARIABLE message : LINE;
BEGIN
IF (CLKA='1' AND CLKA'EVENT) THEN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision := false;
END IF;
-- If the write port is in READ_FIRST mode, there is no collision
IF (C_WRITE_MODE_A="READ_FIRST" AND wea_i/=WEA0 AND web_i=WEB0) THEN
is_collision := false;
END IF;
IF (C_WRITE_MODE_B="READ_FIRST" AND web_i/=WEB0 AND wea_i=WEA0) THEN
is_collision := false;
END IF;
-- Only flag if one of the accesses is a write
IF (is_collision AND (wea_i/=WEA0 OR web_i/=WEB0)) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END IF;
END PROCESS;
END GENERATE;
--*********************************
-- Asynchronous collision checks
--*********************************
async_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=0) GENERATE
SIGNAL addra_delay : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL wea_delay : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL ena_delay : STD_LOGIC;
SIGNAL addrb_delay : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
SIGNAL web_delay : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL enb_delay : STD_LOGIC;
BEGIN
-- Delay A and B addresses in order to mimic setup/hold times
PROCESS (ADDRA, wea_i, ena_i, ADDRB, web_i, enb_i)
BEGIN
addra_delay <= ADDRA AFTER COLL_DELAY;
wea_delay <= wea_i AFTER COLL_DELAY;
ena_delay <= ena_i AFTER COLL_DELAY;
addrb_delay <= ADDRB AFTER COLL_DELAY;
web_delay <= web_i AFTER COLL_DELAY;
enb_delay <= enb_i AFTER COLL_DELAY;
END PROCESS;
-- Do the checks w/rt A
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_a : BOOLEAN;
VARIABLE is_collision_delay_a : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_a := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_a := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_delay_a := collision_check(ADDRA,
wea_i/=WEA0,
addrb_delay,
web_delay/=WEB0);
ELSE
is_collision_delay_a := false;
END IF;
-- Only flag if B access is a write
IF (is_collision_a AND web_i/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_a AND web_delay/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, addrb_delay);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
-- Do the checks w/rt B
PROCESS (CLKB)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_b : BOOLEAN;
VARIABLE is_collision_delay_b : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA) /= 'X') THEN
is_collision_b := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_b := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(addra_delay) /= 'X') THEN
is_collision_delay_b := collision_check(addra_delay,
wea_delay/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_delay_b := false;
END IF;
-- Only flag if A access is a write
-- Modified condition checking (is_collision_b AND WEA0_i=/WEA0) to fix CR526228
IF (is_collision_b AND wea_i/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_b AND wea_delay/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, addra_delay);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
END GENERATE;
END mem_module_behavioral;
--******************************************************************************
-- Top module that wraps SoftECC Input register stage and the main memory module
--
-- This module is the top-level of behavioral model
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1 IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_CTRL_ECC_ALGO : STRING := "NONE";
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
--C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_SLEEP_PIN : INTEGER := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
PORT (
clka : IN STD_LOGIC := '0';
rsta : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '1';
regcea : IN STD_LOGIC := '1';
wea : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addra : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
dina : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
douta : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
clkb : IN STD_LOGIC := '0';
rstb : IN STD_LOGIC := '0';
enb : IN STD_LOGIC := '1';
regceb : IN STD_LOGIC := '1';
web : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addrb : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
dinb : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
doutb : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
injectsbiterr : IN STD_LOGIC := '0';
injectdbiterr : IN STD_LOGIC := '0';
sbiterr : OUT STD_LOGIC := '0';
dbiterr : OUT STD_LOGIC := '0';
rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : in std_logic := '0';
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic := '0';
rstb_busy : out std_logic := '0';
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
s_aclk : IN STD_LOGIC := '0';
s_aresetn : IN STD_LOGIC := '0';
-- axi full/lite slave Write (write side)
s_axi_awid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid : IN STD_LOGIC := '0';
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast : IN STD_LOGIC := '0';
s_axi_wvalid : IN STD_LOGIC := '0';
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC := '0';
-- axi full/lite slave Read (Write side)
s_axi_arid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid : IN STD_LOGIC := '0';
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_rdata : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC := '0';
-- axi full/lite sideband Signals
s_axi_injectsbiterr : IN STD_LOGIC := '0';
s_axi_injectdbiterr : IN STD_LOGIC := '0';
s_axi_sbiterr : OUT STD_LOGIC := '0';
s_axi_dbiterr : OUT STD_LOGIC := '0';
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END blk_mem_gen_v8_3_1;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE behavioral OF blk_mem_gen_v8_3_1 IS
COMPONENT blk_mem_gen_v8_3_1_mem_module
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_mem_module;
COMPONENT blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_axi_regs_fwd_v8_3;
COMPONENT blk_mem_axi_read_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT blk_mem_axi_read_wrapper_beh;
COMPONENT blk_mem_axi_write_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END COMPONENT blk_mem_axi_write_wrapper_beh;
CONSTANT FLOP_DELAY : TIME := 100 ps;
SIGNAL rsta_in : STD_LOGIC := '1';
SIGNAL ena_in : STD_LOGIC := '1';
SIGNAL regcea_in : STD_LOGIC := '1';
SIGNAL wea_in : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL addra_in : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL dina_in : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL injectsbiterr_in : STD_LOGIC := '0';
SIGNAL injectdbiterr_in : STD_LOGIC := '0';
-----------------------------------------------------------------------------
-- FUNCTION: toLowerCaseChar
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
-----------------------------------------------------------------------------
FUNCTION toLowerCaseChar(
char : character )
RETURN character IS
BEGIN
-- If char is not an upper case letter then return char
IF char<'A' OR char>'Z' THEN
RETURN char;
END IF;
-- Otherwise map char to its corresponding lower case character and
-- RETURN that
CASE char IS
WHEN 'A' => RETURN 'a';
WHEN 'B' => RETURN 'b';
WHEN 'C' => RETURN 'c';
WHEN 'D' => RETURN 'd';
WHEN 'E' => RETURN 'e';
WHEN 'F' => RETURN 'f';
WHEN 'G' => RETURN 'g';
WHEN 'H' => RETURN 'h';
WHEN 'I' => RETURN 'i';
WHEN 'J' => RETURN 'j';
WHEN 'K' => RETURN 'k';
WHEN 'L' => RETURN 'l';
WHEN 'M' => RETURN 'm';
WHEN 'N' => RETURN 'n';
WHEN 'O' => RETURN 'o';
WHEN 'P' => RETURN 'p';
WHEN 'Q' => RETURN 'q';
WHEN 'R' => RETURN 'r';
WHEN 'S' => RETURN 's';
WHEN 'T' => RETURN 't';
WHEN 'U' => RETURN 'u';
WHEN 'V' => RETURN 'v';
WHEN 'W' => RETURN 'w';
WHEN 'X' => RETURN 'x';
WHEN 'Y' => RETURN 'y';
WHEN 'Z' => RETURN 'z';
WHEN OTHERS => RETURN char;
END CASE;
END toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
FUNCTION equalIgnoreCase(
str1 : STRING;
str2 : STRING )
RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str2'left TO str1'right LOOP
IF NOT (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equalIgnoreCase;
-----------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
----------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
----------------------------------------------------------------------------
-- FUNCTION : log2roundup
----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
CONSTANT lower_limit : INTEGER := 1;
CONSTANT upper_limit : INTEGER := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
-----------------------------------------------------------------------------
-- FUNCTION : divroundup
-- Returns the ceiling value of the division
-- Data_value - the quantity to be divided, dividend
-- Divisor - the value to divide the data_value by
-----------------------------------------------------------------------------
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
SIGNAL s_axi_awaddr_out_c : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_araddr_out_c : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_wr_en_c : STD_LOGIC := '0';
SIGNAL s_axi_rd_en_c : STD_LOGIC := '0';
SIGNAL s_aresetn_a_c : STD_LOGIC := '0';
--**************************************************************************
-- AXI PARAMETERS
CONSTANT AXI_FULL_MEMORY_SLAVE : integer := if_then_else((C_AXI_SLAVE_TYPE = 0 AND C_AXI_TYPE = 1),1,0);
CONSTANT C_AXI_ADDR_WIDTH_MSB : integer := C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
CONSTANT C_AXI_ADDR_WIDTH : integer := C_AXI_ADDR_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT LOWER_BOUND_VAL : integer := if_then_else((log2roundup(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT C_AXI_ADDR_WIDTH_LSB : integer := if_then_else((AXI_FULL_MEMORY_SLAVE = 1),0,LOWER_BOUND_VAL);
CONSTANT C_AXI_OS_WR : integer := 2;
-- SAFETY LOGIC related Signals
SIGNAL RSTA_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_A : STD_LOGIC := '0';
SIGNAL RSTB_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_B : STD_LOGIC := '0';
SIGNAL ENA_dly : STD_LOGIC := '0';
SIGNAL ENA_dly_D : STD_LOGIC := '0';
SIGNAL ENB_dly : STD_LOGIC := '0';
SIGNAL ENB_dly_D : STD_LOGIC := '0';
SIGNAL RSTA_I_SAFE : STD_LOGIC := '0';
SIGNAL RSTB_I_SAFE : STD_LOGIC := '0';
SIGNAL ENA_I_SAFE : STD_LOGIC := '0';
SIGNAL ENB_I_SAFE : STD_LOGIC := '0';
SIGNAL ram_rstram_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstram_b_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_b_busy : STD_LOGIC := '0';
SIGNAL ENA_dly_reg : STD_LOGIC := '0';
SIGNAL ENB_dly_reg : STD_LOGIC := '0';
SIGNAL ENA_dly_reg_D : STD_LOGIC := '0';
SIGNAL ENB_dly_reg_D : STD_LOGIC := '0';
--**************************************************************************
BEGIN -- Architecture
--*************************************************************************
-- NO INPUT STAGE
--*************************************************************************
no_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=0) GENERATE
rsta_in <= RSTA;
ena_in <= ENA;
regcea_in <= REGCEA;
wea_in <= WEA;
addra_in <= ADDRA;
dina_in <= DINA;
injectsbiterr_in <= INJECTSBITERR;
injectdbiterr_in <= INJECTDBITERR;
END GENERATE no_input_stage;
--**************************************************************************
-- WITH INPUT STAGE
--**************************************************************************
has_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=1) GENERATE
PROCESS (CLKA)
BEGIN
IF (CLKA'EVENT AND CLKA = '1') THEN
rsta_in <= RSTA AFTER FLOP_DELAY;
ena_in <= ENA AFTER FLOP_DELAY;
regcea_in <= REGCEA AFTER FLOP_DELAY;
wea_in <= WEA AFTER FLOP_DELAY;
addra_in <= ADDRA AFTER FLOP_DELAY;
dina_in <= DINA AFTER FLOP_DELAY;
injectsbiterr_in <= INJECTSBITERR AFTER FLOP_DELAY;
injectdbiterr_in <= INJECTDBITERR AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE has_input_stage;
--**************************************************************************
-- NO SAFETY LOGIC
--**************************************************************************
NO_SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 0) GENERATE
ENA_I_SAFE <= ena_in;
ENB_I_SAFE <= ENB;
RSTA_I_SAFE <= rsta_in;
RSTB_I_SAFE <= RSTB;
END GENERATE NO_SAFETY_CKT_GEN;
--**************************************************************************
-- SAFETY LOGIC
--**************************************************************************
SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 1) GENERATE
-- RESET SAFETY LOGIC Generation
-- POR Generation
------------------------------------------------------------------------------
-- Power-ON Reset Generation
------------------------------------------------------------------------------
RST_SHFT_LOGIC_A : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
RSTA_SHFT_REG(4 DOWNTO 0) <= RSTA_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_A;
POR_RSTA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
POR_A <= RSTA_SHFT_REG(4) xor RSTA_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTA_GEN;
RST_SHFT_LOGIC_B : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
RSTB_SHFT_REG(4 DOWNTO 0) <= RSTB_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_B;
POR_RSTB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
POR_B <= RSTB_SHFT_REG(4) xor RSTB_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTB_GEN;
-----------------------------------------------------------------------------
-- Fix for the AR42571
-----------------------------------------------------------------------------
-- Reset Generation
-----------------------------------------------------------------------------
RSTA_I_SAFE <= rsta_in OR POR_A;
SPRAM_RST: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_I_SAFE <= '0';
END GENERATE SPRAM_RST;
nSPRAM_RST: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_I_SAFE <= RSTB OR POR_B;
END GENERATE nSPRAM_RST;
-----------------------------------------------------------------------------
-- RSTA/B_BUSY Generation
-----------------------------------------------------------------------------
RSTA_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
ram_rstram_a_busy <= rsta_in OR ENA_dly OR ENA_dly_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstram_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_NO_REG;
RSTA_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
ram_rstreg_a_busy <= rsta_in OR ENA_dly OR ENA_dly_reg_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstreg_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_WITH_REG;
SPRAM_RST_BUSY: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_BUSY <= '0';
END GENERATE SPRAM_RST_BUSY;
nSPRAM_RST_BUSY: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
ram_rstram_b_busy <= RSTB OR ENB_dly OR ENB_dly_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstram_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_NO_REG;
RSTB_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
ram_rstreg_b_busy <= RSTB OR ENB_dly OR ENB_dly_reg_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstreg_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_WITH_REG;
END GENERATE nSPRAM_RST_BUSY;
-----------------------------------------------------------------------------
-- ENA/ENB Generation
-----------------------------------------------------------------------------
ENA_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly <= rsta_in AFTER FLOP_DELAY;
ENA_dly_D <= ENA_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_D OR ena_in;
END GENERATE ENA_NO_REG;
ENA_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly_reg <= rsta_in AFTER FLOP_DELAY;
ENA_dly_reg_D <= ENA_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_reg_D OR ena_in;
END GENERATE ENA_WITH_REG;
SPRAM_ENB: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
ENB_I_SAFE <= '0';
END GENERATE SPRAM_ENB;
nSPRAM_ENB: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
ENB_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly <= RSTB AFTER FLOP_DELAY;
ENB_dly_D <= ENB_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_D OR ENB;
END GENERATE ENB_NO_REG;
ENB_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly_reg <= RSTB AFTER FLOP_DELAY;
ENB_dly_reg_D <= ENB_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_reg_D OR ENB;
END GENERATE ENB_WITH_REG;
END GENERATE nSPRAM_ENB;
END GENERATE SAFETY_CKT_GEN;
--**************************************************************************
-- NATIVE MEMORY MODULE INSTANCE
--**************************************************************************
native_mem_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 0) GENERATE
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,--rsta_in,
ENA => ENA_I_SAFE,--ena_in,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in,
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => RDADDRECC
);
END GENERATE native_mem_module;
--**************************************************************************
-- NATIVE MEMORY MAPPED MODULE INSTANCE
--**************************************************************************
native_mem_map_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 1) GENERATE
--**************************************************************************
-- NATIVE MEMORY MAPPED PARAMETERS
CONSTANT C_ADDRA_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_A);
CONSTANT C_ADDRB_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_B);
CONSTANT C_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
CONSTANT C_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
CONSTANT C_MEM_MAP_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_MSB;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT MEM_MAP_LOWER_BOUND_VAL_A : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT MEM_MAP_LOWER_BOUND_VAL_B : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_B,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_B,8)));
CONSTANT C_MEM_MAP_ADDRA_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_A;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_B;
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH_ACTUAL-1 DOWNTO 0) := (OTHERS => '0');
--**************************************************************************
BEGIN
RDADDRECC(C_ADDRB_WIDTH-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_MSB) <= (OTHERS => '0');
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB) <= rdaddrecc_i;
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_LSB-1 DOWNTO 0) <= (OTHERS => '0');
mem_map_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH_ACTUAL,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH_ACTUAL,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,
ENA => ENA_I_SAFE,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in(C_MEM_MAP_ADDRA_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRA_WIDTH_LSB),
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB),
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => rdaddrecc_i
);
END GENERATE native_mem_map_module;
--****************************************************************************
-- AXI MEMORY MODULE INSTANCE
--****************************************************************************
axi_mem_module: IF (C_INTERFACE_TYPE = 1) GENERATE
SIGNAL s_axi_rid_c : STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rdata_c : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rresp_c : STD_LOGIC_VECTOR(2-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rlast_c : STD_LOGIC := '0';
SIGNAL s_axi_rvalid_c : STD_LOGIC := '0';
SIGNAL s_axi_rready_c : STD_LOGIC := '0';
SIGNAL regceb_c : STD_LOGIC := '0';
BEGIN
s_aresetn_a_c <= NOT S_ARESETN;
S_AXI_BRESP <= (OTHERS => '0');
s_axi_rresp_c <= (OTHERS => '0');
no_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 0 AND C_HAS_MUX_OUTPUT_REGS_B = 0 ) GENERATE
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RLAST <= s_axi_rlast_c;
S_AXI_RVALID <= s_axi_rvalid_c;
S_AXI_RID <= s_axi_rid_c;
S_AXI_RRESP <= s_axi_rresp_c;
s_axi_rready_c <= S_AXI_RREADY;
END GENERATE no_regs;
has_regs_fwd: IF (C_HAS_MUX_OUTPUT_REGS_B = 1 OR C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
CONSTANT C_AXI_PAYLOAD : INTEGER := if_then_else((C_HAS_MUX_OUTPUT_REGS_B = 1),C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3,C_AXI_ID_WIDTH+3);
SIGNAL s_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
has_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
regceb_c <= s_axi_rvalid_c AND s_axi_rready_c;
END GENERATE has_regceb;
no_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 0) GENERATE
regceb_c <= REGCEB;
END GENERATE no_regceb;
only_core_op_regs: IF (C_HAS_MUX_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rdata_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RDATA <= m_axi_payload_c(C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_core_op_regs;
only_emb_op_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_emb_op_regs;
axi_regs_inst : blk_mem_axi_regs_fwd_v8_3
GENERIC MAP(
C_DATA_WIDTH => C_AXI_PAYLOAD
)
PORT MAP (
ACLK => S_ACLK,
ARESET => s_aresetn_a_c,
S_VALID => s_axi_rvalid_c,
S_READY => s_axi_rready_c,
S_PAYLOAD_DATA => s_axi_payload_c,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY,
M_PAYLOAD_DATA => m_axi_payload_c
);
END GENERATE has_regs_fwd;
axi_wr_fsm : blk_mem_axi_write_wrapper_beh
GENERIC MAP(
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_AXI_AWADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_WDATA_WIDTH => C_WRITE_WIDTH_A,
C_AXI_OS_WR => C_AXI_OS_WR
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Slave Write Interface
S_AXI_AWADDR => S_AXI_AWADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_AWLEN => S_AXI_AWLEN,
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BID => S_AXI_BID,
-- Signals for BRAM interface
S_AXI_AWADDR_OUT =>s_axi_awaddr_out_c,
S_AXI_WR_EN =>s_axi_wr_en_c
);
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => 1, -- For AXI, Read Enable is always C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => 1, -- For AXI C_USE_BYTE_WEA is always 1,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => 1, -- For AXI, Read Enable is always C_HAS_ENB,
C_HAS_REGCEB => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_BYTE_WEB => 1, -- For AXI C_USE_BYTE_WEB is always 1,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => 0, --For AXI, Primitive Registers A is not supported C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => 0,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
--Port A:
CLKA => S_AClk,
RSTA => s_aresetn_a_c,
ENA => s_axi_wr_en_c,
REGCEA => regcea_in,
WEA => S_AXI_WSTRB,
ADDRA => s_axi_awaddr_out_c,
DINA => S_AXI_WDATA,
DOUTA => DOUTA,
--Port B:
CLKB => S_AClk,
RSTB => s_aresetn_a_c,
ENB => s_axi_rd_en_c,
REGCEB => regceb_c,
WEB => (OTHERS => '0'),
ADDRB => s_axi_araddr_out_c,
DINB => DINB,
DOUTB => s_axi_rdata_c,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => '0',
SLEEP => '0',
RDADDRECC => RDADDRECC
);
axi_rd_sm : blk_mem_axi_read_wrapper_beh
GENERIC MAP (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_PIPELINE_STAGES => 1,
C_AXI_ARADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_AClk,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Read Side
S_AXI_ARADDR => S_AXI_ARADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARSIZE => S_AXI_ARSIZE,
S_AXI_ARBURST => S_AXI_ARBURST,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => s_axi_rlast_c,
S_AXI_RVALID => s_axi_rvalid_c,
S_AXI_RREADY => s_axi_rready_c,
S_AXI_ARID => S_AXI_ARID,
S_AXI_RID => s_axi_rid_c,
-- AXI Full/Lite Read FSM Outputs
S_AXI_ARADDR_OUT => s_axi_araddr_out_c,
S_AXI_RD_EN => s_axi_rd_en_c
);
END GENERATE axi_mem_module;
END behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_clr is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_clr;
architecture beh_ff_clr_arch of beh_ff_clr is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(CLR, C)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_clr_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_ce is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_ce;
architecture beh_ff_ce_arch of beh_ff_ce is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, CLR)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
if (CE = '1') then
q_o <= D after 100 ps;
end if;
end if;
end process;
end beh_ff_ce_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_pre is
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end beh_ff_pre;
architecture beh_ff_pre_arch of beh_ff_pre is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, PRE)
begin
if (PRE = '1') then
q_o <= '1';
elsif (C' event and C = '1') then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_pre_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_muxf7 is
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end beh_muxf7;
architecture beh_muxf7_arch of beh_muxf7 is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
else
O <= I1;
end if;
end process;
end beh_muxf7_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity STATE_LOGIC is
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic := '0';
I0 : in std_logic := '0';
I1 : in std_logic := '0';
I2 : in std_logic := '0';
I3 : in std_logic := '0';
I4 : in std_logic := '0';
I5 : in std_logic := '0'
);
end STATE_LOGIC;
architecture STATE_LOGIC_arch of STATE_LOGIC is
constant INIT_reg : std_logic_vector(63 downto 0) := INIT;
begin
LUT_beh:process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
begin
I_reg := I5 & I4 & I3 & I2 & I1 & I0;
O <= INIT_reg(conv_integer(I_reg));
end process;
end STATE_LOGIC_arch;
|
-------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v8_3_1.vhd
--
-- Description:
-- This file is the VHDL behvarial model for the
-- Block Memory Generator Core.
--
-------------------------------------------------------------------------------
-- Author: Xilinx
--
-- History: January 11, 2006: Initial revision
-- June 11, 2007 : Added independent register stages for
-- Port A and Port B (IP1_Jm/v2.5)
-- August 28, 2007 : Added mux pipeline stages feature (IP2_Jm/v2.6)
-- April 07, 2009 : Added support for Spartan-6 and Virtex-6
-- features, including the following:
-- (i) error injection, detection and/or correction
-- (ii) reset priority
-- (iii) special reset behavior
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
ENTITY blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END ENTITY blk_mem_axi_regs_fwd_v8_3;
ARCHITECTURE axi_regs_fwd_arch OF blk_mem_axi_regs_fwd_v8_3 IS
SIGNAL STORAGE_DATA : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_READY_I : STD_LOGIC := '0';
SIGNAL M_VALID_I : STD_LOGIC := '0';
SIGNAL ARESET_D : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');-- Reset delay register
BEGIN
--assign local signal to its output signal
S_READY <= S_READY_I;
M_VALID <= M_VALID_I;
PROCESS(ACLK)
BEGIN
IF(ACLK'event AND ACLK = '1') THEN
ARESET_D <= ARESET_D(0) & ARESET;
END IF;
END PROCESS;
--Save payload data whenever we have a transaction on the slave side
PROCESS(ACLK, ARESET)
BEGIN
IF (ARESET = '1') THEN
STORAGE_DATA <= (OTHERS => '0');
ELSIF(ACLK'event AND ACLK = '1') THEN
IF(S_VALID = '1' AND S_READY_I = '1') THEN
STORAGE_DATA <= S_PAYLOAD_DATA;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= STORAGE_DATA;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
PROCESS(ACLK,ARESET)
BEGIN
IF (ARESET_D /= "00") THEN
M_VALID_I <= '0';
ELSIF(ACLK'event AND ACLK = '1') THEN
IF (S_VALID = '1') THEN
--Always set M_VALID_I when slave side is valid
M_VALID_I <= '1';
ELSIF (M_READY = '1') THEN
--Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= '0';
END IF;
END IF;
END PROCESS;
--Slave Ready is either when Master side drives M_READY or we have space in our storage data
S_READY_I <= (M_READY OR (NOT M_VALID_I)) AND NOT(OR_REDUCE(ARESET_D));
END axi_regs_fwd_arch;
-------------------------------------------------------------------------------
-- Description:
-- This is the behavioral model of write_wrapper for the
-- Block Memory Generator Core.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_axi_write_wrapper_beh IS
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END blk_mem_axi_write_wrapper_beh;
ARCHITECTURE axi_write_wrap_arch OF blk_mem_axi_write_wrapper_beh IS
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_AXI_WDATA_WIDTH=8,0,
if_then_else((C_AXI_WDATA_WIDTH=16),1,
if_then_else((C_AXI_WDATA_WIDTH=32),2,
if_then_else((C_AXI_WDATA_WIDTH=64),3,
if_then_else((C_AXI_WDATA_WIDTH=128),4,
if_then_else((C_AXI_WDATA_WIDTH=256),5,0))))));
SIGNAL bvalid_c : std_logic := '0';
SIGNAL bready_timeout_c : std_logic := '0';
SIGNAL bvalid_rd_cnt_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_r : std_logic := '0';
SIGNAL bvalid_count_r : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL awaddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
C_AXI_AWADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL bvalid_wr_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_rd_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_last_c : std_logic := '0';
SIGNAL addr_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL aw_ready_r : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL awlen_cntr_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1');
SIGNAL awlen_int : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL awburst_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes : integer := 0;
SIGNAL wrap_boundary : integer := 0;
SIGNAL wrap_base_addr : integer := 0;
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
-- Array to store BIDs
TYPE id_array IS ARRAY (3 DOWNTO 0) OF std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
SIGNAL axi_bid_array : id_array := (others => (others => '0'));
COMPONENT write_netlist
GENERIC(
C_AXI_TYPE : integer
);
PORT(
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
S_AXI_AWVALID : IN std_logic;
aw_ready_r : OUT std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN std_logic;
S_AXI_WR_EN : OUT std_logic;
w_last_c : IN std_logic;
bready_timeout_c : IN std_logic;
addr_en_c : OUT std_logic;
incr_addr_c : OUT std_logic;
bvalid_c : OUT std_logic
);
END COMPONENT write_netlist;
BEGIN
---------------------------------------
--AXI WRITE FSM COMPONENT INSTANTIATION
---------------------------------------
axi_wr_fsm : write_netlist
GENERIC MAP (
C_AXI_TYPE => C_AXI_TYPE
)
PORT MAP (
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
S_AXI_AWVALID => S_AXI_AWVALID,
aw_ready_r => aw_ready_r,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BVALID => OPEN,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_WR_EN => S_AXI_WR_EN,
w_last_c => w_last_c,
bready_timeout_c => bready_timeout_c,
addr_en_c => addr_en_c,
incr_addr_c => incr_addr_c,
bvalid_c => bvalid_c
);
--Wrap Address boundary calculation
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWSIZE,"000"));
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(awlen_int)+1);
wrap_base_addr <= (conv_integer(awaddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary <= wrap_base_addr+total_bytes;
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awaddr_reg <= (OTHERS => '0');
num_of_bytes_r <= 0;
awburst_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awaddr_reg <= S_AXI_AWADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWBURST,"01");
ELSIF (incr_addr_c = '1') THEN
IF (awburst_int = "10") THEN
IF(conv_integer(awaddr_reg) = (wrap_boundary-num_of_bytes_r)) THEN
awaddr_reg <= conv_std_logic_vector(wrap_base_addr,C_AXI_AWADDR_WIDTH);
ELSE
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
ELSIF (awburst_int = "01" OR awburst_int = "11") THEN
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
S_AXI_AWADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
awaddr_reg(C_AXI_AWADDR_WIDTH-1 DOWNTO C_RANGE),awaddr_reg);
---------------------------------------------------------------------------
-- AXI wlast generation
---------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awlen_cntr_r <= (OTHERS => '1');
awlen_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awlen_int <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
awlen_cntr_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
ELSIF (dec_alen_c = '1') THEN
awlen_cntr_r <= awlen_cntr_r - ONE AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
w_last_c <= '1' WHEN (awlen_cntr_r = "00000000" AND S_AXI_WVALID = '1') ELSE '0';
dec_alen_c <= (incr_addr_c OR w_last_c);
---------------------------------------------------------------------------
-- Generation of bvalid counter for outstanding transactions
---------------------------------------------------------------------------
P_b_valid_os_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_count_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- bvalid_count_r generation
IF (bvalid_c = '1' AND bvalid_r = '1' AND S_AXI_BREADY = '1') THEN
bvalid_count_r <= bvalid_count_r AFTER FLOP_DELAY;
ELSIF (bvalid_c = '1') THEN
bvalid_count_r <= bvalid_count_r + "01" AFTER FLOP_DELAY;
ELSIF (bvalid_r = '1' AND S_AXI_BREADY = '1' AND bvalid_count_r /= "0") THEN
bvalid_count_r <= bvalid_count_r - "01" AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_os_r ;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is used
---------------------------------------------------------------------------
gaxi_bvalid_id_r:IF (C_HAS_AXI_ID = 1) GENERATE
SIGNAL bvalid_d1_c : std_logic := '0';
BEGIN
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
bvalid_d1_c <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
--external bvalid signal generation
IF (bvalid_d1_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_id_r;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is not used
---------------------------------------------------------------------------
gaxi_bvalid_noid_r:IF (C_HAS_AXI_ID = 0) GENERATE
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
--external bvalid signal generation
IF (bvalid_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_noid_r;
---------------------------------------------------------------------------
-- Generation of Bready timeout
---------------------------------------------------------------------------
P_brdy_tout_c: PROCESS (bvalid_count_r)
BEGIN
-- bready_timeout_c generation
IF(conv_integer(bvalid_count_r) = C_AXI_OS_WR-1) THEN
bready_timeout_c <= '1';
ELSE
bready_timeout_c <= '0';
END IF;
END PROCESS P_brdy_tout_c;
---------------------------------------------------------------------------
-- Generation of BID
---------------------------------------------------------------------------
gaxi_bid_gen:IF (C_HAS_AXI_ID = 1) GENERATE
P_bid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
bvalid_wr_cnt_r <= (OTHERS => '0');
bvalid_rd_cnt_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- STORE AWID IN AN ARRAY
IF(bvalid_c = '1') THEN
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + "01";
END IF;
-- GENERATE BID FROM AWID ARRAY
bvalid_rd_cnt_r <= bvalid_rd_cnt_c AFTER FLOP_DELAY;
S_AXI_BID <= axi_bid_array(conv_integer(bvalid_rd_cnt_c));
END IF;
END PROCESS P_bid_gen;
bvalid_rd_cnt_c <= bvalid_rd_cnt_r + "01" WHEN (bvalid_r = '1' AND S_AXI_BREADY = '1') ELSE bvalid_rd_cnt_r;
---------------------------------------------------------------------------
-- Storing AWID for generation of BID
---------------------------------------------------------------------------
P_awid_reg:PROCESS (S_ACLK)
BEGIN
IF (S_ACLK'event AND S_ACLK='1') THEN
IF(aw_ready_r = '1' AND S_AXI_AWVALID = '1') THEN
axi_bid_array(conv_integer(bvalid_wr_cnt_r)) <= S_AXI_AWID;
END IF;
END IF;
END PROCESS P_awid_reg;
END GENERATE gaxi_bid_gen;
S_AXI_BVALID <= bvalid_r;
S_AXI_AWREADY <= aw_ready_r;
END axi_write_wrap_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity write_netlist is
GENERIC(
C_AXI_TYPE : integer
);
port (
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_AWVALID : in STD_LOGIC := '0';
S_AXI_WVALID : in STD_LOGIC := '0';
S_AXI_BREADY : in STD_LOGIC := '0';
w_last_c : in STD_LOGIC := '0';
bready_timeout_c : in STD_LOGIC := '0';
aw_ready_r : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_WR_EN : out STD_LOGIC;
addr_en_c : out STD_LOGIC;
incr_addr_c : out STD_LOGIC;
bvalid_c : out STD_LOGIC
);
end write_netlist;
architecture STRUCTURE of write_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
BEGIN
---------------------------------------------------------------------------
-- AXI LITE
---------------------------------------------------------------------------
gbeh_axi_lite_sm: IF (C_AXI_TYPE = 0 ) GENERATE
signal w_ready_r_7 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSignal_bvalid_c : STD_LOGIC;
signal NlwRenamedSignal_incr_addr_c : STD_LOGIC;
signal present_state_FSM_FFd3_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal present_state_FSM_FFd1_15 : STD_LOGIC;
signal present_state_FSM_FFd4_16 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd4_In1_21 : STD_LOGIC;
signal Mmux_aw_ready_c : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
S_AXI_WREADY <= w_ready_r_7;
S_AXI_BVALID <= NlwRenamedSignal_incr_addr_c;
S_AXI_WR_EN <= NlwRenamedSignal_bvalid_c;
incr_addr_c <= NlwRenamedSignal_incr_addr_c;
bvalid_c <= NlwRenamedSignal_bvalid_c;
NlwRenamedSignal_incr_addr_c <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_7
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_16
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_13
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_15
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000055554440"
)
port map (
I0 => S_AXI_WVALID,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => '0',
O => present_state_FSM_FFd3_In
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"0000000088880800"
)
port map (
I0 => S_AXI_AWVALID,
I1 => S_AXI_WVALID,
I2 => bready_timeout_c,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => present_state_FSM_FFd2_In
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAA2000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_WVALID,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => addr_en_c
);
Mmux_w_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"F5F07570F5F05500"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => w_ready_c
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd3_13,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd1_15,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_14,
I2 => present_state_FSM_FFd3_13,
I3 => '0',
I4 => '0',
I5 => '0',
O => NlwRenamedSignal_bvalid_c
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"2F0F27072F0F2200"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => present_state_FSM_FFd4_In1_21
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_In1_21,
I3 => '0',
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_aw_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"7535753575305500"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => S_AXI_WVALID,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => present_state_FSM_FFd2_14,
O => Mmux_aw_ready_c(0)
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => Mmux_aw_ready_c(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => aw_ready_c
);
END GENERATE gbeh_axi_lite_sm;
---------------------------------------------------------------------------
-- AXI FULL
---------------------------------------------------------------------------
gbeh_axi_full_sm: IF (C_AXI_TYPE = 1 ) GENERATE
signal w_ready_r_8 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSig_OI_bvalid_c : STD_LOGIC;
signal present_state_FSM_FFd1_16 : STD_LOGIC;
signal present_state_FSM_FFd4_17 : STD_LOGIC;
signal present_state_FSM_FFd3_18 : STD_LOGIC;
signal present_state_FSM_FFd2_19 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd2_In1_24 : STD_LOGIC;
signal present_state_FSM_FFd4_In1_25 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal N4 : STD_LOGIC;
begin
S_AXI_WREADY <= w_ready_r_8;
bvalid_c <= NlwRenamedSig_OI_bvalid_c;
S_AXI_BVALID <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_8
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_17
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_18
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_19
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_16
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000000005540"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd4_17,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd3_In
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"BF3FBB33AF0FAA00"
)
port map (
I0 => S_AXI_BREADY,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd1_16,
I4 => present_state_FSM_FFd4_17,
I5 => NlwRenamedSig_OI_bvalid_c,
O => aw_ready_c
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"AAAAAAAA20000000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_19,
I3 => S_AXI_WVALID,
I4 => w_last_c,
I5 => present_state_FSM_FFd4_17,
O => addr_en_c
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_19,
I2 => present_state_FSM_FFd3_18,
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_WR_EN
);
Mmux_incr_addr_c_0_1 : STATE_LOGIC
generic map(
INIT => X"0000000000002220"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => incr_addr_c
);
Mmux_aw_ready_c_0_11 : STATE_LOGIC
generic map(
INIT => X"0000000000008880"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => NlwRenamedSig_OI_bvalid_c
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"000000000000D5C0"
)
port map (
I0 => w_last_c,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd4_17,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd2_In1_24
);
present_state_FSM_FFd2_In2 : STATE_LOGIC
generic map(
INIT => X"FFFFAAAA08AAAAAA"
)
port map (
I0 => present_state_FSM_FFd2_19,
I1 => S_AXI_AWVALID,
I2 => bready_timeout_c,
I3 => w_last_c,
I4 => S_AXI_WVALID,
I5 => present_state_FSM_FFd2_In1_24,
O => present_state_FSM_FFd2_In
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"00C0004000C00000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => w_last_c,
I2 => S_AXI_WVALID,
I3 => bready_timeout_c,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => present_state_FSM_FFd4_In1_25
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88F8"
)
port map (
I0 => present_state_FSM_FFd1_16,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_17,
I3 => S_AXI_AWVALID,
I4 => present_state_FSM_FFd4_In1_25,
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_w_ready_c_0_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => w_last_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_w_ready_c_0_Q : STATE_LOGIC
generic map(
INIT => X"FABAFABAFAAAF000"
)
port map (
I0 => N2,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd4_17,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => w_ready_c
);
Mmux_aw_ready_c_0_11_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => bready_timeout_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => w_last_c,
I1 => N4,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => present_state_FSM_FFd1_16,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
END GENERATE gbeh_axi_full_sm;
end STRUCTURE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--AXI Behavioral Model entities
ENTITY blk_mem_axi_read_wrapper_beh is
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
port (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END blk_mem_axi_read_wrapper_beh;
architecture blk_mem_axi_read_wrapper_beh_arch of blk_mem_axi_read_wrapper_beh is
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_WRITE_WIDTH_A=8,0,
if_then_else((C_WRITE_WIDTH_A=16),1,
if_then_else((C_WRITE_WIDTH_A=32),2,
if_then_else((C_WRITE_WIDTH_A=64),3,
if_then_else((C_WRITE_WIDTH_A=128),4,
if_then_else((C_WRITE_WIDTH_A=256),5,0))))));
SIGNAL ar_id_r : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
SIGNAL addr_en_c : std_logic := '0';
SIGNAL rd_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL single_trans_c : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL mux_sel_c : std_logic := '0';
SIGNAL r_last_c : std_logic := '0';
SIGNAL r_last_int_c : std_logic := '0';
SIGNAL arlen_int_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL arlen_cntr : std_logic_vector(7 DOWNTO 0) := ONE;
SIGNAL arburst_int_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL arburst_int_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL araddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),C_AXI_ARADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL total_bytes : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
SIGNAL wrap_base_addr_r : integer := 0;
SIGNAL wrap_boundary_r : integer := 0;
SIGNAL arlen_int_c : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes_c : integer := 0;
SIGNAL wrap_base_addr_c : integer := 0;
SIGNAL wrap_boundary_c : integer := 0;
SIGNAL araddr_out : std_logic_vector(C_ADDRB_WIDTH-1 downto 0) := (OTHERS => '0');
COMPONENT read_netlist
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_INCR_ADDR : OUT std_logic := '0';
S_AXI_ADDR_EN : OUT std_logic := '0';
S_AXI_SINGLE_TRANS : OUT std_logic := '0';
S_AXI_MUX_SEL : OUT std_logic := '0';
S_AXI_R_LAST : OUT std_logic := '0';
S_AXI_R_LAST_INT : IN std_logic := '0';
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT read_netlist;
BEGIN
dec_alen_c <= incr_addr_c OR r_last_int_c;
axi_read_fsm : read_netlist
GENERIC MAP(
C_AXI_TYPE => 1,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
S_AXI_INCR_ADDR => incr_addr_c,
S_AXI_ADDR_EN => addr_en_c,
S_AXI_SINGLE_TRANS => single_trans_c,
S_AXI_MUX_SEL => mux_sel_c,
S_AXI_R_LAST => r_last_c,
S_AXI_R_LAST_INT => r_last_int_c,
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN => rd_en_c
);
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(arlen_int_r)+1);
wrap_base_addr_r <= (conv_integer(araddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary_r <= wrap_base_addr_r+total_bytes;
---- combinatorial from interface
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARSIZE,"000"));
arlen_int_c <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
total_bytes_c <= conv_integer(num_of_bytes_c)*(conv_integer(arlen_int_c)+1);
wrap_base_addr_c <= (conv_integer(S_AXI_ARADDR)/if_then_else(total_bytes_c=0,1,total_bytes_c))*(total_bytes_c);
wrap_boundary_c <= wrap_base_addr_c+total_bytes_c;
arburst_int_c <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARBURST,"01");
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
araddr_reg <= (OTHERS => '0');
arburst_int_r <= (OTHERS => '0');
num_of_bytes_r <= 0;
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (incr_addr_c = '1' AND addr_en_c = '1' AND single_trans_c = '0') THEN
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
IF (arburst_int_c = "10") THEN
IF(conv_integer(S_AXI_ARADDR) = (wrap_boundary_c-num_of_bytes_c)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_c,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (arburst_int_c = "01" OR arburst_int_c = "11") THEN
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (addr_en_c = '1') THEN
araddr_reg <= S_AXI_ARADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
ELSIF (incr_addr_c = '1') THEN
IF (arburst_int_r = "10") THEN
IF(conv_integer(araddr_reg) = (wrap_boundary_r-num_of_bytes_r)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_r,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
ELSIF (arburst_int_r = "01" OR arburst_int_r = "11") THEN
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
araddr_out <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),araddr_reg(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),araddr_reg);
--------------------------------------------------------------------------
-- Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
--------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF S_ARESETN = '1' THEN
arlen_cntr <= ONE;
arlen_int_r <= (OTHERS => '0');
ELSIF S_ACLK'event AND S_ACLK = '1' THEN
IF (addr_en_c = '1' AND dec_alen_c = '1' AND single_trans_c = '0') THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= S_AXI_ARLEN - ONE AFTER FLOP_DELAY;
ELSIF addr_en_c = '1' THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
ELSIF dec_alen_c = '1' THEN
arlen_cntr <= arlen_cntr - ONE AFTER FLOP_DELAY;
ELSE
arlen_cntr <= arlen_cntr AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
r_last_int_c <= '1' WHEN (arlen_cntr = "00000000" AND S_AXI_RREADY = '1') ELSE '0' ;
--------------------------------------------------------------------------
-- AXI FULL FSM
-- Mux Selection of ARADDR
-- ARADDR is driven out from the read fsm based on the mux_sel_c
-- Based on mux_sel either ARADDR is given out or the latched ARADDR is
-- given out to BRAM
--------------------------------------------------------------------------
P_araddr_mux: PROCESS (mux_sel_c,S_AXI_ARADDR,araddr_out)
BEGIN
IF (mux_sel_c = '0') THEN
S_AXI_ARADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARADDR(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),S_AXI_ARADDR);
ELSE
S_AXI_ARADDR_OUT <= araddr_out;
END IF;
END PROCESS P_araddr_mux;
--------------------------------------------------------------------------
-- Assign output signals - AXI FULL FSM
--------------------------------------------------------------------------
S_AXI_RD_EN <= rd_en_c;
grid: IF (C_HAS_AXI_ID = 1) GENERATE
P_rid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
S_AXI_RID <= (OTHERS => '0');
ar_id_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
IF (addr_en_c = '1' AND rd_en_c = '1') THEN
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
ELSIF (addr_en_c = '1' AND rd_en_c = '0') THEN
ar_id_r <= S_AXI_ARID;
ELSIF (rd_en_c = '1') THEN
S_AXI_RID <= ar_id_r;
END IF;
END IF;
END PROCESS P_rid_gen;
END GENERATE grid;
END blk_mem_axi_read_wrapper_beh_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity read_netlist is
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_R_LAST_INT : in STD_LOGIC := '0';
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_ARVALID : in STD_LOGIC := '0';
S_AXI_RREADY : in STD_LOGIC := '0';
S_AXI_INCR_ADDR : out STD_LOGIC;
S_AXI_ADDR_EN : out STD_LOGIC;
S_AXI_SINGLE_TRANS : out STD_LOGIC;
S_AXI_MUX_SEL : out STD_LOGIC;
S_AXI_R_LAST : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RLAST : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RD_EN : out STD_LOGIC;
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end read_netlist;
architecture STRUCTURE of read_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
signal present_state_FSM_FFd1_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_r_15 : STD_LOGIC;
signal gaxi_full_sm_ar_ready_r_16 : STD_LOGIC;
signal gaxi_full_sm_r_last_r_17 : STD_LOGIC;
signal NlwRenamedSig_OI_gaxi_full_sm_r_valid_r : STD_LOGIC;
signal gaxi_full_sm_r_valid_c : STD_LOGIC;
signal S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o : STD_LOGIC;
signal gaxi_full_sm_ar_ready_c : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_c : STD_LOGIC;
signal NlwRenamedSig_OI_S_AXI_R_LAST : STD_LOGIC;
signal S_AXI_ARLEN_7_GND_8_o_equal_1_o : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal Mmux_S_AXI_R_LAST13 : STD_LOGIC;
signal N01 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal Mmux_gaxi_full_sm_ar_ready_c11 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N8 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N13 : STD_LOGIC;
begin
S_AXI_R_LAST <= NlwRenamedSig_OI_S_AXI_R_LAST;
S_AXI_ARREADY <= gaxi_full_sm_ar_ready_r_16;
S_AXI_RLAST <= gaxi_full_sm_r_last_r_17;
S_AXI_RVALID <= NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
gaxi_full_sm_outstanding_read_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_outstanding_read_c,
Q => gaxi_full_sm_outstanding_read_r_15
);
gaxi_full_sm_r_valid_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => gaxi_full_sm_r_valid_c,
Q => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r
);
gaxi_full_sm_ar_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_ar_ready_c,
Q => gaxi_full_sm_ar_ready_r_16
);
gaxi_full_sm_r_last_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => NlwRenamedSig_OI_S_AXI_R_LAST,
Q => gaxi_full_sm_r_last_r_17
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_13
);
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 : STATE_LOGIC
generic map(
INIT => X"000000000000000B"
)
port map (
I0 => S_AXI_RREADY,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o
);
Mmux_S_AXI_SINGLE_TRANS11 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_SINGLE_TRANS
);
Mmux_S_AXI_ADDR_EN11 : STATE_LOGIC
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_ADDR_EN
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"ECEE2022EEEE2022"
)
port map (
I0 => S_AXI_ARVALID,
I1 => present_state_FSM_FFd1_13,
I2 => S_AXI_RREADY,
I3 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I4 => present_state_FSM_FFd2_14,
I5 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
O => present_state_FSM_FFd2_In
);
Mmux_S_AXI_R_LAST131 : STATE_LOGIC
generic map(
INIT => X"0000000044440444"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_RREADY,
I5 => '0',
O => Mmux_S_AXI_R_LAST13
);
Mmux_S_AXI_INCR_ADDR11 : STATE_LOGIC
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => S_AXI_R_LAST_INT,
I1 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => Mmux_S_AXI_R_LAST13,
O => S_AXI_INCR_ADDR
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000FE"
)
port map (
I0 => S_AXI_ARLEN(2),
I1 => S_AXI_ARLEN(1),
I2 => S_AXI_ARLEN(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => N01
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q : STATE_LOGIC
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => S_AXI_ARLEN(7),
I1 => S_AXI_ARLEN(6),
I2 => S_AXI_ARLEN(5),
I3 => S_AXI_ARLEN(4),
I4 => S_AXI_ARLEN(3),
I5 => N01,
O => S_AXI_ARLEN_7_GND_8_o_equal_1_o
);
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_gaxi_full_sm_outstanding_read_c1 : STATE_LOGIC
generic map(
INIT => X"0020000002200200"
)
port map (
I0 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd1_13,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => N2,
O => gaxi_full_sm_outstanding_read_c
);
Mmux_gaxi_full_sm_ar_ready_c12 : STATE_LOGIC
generic map(
INIT => X"0000000000004555"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => '0',
I5 => '0',
O => Mmux_gaxi_full_sm_ar_ready_c11
);
Mmux_S_AXI_R_LAST11_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000EF"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
Mmux_S_AXI_R_LAST11 : STATE_LOGIC
generic map(
INIT => X"FCAAFC0A00AA000A"
)
port map (
I0 => S_AXI_ARVALID,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => N4,
I5 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
O => gaxi_full_sm_r_valid_c
);
S_AXI_MUX_SEL1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAAAA08"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => '0',
O => S_AXI_MUX_SEL
);
Mmux_S_AXI_RD_EN11 : STATE_LOGIC
generic map(
INIT => X"F3F3F755A2A2A200"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => gaxi_full_sm_outstanding_read_r_15,
I4 => present_state_FSM_FFd2_14,
I5 => S_AXI_ARVALID,
O => S_AXI_RD_EN
);
present_state_FSM_FFd1_In3 : beh_muxf7
port map (
I0 => N8,
I1 => N9,
S => present_state_FSM_FFd1_13,
O => present_state_FSM_FFd1_In
);
present_state_FSM_FFd1_In3_F : STATE_LOGIC
generic map(
INIT => X"000000005410F4F0"
)
port map (
I0 => S_AXI_RREADY,
I1 => present_state_FSM_FFd2_14,
I2 => S_AXI_ARVALID,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => '0',
O => N8
);
present_state_FSM_FFd1_In3_G : STATE_LOGIC
generic map(
INIT => X"0000000072FF7272"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N9
);
Mmux_gaxi_full_sm_ar_ready_c14 : beh_muxf7
port map (
I0 => N10,
I1 => N11,
S => present_state_FSM_FFd1_13,
O => gaxi_full_sm_ar_ready_c
);
Mmux_gaxi_full_sm_ar_ready_c14_F : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88A8"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => Mmux_gaxi_full_sm_ar_ready_c11,
I5 => '0',
O => N10
);
Mmux_gaxi_full_sm_ar_ready_c14_G : STATE_LOGIC
generic map(
INIT => X"000000008D008D8D"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N11
);
Mmux_S_AXI_R_LAST1 : beh_muxf7
port map (
I0 => N12,
I1 => N13,
S => present_state_FSM_FFd1_13,
O => NlwRenamedSig_OI_S_AXI_R_LAST
);
Mmux_S_AXI_R_LAST1_F : STATE_LOGIC
generic map(
INIT => X"0000000088088888"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N12
);
Mmux_S_AXI_R_LAST1_G : STATE_LOGIC
generic map(
INIT => X"00000000E400E4E4"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => S_AXI_R_LAST_INT,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N13
);
end STRUCTURE;
-------------------------------------------------------------------------------
-- Output Register Stage Entity
--
-- This module builds the output register stages of the memory. This module is
-- instantiated in the main memory module (blk_mem_gen_v8_3_1) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_output_stage IS
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_output_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6" and "virtex6l".
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
-- C_HAS_RST : Determines the presence of the RST port
-- C_RSTRAM : Determines if special reset behavior is used
-- C_RST_PRIORITY : Determines the priority between CE and SR
-- C_INIT_VAL : Initialization value
-- C_HAS_EN : Determines the presence of the EN port
-- C_HAS_REGCE : Determines the presence of the REGCE port
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
-- of the RAM primitive
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- NUM_STAGES : Determines the number of output stages
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE output_stage_behavioral OF blk_mem_gen_v8_3_1_output_stage IS
--*******************************************************
-- Functions used in the output stage ARCHITECTURE
--*******************************************************
-- Calculate num_reg_stages
FUNCTION get_num_reg_stages(NUM_STAGES: INTEGER) RETURN INTEGER IS
VARIABLE num_reg_stages : INTEGER := 0;
BEGIN
IF (NUM_STAGES = 0) THEN
num_reg_stages := 0;
ELSE
num_reg_stages := NUM_STAGES - 1;
END IF;
RETURN num_reg_stages;
END get_num_reg_stages;
-- Check if the INTEGER is zero or non-zero
FUNCTION int_to_bit(input: INTEGER) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = 0) THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END int_to_bit;
-- Constants
CONSTANT HAS_EN : STD_LOGIC := int_to_bit(C_HAS_EN);
CONSTANT HAS_REGCE : STD_LOGIC := int_to_bit(C_HAS_REGCE);
CONSTANT HAS_RST : STD_LOGIC := int_to_bit(C_HAS_RST);
CONSTANT REG_STAGES : INTEGER := get_num_reg_stages(NUM_STAGES);
-- Pipeline array
TYPE reg_data_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
TYPE reg_ecc_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC;
TYPE reg_eccaddr_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
CONSTANT REG_INIT : reg_data_array := (OTHERS => init_val);
SIGNAL out_regs : reg_data_array := REG_INIT;
SIGNAL sbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL dbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL rdaddrecc_regs: reg_eccaddr_array := (OTHERS => (OTHERS => '0'));
-- Internal signals
SIGNAL en_i : STD_LOGIC;
SIGNAL regce_i : STD_LOGIC;
SIGNAL rst_i : STD_LOGIC;
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := init_val;
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL DIN : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL RDADDRECC_IN : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ;
SIGNAL SBITERR_IN : STD_LOGIC := '0';
SIGNAL DBITERR_IN : STD_LOGIC := '0';
BEGIN
--***********************************************************************
-- Assign internal signals. This effectively wires off optional inputs.
--***********************************************************************
-- Internal enable for output registers is tied to user EN or '1' depending
-- on parameters
en_i <= EN OR (NOT HAS_EN);
-- Internal register enable for output registers is tied to user REGCE, EN
-- or '1' depending on parameters
regce_i <= (HAS_REGCE AND REGCE)
OR ((NOT HAS_REGCE) AND en_i);
-- Internal SRR is tied to user RST or '0' depending on parameters
rst_i <= RST AND HAS_RST;
--***************************************************************************
-- NUM_STAGES = 0 (No output registers. RAM only)
--***************************************************************************
zero_stages: IF (NUM_STAGES = 0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE zero_stages;
NO_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 0) GENERATE
DIN <= DIN_I;
RDADDRECC_IN <= RDADDRECC_IN_I;
SBITERR_IN <= SBITERR_IN_I;
DBITERR_IN <= DBITERR_IN_I;
END GENERATE NO_ECC_PIPE_REG;
WITH_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(ECCPIPECE = '1') THEN
DIN <= DIN_I AFTER FLOP_DELAY;
RDADDRECC_IN <= RDADDRECC_IN_I AFTER FLOP_DELAY;
SBITERR_IN <= SBITERR_IN_I AFTER FLOP_DELAY;
DBITERR_IN <= DBITERR_IN_I AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS;
END GENERATE WITH_ECC_PIPE_REG;
--***************************************************************************
-- NUM_STAGES = 1
-- (Mem Output Reg only or Mux Output Reg only)
--***************************************************************************
-- Possible valid combinations:
-- Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
-- +-----------------------------------------+
-- | C_RSTRAM_* | Reset Behavior |
-- +----------------+------------------------+
-- | 0 | Normal Behavior |
-- +----------------+------------------------+
-- | 1 | Special Behavior |
-- +----------------+------------------------+
--
-- Normal = REGCE gates reset, as in the case of all Virtex families and all
-- spartan families with the exception of S3ADSP and S6.
-- Special = EN gates reset, as in the case of S3ADSP and S6.
one_stage_norm: IF (NUM_STAGES = 1 AND
(C_RSTRAM=0 OR (C_RSTRAM=1 AND (C_XDEVICEFAMILY/="spartan3adsp" AND C_XDEVICEFAMILY/="aspartan3adsp")) OR
C_HAS_MEM_OUTPUT_REGS=0 OR C_HAS_RST=0)) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i = '1' AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
END IF;--CLK
END PROCESS;
END GENERATE one_stage_norm;
-- Special Reset Behavior for S6 and S3ADSP
one_stage_splbhv: IF (NUM_STAGES=1 AND C_RSTRAM=1 AND (C_XDEVICEFAMILY ="spartan3adsp" OR C_XDEVICEFAMILY ="aspartan3adsp"))
GENERATE
DOUT <= dout_i;
SBITERR <= '0';
DBITERR <= '0';
RDADDRECC <= (OTHERS => '0');
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (rst_i='1' AND en_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
ELSIF (regce_i='1' AND rst_i/='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE one_stage_splbhv;
--****************************************************************************
-- NUM_STAGES > 1
-- Mem Output Reg + Mux Output Reg
-- or
-- Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
-- or
-- Mux Pipeline Stages (>0) + Mux Output Reg
--****************************************************************************
multi_stage: IF (NUM_STAGES > 1) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i='1'AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
IF (en_i='1') THEN
-- Shift the data through the output stages
FOR i IN 1 TO REG_STAGES-1 LOOP
out_regs(i) <= out_regs(i-1) AFTER FLOP_DELAY;
sbiterr_regs(i) <= sbiterr_regs(i-1) AFTER FLOP_DELAY;
dbiterr_regs(i) <= dbiterr_regs(i-1) AFTER FLOP_DELAY;
rdaddrecc_regs(i) <= rdaddrecc_regs(i-1) AFTER FLOP_DELAY;
END LOOP;
out_regs(0) <= DIN;
sbiterr_regs(0) <= SBITERR_IN;
dbiterr_regs(0) <= DBITERR_IN;
rdaddrecc_regs(0) <= RDADDRECC_IN;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE multi_stage;
END output_stage_behavioral;
-------------------------------------------------------------------------------
-- SoftECC Output Register Stage Entity
-- This module builds the softecc output register stages. This module is
-- instantiated in the memory module (blk_mem_gen_v8_3_1_mem_module) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ;
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- of the RAM primitive
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE softecc_output_reg_stage_behavioral OF blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
-- Internal signals
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
--***************************************************************************
-- NO OUTPUT STAGES
--***************************************************************************
no_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE no_output_stage;
--****************************************************************************
-- WITH OUTPUT STAGE
--****************************************************************************
has_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END PROCESS;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
END GENERATE has_output_stage;
END softecc_output_reg_stage_behavioral;
--******************************************************************************
-- Main Memory module
--
-- This module is the behavioral model which implements the RAM
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
ENTITY blk_mem_gen_v8_3_1_mem_module IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_mem_module;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE mem_module_behavioral OF blk_mem_gen_v8_3_1_mem_module IS
--****************************************
-- min/max constant functions
--****************************************
-- get_max
----------
function SLV_TO_INT(SLV: in std_logic_vector
) return integer is
variable int : integer;
begin
int := 0;
for i in SLV'high downto SLV'low loop
int := int * 2;
if SLV(i) = '1' then
int := int + 1;
end if;
end loop;
return int;
end;
FUNCTION get_max(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a > b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-- get_min
----------
FUNCTION get_min(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
--***************************************************************
-- convert write_mode from STRING type for use in case statement
--***************************************************************
FUNCTION write_mode_to_vector(mode: STRING) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF (mode = "NO_CHANGE") THEN
RETURN "10";
ELSIF (mode = "READ_FIRST") THEN
RETURN "01";
ELSE
RETURN "00"; -- WRITE_FIRST
END IF;
END FUNCTION;
--***************************************************************
-- convert hex STRING to STD_LOGIC_VECTOR
--***************************************************************
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
--***************************************************************
-- locally derived constants to determine memory shape
--***************************************************************
CONSTANT MIN_WIDTH_A : INTEGER := get_min(C_WRITE_WIDTH_A, C_READ_WIDTH_A);
CONSTANT MIN_WIDTH_B : INTEGER := get_min(C_WRITE_WIDTH_B,C_READ_WIDTH_B);
CONSTANT MIN_WIDTH : INTEGER := get_min(MIN_WIDTH_A, MIN_WIDTH_B);
CONSTANT MAX_DEPTH_A : INTEGER := get_max(C_WRITE_DEPTH_A, C_READ_DEPTH_A);
CONSTANT MAX_DEPTH_B : INTEGER := get_max(C_WRITE_DEPTH_B, C_READ_DEPTH_B);
CONSTANT MAX_DEPTH : INTEGER := get_max(MAX_DEPTH_A, MAX_DEPTH_B);
TYPE int_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF std_logic_vector(C_WRITE_WIDTH_A-1 DOWNTO 0);
TYPE mem_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC_VECTOR(MIN_WIDTH-1 DOWNTO 0);
TYPE ecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
TYPE softecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
--***************************************************************
-- memory initialization function
--***************************************************************
IMPURE FUNCTION init_memory(DEFAULT_DATA :
STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
write_width_a : INTEGER;
depth : INTEGER;
width : INTEGER)
RETURN mem_array IS
VARIABLE init_return : mem_array := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(write_width_a-1 DOWNTO 0);
VARIABLE int_mem_vector : int_array:= (OTHERS => (OTHERS => '0'));
VARIABLE file_buffer : LINE;
VARIABLE i : INTEGER := 0;
VARIABLE j : INTEGER;
VARIABLE k : INTEGER;
VARIABLE ignore_line : BOOLEAN := false;
VARIABLE good_data : BOOLEAN := false;
VARIABLE char_tmp : CHARACTER;
VARIABLE index : INTEGER;
variable init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable data : std_logic_vector(255 downto 0) := (others => '0');
variable inside_init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable k_slv : std_logic_vector(31 downto 0) := (others => '0');
variable i_slv : std_logic_vector(31 downto 0) := (others => '0');
VARIABLE disp_line : line := null;
variable open_status : file_open_status;
variable input_initf_tmp : mem_array ;
variable input_initf : mem_array := (others => (others => '0'));
file int_infile : text;
variable data_line, data_line_tmp, out_data_line : line;
variable slv_width : integer;
VARIABLE d_l : LINE;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
index := 0;
FOR i IN 0 TO depth-1 LOOP
FOR j IN 0 TO width-1 LOOP
init_return(i)(j) := DEFAULT_DATA(index);
index := (index + 1) MOD C_WRITE_WIDTH_A;
END LOOP;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, file_buffer);
read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO write_width_a-1 LOOP
IF (j MOD width = 0 AND j /= 0) THEN
i := i + 1;
END IF;
init_return(i)(j MOD width) := bit_to_sl(mem_vector(j));
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
--Display output message indicating that the behavioral model is done
--initializing
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator data initialization complete." SEVERITY NOTE;
if (C_USE_BRAM_BLOCK = 1) then
--Display output message indicating that the behavioral model is being
--initialized
-- Read in the .mem file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_INIT_FILE /= "NONE") then
file_open(open_status, int_infile, C_INIT_FILE, read_mode);
while not endfile(int_infile) loop
readline(int_infile, data_line);
while (data_line /= null and data_line'length > 0) loop
if (data_line(data_line'low to data_line'low + 1) = "//") then
deallocate(data_line);
elsif ((data_line(data_line'low to data_line'low + 1) = "/*") and (data_line(data_line'high-1 to data_line'high) = "*/")) then
deallocate(data_line);
elsif (data_line(data_line'low to data_line'low + 1) = "/*") then
deallocate(data_line);
ignore_line := true;
elsif (ignore_line = true and data_line(data_line'high-1 to data_line'high) = "*/") then
deallocate(data_line);
ignore_line := false;
elsif (ignore_line = false and data_line(data_line'low) = '@') then
read(data_line, char_tmp);
hread(data_line, init_addr_slv, good_data);
i := SLV_TO_INT(init_addr_slv);
elsif (ignore_line = false) then
hread(data_line, input_initf_tmp(i), good_data);
init_return(i)(write_width_a - 1 downto 0) := input_initf_tmp(i)(write_width_a - 1 downto 0);
if (good_data = true) then
i := i + 1;
end if;
else
deallocate(data_line);
end if;
end loop;
end loop;
file_close(int_infile);
END IF;
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- memory type constants
--***************************************************************
CONSTANT MEM_TYPE_SP_RAM : INTEGER := 0;
CONSTANT MEM_TYPE_SDP_RAM : INTEGER := 1;
CONSTANT MEM_TYPE_TDP_RAM : INTEGER := 2;
CONSTANT MEM_TYPE_SP_ROM : INTEGER := 3;
CONSTANT MEM_TYPE_DP_ROM : INTEGER := 4;
--***************************************************************
-- memory configuration constant functions
--***************************************************************
--get_single_port
-----------------
FUNCTION get_single_port(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_RAM OR mem_type=MEM_TYPE_SP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_single_port;
--get_is_rom
--------------
FUNCTION get_is_rom(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_ROM OR mem_type=MEM_TYPE_DP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_is_rom;
--get_has_a_write
------------------
FUNCTION get_has_a_write(IS_ROM : INTEGER) RETURN INTEGER IS
BEGIN
IF (IS_ROM=0) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_a_write;
--get_has_b_write
------------------
FUNCTION get_has_b_write(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_TDP_RAM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_write;
--get_has_a_read
------------------
FUNCTION get_has_a_read(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SDP_RAM) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_a_read;
--get_has_b_read
------------------
FUNCTION get_has_b_read(SINGLE_PORT : INTEGER) RETURN INTEGER IS
BEGIN
IF (SINGLE_PORT=1) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_b_read;
--get_has_b_port
------------------
FUNCTION get_has_b_port(HAS_B_READ : INTEGER;
HAS_B_WRITE : INTEGER)
RETURN INTEGER IS
BEGIN
IF (HAS_B_READ=1 OR HAS_B_WRITE=1) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_port;
--get_num_output_stages
-----------------------
FUNCTION get_num_output_stages(has_mem_output_regs : INTEGER;
has_mux_output_regs : INTEGER;
mux_pipeline_stages : INTEGER)
RETURN INTEGER IS
VARIABLE actual_mux_pipeline_stages : INTEGER;
BEGIN
-- Mux pipeline stages can be non-zero only when there is a mux
-- output register.
IF (has_mux_output_regs=1) THEN
actual_mux_pipeline_stages := mux_pipeline_stages;
ELSE
actual_mux_pipeline_stages := 0;
END IF;
RETURN has_mem_output_regs+actual_mux_pipeline_stages+has_mux_output_regs;
END get_num_output_stages;
--***************************************************************************
-- Component declaration of the VARIABLE depth output register stage
--***************************************************************************
COMPONENT blk_mem_gen_v8_3_1_output_stage
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
EN : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
ECCPIPECE : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_output_stage;
COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************************************
-- locally derived constants to assist memory access
--******************************************************
CONSTANT WRITE_WIDTH_RATIO_A : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_A : INTEGER := C_READ_WIDTH_A/MIN_WIDTH;
CONSTANT WRITE_WIDTH_RATIO_B : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_B : INTEGER := C_READ_WIDTH_B/MIN_WIDTH;
--******************************************************
-- To modify the LSBs of the 'wider' data to the actual
-- address value
--******************************************************
CONSTANT WRITE_ADDR_A_DIV : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH_A;
CONSTANT READ_ADDR_A_DIV : INTEGER := C_READ_WIDTH_A/MIN_WIDTH_A;
CONSTANT WRITE_ADDR_B_DIV : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH_B;
CONSTANT READ_ADDR_B_DIV : INTEGER := C_READ_WIDTH_B/MIN_WIDTH_B;
--******************************************************
-- FUNCTION : log2roundup
--******************************************************
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
--******************************************************
-- Other constants and signals
--******************************************************
CONSTANT COLL_DELAY : TIME := 100 ps;
-- default data vector
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_DEFAULT_DATA,
C_WRITE_WIDTH_A);
CONSTANT CHKBIT_WIDTH : INTEGER := if_then_else(C_WRITE_WIDTH_A>57,8,if_then_else(C_WRITE_WIDTH_A>26,7,if_then_else(C_WRITE_WIDTH_A>11,6,if_then_else(C_WRITE_WIDTH_A>4,5,if_then_else(C_WRITE_WIDTH_A<5,4,0)))));
-- the init memory SIGNAL
SIGNAL memory_i : mem_array;
SIGNAL doublebit_error_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0);
SIGNAL current_contents_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
-- write mode constants
CONSTANT WRITE_MODE_A : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_A);
CONSTANT WRITE_MODE_B : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_B);
CONSTANT WRITE_MODES : STD_LOGIC_VECTOR(3 DOWNTO 0) :=
WRITE_MODE_A & WRITE_MODE_B;
-- reset values
CONSTANT INITA_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITA_VAL,
C_READ_WIDTH_A);
CONSTANT INITB_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITB_VAL,
C_READ_WIDTH_B);
-- memory output 'latches'
SIGNAL memory_out_a : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0) :=
INITA_VAL;
SIGNAL memory_out_b : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) :=
INITB_VAL;
SIGNAL sbiterr_in : STD_LOGIC := '0';
SIGNAL sbiterr_sdp : STD_LOGIC := '0';
SIGNAL dbiterr_in : STD_LOGIC := '0';
SIGNAL dbiterr_sdp : STD_LOGIC := '0';
SIGNAL rdaddrecc_in : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_sdp : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL doutb_i : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i : STD_LOGIC := '0';
SIGNAL dbiterr_i : STD_LOGIC := '0';
-- memory configuration constants
-----------------------------------------------
CONSTANT SINGLE_PORT : INTEGER := get_single_port(C_MEM_TYPE);
CONSTANT IS_ROM : INTEGER := get_is_rom(C_MEM_TYPE);
CONSTANT HAS_A_WRITE : INTEGER := get_has_a_write(IS_ROM);
CONSTANT HAS_B_WRITE : INTEGER := get_has_b_write(C_MEM_TYPE);
CONSTANT HAS_A_READ : INTEGER := get_has_a_read(C_MEM_TYPE);
CONSTANT HAS_B_READ : INTEGER := get_has_b_read(SINGLE_PORT);
CONSTANT HAS_B_PORT : INTEGER := get_has_b_port(HAS_B_READ, HAS_B_WRITE);
CONSTANT NUM_OUTPUT_STAGES_A : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_A,
C_MUX_PIPELINE_STAGES);
CONSTANT NUM_OUTPUT_STAGES_B : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES);
CONSTANT WEA0 : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT WEB0 : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-----------------------------------------------------------------------------
-- DEBUG CONTROL
-- DEBUG=0 : Debug output OFF
-- DEBUG=1 : Some debug info printed
-----------------------------------------------------------------------------
CONSTANT DEBUG : INTEGER := 0;
-- internal signals
-----------------------------------------------
SIGNAL ena_i : STD_LOGIC;
SIGNAL enb_i : STD_LOGIC;
SIGNAL reseta_i : STD_LOGIC;
SIGNAL resetb_i : STD_LOGIC;
SIGNAL wea_i : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL web_i : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL rea_i : STD_LOGIC;
SIGNAL reb_i : STD_LOGIC;
SIGNAL message_complete : BOOLEAN := false;
SIGNAL rsta_outp_stage : STD_LOGIC := '0';
SIGNAL rstb_outp_stage : STD_LOGIC := '0';
--*********************************************************
--FUNCTION : Collision check
--*********************************************************
FUNCTION collision_check (addr_a :
STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
iswrite_a : BOOLEAN;
addr_b :
STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
iswrite_b : BOOLEAN)
RETURN BOOLEAN IS
VARIABLE c_aw_bw : INTEGER;
VARIABLE c_aw_br : INTEGER;
VARIABLE c_ar_bw : INTEGER;
VARIABLE write_addr_a_width : INTEGER;
VARIABLE read_addr_a_width : INTEGER;
VARIABLE write_addr_b_width : INTEGER;
VARIABLE read_addr_b_width : INTEGER;
BEGIN
c_aw_bw := 0;
c_aw_br := 0;
c_ar_bw := 0;
-- Determine the effective address widths FOR each of the 4 ports
write_addr_a_width := C_ADDRA_WIDTH-log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width := C_ADDRA_WIDTH-log2roundup(READ_ADDR_A_DIV);
write_addr_b_width := C_ADDRB_WIDTH-log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width := C_ADDRB_WIDTH-log2roundup(READ_ADDR_B_DIV);
--Look FOR a write-write collision. In order FOR a write-write
--collision to exist, both ports must have a write transaction.
IF (iswrite_a AND iswrite_b) THEN
IF (write_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_a and iswrite_b
--If the B port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_a) THEN
IF (write_addr_a_width > read_addr_b_width) THEN
--read_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_b_width
--Once both are scaled to read_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
END IF; --width
END IF; --iswrite_a
--If the A port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_b) THEN
IF (read_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
ELSE
--read_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_a_width
--Once both are scaled to read_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_b
RETURN (c_aw_bw=1 OR c_aw_br=1 OR c_ar_bw=1);
END FUNCTION collision_check;
BEGIN -- Architecture
-----------------------------------------------------------------------------
-- SOFTECC and ECC SBITERR/DBITERR Outputs
-- The ECC Behavior is modeled by the behavioral models only for Virtex-6.
-- The SOFTECC Behavior is modeled by the behavioral models for Spartan-6.
-- For Virtex-5, these outputs will be tied to 0.
-----------------------------------------------------------------------------
SBITERR <= sbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_sdp WHEN (((C_FAMILY="virtex7") AND C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
-----------------------------------------------
-- This effectively wires off optional inputs
-----------------------------------------------
ena_i <= ENA WHEN (C_HAS_ENA=1) ELSE '1';
enb_i <= ENB WHEN (C_HAS_ENB=1 AND HAS_B_PORT=1) ELSE '1';
-- We are doing an "AND" operation of WEA and ENA and passing to Enbale pin of BRAM when built-in ECC is enabled,
-- what this means is that the write operation happens only when both WEA and ENA are high.
wea_i <= WEA WHEN (HAS_A_WRITE=1 AND ena_i='1') ELSE WEA0;
-- wea_i <= (OTHERS => '1') WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=1 AND ENA = '1') ELSE -- Use_ENA_pin
-- WEA WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=0) ELSE -- Always_enabled
-- WEA WHEN (HAS_A_WRITE=1 AND ena_i='1' AND C_USE_ECC = 0) ELSE
-- WEA0;
web_i <= WEB WHEN (HAS_B_WRITE=1 AND enb_i='1') ELSE WEB0;
rea_i <= ena_i WHEN (HAS_A_READ=1) ELSE '0';
reb_i <= enb_i WHEN (HAS_B_READ=1) ELSE '0';
-- these signals reset the memory latches
-- For the special reset behaviors in some of the families, the C_RSTRAM
-- attribute of the corresponding port is used to indicate if the latch is
-- reset or not.
reseta_i <= RSTA WHEN
((C_HAS_RSTA=1 AND NUM_OUTPUT_STAGES_A=0) OR
(C_HAS_RSTA=1 AND C_RSTRAM_A=1))
ELSE '0';
resetb_i <= RSTB WHEN
((C_HAS_RSTB=1 AND NUM_OUTPUT_STAGES_B=0) OR
(C_HAS_RSTB=1 AND C_RSTRAM_B=1) )
ELSE '0';
--***************************************************************************
-- This is the main PROCESS which includes the memory VARIABLE and the read
-- and write procedures. It also schedules read and write operations
--***************************************************************************
PROCESS (CLKA, CLKB,rea_i,reb_i,reseta_i,resetb_i)
-- Initialize the init memory array
------------------------------------
VARIABLE memory : mem_array := init_memory(DEFAULT_DATA,
C_WRITE_WIDTH_A,
MAX_DEPTH,
MIN_WIDTH);
-- Initialize the mem memory array
------------------------------------
VARIABLE softecc_sbiterr_arr : softecc_err_array;
VARIABLE softecc_dbiterr_arr : softecc_err_array;
VARIABLE sbiterr_arr : ecc_err_array;
VARIABLE dbiterr_arr : ecc_err_array;
CONSTANT doublebit_lsb : STD_LOGIC_VECTOR (1 DOWNTO 0):="11";
CONSTANT doublebit_msb : STD_LOGIC_VECTOR (C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 DOWNTO 0):= (OTHERS => '0');
VARIABLE doublebit_error : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0) := doublebit_msb & doublebit_lsb ;
VARIABLE current_contents_var : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
--***********************************
-- procedures to access the memory
--***********************************
-- write_a
----------
PROCEDURE write_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
inj_sbiterr : IN STD_LOGIC;
inj_dbiterr : IN STD_LOGIC) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
VARIABLE message : LINE;
VARIABLE errbit_current_contents : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
-- Block Memory Generator non-cycle-accurate message
ASSERT (message_complete) REPORT "Block Memory Generator module is using a behavioral model FOR simulation which will not precisely model memory collision behavior."
SEVERITY NOTE;
message_complete <= true;
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_A_DIV);
IF (address_i >= C_WRITE_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range FOR A Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEA = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_A + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEA_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Insert double bit errors:
IF (C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
current_contents(0) := NOT(current_contents(0));
current_contents(1) := NOT(current_contents(1));
--current_contents(0) := NOT(current_contents(30));
--current_contents(1) := NOT(current_contents(62));
END IF;
END IF;
-- Insert double bit errors:
IF (C_USE_SOFTECC=1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 downto 2) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 downto 0);
doublebit_error(0) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1);
doublebit_error(1) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-2);
current_contents := current_contents XOR doublebit_error(C_WRITE_WIDTH_A-1 DOWNTO 0);
END IF;
END IF;
IF(DEBUG=1) THEN
current_contents_var := current_contents; --for debugging current
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_A + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
-- Store address at which error is injected:
IF ((C_FAMILY = "virtex7") AND C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
sbiterr_arr(address_i) := '1';
ELSE
sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
dbiterr_arr(address_i) := '1';
ELSE
dbiterr_arr(address_i) := '0';
END IF;
END IF;
-- Store address at which softecc error is injected:
IF (C_USE_SOFTECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
softecc_sbiterr_arr(address_i) := '1';
ELSE
softecc_sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
softecc_dbiterr_arr(address_i) := '1';
ELSE
softecc_dbiterr_arr(address_i) := '0';
END IF;
END IF;
END IF;
END PROCEDURE;
-- write_b
----------
PROCEDURE write_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_B_DIV);
IF (address_i >= C_WRITE_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEB = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_B + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEB_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_B + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
END IF;
END PROCEDURE;
-- read_a
----------
PROCEDURE read_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_A_DIV);
IF (address_i >= C_READ_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for A Read"
SEVERITY WARNING;
END IF;
memory_out_a <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_A-1 LOOP
memory_out_a(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_A + i) AFTER FLOP_DELAY;
END LOOP;
END IF;
END IF;
END PROCEDURE;
-- read_b
----------
PROCEDURE read_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_B_DIV);
IF (address_i >= C_READ_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Read"
SEVERITY WARNING;
END IF;
memory_out_b <= (OTHERS => 'X') AFTER FLOP_DELAY;
sbiterr_in <= 'X' AFTER FLOP_DELAY;
dbiterr_in <= 'X' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_B-1 LOOP
memory_out_b(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_B + i) AFTER FLOP_DELAY;
END LOOP;
--assert sbiterr and dbiterr signals
IF ((C_FAMILY="virtex7") AND C_USE_ECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
--assert softecc sbiterr and dbiterr signals
ELSIF (C_USE_SOFTECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (softecc_sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (softecc_dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
END IF;
END IF;
END IF;
END PROCEDURE;
-- reset_a
----------
PROCEDURE reset_a
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
-- reset_b
----------
PROCEDURE reset_b
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
BEGIN -- begin the main PROCESS
--***************************************************************************
-- These are the main blocks which schedule read and write operations
-- Note that the reset priority feature at the latch stage is only supported
-- for Spartan-6. For other families, the default priority at the latch stage
-- is "CE"
--***************************************************************************
-- Synchronous clocks: schedule port operations with respect to both
-- write operating modes
IF (C_COMMON_CLK=1) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODES IS
WHEN "0000" => -- write_first write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "0100" => -- read_first write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "0001" => -- write_first read_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0101" => --read_first read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0010" => -- write_first no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0110" => -- read_first no_change
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1000" => -- no_change write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "1001" => -- no_change read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1010" => -- no_change no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Synchronous clocks
-- Asynchronous clocks: port operation is independent
IF (C_COMMON_CLK=0) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODE_A IS
WHEN "00" => -- write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN "01" => -- read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "10" => -- no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
IF (CLKB='1' AND CLKB'EVENT) THEN
CASE WRITE_MODE_B IS
WHEN "00" => -- write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "01" => -- read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "10" => -- no_change
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Asynchronous clocks
-- Assign the memory VARIABLE to the user_visible memory_i SIGNAL
IF(DEBUG=1) THEN
memory_i <= memory;
doublebit_error_i <= doublebit_error;
current_contents_i <= current_contents_var;
END IF;
END PROCESS;
--********************************************************************
-- Instantiate the VARIABLE depth output stage
--********************************************************************
-- Port A
rsta_outp_stage <= RSTA and not sleep;
rstb_outp_stage <= RSTB and not sleep;
reg_a : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTA,
C_RSTRAM => C_RSTRAM_A,
C_RST_PRIORITY => C_RST_PRIORITY_A,
init_val => INITA_VAL,
C_HAS_EN => C_HAS_ENA,
C_HAS_REGCE => C_HAS_REGCEA,
C_DATA_WIDTH => C_READ_WIDTH_A,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_A,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_A,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKA,
RST => rsta_outp_stage, --RSTA,
EN => ENA,
REGCE => REGCEA,
DIN_I => memory_out_a,
DOUT => DOUTA,
SBITERR_IN_I => '0',
DBITERR_IN_I => '0',
SBITERR => OPEN,
DBITERR => OPEN,
RDADDRECC_IN_I => (OTHERS => '0'),
ECCPIPECE => '0',
RDADDRECC => OPEN
);
-- Port B
reg_b : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTB,
C_RSTRAM => C_RSTRAM_B,
C_RST_PRIORITY => C_RST_PRIORITY_B,
init_val => INITB_VAL,
C_HAS_EN => C_HAS_ENB,
C_HAS_REGCE => C_HAS_REGCEB,
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_B,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKB,
RST => rstb_outp_stage,--RSTB,
EN => ENB,
REGCE => REGCEB,
DIN_I => memory_out_b,
DOUT => doutb_i,
SBITERR_IN_I => sbiterr_in,
DBITERR_IN_I => dbiterr_in,
SBITERR => sbiterr_i,
DBITERR => dbiterr_i,
RDADDRECC_IN_I => rdaddrecc_in,
ECCPIPECE => ECCPIPECE,
RDADDRECC => rdaddrecc_i
);
--********************************************************************
-- Instantiate the input / Output Register stages
--********************************************************************
output_reg_stage: blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC MAP(
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP(
CLK => CLKB,
DIN => doutb_i,
DOUT => DOUTB,
SBITERR_IN => sbiterr_i,
DBITERR_IN => dbiterr_i,
SBITERR => sbiterr_sdp,
DBITERR => dbiterr_sdp,
RDADDRECC_IN => rdaddrecc_i,
RDADDRECC => rdaddrecc_sdp
);
--*********************************
-- Synchronous collision checks
--*********************************
sync_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=1) GENERATE
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
-- collision detect
VARIABLE is_collision : BOOLEAN;
VARIABLE message : LINE;
BEGIN
IF (CLKA='1' AND CLKA'EVENT) THEN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision := false;
END IF;
-- If the write port is in READ_FIRST mode, there is no collision
IF (C_WRITE_MODE_A="READ_FIRST" AND wea_i/=WEA0 AND web_i=WEB0) THEN
is_collision := false;
END IF;
IF (C_WRITE_MODE_B="READ_FIRST" AND web_i/=WEB0 AND wea_i=WEA0) THEN
is_collision := false;
END IF;
-- Only flag if one of the accesses is a write
IF (is_collision AND (wea_i/=WEA0 OR web_i/=WEB0)) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END IF;
END PROCESS;
END GENERATE;
--*********************************
-- Asynchronous collision checks
--*********************************
async_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=0) GENERATE
SIGNAL addra_delay : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL wea_delay : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL ena_delay : STD_LOGIC;
SIGNAL addrb_delay : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
SIGNAL web_delay : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL enb_delay : STD_LOGIC;
BEGIN
-- Delay A and B addresses in order to mimic setup/hold times
PROCESS (ADDRA, wea_i, ena_i, ADDRB, web_i, enb_i)
BEGIN
addra_delay <= ADDRA AFTER COLL_DELAY;
wea_delay <= wea_i AFTER COLL_DELAY;
ena_delay <= ena_i AFTER COLL_DELAY;
addrb_delay <= ADDRB AFTER COLL_DELAY;
web_delay <= web_i AFTER COLL_DELAY;
enb_delay <= enb_i AFTER COLL_DELAY;
END PROCESS;
-- Do the checks w/rt A
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_a : BOOLEAN;
VARIABLE is_collision_delay_a : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_a := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_a := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_delay_a := collision_check(ADDRA,
wea_i/=WEA0,
addrb_delay,
web_delay/=WEB0);
ELSE
is_collision_delay_a := false;
END IF;
-- Only flag if B access is a write
IF (is_collision_a AND web_i/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_a AND web_delay/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, addrb_delay);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
-- Do the checks w/rt B
PROCESS (CLKB)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_b : BOOLEAN;
VARIABLE is_collision_delay_b : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA) /= 'X') THEN
is_collision_b := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_b := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(addra_delay) /= 'X') THEN
is_collision_delay_b := collision_check(addra_delay,
wea_delay/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_delay_b := false;
END IF;
-- Only flag if A access is a write
-- Modified condition checking (is_collision_b AND WEA0_i=/WEA0) to fix CR526228
IF (is_collision_b AND wea_i/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_b AND wea_delay/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, addra_delay);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
END GENERATE;
END mem_module_behavioral;
--******************************************************************************
-- Top module that wraps SoftECC Input register stage and the main memory module
--
-- This module is the top-level of behavioral model
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1 IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_CTRL_ECC_ALGO : STRING := "NONE";
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
--C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_SLEEP_PIN : INTEGER := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
PORT (
clka : IN STD_LOGIC := '0';
rsta : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '1';
regcea : IN STD_LOGIC := '1';
wea : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addra : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
dina : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
douta : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
clkb : IN STD_LOGIC := '0';
rstb : IN STD_LOGIC := '0';
enb : IN STD_LOGIC := '1';
regceb : IN STD_LOGIC := '1';
web : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addrb : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
dinb : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
doutb : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
injectsbiterr : IN STD_LOGIC := '0';
injectdbiterr : IN STD_LOGIC := '0';
sbiterr : OUT STD_LOGIC := '0';
dbiterr : OUT STD_LOGIC := '0';
rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : in std_logic := '0';
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic := '0';
rstb_busy : out std_logic := '0';
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
s_aclk : IN STD_LOGIC := '0';
s_aresetn : IN STD_LOGIC := '0';
-- axi full/lite slave Write (write side)
s_axi_awid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid : IN STD_LOGIC := '0';
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast : IN STD_LOGIC := '0';
s_axi_wvalid : IN STD_LOGIC := '0';
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC := '0';
-- axi full/lite slave Read (Write side)
s_axi_arid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid : IN STD_LOGIC := '0';
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_rdata : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC := '0';
-- axi full/lite sideband Signals
s_axi_injectsbiterr : IN STD_LOGIC := '0';
s_axi_injectdbiterr : IN STD_LOGIC := '0';
s_axi_sbiterr : OUT STD_LOGIC := '0';
s_axi_dbiterr : OUT STD_LOGIC := '0';
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END blk_mem_gen_v8_3_1;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE behavioral OF blk_mem_gen_v8_3_1 IS
COMPONENT blk_mem_gen_v8_3_1_mem_module
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_mem_module;
COMPONENT blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_axi_regs_fwd_v8_3;
COMPONENT blk_mem_axi_read_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT blk_mem_axi_read_wrapper_beh;
COMPONENT blk_mem_axi_write_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END COMPONENT blk_mem_axi_write_wrapper_beh;
CONSTANT FLOP_DELAY : TIME := 100 ps;
SIGNAL rsta_in : STD_LOGIC := '1';
SIGNAL ena_in : STD_LOGIC := '1';
SIGNAL regcea_in : STD_LOGIC := '1';
SIGNAL wea_in : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL addra_in : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL dina_in : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL injectsbiterr_in : STD_LOGIC := '0';
SIGNAL injectdbiterr_in : STD_LOGIC := '0';
-----------------------------------------------------------------------------
-- FUNCTION: toLowerCaseChar
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
-----------------------------------------------------------------------------
FUNCTION toLowerCaseChar(
char : character )
RETURN character IS
BEGIN
-- If char is not an upper case letter then return char
IF char<'A' OR char>'Z' THEN
RETURN char;
END IF;
-- Otherwise map char to its corresponding lower case character and
-- RETURN that
CASE char IS
WHEN 'A' => RETURN 'a';
WHEN 'B' => RETURN 'b';
WHEN 'C' => RETURN 'c';
WHEN 'D' => RETURN 'd';
WHEN 'E' => RETURN 'e';
WHEN 'F' => RETURN 'f';
WHEN 'G' => RETURN 'g';
WHEN 'H' => RETURN 'h';
WHEN 'I' => RETURN 'i';
WHEN 'J' => RETURN 'j';
WHEN 'K' => RETURN 'k';
WHEN 'L' => RETURN 'l';
WHEN 'M' => RETURN 'm';
WHEN 'N' => RETURN 'n';
WHEN 'O' => RETURN 'o';
WHEN 'P' => RETURN 'p';
WHEN 'Q' => RETURN 'q';
WHEN 'R' => RETURN 'r';
WHEN 'S' => RETURN 's';
WHEN 'T' => RETURN 't';
WHEN 'U' => RETURN 'u';
WHEN 'V' => RETURN 'v';
WHEN 'W' => RETURN 'w';
WHEN 'X' => RETURN 'x';
WHEN 'Y' => RETURN 'y';
WHEN 'Z' => RETURN 'z';
WHEN OTHERS => RETURN char;
END CASE;
END toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
FUNCTION equalIgnoreCase(
str1 : STRING;
str2 : STRING )
RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str2'left TO str1'right LOOP
IF NOT (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equalIgnoreCase;
-----------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
----------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
----------------------------------------------------------------------------
-- FUNCTION : log2roundup
----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
CONSTANT lower_limit : INTEGER := 1;
CONSTANT upper_limit : INTEGER := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
-----------------------------------------------------------------------------
-- FUNCTION : divroundup
-- Returns the ceiling value of the division
-- Data_value - the quantity to be divided, dividend
-- Divisor - the value to divide the data_value by
-----------------------------------------------------------------------------
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
SIGNAL s_axi_awaddr_out_c : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_araddr_out_c : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_wr_en_c : STD_LOGIC := '0';
SIGNAL s_axi_rd_en_c : STD_LOGIC := '0';
SIGNAL s_aresetn_a_c : STD_LOGIC := '0';
--**************************************************************************
-- AXI PARAMETERS
CONSTANT AXI_FULL_MEMORY_SLAVE : integer := if_then_else((C_AXI_SLAVE_TYPE = 0 AND C_AXI_TYPE = 1),1,0);
CONSTANT C_AXI_ADDR_WIDTH_MSB : integer := C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
CONSTANT C_AXI_ADDR_WIDTH : integer := C_AXI_ADDR_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT LOWER_BOUND_VAL : integer := if_then_else((log2roundup(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT C_AXI_ADDR_WIDTH_LSB : integer := if_then_else((AXI_FULL_MEMORY_SLAVE = 1),0,LOWER_BOUND_VAL);
CONSTANT C_AXI_OS_WR : integer := 2;
-- SAFETY LOGIC related Signals
SIGNAL RSTA_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_A : STD_LOGIC := '0';
SIGNAL RSTB_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_B : STD_LOGIC := '0';
SIGNAL ENA_dly : STD_LOGIC := '0';
SIGNAL ENA_dly_D : STD_LOGIC := '0';
SIGNAL ENB_dly : STD_LOGIC := '0';
SIGNAL ENB_dly_D : STD_LOGIC := '0';
SIGNAL RSTA_I_SAFE : STD_LOGIC := '0';
SIGNAL RSTB_I_SAFE : STD_LOGIC := '0';
SIGNAL ENA_I_SAFE : STD_LOGIC := '0';
SIGNAL ENB_I_SAFE : STD_LOGIC := '0';
SIGNAL ram_rstram_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstram_b_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_b_busy : STD_LOGIC := '0';
SIGNAL ENA_dly_reg : STD_LOGIC := '0';
SIGNAL ENB_dly_reg : STD_LOGIC := '0';
SIGNAL ENA_dly_reg_D : STD_LOGIC := '0';
SIGNAL ENB_dly_reg_D : STD_LOGIC := '0';
--**************************************************************************
BEGIN -- Architecture
--*************************************************************************
-- NO INPUT STAGE
--*************************************************************************
no_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=0) GENERATE
rsta_in <= RSTA;
ena_in <= ENA;
regcea_in <= REGCEA;
wea_in <= WEA;
addra_in <= ADDRA;
dina_in <= DINA;
injectsbiterr_in <= INJECTSBITERR;
injectdbiterr_in <= INJECTDBITERR;
END GENERATE no_input_stage;
--**************************************************************************
-- WITH INPUT STAGE
--**************************************************************************
has_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=1) GENERATE
PROCESS (CLKA)
BEGIN
IF (CLKA'EVENT AND CLKA = '1') THEN
rsta_in <= RSTA AFTER FLOP_DELAY;
ena_in <= ENA AFTER FLOP_DELAY;
regcea_in <= REGCEA AFTER FLOP_DELAY;
wea_in <= WEA AFTER FLOP_DELAY;
addra_in <= ADDRA AFTER FLOP_DELAY;
dina_in <= DINA AFTER FLOP_DELAY;
injectsbiterr_in <= INJECTSBITERR AFTER FLOP_DELAY;
injectdbiterr_in <= INJECTDBITERR AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE has_input_stage;
--**************************************************************************
-- NO SAFETY LOGIC
--**************************************************************************
NO_SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 0) GENERATE
ENA_I_SAFE <= ena_in;
ENB_I_SAFE <= ENB;
RSTA_I_SAFE <= rsta_in;
RSTB_I_SAFE <= RSTB;
END GENERATE NO_SAFETY_CKT_GEN;
--**************************************************************************
-- SAFETY LOGIC
--**************************************************************************
SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 1) GENERATE
-- RESET SAFETY LOGIC Generation
-- POR Generation
------------------------------------------------------------------------------
-- Power-ON Reset Generation
------------------------------------------------------------------------------
RST_SHFT_LOGIC_A : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
RSTA_SHFT_REG(4 DOWNTO 0) <= RSTA_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_A;
POR_RSTA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
POR_A <= RSTA_SHFT_REG(4) xor RSTA_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTA_GEN;
RST_SHFT_LOGIC_B : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
RSTB_SHFT_REG(4 DOWNTO 0) <= RSTB_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_B;
POR_RSTB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
POR_B <= RSTB_SHFT_REG(4) xor RSTB_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTB_GEN;
-----------------------------------------------------------------------------
-- Fix for the AR42571
-----------------------------------------------------------------------------
-- Reset Generation
-----------------------------------------------------------------------------
RSTA_I_SAFE <= rsta_in OR POR_A;
SPRAM_RST: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_I_SAFE <= '0';
END GENERATE SPRAM_RST;
nSPRAM_RST: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_I_SAFE <= RSTB OR POR_B;
END GENERATE nSPRAM_RST;
-----------------------------------------------------------------------------
-- RSTA/B_BUSY Generation
-----------------------------------------------------------------------------
RSTA_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
ram_rstram_a_busy <= rsta_in OR ENA_dly OR ENA_dly_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstram_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_NO_REG;
RSTA_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
ram_rstreg_a_busy <= rsta_in OR ENA_dly OR ENA_dly_reg_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstreg_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_WITH_REG;
SPRAM_RST_BUSY: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_BUSY <= '0';
END GENERATE SPRAM_RST_BUSY;
nSPRAM_RST_BUSY: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
ram_rstram_b_busy <= RSTB OR ENB_dly OR ENB_dly_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstram_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_NO_REG;
RSTB_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
ram_rstreg_b_busy <= RSTB OR ENB_dly OR ENB_dly_reg_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstreg_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_WITH_REG;
END GENERATE nSPRAM_RST_BUSY;
-----------------------------------------------------------------------------
-- ENA/ENB Generation
-----------------------------------------------------------------------------
ENA_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly <= rsta_in AFTER FLOP_DELAY;
ENA_dly_D <= ENA_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_D OR ena_in;
END GENERATE ENA_NO_REG;
ENA_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly_reg <= rsta_in AFTER FLOP_DELAY;
ENA_dly_reg_D <= ENA_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_reg_D OR ena_in;
END GENERATE ENA_WITH_REG;
SPRAM_ENB: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
ENB_I_SAFE <= '0';
END GENERATE SPRAM_ENB;
nSPRAM_ENB: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
ENB_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly <= RSTB AFTER FLOP_DELAY;
ENB_dly_D <= ENB_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_D OR ENB;
END GENERATE ENB_NO_REG;
ENB_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly_reg <= RSTB AFTER FLOP_DELAY;
ENB_dly_reg_D <= ENB_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_reg_D OR ENB;
END GENERATE ENB_WITH_REG;
END GENERATE nSPRAM_ENB;
END GENERATE SAFETY_CKT_GEN;
--**************************************************************************
-- NATIVE MEMORY MODULE INSTANCE
--**************************************************************************
native_mem_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 0) GENERATE
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,--rsta_in,
ENA => ENA_I_SAFE,--ena_in,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in,
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => RDADDRECC
);
END GENERATE native_mem_module;
--**************************************************************************
-- NATIVE MEMORY MAPPED MODULE INSTANCE
--**************************************************************************
native_mem_map_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 1) GENERATE
--**************************************************************************
-- NATIVE MEMORY MAPPED PARAMETERS
CONSTANT C_ADDRA_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_A);
CONSTANT C_ADDRB_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_B);
CONSTANT C_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
CONSTANT C_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
CONSTANT C_MEM_MAP_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_MSB;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT MEM_MAP_LOWER_BOUND_VAL_A : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT MEM_MAP_LOWER_BOUND_VAL_B : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_B,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_B,8)));
CONSTANT C_MEM_MAP_ADDRA_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_A;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_B;
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH_ACTUAL-1 DOWNTO 0) := (OTHERS => '0');
--**************************************************************************
BEGIN
RDADDRECC(C_ADDRB_WIDTH-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_MSB) <= (OTHERS => '0');
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB) <= rdaddrecc_i;
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_LSB-1 DOWNTO 0) <= (OTHERS => '0');
mem_map_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH_ACTUAL,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH_ACTUAL,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,
ENA => ENA_I_SAFE,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in(C_MEM_MAP_ADDRA_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRA_WIDTH_LSB),
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB),
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => rdaddrecc_i
);
END GENERATE native_mem_map_module;
--****************************************************************************
-- AXI MEMORY MODULE INSTANCE
--****************************************************************************
axi_mem_module: IF (C_INTERFACE_TYPE = 1) GENERATE
SIGNAL s_axi_rid_c : STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rdata_c : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rresp_c : STD_LOGIC_VECTOR(2-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rlast_c : STD_LOGIC := '0';
SIGNAL s_axi_rvalid_c : STD_LOGIC := '0';
SIGNAL s_axi_rready_c : STD_LOGIC := '0';
SIGNAL regceb_c : STD_LOGIC := '0';
BEGIN
s_aresetn_a_c <= NOT S_ARESETN;
S_AXI_BRESP <= (OTHERS => '0');
s_axi_rresp_c <= (OTHERS => '0');
no_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 0 AND C_HAS_MUX_OUTPUT_REGS_B = 0 ) GENERATE
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RLAST <= s_axi_rlast_c;
S_AXI_RVALID <= s_axi_rvalid_c;
S_AXI_RID <= s_axi_rid_c;
S_AXI_RRESP <= s_axi_rresp_c;
s_axi_rready_c <= S_AXI_RREADY;
END GENERATE no_regs;
has_regs_fwd: IF (C_HAS_MUX_OUTPUT_REGS_B = 1 OR C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
CONSTANT C_AXI_PAYLOAD : INTEGER := if_then_else((C_HAS_MUX_OUTPUT_REGS_B = 1),C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3,C_AXI_ID_WIDTH+3);
SIGNAL s_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
has_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
regceb_c <= s_axi_rvalid_c AND s_axi_rready_c;
END GENERATE has_regceb;
no_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 0) GENERATE
regceb_c <= REGCEB;
END GENERATE no_regceb;
only_core_op_regs: IF (C_HAS_MUX_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rdata_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RDATA <= m_axi_payload_c(C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_core_op_regs;
only_emb_op_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_emb_op_regs;
axi_regs_inst : blk_mem_axi_regs_fwd_v8_3
GENERIC MAP(
C_DATA_WIDTH => C_AXI_PAYLOAD
)
PORT MAP (
ACLK => S_ACLK,
ARESET => s_aresetn_a_c,
S_VALID => s_axi_rvalid_c,
S_READY => s_axi_rready_c,
S_PAYLOAD_DATA => s_axi_payload_c,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY,
M_PAYLOAD_DATA => m_axi_payload_c
);
END GENERATE has_regs_fwd;
axi_wr_fsm : blk_mem_axi_write_wrapper_beh
GENERIC MAP(
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_AXI_AWADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_WDATA_WIDTH => C_WRITE_WIDTH_A,
C_AXI_OS_WR => C_AXI_OS_WR
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Slave Write Interface
S_AXI_AWADDR => S_AXI_AWADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_AWLEN => S_AXI_AWLEN,
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BID => S_AXI_BID,
-- Signals for BRAM interface
S_AXI_AWADDR_OUT =>s_axi_awaddr_out_c,
S_AXI_WR_EN =>s_axi_wr_en_c
);
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => 1, -- For AXI, Read Enable is always C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => 1, -- For AXI C_USE_BYTE_WEA is always 1,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => 1, -- For AXI, Read Enable is always C_HAS_ENB,
C_HAS_REGCEB => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_BYTE_WEB => 1, -- For AXI C_USE_BYTE_WEB is always 1,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => 0, --For AXI, Primitive Registers A is not supported C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => 0,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
--Port A:
CLKA => S_AClk,
RSTA => s_aresetn_a_c,
ENA => s_axi_wr_en_c,
REGCEA => regcea_in,
WEA => S_AXI_WSTRB,
ADDRA => s_axi_awaddr_out_c,
DINA => S_AXI_WDATA,
DOUTA => DOUTA,
--Port B:
CLKB => S_AClk,
RSTB => s_aresetn_a_c,
ENB => s_axi_rd_en_c,
REGCEB => regceb_c,
WEB => (OTHERS => '0'),
ADDRB => s_axi_araddr_out_c,
DINB => DINB,
DOUTB => s_axi_rdata_c,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => '0',
SLEEP => '0',
RDADDRECC => RDADDRECC
);
axi_rd_sm : blk_mem_axi_read_wrapper_beh
GENERIC MAP (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_PIPELINE_STAGES => 1,
C_AXI_ARADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_AClk,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Read Side
S_AXI_ARADDR => S_AXI_ARADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARSIZE => S_AXI_ARSIZE,
S_AXI_ARBURST => S_AXI_ARBURST,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => s_axi_rlast_c,
S_AXI_RVALID => s_axi_rvalid_c,
S_AXI_RREADY => s_axi_rready_c,
S_AXI_ARID => S_AXI_ARID,
S_AXI_RID => s_axi_rid_c,
-- AXI Full/Lite Read FSM Outputs
S_AXI_ARADDR_OUT => s_axi_araddr_out_c,
S_AXI_RD_EN => s_axi_rd_en_c
);
END GENERATE axi_mem_module;
END behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_clr is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_clr;
architecture beh_ff_clr_arch of beh_ff_clr is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(CLR, C)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_clr_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_ce is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_ce;
architecture beh_ff_ce_arch of beh_ff_ce is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, CLR)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
if (CE = '1') then
q_o <= D after 100 ps;
end if;
end if;
end process;
end beh_ff_ce_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_pre is
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end beh_ff_pre;
architecture beh_ff_pre_arch of beh_ff_pre is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, PRE)
begin
if (PRE = '1') then
q_o <= '1';
elsif (C' event and C = '1') then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_pre_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_muxf7 is
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end beh_muxf7;
architecture beh_muxf7_arch of beh_muxf7 is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
else
O <= I1;
end if;
end process;
end beh_muxf7_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity STATE_LOGIC is
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic := '0';
I0 : in std_logic := '0';
I1 : in std_logic := '0';
I2 : in std_logic := '0';
I3 : in std_logic := '0';
I4 : in std_logic := '0';
I5 : in std_logic := '0'
);
end STATE_LOGIC;
architecture STATE_LOGIC_arch of STATE_LOGIC is
constant INIT_reg : std_logic_vector(63 downto 0) := INIT;
begin
LUT_beh:process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
begin
I_reg := I5 & I4 & I3 & I2 & I1 & I0;
O <= INIT_reg(conv_integer(I_reg));
end process;
end STATE_LOGIC_arch;
|
-------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v8_3_1.vhd
--
-- Description:
-- This file is the VHDL behvarial model for the
-- Block Memory Generator Core.
--
-------------------------------------------------------------------------------
-- Author: Xilinx
--
-- History: January 11, 2006: Initial revision
-- June 11, 2007 : Added independent register stages for
-- Port A and Port B (IP1_Jm/v2.5)
-- August 28, 2007 : Added mux pipeline stages feature (IP2_Jm/v2.6)
-- April 07, 2009 : Added support for Spartan-6 and Virtex-6
-- features, including the following:
-- (i) error injection, detection and/or correction
-- (ii) reset priority
-- (iii) special reset behavior
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
ENTITY blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END ENTITY blk_mem_axi_regs_fwd_v8_3;
ARCHITECTURE axi_regs_fwd_arch OF blk_mem_axi_regs_fwd_v8_3 IS
SIGNAL STORAGE_DATA : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_READY_I : STD_LOGIC := '0';
SIGNAL M_VALID_I : STD_LOGIC := '0';
SIGNAL ARESET_D : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');-- Reset delay register
BEGIN
--assign local signal to its output signal
S_READY <= S_READY_I;
M_VALID <= M_VALID_I;
PROCESS(ACLK)
BEGIN
IF(ACLK'event AND ACLK = '1') THEN
ARESET_D <= ARESET_D(0) & ARESET;
END IF;
END PROCESS;
--Save payload data whenever we have a transaction on the slave side
PROCESS(ACLK, ARESET)
BEGIN
IF (ARESET = '1') THEN
STORAGE_DATA <= (OTHERS => '0');
ELSIF(ACLK'event AND ACLK = '1') THEN
IF(S_VALID = '1' AND S_READY_I = '1') THEN
STORAGE_DATA <= S_PAYLOAD_DATA;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= STORAGE_DATA;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
PROCESS(ACLK,ARESET)
BEGIN
IF (ARESET_D /= "00") THEN
M_VALID_I <= '0';
ELSIF(ACLK'event AND ACLK = '1') THEN
IF (S_VALID = '1') THEN
--Always set M_VALID_I when slave side is valid
M_VALID_I <= '1';
ELSIF (M_READY = '1') THEN
--Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= '0';
END IF;
END IF;
END PROCESS;
--Slave Ready is either when Master side drives M_READY or we have space in our storage data
S_READY_I <= (M_READY OR (NOT M_VALID_I)) AND NOT(OR_REDUCE(ARESET_D));
END axi_regs_fwd_arch;
-------------------------------------------------------------------------------
-- Description:
-- This is the behavioral model of write_wrapper for the
-- Block Memory Generator Core.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_axi_write_wrapper_beh IS
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END blk_mem_axi_write_wrapper_beh;
ARCHITECTURE axi_write_wrap_arch OF blk_mem_axi_write_wrapper_beh IS
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_AXI_WDATA_WIDTH=8,0,
if_then_else((C_AXI_WDATA_WIDTH=16),1,
if_then_else((C_AXI_WDATA_WIDTH=32),2,
if_then_else((C_AXI_WDATA_WIDTH=64),3,
if_then_else((C_AXI_WDATA_WIDTH=128),4,
if_then_else((C_AXI_WDATA_WIDTH=256),5,0))))));
SIGNAL bvalid_c : std_logic := '0';
SIGNAL bready_timeout_c : std_logic := '0';
SIGNAL bvalid_rd_cnt_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_r : std_logic := '0';
SIGNAL bvalid_count_r : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL awaddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
C_AXI_AWADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL bvalid_wr_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_rd_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_last_c : std_logic := '0';
SIGNAL addr_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL aw_ready_r : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL awlen_cntr_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1');
SIGNAL awlen_int : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL awburst_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes : integer := 0;
SIGNAL wrap_boundary : integer := 0;
SIGNAL wrap_base_addr : integer := 0;
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
-- Array to store BIDs
TYPE id_array IS ARRAY (3 DOWNTO 0) OF std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
SIGNAL axi_bid_array : id_array := (others => (others => '0'));
COMPONENT write_netlist
GENERIC(
C_AXI_TYPE : integer
);
PORT(
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
S_AXI_AWVALID : IN std_logic;
aw_ready_r : OUT std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN std_logic;
S_AXI_WR_EN : OUT std_logic;
w_last_c : IN std_logic;
bready_timeout_c : IN std_logic;
addr_en_c : OUT std_logic;
incr_addr_c : OUT std_logic;
bvalid_c : OUT std_logic
);
END COMPONENT write_netlist;
BEGIN
---------------------------------------
--AXI WRITE FSM COMPONENT INSTANTIATION
---------------------------------------
axi_wr_fsm : write_netlist
GENERIC MAP (
C_AXI_TYPE => C_AXI_TYPE
)
PORT MAP (
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
S_AXI_AWVALID => S_AXI_AWVALID,
aw_ready_r => aw_ready_r,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BVALID => OPEN,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_WR_EN => S_AXI_WR_EN,
w_last_c => w_last_c,
bready_timeout_c => bready_timeout_c,
addr_en_c => addr_en_c,
incr_addr_c => incr_addr_c,
bvalid_c => bvalid_c
);
--Wrap Address boundary calculation
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWSIZE,"000"));
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(awlen_int)+1);
wrap_base_addr <= (conv_integer(awaddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary <= wrap_base_addr+total_bytes;
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awaddr_reg <= (OTHERS => '0');
num_of_bytes_r <= 0;
awburst_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awaddr_reg <= S_AXI_AWADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWBURST,"01");
ELSIF (incr_addr_c = '1') THEN
IF (awburst_int = "10") THEN
IF(conv_integer(awaddr_reg) = (wrap_boundary-num_of_bytes_r)) THEN
awaddr_reg <= conv_std_logic_vector(wrap_base_addr,C_AXI_AWADDR_WIDTH);
ELSE
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
ELSIF (awburst_int = "01" OR awburst_int = "11") THEN
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
S_AXI_AWADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
awaddr_reg(C_AXI_AWADDR_WIDTH-1 DOWNTO C_RANGE),awaddr_reg);
---------------------------------------------------------------------------
-- AXI wlast generation
---------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awlen_cntr_r <= (OTHERS => '1');
awlen_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awlen_int <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
awlen_cntr_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
ELSIF (dec_alen_c = '1') THEN
awlen_cntr_r <= awlen_cntr_r - ONE AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
w_last_c <= '1' WHEN (awlen_cntr_r = "00000000" AND S_AXI_WVALID = '1') ELSE '0';
dec_alen_c <= (incr_addr_c OR w_last_c);
---------------------------------------------------------------------------
-- Generation of bvalid counter for outstanding transactions
---------------------------------------------------------------------------
P_b_valid_os_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_count_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- bvalid_count_r generation
IF (bvalid_c = '1' AND bvalid_r = '1' AND S_AXI_BREADY = '1') THEN
bvalid_count_r <= bvalid_count_r AFTER FLOP_DELAY;
ELSIF (bvalid_c = '1') THEN
bvalid_count_r <= bvalid_count_r + "01" AFTER FLOP_DELAY;
ELSIF (bvalid_r = '1' AND S_AXI_BREADY = '1' AND bvalid_count_r /= "0") THEN
bvalid_count_r <= bvalid_count_r - "01" AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_os_r ;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is used
---------------------------------------------------------------------------
gaxi_bvalid_id_r:IF (C_HAS_AXI_ID = 1) GENERATE
SIGNAL bvalid_d1_c : std_logic := '0';
BEGIN
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
bvalid_d1_c <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
--external bvalid signal generation
IF (bvalid_d1_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_id_r;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is not used
---------------------------------------------------------------------------
gaxi_bvalid_noid_r:IF (C_HAS_AXI_ID = 0) GENERATE
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
--external bvalid signal generation
IF (bvalid_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_noid_r;
---------------------------------------------------------------------------
-- Generation of Bready timeout
---------------------------------------------------------------------------
P_brdy_tout_c: PROCESS (bvalid_count_r)
BEGIN
-- bready_timeout_c generation
IF(conv_integer(bvalid_count_r) = C_AXI_OS_WR-1) THEN
bready_timeout_c <= '1';
ELSE
bready_timeout_c <= '0';
END IF;
END PROCESS P_brdy_tout_c;
---------------------------------------------------------------------------
-- Generation of BID
---------------------------------------------------------------------------
gaxi_bid_gen:IF (C_HAS_AXI_ID = 1) GENERATE
P_bid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
bvalid_wr_cnt_r <= (OTHERS => '0');
bvalid_rd_cnt_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- STORE AWID IN AN ARRAY
IF(bvalid_c = '1') THEN
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + "01";
END IF;
-- GENERATE BID FROM AWID ARRAY
bvalid_rd_cnt_r <= bvalid_rd_cnt_c AFTER FLOP_DELAY;
S_AXI_BID <= axi_bid_array(conv_integer(bvalid_rd_cnt_c));
END IF;
END PROCESS P_bid_gen;
bvalid_rd_cnt_c <= bvalid_rd_cnt_r + "01" WHEN (bvalid_r = '1' AND S_AXI_BREADY = '1') ELSE bvalid_rd_cnt_r;
---------------------------------------------------------------------------
-- Storing AWID for generation of BID
---------------------------------------------------------------------------
P_awid_reg:PROCESS (S_ACLK)
BEGIN
IF (S_ACLK'event AND S_ACLK='1') THEN
IF(aw_ready_r = '1' AND S_AXI_AWVALID = '1') THEN
axi_bid_array(conv_integer(bvalid_wr_cnt_r)) <= S_AXI_AWID;
END IF;
END IF;
END PROCESS P_awid_reg;
END GENERATE gaxi_bid_gen;
S_AXI_BVALID <= bvalid_r;
S_AXI_AWREADY <= aw_ready_r;
END axi_write_wrap_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity write_netlist is
GENERIC(
C_AXI_TYPE : integer
);
port (
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_AWVALID : in STD_LOGIC := '0';
S_AXI_WVALID : in STD_LOGIC := '0';
S_AXI_BREADY : in STD_LOGIC := '0';
w_last_c : in STD_LOGIC := '0';
bready_timeout_c : in STD_LOGIC := '0';
aw_ready_r : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_WR_EN : out STD_LOGIC;
addr_en_c : out STD_LOGIC;
incr_addr_c : out STD_LOGIC;
bvalid_c : out STD_LOGIC
);
end write_netlist;
architecture STRUCTURE of write_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
BEGIN
---------------------------------------------------------------------------
-- AXI LITE
---------------------------------------------------------------------------
gbeh_axi_lite_sm: IF (C_AXI_TYPE = 0 ) GENERATE
signal w_ready_r_7 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSignal_bvalid_c : STD_LOGIC;
signal NlwRenamedSignal_incr_addr_c : STD_LOGIC;
signal present_state_FSM_FFd3_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal present_state_FSM_FFd1_15 : STD_LOGIC;
signal present_state_FSM_FFd4_16 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd4_In1_21 : STD_LOGIC;
signal Mmux_aw_ready_c : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
S_AXI_WREADY <= w_ready_r_7;
S_AXI_BVALID <= NlwRenamedSignal_incr_addr_c;
S_AXI_WR_EN <= NlwRenamedSignal_bvalid_c;
incr_addr_c <= NlwRenamedSignal_incr_addr_c;
bvalid_c <= NlwRenamedSignal_bvalid_c;
NlwRenamedSignal_incr_addr_c <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_7
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_16
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_13
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_15
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000055554440"
)
port map (
I0 => S_AXI_WVALID,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => '0',
O => present_state_FSM_FFd3_In
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"0000000088880800"
)
port map (
I0 => S_AXI_AWVALID,
I1 => S_AXI_WVALID,
I2 => bready_timeout_c,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => present_state_FSM_FFd2_In
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAA2000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_WVALID,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => addr_en_c
);
Mmux_w_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"F5F07570F5F05500"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => w_ready_c
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd3_13,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd1_15,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_14,
I2 => present_state_FSM_FFd3_13,
I3 => '0',
I4 => '0',
I5 => '0',
O => NlwRenamedSignal_bvalid_c
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"2F0F27072F0F2200"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => present_state_FSM_FFd4_In1_21
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_In1_21,
I3 => '0',
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_aw_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"7535753575305500"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => S_AXI_WVALID,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => present_state_FSM_FFd2_14,
O => Mmux_aw_ready_c(0)
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => Mmux_aw_ready_c(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => aw_ready_c
);
END GENERATE gbeh_axi_lite_sm;
---------------------------------------------------------------------------
-- AXI FULL
---------------------------------------------------------------------------
gbeh_axi_full_sm: IF (C_AXI_TYPE = 1 ) GENERATE
signal w_ready_r_8 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSig_OI_bvalid_c : STD_LOGIC;
signal present_state_FSM_FFd1_16 : STD_LOGIC;
signal present_state_FSM_FFd4_17 : STD_LOGIC;
signal present_state_FSM_FFd3_18 : STD_LOGIC;
signal present_state_FSM_FFd2_19 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd2_In1_24 : STD_LOGIC;
signal present_state_FSM_FFd4_In1_25 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal N4 : STD_LOGIC;
begin
S_AXI_WREADY <= w_ready_r_8;
bvalid_c <= NlwRenamedSig_OI_bvalid_c;
S_AXI_BVALID <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_8
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_17
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_18
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_19
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_16
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000000005540"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd4_17,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd3_In
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"BF3FBB33AF0FAA00"
)
port map (
I0 => S_AXI_BREADY,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd1_16,
I4 => present_state_FSM_FFd4_17,
I5 => NlwRenamedSig_OI_bvalid_c,
O => aw_ready_c
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"AAAAAAAA20000000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_19,
I3 => S_AXI_WVALID,
I4 => w_last_c,
I5 => present_state_FSM_FFd4_17,
O => addr_en_c
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_19,
I2 => present_state_FSM_FFd3_18,
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_WR_EN
);
Mmux_incr_addr_c_0_1 : STATE_LOGIC
generic map(
INIT => X"0000000000002220"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => incr_addr_c
);
Mmux_aw_ready_c_0_11 : STATE_LOGIC
generic map(
INIT => X"0000000000008880"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => NlwRenamedSig_OI_bvalid_c
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"000000000000D5C0"
)
port map (
I0 => w_last_c,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd4_17,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd2_In1_24
);
present_state_FSM_FFd2_In2 : STATE_LOGIC
generic map(
INIT => X"FFFFAAAA08AAAAAA"
)
port map (
I0 => present_state_FSM_FFd2_19,
I1 => S_AXI_AWVALID,
I2 => bready_timeout_c,
I3 => w_last_c,
I4 => S_AXI_WVALID,
I5 => present_state_FSM_FFd2_In1_24,
O => present_state_FSM_FFd2_In
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"00C0004000C00000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => w_last_c,
I2 => S_AXI_WVALID,
I3 => bready_timeout_c,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => present_state_FSM_FFd4_In1_25
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88F8"
)
port map (
I0 => present_state_FSM_FFd1_16,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_17,
I3 => S_AXI_AWVALID,
I4 => present_state_FSM_FFd4_In1_25,
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_w_ready_c_0_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => w_last_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_w_ready_c_0_Q : STATE_LOGIC
generic map(
INIT => X"FABAFABAFAAAF000"
)
port map (
I0 => N2,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd4_17,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => w_ready_c
);
Mmux_aw_ready_c_0_11_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => bready_timeout_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => w_last_c,
I1 => N4,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => present_state_FSM_FFd1_16,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
END GENERATE gbeh_axi_full_sm;
end STRUCTURE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--AXI Behavioral Model entities
ENTITY blk_mem_axi_read_wrapper_beh is
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
port (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END blk_mem_axi_read_wrapper_beh;
architecture blk_mem_axi_read_wrapper_beh_arch of blk_mem_axi_read_wrapper_beh is
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_WRITE_WIDTH_A=8,0,
if_then_else((C_WRITE_WIDTH_A=16),1,
if_then_else((C_WRITE_WIDTH_A=32),2,
if_then_else((C_WRITE_WIDTH_A=64),3,
if_then_else((C_WRITE_WIDTH_A=128),4,
if_then_else((C_WRITE_WIDTH_A=256),5,0))))));
SIGNAL ar_id_r : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
SIGNAL addr_en_c : std_logic := '0';
SIGNAL rd_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL single_trans_c : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL mux_sel_c : std_logic := '0';
SIGNAL r_last_c : std_logic := '0';
SIGNAL r_last_int_c : std_logic := '0';
SIGNAL arlen_int_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL arlen_cntr : std_logic_vector(7 DOWNTO 0) := ONE;
SIGNAL arburst_int_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL arburst_int_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL araddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),C_AXI_ARADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL total_bytes : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
SIGNAL wrap_base_addr_r : integer := 0;
SIGNAL wrap_boundary_r : integer := 0;
SIGNAL arlen_int_c : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes_c : integer := 0;
SIGNAL wrap_base_addr_c : integer := 0;
SIGNAL wrap_boundary_c : integer := 0;
SIGNAL araddr_out : std_logic_vector(C_ADDRB_WIDTH-1 downto 0) := (OTHERS => '0');
COMPONENT read_netlist
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_INCR_ADDR : OUT std_logic := '0';
S_AXI_ADDR_EN : OUT std_logic := '0';
S_AXI_SINGLE_TRANS : OUT std_logic := '0';
S_AXI_MUX_SEL : OUT std_logic := '0';
S_AXI_R_LAST : OUT std_logic := '0';
S_AXI_R_LAST_INT : IN std_logic := '0';
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT read_netlist;
BEGIN
dec_alen_c <= incr_addr_c OR r_last_int_c;
axi_read_fsm : read_netlist
GENERIC MAP(
C_AXI_TYPE => 1,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
S_AXI_INCR_ADDR => incr_addr_c,
S_AXI_ADDR_EN => addr_en_c,
S_AXI_SINGLE_TRANS => single_trans_c,
S_AXI_MUX_SEL => mux_sel_c,
S_AXI_R_LAST => r_last_c,
S_AXI_R_LAST_INT => r_last_int_c,
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN => rd_en_c
);
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(arlen_int_r)+1);
wrap_base_addr_r <= (conv_integer(araddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary_r <= wrap_base_addr_r+total_bytes;
---- combinatorial from interface
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARSIZE,"000"));
arlen_int_c <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
total_bytes_c <= conv_integer(num_of_bytes_c)*(conv_integer(arlen_int_c)+1);
wrap_base_addr_c <= (conv_integer(S_AXI_ARADDR)/if_then_else(total_bytes_c=0,1,total_bytes_c))*(total_bytes_c);
wrap_boundary_c <= wrap_base_addr_c+total_bytes_c;
arburst_int_c <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARBURST,"01");
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
araddr_reg <= (OTHERS => '0');
arburst_int_r <= (OTHERS => '0');
num_of_bytes_r <= 0;
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (incr_addr_c = '1' AND addr_en_c = '1' AND single_trans_c = '0') THEN
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
IF (arburst_int_c = "10") THEN
IF(conv_integer(S_AXI_ARADDR) = (wrap_boundary_c-num_of_bytes_c)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_c,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (arburst_int_c = "01" OR arburst_int_c = "11") THEN
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (addr_en_c = '1') THEN
araddr_reg <= S_AXI_ARADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
ELSIF (incr_addr_c = '1') THEN
IF (arburst_int_r = "10") THEN
IF(conv_integer(araddr_reg) = (wrap_boundary_r-num_of_bytes_r)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_r,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
ELSIF (arburst_int_r = "01" OR arburst_int_r = "11") THEN
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
araddr_out <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),araddr_reg(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),araddr_reg);
--------------------------------------------------------------------------
-- Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
--------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF S_ARESETN = '1' THEN
arlen_cntr <= ONE;
arlen_int_r <= (OTHERS => '0');
ELSIF S_ACLK'event AND S_ACLK = '1' THEN
IF (addr_en_c = '1' AND dec_alen_c = '1' AND single_trans_c = '0') THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= S_AXI_ARLEN - ONE AFTER FLOP_DELAY;
ELSIF addr_en_c = '1' THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
ELSIF dec_alen_c = '1' THEN
arlen_cntr <= arlen_cntr - ONE AFTER FLOP_DELAY;
ELSE
arlen_cntr <= arlen_cntr AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
r_last_int_c <= '1' WHEN (arlen_cntr = "00000000" AND S_AXI_RREADY = '1') ELSE '0' ;
--------------------------------------------------------------------------
-- AXI FULL FSM
-- Mux Selection of ARADDR
-- ARADDR is driven out from the read fsm based on the mux_sel_c
-- Based on mux_sel either ARADDR is given out or the latched ARADDR is
-- given out to BRAM
--------------------------------------------------------------------------
P_araddr_mux: PROCESS (mux_sel_c,S_AXI_ARADDR,araddr_out)
BEGIN
IF (mux_sel_c = '0') THEN
S_AXI_ARADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARADDR(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),S_AXI_ARADDR);
ELSE
S_AXI_ARADDR_OUT <= araddr_out;
END IF;
END PROCESS P_araddr_mux;
--------------------------------------------------------------------------
-- Assign output signals - AXI FULL FSM
--------------------------------------------------------------------------
S_AXI_RD_EN <= rd_en_c;
grid: IF (C_HAS_AXI_ID = 1) GENERATE
P_rid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
S_AXI_RID <= (OTHERS => '0');
ar_id_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
IF (addr_en_c = '1' AND rd_en_c = '1') THEN
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
ELSIF (addr_en_c = '1' AND rd_en_c = '0') THEN
ar_id_r <= S_AXI_ARID;
ELSIF (rd_en_c = '1') THEN
S_AXI_RID <= ar_id_r;
END IF;
END IF;
END PROCESS P_rid_gen;
END GENERATE grid;
END blk_mem_axi_read_wrapper_beh_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity read_netlist is
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_R_LAST_INT : in STD_LOGIC := '0';
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_ARVALID : in STD_LOGIC := '0';
S_AXI_RREADY : in STD_LOGIC := '0';
S_AXI_INCR_ADDR : out STD_LOGIC;
S_AXI_ADDR_EN : out STD_LOGIC;
S_AXI_SINGLE_TRANS : out STD_LOGIC;
S_AXI_MUX_SEL : out STD_LOGIC;
S_AXI_R_LAST : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RLAST : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RD_EN : out STD_LOGIC;
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end read_netlist;
architecture STRUCTURE of read_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
signal present_state_FSM_FFd1_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_r_15 : STD_LOGIC;
signal gaxi_full_sm_ar_ready_r_16 : STD_LOGIC;
signal gaxi_full_sm_r_last_r_17 : STD_LOGIC;
signal NlwRenamedSig_OI_gaxi_full_sm_r_valid_r : STD_LOGIC;
signal gaxi_full_sm_r_valid_c : STD_LOGIC;
signal S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o : STD_LOGIC;
signal gaxi_full_sm_ar_ready_c : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_c : STD_LOGIC;
signal NlwRenamedSig_OI_S_AXI_R_LAST : STD_LOGIC;
signal S_AXI_ARLEN_7_GND_8_o_equal_1_o : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal Mmux_S_AXI_R_LAST13 : STD_LOGIC;
signal N01 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal Mmux_gaxi_full_sm_ar_ready_c11 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N8 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N13 : STD_LOGIC;
begin
S_AXI_R_LAST <= NlwRenamedSig_OI_S_AXI_R_LAST;
S_AXI_ARREADY <= gaxi_full_sm_ar_ready_r_16;
S_AXI_RLAST <= gaxi_full_sm_r_last_r_17;
S_AXI_RVALID <= NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
gaxi_full_sm_outstanding_read_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_outstanding_read_c,
Q => gaxi_full_sm_outstanding_read_r_15
);
gaxi_full_sm_r_valid_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => gaxi_full_sm_r_valid_c,
Q => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r
);
gaxi_full_sm_ar_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_ar_ready_c,
Q => gaxi_full_sm_ar_ready_r_16
);
gaxi_full_sm_r_last_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => NlwRenamedSig_OI_S_AXI_R_LAST,
Q => gaxi_full_sm_r_last_r_17
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_13
);
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 : STATE_LOGIC
generic map(
INIT => X"000000000000000B"
)
port map (
I0 => S_AXI_RREADY,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o
);
Mmux_S_AXI_SINGLE_TRANS11 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_SINGLE_TRANS
);
Mmux_S_AXI_ADDR_EN11 : STATE_LOGIC
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_ADDR_EN
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"ECEE2022EEEE2022"
)
port map (
I0 => S_AXI_ARVALID,
I1 => present_state_FSM_FFd1_13,
I2 => S_AXI_RREADY,
I3 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I4 => present_state_FSM_FFd2_14,
I5 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
O => present_state_FSM_FFd2_In
);
Mmux_S_AXI_R_LAST131 : STATE_LOGIC
generic map(
INIT => X"0000000044440444"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_RREADY,
I5 => '0',
O => Mmux_S_AXI_R_LAST13
);
Mmux_S_AXI_INCR_ADDR11 : STATE_LOGIC
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => S_AXI_R_LAST_INT,
I1 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => Mmux_S_AXI_R_LAST13,
O => S_AXI_INCR_ADDR
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000FE"
)
port map (
I0 => S_AXI_ARLEN(2),
I1 => S_AXI_ARLEN(1),
I2 => S_AXI_ARLEN(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => N01
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q : STATE_LOGIC
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => S_AXI_ARLEN(7),
I1 => S_AXI_ARLEN(6),
I2 => S_AXI_ARLEN(5),
I3 => S_AXI_ARLEN(4),
I4 => S_AXI_ARLEN(3),
I5 => N01,
O => S_AXI_ARLEN_7_GND_8_o_equal_1_o
);
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_gaxi_full_sm_outstanding_read_c1 : STATE_LOGIC
generic map(
INIT => X"0020000002200200"
)
port map (
I0 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd1_13,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => N2,
O => gaxi_full_sm_outstanding_read_c
);
Mmux_gaxi_full_sm_ar_ready_c12 : STATE_LOGIC
generic map(
INIT => X"0000000000004555"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => '0',
I5 => '0',
O => Mmux_gaxi_full_sm_ar_ready_c11
);
Mmux_S_AXI_R_LAST11_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000EF"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
Mmux_S_AXI_R_LAST11 : STATE_LOGIC
generic map(
INIT => X"FCAAFC0A00AA000A"
)
port map (
I0 => S_AXI_ARVALID,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => N4,
I5 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
O => gaxi_full_sm_r_valid_c
);
S_AXI_MUX_SEL1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAAAA08"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => '0',
O => S_AXI_MUX_SEL
);
Mmux_S_AXI_RD_EN11 : STATE_LOGIC
generic map(
INIT => X"F3F3F755A2A2A200"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => gaxi_full_sm_outstanding_read_r_15,
I4 => present_state_FSM_FFd2_14,
I5 => S_AXI_ARVALID,
O => S_AXI_RD_EN
);
present_state_FSM_FFd1_In3 : beh_muxf7
port map (
I0 => N8,
I1 => N9,
S => present_state_FSM_FFd1_13,
O => present_state_FSM_FFd1_In
);
present_state_FSM_FFd1_In3_F : STATE_LOGIC
generic map(
INIT => X"000000005410F4F0"
)
port map (
I0 => S_AXI_RREADY,
I1 => present_state_FSM_FFd2_14,
I2 => S_AXI_ARVALID,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => '0',
O => N8
);
present_state_FSM_FFd1_In3_G : STATE_LOGIC
generic map(
INIT => X"0000000072FF7272"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N9
);
Mmux_gaxi_full_sm_ar_ready_c14 : beh_muxf7
port map (
I0 => N10,
I1 => N11,
S => present_state_FSM_FFd1_13,
O => gaxi_full_sm_ar_ready_c
);
Mmux_gaxi_full_sm_ar_ready_c14_F : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88A8"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => Mmux_gaxi_full_sm_ar_ready_c11,
I5 => '0',
O => N10
);
Mmux_gaxi_full_sm_ar_ready_c14_G : STATE_LOGIC
generic map(
INIT => X"000000008D008D8D"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N11
);
Mmux_S_AXI_R_LAST1 : beh_muxf7
port map (
I0 => N12,
I1 => N13,
S => present_state_FSM_FFd1_13,
O => NlwRenamedSig_OI_S_AXI_R_LAST
);
Mmux_S_AXI_R_LAST1_F : STATE_LOGIC
generic map(
INIT => X"0000000088088888"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N12
);
Mmux_S_AXI_R_LAST1_G : STATE_LOGIC
generic map(
INIT => X"00000000E400E4E4"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => S_AXI_R_LAST_INT,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N13
);
end STRUCTURE;
-------------------------------------------------------------------------------
-- Output Register Stage Entity
--
-- This module builds the output register stages of the memory. This module is
-- instantiated in the main memory module (blk_mem_gen_v8_3_1) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_output_stage IS
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_output_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6" and "virtex6l".
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
-- C_HAS_RST : Determines the presence of the RST port
-- C_RSTRAM : Determines if special reset behavior is used
-- C_RST_PRIORITY : Determines the priority between CE and SR
-- C_INIT_VAL : Initialization value
-- C_HAS_EN : Determines the presence of the EN port
-- C_HAS_REGCE : Determines the presence of the REGCE port
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
-- of the RAM primitive
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- NUM_STAGES : Determines the number of output stages
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE output_stage_behavioral OF blk_mem_gen_v8_3_1_output_stage IS
--*******************************************************
-- Functions used in the output stage ARCHITECTURE
--*******************************************************
-- Calculate num_reg_stages
FUNCTION get_num_reg_stages(NUM_STAGES: INTEGER) RETURN INTEGER IS
VARIABLE num_reg_stages : INTEGER := 0;
BEGIN
IF (NUM_STAGES = 0) THEN
num_reg_stages := 0;
ELSE
num_reg_stages := NUM_STAGES - 1;
END IF;
RETURN num_reg_stages;
END get_num_reg_stages;
-- Check if the INTEGER is zero or non-zero
FUNCTION int_to_bit(input: INTEGER) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = 0) THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END int_to_bit;
-- Constants
CONSTANT HAS_EN : STD_LOGIC := int_to_bit(C_HAS_EN);
CONSTANT HAS_REGCE : STD_LOGIC := int_to_bit(C_HAS_REGCE);
CONSTANT HAS_RST : STD_LOGIC := int_to_bit(C_HAS_RST);
CONSTANT REG_STAGES : INTEGER := get_num_reg_stages(NUM_STAGES);
-- Pipeline array
TYPE reg_data_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
TYPE reg_ecc_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC;
TYPE reg_eccaddr_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
CONSTANT REG_INIT : reg_data_array := (OTHERS => init_val);
SIGNAL out_regs : reg_data_array := REG_INIT;
SIGNAL sbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL dbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL rdaddrecc_regs: reg_eccaddr_array := (OTHERS => (OTHERS => '0'));
-- Internal signals
SIGNAL en_i : STD_LOGIC;
SIGNAL regce_i : STD_LOGIC;
SIGNAL rst_i : STD_LOGIC;
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := init_val;
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL DIN : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL RDADDRECC_IN : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ;
SIGNAL SBITERR_IN : STD_LOGIC := '0';
SIGNAL DBITERR_IN : STD_LOGIC := '0';
BEGIN
--***********************************************************************
-- Assign internal signals. This effectively wires off optional inputs.
--***********************************************************************
-- Internal enable for output registers is tied to user EN or '1' depending
-- on parameters
en_i <= EN OR (NOT HAS_EN);
-- Internal register enable for output registers is tied to user REGCE, EN
-- or '1' depending on parameters
regce_i <= (HAS_REGCE AND REGCE)
OR ((NOT HAS_REGCE) AND en_i);
-- Internal SRR is tied to user RST or '0' depending on parameters
rst_i <= RST AND HAS_RST;
--***************************************************************************
-- NUM_STAGES = 0 (No output registers. RAM only)
--***************************************************************************
zero_stages: IF (NUM_STAGES = 0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE zero_stages;
NO_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 0) GENERATE
DIN <= DIN_I;
RDADDRECC_IN <= RDADDRECC_IN_I;
SBITERR_IN <= SBITERR_IN_I;
DBITERR_IN <= DBITERR_IN_I;
END GENERATE NO_ECC_PIPE_REG;
WITH_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(ECCPIPECE = '1') THEN
DIN <= DIN_I AFTER FLOP_DELAY;
RDADDRECC_IN <= RDADDRECC_IN_I AFTER FLOP_DELAY;
SBITERR_IN <= SBITERR_IN_I AFTER FLOP_DELAY;
DBITERR_IN <= DBITERR_IN_I AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS;
END GENERATE WITH_ECC_PIPE_REG;
--***************************************************************************
-- NUM_STAGES = 1
-- (Mem Output Reg only or Mux Output Reg only)
--***************************************************************************
-- Possible valid combinations:
-- Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
-- +-----------------------------------------+
-- | C_RSTRAM_* | Reset Behavior |
-- +----------------+------------------------+
-- | 0 | Normal Behavior |
-- +----------------+------------------------+
-- | 1 | Special Behavior |
-- +----------------+------------------------+
--
-- Normal = REGCE gates reset, as in the case of all Virtex families and all
-- spartan families with the exception of S3ADSP and S6.
-- Special = EN gates reset, as in the case of S3ADSP and S6.
one_stage_norm: IF (NUM_STAGES = 1 AND
(C_RSTRAM=0 OR (C_RSTRAM=1 AND (C_XDEVICEFAMILY/="spartan3adsp" AND C_XDEVICEFAMILY/="aspartan3adsp")) OR
C_HAS_MEM_OUTPUT_REGS=0 OR C_HAS_RST=0)) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i = '1' AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
END IF;--CLK
END PROCESS;
END GENERATE one_stage_norm;
-- Special Reset Behavior for S6 and S3ADSP
one_stage_splbhv: IF (NUM_STAGES=1 AND C_RSTRAM=1 AND (C_XDEVICEFAMILY ="spartan3adsp" OR C_XDEVICEFAMILY ="aspartan3adsp"))
GENERATE
DOUT <= dout_i;
SBITERR <= '0';
DBITERR <= '0';
RDADDRECC <= (OTHERS => '0');
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (rst_i='1' AND en_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
ELSIF (regce_i='1' AND rst_i/='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE one_stage_splbhv;
--****************************************************************************
-- NUM_STAGES > 1
-- Mem Output Reg + Mux Output Reg
-- or
-- Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
-- or
-- Mux Pipeline Stages (>0) + Mux Output Reg
--****************************************************************************
multi_stage: IF (NUM_STAGES > 1) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i='1'AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
IF (en_i='1') THEN
-- Shift the data through the output stages
FOR i IN 1 TO REG_STAGES-1 LOOP
out_regs(i) <= out_regs(i-1) AFTER FLOP_DELAY;
sbiterr_regs(i) <= sbiterr_regs(i-1) AFTER FLOP_DELAY;
dbiterr_regs(i) <= dbiterr_regs(i-1) AFTER FLOP_DELAY;
rdaddrecc_regs(i) <= rdaddrecc_regs(i-1) AFTER FLOP_DELAY;
END LOOP;
out_regs(0) <= DIN;
sbiterr_regs(0) <= SBITERR_IN;
dbiterr_regs(0) <= DBITERR_IN;
rdaddrecc_regs(0) <= RDADDRECC_IN;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE multi_stage;
END output_stage_behavioral;
-------------------------------------------------------------------------------
-- SoftECC Output Register Stage Entity
-- This module builds the softecc output register stages. This module is
-- instantiated in the memory module (blk_mem_gen_v8_3_1_mem_module) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ;
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- of the RAM primitive
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE softecc_output_reg_stage_behavioral OF blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
-- Internal signals
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
--***************************************************************************
-- NO OUTPUT STAGES
--***************************************************************************
no_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE no_output_stage;
--****************************************************************************
-- WITH OUTPUT STAGE
--****************************************************************************
has_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END PROCESS;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
END GENERATE has_output_stage;
END softecc_output_reg_stage_behavioral;
--******************************************************************************
-- Main Memory module
--
-- This module is the behavioral model which implements the RAM
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
ENTITY blk_mem_gen_v8_3_1_mem_module IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_mem_module;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE mem_module_behavioral OF blk_mem_gen_v8_3_1_mem_module IS
--****************************************
-- min/max constant functions
--****************************************
-- get_max
----------
function SLV_TO_INT(SLV: in std_logic_vector
) return integer is
variable int : integer;
begin
int := 0;
for i in SLV'high downto SLV'low loop
int := int * 2;
if SLV(i) = '1' then
int := int + 1;
end if;
end loop;
return int;
end;
FUNCTION get_max(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a > b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-- get_min
----------
FUNCTION get_min(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
--***************************************************************
-- convert write_mode from STRING type for use in case statement
--***************************************************************
FUNCTION write_mode_to_vector(mode: STRING) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF (mode = "NO_CHANGE") THEN
RETURN "10";
ELSIF (mode = "READ_FIRST") THEN
RETURN "01";
ELSE
RETURN "00"; -- WRITE_FIRST
END IF;
END FUNCTION;
--***************************************************************
-- convert hex STRING to STD_LOGIC_VECTOR
--***************************************************************
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
--***************************************************************
-- locally derived constants to determine memory shape
--***************************************************************
CONSTANT MIN_WIDTH_A : INTEGER := get_min(C_WRITE_WIDTH_A, C_READ_WIDTH_A);
CONSTANT MIN_WIDTH_B : INTEGER := get_min(C_WRITE_WIDTH_B,C_READ_WIDTH_B);
CONSTANT MIN_WIDTH : INTEGER := get_min(MIN_WIDTH_A, MIN_WIDTH_B);
CONSTANT MAX_DEPTH_A : INTEGER := get_max(C_WRITE_DEPTH_A, C_READ_DEPTH_A);
CONSTANT MAX_DEPTH_B : INTEGER := get_max(C_WRITE_DEPTH_B, C_READ_DEPTH_B);
CONSTANT MAX_DEPTH : INTEGER := get_max(MAX_DEPTH_A, MAX_DEPTH_B);
TYPE int_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF std_logic_vector(C_WRITE_WIDTH_A-1 DOWNTO 0);
TYPE mem_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC_VECTOR(MIN_WIDTH-1 DOWNTO 0);
TYPE ecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
TYPE softecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
--***************************************************************
-- memory initialization function
--***************************************************************
IMPURE FUNCTION init_memory(DEFAULT_DATA :
STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
write_width_a : INTEGER;
depth : INTEGER;
width : INTEGER)
RETURN mem_array IS
VARIABLE init_return : mem_array := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(write_width_a-1 DOWNTO 0);
VARIABLE int_mem_vector : int_array:= (OTHERS => (OTHERS => '0'));
VARIABLE file_buffer : LINE;
VARIABLE i : INTEGER := 0;
VARIABLE j : INTEGER;
VARIABLE k : INTEGER;
VARIABLE ignore_line : BOOLEAN := false;
VARIABLE good_data : BOOLEAN := false;
VARIABLE char_tmp : CHARACTER;
VARIABLE index : INTEGER;
variable init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable data : std_logic_vector(255 downto 0) := (others => '0');
variable inside_init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable k_slv : std_logic_vector(31 downto 0) := (others => '0');
variable i_slv : std_logic_vector(31 downto 0) := (others => '0');
VARIABLE disp_line : line := null;
variable open_status : file_open_status;
variable input_initf_tmp : mem_array ;
variable input_initf : mem_array := (others => (others => '0'));
file int_infile : text;
variable data_line, data_line_tmp, out_data_line : line;
variable slv_width : integer;
VARIABLE d_l : LINE;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
index := 0;
FOR i IN 0 TO depth-1 LOOP
FOR j IN 0 TO width-1 LOOP
init_return(i)(j) := DEFAULT_DATA(index);
index := (index + 1) MOD C_WRITE_WIDTH_A;
END LOOP;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, file_buffer);
read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO write_width_a-1 LOOP
IF (j MOD width = 0 AND j /= 0) THEN
i := i + 1;
END IF;
init_return(i)(j MOD width) := bit_to_sl(mem_vector(j));
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
--Display output message indicating that the behavioral model is done
--initializing
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator data initialization complete." SEVERITY NOTE;
if (C_USE_BRAM_BLOCK = 1) then
--Display output message indicating that the behavioral model is being
--initialized
-- Read in the .mem file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_INIT_FILE /= "NONE") then
file_open(open_status, int_infile, C_INIT_FILE, read_mode);
while not endfile(int_infile) loop
readline(int_infile, data_line);
while (data_line /= null and data_line'length > 0) loop
if (data_line(data_line'low to data_line'low + 1) = "//") then
deallocate(data_line);
elsif ((data_line(data_line'low to data_line'low + 1) = "/*") and (data_line(data_line'high-1 to data_line'high) = "*/")) then
deallocate(data_line);
elsif (data_line(data_line'low to data_line'low + 1) = "/*") then
deallocate(data_line);
ignore_line := true;
elsif (ignore_line = true and data_line(data_line'high-1 to data_line'high) = "*/") then
deallocate(data_line);
ignore_line := false;
elsif (ignore_line = false and data_line(data_line'low) = '@') then
read(data_line, char_tmp);
hread(data_line, init_addr_slv, good_data);
i := SLV_TO_INT(init_addr_slv);
elsif (ignore_line = false) then
hread(data_line, input_initf_tmp(i), good_data);
init_return(i)(write_width_a - 1 downto 0) := input_initf_tmp(i)(write_width_a - 1 downto 0);
if (good_data = true) then
i := i + 1;
end if;
else
deallocate(data_line);
end if;
end loop;
end loop;
file_close(int_infile);
END IF;
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- memory type constants
--***************************************************************
CONSTANT MEM_TYPE_SP_RAM : INTEGER := 0;
CONSTANT MEM_TYPE_SDP_RAM : INTEGER := 1;
CONSTANT MEM_TYPE_TDP_RAM : INTEGER := 2;
CONSTANT MEM_TYPE_SP_ROM : INTEGER := 3;
CONSTANT MEM_TYPE_DP_ROM : INTEGER := 4;
--***************************************************************
-- memory configuration constant functions
--***************************************************************
--get_single_port
-----------------
FUNCTION get_single_port(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_RAM OR mem_type=MEM_TYPE_SP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_single_port;
--get_is_rom
--------------
FUNCTION get_is_rom(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_ROM OR mem_type=MEM_TYPE_DP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_is_rom;
--get_has_a_write
------------------
FUNCTION get_has_a_write(IS_ROM : INTEGER) RETURN INTEGER IS
BEGIN
IF (IS_ROM=0) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_a_write;
--get_has_b_write
------------------
FUNCTION get_has_b_write(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_TDP_RAM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_write;
--get_has_a_read
------------------
FUNCTION get_has_a_read(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SDP_RAM) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_a_read;
--get_has_b_read
------------------
FUNCTION get_has_b_read(SINGLE_PORT : INTEGER) RETURN INTEGER IS
BEGIN
IF (SINGLE_PORT=1) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_b_read;
--get_has_b_port
------------------
FUNCTION get_has_b_port(HAS_B_READ : INTEGER;
HAS_B_WRITE : INTEGER)
RETURN INTEGER IS
BEGIN
IF (HAS_B_READ=1 OR HAS_B_WRITE=1) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_port;
--get_num_output_stages
-----------------------
FUNCTION get_num_output_stages(has_mem_output_regs : INTEGER;
has_mux_output_regs : INTEGER;
mux_pipeline_stages : INTEGER)
RETURN INTEGER IS
VARIABLE actual_mux_pipeline_stages : INTEGER;
BEGIN
-- Mux pipeline stages can be non-zero only when there is a mux
-- output register.
IF (has_mux_output_regs=1) THEN
actual_mux_pipeline_stages := mux_pipeline_stages;
ELSE
actual_mux_pipeline_stages := 0;
END IF;
RETURN has_mem_output_regs+actual_mux_pipeline_stages+has_mux_output_regs;
END get_num_output_stages;
--***************************************************************************
-- Component declaration of the VARIABLE depth output register stage
--***************************************************************************
COMPONENT blk_mem_gen_v8_3_1_output_stage
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
EN : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
ECCPIPECE : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_output_stage;
COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************************************
-- locally derived constants to assist memory access
--******************************************************
CONSTANT WRITE_WIDTH_RATIO_A : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_A : INTEGER := C_READ_WIDTH_A/MIN_WIDTH;
CONSTANT WRITE_WIDTH_RATIO_B : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_B : INTEGER := C_READ_WIDTH_B/MIN_WIDTH;
--******************************************************
-- To modify the LSBs of the 'wider' data to the actual
-- address value
--******************************************************
CONSTANT WRITE_ADDR_A_DIV : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH_A;
CONSTANT READ_ADDR_A_DIV : INTEGER := C_READ_WIDTH_A/MIN_WIDTH_A;
CONSTANT WRITE_ADDR_B_DIV : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH_B;
CONSTANT READ_ADDR_B_DIV : INTEGER := C_READ_WIDTH_B/MIN_WIDTH_B;
--******************************************************
-- FUNCTION : log2roundup
--******************************************************
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
--******************************************************
-- Other constants and signals
--******************************************************
CONSTANT COLL_DELAY : TIME := 100 ps;
-- default data vector
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_DEFAULT_DATA,
C_WRITE_WIDTH_A);
CONSTANT CHKBIT_WIDTH : INTEGER := if_then_else(C_WRITE_WIDTH_A>57,8,if_then_else(C_WRITE_WIDTH_A>26,7,if_then_else(C_WRITE_WIDTH_A>11,6,if_then_else(C_WRITE_WIDTH_A>4,5,if_then_else(C_WRITE_WIDTH_A<5,4,0)))));
-- the init memory SIGNAL
SIGNAL memory_i : mem_array;
SIGNAL doublebit_error_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0);
SIGNAL current_contents_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
-- write mode constants
CONSTANT WRITE_MODE_A : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_A);
CONSTANT WRITE_MODE_B : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_B);
CONSTANT WRITE_MODES : STD_LOGIC_VECTOR(3 DOWNTO 0) :=
WRITE_MODE_A & WRITE_MODE_B;
-- reset values
CONSTANT INITA_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITA_VAL,
C_READ_WIDTH_A);
CONSTANT INITB_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITB_VAL,
C_READ_WIDTH_B);
-- memory output 'latches'
SIGNAL memory_out_a : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0) :=
INITA_VAL;
SIGNAL memory_out_b : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) :=
INITB_VAL;
SIGNAL sbiterr_in : STD_LOGIC := '0';
SIGNAL sbiterr_sdp : STD_LOGIC := '0';
SIGNAL dbiterr_in : STD_LOGIC := '0';
SIGNAL dbiterr_sdp : STD_LOGIC := '0';
SIGNAL rdaddrecc_in : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_sdp : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL doutb_i : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i : STD_LOGIC := '0';
SIGNAL dbiterr_i : STD_LOGIC := '0';
-- memory configuration constants
-----------------------------------------------
CONSTANT SINGLE_PORT : INTEGER := get_single_port(C_MEM_TYPE);
CONSTANT IS_ROM : INTEGER := get_is_rom(C_MEM_TYPE);
CONSTANT HAS_A_WRITE : INTEGER := get_has_a_write(IS_ROM);
CONSTANT HAS_B_WRITE : INTEGER := get_has_b_write(C_MEM_TYPE);
CONSTANT HAS_A_READ : INTEGER := get_has_a_read(C_MEM_TYPE);
CONSTANT HAS_B_READ : INTEGER := get_has_b_read(SINGLE_PORT);
CONSTANT HAS_B_PORT : INTEGER := get_has_b_port(HAS_B_READ, HAS_B_WRITE);
CONSTANT NUM_OUTPUT_STAGES_A : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_A,
C_MUX_PIPELINE_STAGES);
CONSTANT NUM_OUTPUT_STAGES_B : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES);
CONSTANT WEA0 : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT WEB0 : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-----------------------------------------------------------------------------
-- DEBUG CONTROL
-- DEBUG=0 : Debug output OFF
-- DEBUG=1 : Some debug info printed
-----------------------------------------------------------------------------
CONSTANT DEBUG : INTEGER := 0;
-- internal signals
-----------------------------------------------
SIGNAL ena_i : STD_LOGIC;
SIGNAL enb_i : STD_LOGIC;
SIGNAL reseta_i : STD_LOGIC;
SIGNAL resetb_i : STD_LOGIC;
SIGNAL wea_i : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL web_i : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL rea_i : STD_LOGIC;
SIGNAL reb_i : STD_LOGIC;
SIGNAL message_complete : BOOLEAN := false;
SIGNAL rsta_outp_stage : STD_LOGIC := '0';
SIGNAL rstb_outp_stage : STD_LOGIC := '0';
--*********************************************************
--FUNCTION : Collision check
--*********************************************************
FUNCTION collision_check (addr_a :
STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
iswrite_a : BOOLEAN;
addr_b :
STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
iswrite_b : BOOLEAN)
RETURN BOOLEAN IS
VARIABLE c_aw_bw : INTEGER;
VARIABLE c_aw_br : INTEGER;
VARIABLE c_ar_bw : INTEGER;
VARIABLE write_addr_a_width : INTEGER;
VARIABLE read_addr_a_width : INTEGER;
VARIABLE write_addr_b_width : INTEGER;
VARIABLE read_addr_b_width : INTEGER;
BEGIN
c_aw_bw := 0;
c_aw_br := 0;
c_ar_bw := 0;
-- Determine the effective address widths FOR each of the 4 ports
write_addr_a_width := C_ADDRA_WIDTH-log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width := C_ADDRA_WIDTH-log2roundup(READ_ADDR_A_DIV);
write_addr_b_width := C_ADDRB_WIDTH-log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width := C_ADDRB_WIDTH-log2roundup(READ_ADDR_B_DIV);
--Look FOR a write-write collision. In order FOR a write-write
--collision to exist, both ports must have a write transaction.
IF (iswrite_a AND iswrite_b) THEN
IF (write_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_a and iswrite_b
--If the B port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_a) THEN
IF (write_addr_a_width > read_addr_b_width) THEN
--read_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_b_width
--Once both are scaled to read_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
END IF; --width
END IF; --iswrite_a
--If the A port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_b) THEN
IF (read_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
ELSE
--read_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_a_width
--Once both are scaled to read_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_b
RETURN (c_aw_bw=1 OR c_aw_br=1 OR c_ar_bw=1);
END FUNCTION collision_check;
BEGIN -- Architecture
-----------------------------------------------------------------------------
-- SOFTECC and ECC SBITERR/DBITERR Outputs
-- The ECC Behavior is modeled by the behavioral models only for Virtex-6.
-- The SOFTECC Behavior is modeled by the behavioral models for Spartan-6.
-- For Virtex-5, these outputs will be tied to 0.
-----------------------------------------------------------------------------
SBITERR <= sbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_sdp WHEN (((C_FAMILY="virtex7") AND C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
-----------------------------------------------
-- This effectively wires off optional inputs
-----------------------------------------------
ena_i <= ENA WHEN (C_HAS_ENA=1) ELSE '1';
enb_i <= ENB WHEN (C_HAS_ENB=1 AND HAS_B_PORT=1) ELSE '1';
-- We are doing an "AND" operation of WEA and ENA and passing to Enbale pin of BRAM when built-in ECC is enabled,
-- what this means is that the write operation happens only when both WEA and ENA are high.
wea_i <= WEA WHEN (HAS_A_WRITE=1 AND ena_i='1') ELSE WEA0;
-- wea_i <= (OTHERS => '1') WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=1 AND ENA = '1') ELSE -- Use_ENA_pin
-- WEA WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=0) ELSE -- Always_enabled
-- WEA WHEN (HAS_A_WRITE=1 AND ena_i='1' AND C_USE_ECC = 0) ELSE
-- WEA0;
web_i <= WEB WHEN (HAS_B_WRITE=1 AND enb_i='1') ELSE WEB0;
rea_i <= ena_i WHEN (HAS_A_READ=1) ELSE '0';
reb_i <= enb_i WHEN (HAS_B_READ=1) ELSE '0';
-- these signals reset the memory latches
-- For the special reset behaviors in some of the families, the C_RSTRAM
-- attribute of the corresponding port is used to indicate if the latch is
-- reset or not.
reseta_i <= RSTA WHEN
((C_HAS_RSTA=1 AND NUM_OUTPUT_STAGES_A=0) OR
(C_HAS_RSTA=1 AND C_RSTRAM_A=1))
ELSE '0';
resetb_i <= RSTB WHEN
((C_HAS_RSTB=1 AND NUM_OUTPUT_STAGES_B=0) OR
(C_HAS_RSTB=1 AND C_RSTRAM_B=1) )
ELSE '0';
--***************************************************************************
-- This is the main PROCESS which includes the memory VARIABLE and the read
-- and write procedures. It also schedules read and write operations
--***************************************************************************
PROCESS (CLKA, CLKB,rea_i,reb_i,reseta_i,resetb_i)
-- Initialize the init memory array
------------------------------------
VARIABLE memory : mem_array := init_memory(DEFAULT_DATA,
C_WRITE_WIDTH_A,
MAX_DEPTH,
MIN_WIDTH);
-- Initialize the mem memory array
------------------------------------
VARIABLE softecc_sbiterr_arr : softecc_err_array;
VARIABLE softecc_dbiterr_arr : softecc_err_array;
VARIABLE sbiterr_arr : ecc_err_array;
VARIABLE dbiterr_arr : ecc_err_array;
CONSTANT doublebit_lsb : STD_LOGIC_VECTOR (1 DOWNTO 0):="11";
CONSTANT doublebit_msb : STD_LOGIC_VECTOR (C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 DOWNTO 0):= (OTHERS => '0');
VARIABLE doublebit_error : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0) := doublebit_msb & doublebit_lsb ;
VARIABLE current_contents_var : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
--***********************************
-- procedures to access the memory
--***********************************
-- write_a
----------
PROCEDURE write_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
inj_sbiterr : IN STD_LOGIC;
inj_dbiterr : IN STD_LOGIC) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
VARIABLE message : LINE;
VARIABLE errbit_current_contents : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
-- Block Memory Generator non-cycle-accurate message
ASSERT (message_complete) REPORT "Block Memory Generator module is using a behavioral model FOR simulation which will not precisely model memory collision behavior."
SEVERITY NOTE;
message_complete <= true;
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_A_DIV);
IF (address_i >= C_WRITE_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range FOR A Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEA = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_A + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEA_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Insert double bit errors:
IF (C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
current_contents(0) := NOT(current_contents(0));
current_contents(1) := NOT(current_contents(1));
--current_contents(0) := NOT(current_contents(30));
--current_contents(1) := NOT(current_contents(62));
END IF;
END IF;
-- Insert double bit errors:
IF (C_USE_SOFTECC=1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 downto 2) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 downto 0);
doublebit_error(0) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1);
doublebit_error(1) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-2);
current_contents := current_contents XOR doublebit_error(C_WRITE_WIDTH_A-1 DOWNTO 0);
END IF;
END IF;
IF(DEBUG=1) THEN
current_contents_var := current_contents; --for debugging current
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_A + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
-- Store address at which error is injected:
IF ((C_FAMILY = "virtex7") AND C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
sbiterr_arr(address_i) := '1';
ELSE
sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
dbiterr_arr(address_i) := '1';
ELSE
dbiterr_arr(address_i) := '0';
END IF;
END IF;
-- Store address at which softecc error is injected:
IF (C_USE_SOFTECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
softecc_sbiterr_arr(address_i) := '1';
ELSE
softecc_sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
softecc_dbiterr_arr(address_i) := '1';
ELSE
softecc_dbiterr_arr(address_i) := '0';
END IF;
END IF;
END IF;
END PROCEDURE;
-- write_b
----------
PROCEDURE write_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_B_DIV);
IF (address_i >= C_WRITE_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEB = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_B + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEB_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_B + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
END IF;
END PROCEDURE;
-- read_a
----------
PROCEDURE read_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_A_DIV);
IF (address_i >= C_READ_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for A Read"
SEVERITY WARNING;
END IF;
memory_out_a <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_A-1 LOOP
memory_out_a(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_A + i) AFTER FLOP_DELAY;
END LOOP;
END IF;
END IF;
END PROCEDURE;
-- read_b
----------
PROCEDURE read_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_B_DIV);
IF (address_i >= C_READ_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Read"
SEVERITY WARNING;
END IF;
memory_out_b <= (OTHERS => 'X') AFTER FLOP_DELAY;
sbiterr_in <= 'X' AFTER FLOP_DELAY;
dbiterr_in <= 'X' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_B-1 LOOP
memory_out_b(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_B + i) AFTER FLOP_DELAY;
END LOOP;
--assert sbiterr and dbiterr signals
IF ((C_FAMILY="virtex7") AND C_USE_ECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
--assert softecc sbiterr and dbiterr signals
ELSIF (C_USE_SOFTECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (softecc_sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (softecc_dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
END IF;
END IF;
END IF;
END PROCEDURE;
-- reset_a
----------
PROCEDURE reset_a
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
-- reset_b
----------
PROCEDURE reset_b
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
BEGIN -- begin the main PROCESS
--***************************************************************************
-- These are the main blocks which schedule read and write operations
-- Note that the reset priority feature at the latch stage is only supported
-- for Spartan-6. For other families, the default priority at the latch stage
-- is "CE"
--***************************************************************************
-- Synchronous clocks: schedule port operations with respect to both
-- write operating modes
IF (C_COMMON_CLK=1) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODES IS
WHEN "0000" => -- write_first write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "0100" => -- read_first write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "0001" => -- write_first read_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0101" => --read_first read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0010" => -- write_first no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0110" => -- read_first no_change
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1000" => -- no_change write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "1001" => -- no_change read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1010" => -- no_change no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Synchronous clocks
-- Asynchronous clocks: port operation is independent
IF (C_COMMON_CLK=0) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODE_A IS
WHEN "00" => -- write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN "01" => -- read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "10" => -- no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
IF (CLKB='1' AND CLKB'EVENT) THEN
CASE WRITE_MODE_B IS
WHEN "00" => -- write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "01" => -- read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "10" => -- no_change
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Asynchronous clocks
-- Assign the memory VARIABLE to the user_visible memory_i SIGNAL
IF(DEBUG=1) THEN
memory_i <= memory;
doublebit_error_i <= doublebit_error;
current_contents_i <= current_contents_var;
END IF;
END PROCESS;
--********************************************************************
-- Instantiate the VARIABLE depth output stage
--********************************************************************
-- Port A
rsta_outp_stage <= RSTA and not sleep;
rstb_outp_stage <= RSTB and not sleep;
reg_a : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTA,
C_RSTRAM => C_RSTRAM_A,
C_RST_PRIORITY => C_RST_PRIORITY_A,
init_val => INITA_VAL,
C_HAS_EN => C_HAS_ENA,
C_HAS_REGCE => C_HAS_REGCEA,
C_DATA_WIDTH => C_READ_WIDTH_A,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_A,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_A,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKA,
RST => rsta_outp_stage, --RSTA,
EN => ENA,
REGCE => REGCEA,
DIN_I => memory_out_a,
DOUT => DOUTA,
SBITERR_IN_I => '0',
DBITERR_IN_I => '0',
SBITERR => OPEN,
DBITERR => OPEN,
RDADDRECC_IN_I => (OTHERS => '0'),
ECCPIPECE => '0',
RDADDRECC => OPEN
);
-- Port B
reg_b : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTB,
C_RSTRAM => C_RSTRAM_B,
C_RST_PRIORITY => C_RST_PRIORITY_B,
init_val => INITB_VAL,
C_HAS_EN => C_HAS_ENB,
C_HAS_REGCE => C_HAS_REGCEB,
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_B,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKB,
RST => rstb_outp_stage,--RSTB,
EN => ENB,
REGCE => REGCEB,
DIN_I => memory_out_b,
DOUT => doutb_i,
SBITERR_IN_I => sbiterr_in,
DBITERR_IN_I => dbiterr_in,
SBITERR => sbiterr_i,
DBITERR => dbiterr_i,
RDADDRECC_IN_I => rdaddrecc_in,
ECCPIPECE => ECCPIPECE,
RDADDRECC => rdaddrecc_i
);
--********************************************************************
-- Instantiate the input / Output Register stages
--********************************************************************
output_reg_stage: blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC MAP(
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP(
CLK => CLKB,
DIN => doutb_i,
DOUT => DOUTB,
SBITERR_IN => sbiterr_i,
DBITERR_IN => dbiterr_i,
SBITERR => sbiterr_sdp,
DBITERR => dbiterr_sdp,
RDADDRECC_IN => rdaddrecc_i,
RDADDRECC => rdaddrecc_sdp
);
--*********************************
-- Synchronous collision checks
--*********************************
sync_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=1) GENERATE
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
-- collision detect
VARIABLE is_collision : BOOLEAN;
VARIABLE message : LINE;
BEGIN
IF (CLKA='1' AND CLKA'EVENT) THEN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision := false;
END IF;
-- If the write port is in READ_FIRST mode, there is no collision
IF (C_WRITE_MODE_A="READ_FIRST" AND wea_i/=WEA0 AND web_i=WEB0) THEN
is_collision := false;
END IF;
IF (C_WRITE_MODE_B="READ_FIRST" AND web_i/=WEB0 AND wea_i=WEA0) THEN
is_collision := false;
END IF;
-- Only flag if one of the accesses is a write
IF (is_collision AND (wea_i/=WEA0 OR web_i/=WEB0)) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END IF;
END PROCESS;
END GENERATE;
--*********************************
-- Asynchronous collision checks
--*********************************
async_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=0) GENERATE
SIGNAL addra_delay : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL wea_delay : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL ena_delay : STD_LOGIC;
SIGNAL addrb_delay : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
SIGNAL web_delay : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL enb_delay : STD_LOGIC;
BEGIN
-- Delay A and B addresses in order to mimic setup/hold times
PROCESS (ADDRA, wea_i, ena_i, ADDRB, web_i, enb_i)
BEGIN
addra_delay <= ADDRA AFTER COLL_DELAY;
wea_delay <= wea_i AFTER COLL_DELAY;
ena_delay <= ena_i AFTER COLL_DELAY;
addrb_delay <= ADDRB AFTER COLL_DELAY;
web_delay <= web_i AFTER COLL_DELAY;
enb_delay <= enb_i AFTER COLL_DELAY;
END PROCESS;
-- Do the checks w/rt A
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_a : BOOLEAN;
VARIABLE is_collision_delay_a : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_a := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_a := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_delay_a := collision_check(ADDRA,
wea_i/=WEA0,
addrb_delay,
web_delay/=WEB0);
ELSE
is_collision_delay_a := false;
END IF;
-- Only flag if B access is a write
IF (is_collision_a AND web_i/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_a AND web_delay/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, addrb_delay);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
-- Do the checks w/rt B
PROCESS (CLKB)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_b : BOOLEAN;
VARIABLE is_collision_delay_b : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA) /= 'X') THEN
is_collision_b := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_b := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(addra_delay) /= 'X') THEN
is_collision_delay_b := collision_check(addra_delay,
wea_delay/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_delay_b := false;
END IF;
-- Only flag if A access is a write
-- Modified condition checking (is_collision_b AND WEA0_i=/WEA0) to fix CR526228
IF (is_collision_b AND wea_i/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_b AND wea_delay/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, addra_delay);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
END GENERATE;
END mem_module_behavioral;
--******************************************************************************
-- Top module that wraps SoftECC Input register stage and the main memory module
--
-- This module is the top-level of behavioral model
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1 IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_CTRL_ECC_ALGO : STRING := "NONE";
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
--C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_SLEEP_PIN : INTEGER := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
PORT (
clka : IN STD_LOGIC := '0';
rsta : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '1';
regcea : IN STD_LOGIC := '1';
wea : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addra : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
dina : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
douta : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
clkb : IN STD_LOGIC := '0';
rstb : IN STD_LOGIC := '0';
enb : IN STD_LOGIC := '1';
regceb : IN STD_LOGIC := '1';
web : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addrb : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
dinb : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
doutb : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
injectsbiterr : IN STD_LOGIC := '0';
injectdbiterr : IN STD_LOGIC := '0';
sbiterr : OUT STD_LOGIC := '0';
dbiterr : OUT STD_LOGIC := '0';
rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : in std_logic := '0';
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic := '0';
rstb_busy : out std_logic := '0';
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
s_aclk : IN STD_LOGIC := '0';
s_aresetn : IN STD_LOGIC := '0';
-- axi full/lite slave Write (write side)
s_axi_awid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid : IN STD_LOGIC := '0';
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast : IN STD_LOGIC := '0';
s_axi_wvalid : IN STD_LOGIC := '0';
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC := '0';
-- axi full/lite slave Read (Write side)
s_axi_arid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid : IN STD_LOGIC := '0';
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_rdata : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC := '0';
-- axi full/lite sideband Signals
s_axi_injectsbiterr : IN STD_LOGIC := '0';
s_axi_injectdbiterr : IN STD_LOGIC := '0';
s_axi_sbiterr : OUT STD_LOGIC := '0';
s_axi_dbiterr : OUT STD_LOGIC := '0';
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END blk_mem_gen_v8_3_1;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE behavioral OF blk_mem_gen_v8_3_1 IS
COMPONENT blk_mem_gen_v8_3_1_mem_module
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_mem_module;
COMPONENT blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_axi_regs_fwd_v8_3;
COMPONENT blk_mem_axi_read_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT blk_mem_axi_read_wrapper_beh;
COMPONENT blk_mem_axi_write_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END COMPONENT blk_mem_axi_write_wrapper_beh;
CONSTANT FLOP_DELAY : TIME := 100 ps;
SIGNAL rsta_in : STD_LOGIC := '1';
SIGNAL ena_in : STD_LOGIC := '1';
SIGNAL regcea_in : STD_LOGIC := '1';
SIGNAL wea_in : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL addra_in : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL dina_in : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL injectsbiterr_in : STD_LOGIC := '0';
SIGNAL injectdbiterr_in : STD_LOGIC := '0';
-----------------------------------------------------------------------------
-- FUNCTION: toLowerCaseChar
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
-----------------------------------------------------------------------------
FUNCTION toLowerCaseChar(
char : character )
RETURN character IS
BEGIN
-- If char is not an upper case letter then return char
IF char<'A' OR char>'Z' THEN
RETURN char;
END IF;
-- Otherwise map char to its corresponding lower case character and
-- RETURN that
CASE char IS
WHEN 'A' => RETURN 'a';
WHEN 'B' => RETURN 'b';
WHEN 'C' => RETURN 'c';
WHEN 'D' => RETURN 'd';
WHEN 'E' => RETURN 'e';
WHEN 'F' => RETURN 'f';
WHEN 'G' => RETURN 'g';
WHEN 'H' => RETURN 'h';
WHEN 'I' => RETURN 'i';
WHEN 'J' => RETURN 'j';
WHEN 'K' => RETURN 'k';
WHEN 'L' => RETURN 'l';
WHEN 'M' => RETURN 'm';
WHEN 'N' => RETURN 'n';
WHEN 'O' => RETURN 'o';
WHEN 'P' => RETURN 'p';
WHEN 'Q' => RETURN 'q';
WHEN 'R' => RETURN 'r';
WHEN 'S' => RETURN 's';
WHEN 'T' => RETURN 't';
WHEN 'U' => RETURN 'u';
WHEN 'V' => RETURN 'v';
WHEN 'W' => RETURN 'w';
WHEN 'X' => RETURN 'x';
WHEN 'Y' => RETURN 'y';
WHEN 'Z' => RETURN 'z';
WHEN OTHERS => RETURN char;
END CASE;
END toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
FUNCTION equalIgnoreCase(
str1 : STRING;
str2 : STRING )
RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str2'left TO str1'right LOOP
IF NOT (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equalIgnoreCase;
-----------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
----------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
----------------------------------------------------------------------------
-- FUNCTION : log2roundup
----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
CONSTANT lower_limit : INTEGER := 1;
CONSTANT upper_limit : INTEGER := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
-----------------------------------------------------------------------------
-- FUNCTION : divroundup
-- Returns the ceiling value of the division
-- Data_value - the quantity to be divided, dividend
-- Divisor - the value to divide the data_value by
-----------------------------------------------------------------------------
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
SIGNAL s_axi_awaddr_out_c : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_araddr_out_c : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_wr_en_c : STD_LOGIC := '0';
SIGNAL s_axi_rd_en_c : STD_LOGIC := '0';
SIGNAL s_aresetn_a_c : STD_LOGIC := '0';
--**************************************************************************
-- AXI PARAMETERS
CONSTANT AXI_FULL_MEMORY_SLAVE : integer := if_then_else((C_AXI_SLAVE_TYPE = 0 AND C_AXI_TYPE = 1),1,0);
CONSTANT C_AXI_ADDR_WIDTH_MSB : integer := C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
CONSTANT C_AXI_ADDR_WIDTH : integer := C_AXI_ADDR_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT LOWER_BOUND_VAL : integer := if_then_else((log2roundup(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT C_AXI_ADDR_WIDTH_LSB : integer := if_then_else((AXI_FULL_MEMORY_SLAVE = 1),0,LOWER_BOUND_VAL);
CONSTANT C_AXI_OS_WR : integer := 2;
-- SAFETY LOGIC related Signals
SIGNAL RSTA_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_A : STD_LOGIC := '0';
SIGNAL RSTB_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_B : STD_LOGIC := '0';
SIGNAL ENA_dly : STD_LOGIC := '0';
SIGNAL ENA_dly_D : STD_LOGIC := '0';
SIGNAL ENB_dly : STD_LOGIC := '0';
SIGNAL ENB_dly_D : STD_LOGIC := '0';
SIGNAL RSTA_I_SAFE : STD_LOGIC := '0';
SIGNAL RSTB_I_SAFE : STD_LOGIC := '0';
SIGNAL ENA_I_SAFE : STD_LOGIC := '0';
SIGNAL ENB_I_SAFE : STD_LOGIC := '0';
SIGNAL ram_rstram_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstram_b_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_b_busy : STD_LOGIC := '0';
SIGNAL ENA_dly_reg : STD_LOGIC := '0';
SIGNAL ENB_dly_reg : STD_LOGIC := '0';
SIGNAL ENA_dly_reg_D : STD_LOGIC := '0';
SIGNAL ENB_dly_reg_D : STD_LOGIC := '0';
--**************************************************************************
BEGIN -- Architecture
--*************************************************************************
-- NO INPUT STAGE
--*************************************************************************
no_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=0) GENERATE
rsta_in <= RSTA;
ena_in <= ENA;
regcea_in <= REGCEA;
wea_in <= WEA;
addra_in <= ADDRA;
dina_in <= DINA;
injectsbiterr_in <= INJECTSBITERR;
injectdbiterr_in <= INJECTDBITERR;
END GENERATE no_input_stage;
--**************************************************************************
-- WITH INPUT STAGE
--**************************************************************************
has_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=1) GENERATE
PROCESS (CLKA)
BEGIN
IF (CLKA'EVENT AND CLKA = '1') THEN
rsta_in <= RSTA AFTER FLOP_DELAY;
ena_in <= ENA AFTER FLOP_DELAY;
regcea_in <= REGCEA AFTER FLOP_DELAY;
wea_in <= WEA AFTER FLOP_DELAY;
addra_in <= ADDRA AFTER FLOP_DELAY;
dina_in <= DINA AFTER FLOP_DELAY;
injectsbiterr_in <= INJECTSBITERR AFTER FLOP_DELAY;
injectdbiterr_in <= INJECTDBITERR AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE has_input_stage;
--**************************************************************************
-- NO SAFETY LOGIC
--**************************************************************************
NO_SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 0) GENERATE
ENA_I_SAFE <= ena_in;
ENB_I_SAFE <= ENB;
RSTA_I_SAFE <= rsta_in;
RSTB_I_SAFE <= RSTB;
END GENERATE NO_SAFETY_CKT_GEN;
--**************************************************************************
-- SAFETY LOGIC
--**************************************************************************
SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 1) GENERATE
-- RESET SAFETY LOGIC Generation
-- POR Generation
------------------------------------------------------------------------------
-- Power-ON Reset Generation
------------------------------------------------------------------------------
RST_SHFT_LOGIC_A : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
RSTA_SHFT_REG(4 DOWNTO 0) <= RSTA_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_A;
POR_RSTA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
POR_A <= RSTA_SHFT_REG(4) xor RSTA_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTA_GEN;
RST_SHFT_LOGIC_B : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
RSTB_SHFT_REG(4 DOWNTO 0) <= RSTB_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_B;
POR_RSTB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
POR_B <= RSTB_SHFT_REG(4) xor RSTB_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTB_GEN;
-----------------------------------------------------------------------------
-- Fix for the AR42571
-----------------------------------------------------------------------------
-- Reset Generation
-----------------------------------------------------------------------------
RSTA_I_SAFE <= rsta_in OR POR_A;
SPRAM_RST: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_I_SAFE <= '0';
END GENERATE SPRAM_RST;
nSPRAM_RST: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_I_SAFE <= RSTB OR POR_B;
END GENERATE nSPRAM_RST;
-----------------------------------------------------------------------------
-- RSTA/B_BUSY Generation
-----------------------------------------------------------------------------
RSTA_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
ram_rstram_a_busy <= rsta_in OR ENA_dly OR ENA_dly_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstram_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_NO_REG;
RSTA_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
ram_rstreg_a_busy <= rsta_in OR ENA_dly OR ENA_dly_reg_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstreg_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_WITH_REG;
SPRAM_RST_BUSY: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_BUSY <= '0';
END GENERATE SPRAM_RST_BUSY;
nSPRAM_RST_BUSY: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
ram_rstram_b_busy <= RSTB OR ENB_dly OR ENB_dly_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstram_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_NO_REG;
RSTB_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
ram_rstreg_b_busy <= RSTB OR ENB_dly OR ENB_dly_reg_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstreg_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_WITH_REG;
END GENERATE nSPRAM_RST_BUSY;
-----------------------------------------------------------------------------
-- ENA/ENB Generation
-----------------------------------------------------------------------------
ENA_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly <= rsta_in AFTER FLOP_DELAY;
ENA_dly_D <= ENA_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_D OR ena_in;
END GENERATE ENA_NO_REG;
ENA_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly_reg <= rsta_in AFTER FLOP_DELAY;
ENA_dly_reg_D <= ENA_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_reg_D OR ena_in;
END GENERATE ENA_WITH_REG;
SPRAM_ENB: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
ENB_I_SAFE <= '0';
END GENERATE SPRAM_ENB;
nSPRAM_ENB: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
ENB_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly <= RSTB AFTER FLOP_DELAY;
ENB_dly_D <= ENB_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_D OR ENB;
END GENERATE ENB_NO_REG;
ENB_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly_reg <= RSTB AFTER FLOP_DELAY;
ENB_dly_reg_D <= ENB_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_reg_D OR ENB;
END GENERATE ENB_WITH_REG;
END GENERATE nSPRAM_ENB;
END GENERATE SAFETY_CKT_GEN;
--**************************************************************************
-- NATIVE MEMORY MODULE INSTANCE
--**************************************************************************
native_mem_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 0) GENERATE
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,--rsta_in,
ENA => ENA_I_SAFE,--ena_in,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in,
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => RDADDRECC
);
END GENERATE native_mem_module;
--**************************************************************************
-- NATIVE MEMORY MAPPED MODULE INSTANCE
--**************************************************************************
native_mem_map_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 1) GENERATE
--**************************************************************************
-- NATIVE MEMORY MAPPED PARAMETERS
CONSTANT C_ADDRA_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_A);
CONSTANT C_ADDRB_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_B);
CONSTANT C_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
CONSTANT C_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
CONSTANT C_MEM_MAP_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_MSB;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT MEM_MAP_LOWER_BOUND_VAL_A : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT MEM_MAP_LOWER_BOUND_VAL_B : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_B,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_B,8)));
CONSTANT C_MEM_MAP_ADDRA_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_A;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_B;
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH_ACTUAL-1 DOWNTO 0) := (OTHERS => '0');
--**************************************************************************
BEGIN
RDADDRECC(C_ADDRB_WIDTH-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_MSB) <= (OTHERS => '0');
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB) <= rdaddrecc_i;
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_LSB-1 DOWNTO 0) <= (OTHERS => '0');
mem_map_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH_ACTUAL,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH_ACTUAL,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,
ENA => ENA_I_SAFE,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in(C_MEM_MAP_ADDRA_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRA_WIDTH_LSB),
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB),
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => rdaddrecc_i
);
END GENERATE native_mem_map_module;
--****************************************************************************
-- AXI MEMORY MODULE INSTANCE
--****************************************************************************
axi_mem_module: IF (C_INTERFACE_TYPE = 1) GENERATE
SIGNAL s_axi_rid_c : STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rdata_c : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rresp_c : STD_LOGIC_VECTOR(2-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rlast_c : STD_LOGIC := '0';
SIGNAL s_axi_rvalid_c : STD_LOGIC := '0';
SIGNAL s_axi_rready_c : STD_LOGIC := '0';
SIGNAL regceb_c : STD_LOGIC := '0';
BEGIN
s_aresetn_a_c <= NOT S_ARESETN;
S_AXI_BRESP <= (OTHERS => '0');
s_axi_rresp_c <= (OTHERS => '0');
no_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 0 AND C_HAS_MUX_OUTPUT_REGS_B = 0 ) GENERATE
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RLAST <= s_axi_rlast_c;
S_AXI_RVALID <= s_axi_rvalid_c;
S_AXI_RID <= s_axi_rid_c;
S_AXI_RRESP <= s_axi_rresp_c;
s_axi_rready_c <= S_AXI_RREADY;
END GENERATE no_regs;
has_regs_fwd: IF (C_HAS_MUX_OUTPUT_REGS_B = 1 OR C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
CONSTANT C_AXI_PAYLOAD : INTEGER := if_then_else((C_HAS_MUX_OUTPUT_REGS_B = 1),C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3,C_AXI_ID_WIDTH+3);
SIGNAL s_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
has_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
regceb_c <= s_axi_rvalid_c AND s_axi_rready_c;
END GENERATE has_regceb;
no_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 0) GENERATE
regceb_c <= REGCEB;
END GENERATE no_regceb;
only_core_op_regs: IF (C_HAS_MUX_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rdata_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RDATA <= m_axi_payload_c(C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_core_op_regs;
only_emb_op_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_emb_op_regs;
axi_regs_inst : blk_mem_axi_regs_fwd_v8_3
GENERIC MAP(
C_DATA_WIDTH => C_AXI_PAYLOAD
)
PORT MAP (
ACLK => S_ACLK,
ARESET => s_aresetn_a_c,
S_VALID => s_axi_rvalid_c,
S_READY => s_axi_rready_c,
S_PAYLOAD_DATA => s_axi_payload_c,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY,
M_PAYLOAD_DATA => m_axi_payload_c
);
END GENERATE has_regs_fwd;
axi_wr_fsm : blk_mem_axi_write_wrapper_beh
GENERIC MAP(
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_AXI_AWADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_WDATA_WIDTH => C_WRITE_WIDTH_A,
C_AXI_OS_WR => C_AXI_OS_WR
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Slave Write Interface
S_AXI_AWADDR => S_AXI_AWADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_AWLEN => S_AXI_AWLEN,
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BID => S_AXI_BID,
-- Signals for BRAM interface
S_AXI_AWADDR_OUT =>s_axi_awaddr_out_c,
S_AXI_WR_EN =>s_axi_wr_en_c
);
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => 1, -- For AXI, Read Enable is always C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => 1, -- For AXI C_USE_BYTE_WEA is always 1,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => 1, -- For AXI, Read Enable is always C_HAS_ENB,
C_HAS_REGCEB => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_BYTE_WEB => 1, -- For AXI C_USE_BYTE_WEB is always 1,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => 0, --For AXI, Primitive Registers A is not supported C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => 0,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
--Port A:
CLKA => S_AClk,
RSTA => s_aresetn_a_c,
ENA => s_axi_wr_en_c,
REGCEA => regcea_in,
WEA => S_AXI_WSTRB,
ADDRA => s_axi_awaddr_out_c,
DINA => S_AXI_WDATA,
DOUTA => DOUTA,
--Port B:
CLKB => S_AClk,
RSTB => s_aresetn_a_c,
ENB => s_axi_rd_en_c,
REGCEB => regceb_c,
WEB => (OTHERS => '0'),
ADDRB => s_axi_araddr_out_c,
DINB => DINB,
DOUTB => s_axi_rdata_c,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => '0',
SLEEP => '0',
RDADDRECC => RDADDRECC
);
axi_rd_sm : blk_mem_axi_read_wrapper_beh
GENERIC MAP (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_PIPELINE_STAGES => 1,
C_AXI_ARADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_AClk,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Read Side
S_AXI_ARADDR => S_AXI_ARADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARSIZE => S_AXI_ARSIZE,
S_AXI_ARBURST => S_AXI_ARBURST,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => s_axi_rlast_c,
S_AXI_RVALID => s_axi_rvalid_c,
S_AXI_RREADY => s_axi_rready_c,
S_AXI_ARID => S_AXI_ARID,
S_AXI_RID => s_axi_rid_c,
-- AXI Full/Lite Read FSM Outputs
S_AXI_ARADDR_OUT => s_axi_araddr_out_c,
S_AXI_RD_EN => s_axi_rd_en_c
);
END GENERATE axi_mem_module;
END behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_clr is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_clr;
architecture beh_ff_clr_arch of beh_ff_clr is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(CLR, C)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_clr_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_ce is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_ce;
architecture beh_ff_ce_arch of beh_ff_ce is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, CLR)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
if (CE = '1') then
q_o <= D after 100 ps;
end if;
end if;
end process;
end beh_ff_ce_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_pre is
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end beh_ff_pre;
architecture beh_ff_pre_arch of beh_ff_pre is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, PRE)
begin
if (PRE = '1') then
q_o <= '1';
elsif (C' event and C = '1') then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_pre_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_muxf7 is
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end beh_muxf7;
architecture beh_muxf7_arch of beh_muxf7 is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
else
O <= I1;
end if;
end process;
end beh_muxf7_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity STATE_LOGIC is
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic := '0';
I0 : in std_logic := '0';
I1 : in std_logic := '0';
I2 : in std_logic := '0';
I3 : in std_logic := '0';
I4 : in std_logic := '0';
I5 : in std_logic := '0'
);
end STATE_LOGIC;
architecture STATE_LOGIC_arch of STATE_LOGIC is
constant INIT_reg : std_logic_vector(63 downto 0) := INIT;
begin
LUT_beh:process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
begin
I_reg := I5 & I4 & I3 & I2 & I1 & I0;
O <= INIT_reg(conv_integer(I_reg));
end process;
end STATE_LOGIC_arch;
|
-------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v8_3_1.vhd
--
-- Description:
-- This file is the VHDL behvarial model for the
-- Block Memory Generator Core.
--
-------------------------------------------------------------------------------
-- Author: Xilinx
--
-- History: January 11, 2006: Initial revision
-- June 11, 2007 : Added independent register stages for
-- Port A and Port B (IP1_Jm/v2.5)
-- August 28, 2007 : Added mux pipeline stages feature (IP2_Jm/v2.6)
-- April 07, 2009 : Added support for Spartan-6 and Virtex-6
-- features, including the following:
-- (i) error injection, detection and/or correction
-- (ii) reset priority
-- (iii) special reset behavior
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
ENTITY blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END ENTITY blk_mem_axi_regs_fwd_v8_3;
ARCHITECTURE axi_regs_fwd_arch OF blk_mem_axi_regs_fwd_v8_3 IS
SIGNAL STORAGE_DATA : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_READY_I : STD_LOGIC := '0';
SIGNAL M_VALID_I : STD_LOGIC := '0';
SIGNAL ARESET_D : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');-- Reset delay register
BEGIN
--assign local signal to its output signal
S_READY <= S_READY_I;
M_VALID <= M_VALID_I;
PROCESS(ACLK)
BEGIN
IF(ACLK'event AND ACLK = '1') THEN
ARESET_D <= ARESET_D(0) & ARESET;
END IF;
END PROCESS;
--Save payload data whenever we have a transaction on the slave side
PROCESS(ACLK, ARESET)
BEGIN
IF (ARESET = '1') THEN
STORAGE_DATA <= (OTHERS => '0');
ELSIF(ACLK'event AND ACLK = '1') THEN
IF(S_VALID = '1' AND S_READY_I = '1') THEN
STORAGE_DATA <= S_PAYLOAD_DATA;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= STORAGE_DATA;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
PROCESS(ACLK,ARESET)
BEGIN
IF (ARESET_D /= "00") THEN
M_VALID_I <= '0';
ELSIF(ACLK'event AND ACLK = '1') THEN
IF (S_VALID = '1') THEN
--Always set M_VALID_I when slave side is valid
M_VALID_I <= '1';
ELSIF (M_READY = '1') THEN
--Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= '0';
END IF;
END IF;
END PROCESS;
--Slave Ready is either when Master side drives M_READY or we have space in our storage data
S_READY_I <= (M_READY OR (NOT M_VALID_I)) AND NOT(OR_REDUCE(ARESET_D));
END axi_regs_fwd_arch;
-------------------------------------------------------------------------------
-- Description:
-- This is the behavioral model of write_wrapper for the
-- Block Memory Generator Core.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_axi_write_wrapper_beh IS
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END blk_mem_axi_write_wrapper_beh;
ARCHITECTURE axi_write_wrap_arch OF blk_mem_axi_write_wrapper_beh IS
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_AXI_WDATA_WIDTH=8,0,
if_then_else((C_AXI_WDATA_WIDTH=16),1,
if_then_else((C_AXI_WDATA_WIDTH=32),2,
if_then_else((C_AXI_WDATA_WIDTH=64),3,
if_then_else((C_AXI_WDATA_WIDTH=128),4,
if_then_else((C_AXI_WDATA_WIDTH=256),5,0))))));
SIGNAL bvalid_c : std_logic := '0';
SIGNAL bready_timeout_c : std_logic := '0';
SIGNAL bvalid_rd_cnt_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_r : std_logic := '0';
SIGNAL bvalid_count_r : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL awaddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
C_AXI_AWADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL bvalid_wr_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_rd_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_last_c : std_logic := '0';
SIGNAL addr_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL aw_ready_r : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL awlen_cntr_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1');
SIGNAL awlen_int : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL awburst_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes : integer := 0;
SIGNAL wrap_boundary : integer := 0;
SIGNAL wrap_base_addr : integer := 0;
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
-- Array to store BIDs
TYPE id_array IS ARRAY (3 DOWNTO 0) OF std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
SIGNAL axi_bid_array : id_array := (others => (others => '0'));
COMPONENT write_netlist
GENERIC(
C_AXI_TYPE : integer
);
PORT(
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
S_AXI_AWVALID : IN std_logic;
aw_ready_r : OUT std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN std_logic;
S_AXI_WR_EN : OUT std_logic;
w_last_c : IN std_logic;
bready_timeout_c : IN std_logic;
addr_en_c : OUT std_logic;
incr_addr_c : OUT std_logic;
bvalid_c : OUT std_logic
);
END COMPONENT write_netlist;
BEGIN
---------------------------------------
--AXI WRITE FSM COMPONENT INSTANTIATION
---------------------------------------
axi_wr_fsm : write_netlist
GENERIC MAP (
C_AXI_TYPE => C_AXI_TYPE
)
PORT MAP (
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
S_AXI_AWVALID => S_AXI_AWVALID,
aw_ready_r => aw_ready_r,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BVALID => OPEN,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_WR_EN => S_AXI_WR_EN,
w_last_c => w_last_c,
bready_timeout_c => bready_timeout_c,
addr_en_c => addr_en_c,
incr_addr_c => incr_addr_c,
bvalid_c => bvalid_c
);
--Wrap Address boundary calculation
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWSIZE,"000"));
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(awlen_int)+1);
wrap_base_addr <= (conv_integer(awaddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary <= wrap_base_addr+total_bytes;
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awaddr_reg <= (OTHERS => '0');
num_of_bytes_r <= 0;
awburst_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awaddr_reg <= S_AXI_AWADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWBURST,"01");
ELSIF (incr_addr_c = '1') THEN
IF (awburst_int = "10") THEN
IF(conv_integer(awaddr_reg) = (wrap_boundary-num_of_bytes_r)) THEN
awaddr_reg <= conv_std_logic_vector(wrap_base_addr,C_AXI_AWADDR_WIDTH);
ELSE
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
ELSIF (awburst_int = "01" OR awburst_int = "11") THEN
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
S_AXI_AWADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
awaddr_reg(C_AXI_AWADDR_WIDTH-1 DOWNTO C_RANGE),awaddr_reg);
---------------------------------------------------------------------------
-- AXI wlast generation
---------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awlen_cntr_r <= (OTHERS => '1');
awlen_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awlen_int <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
awlen_cntr_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
ELSIF (dec_alen_c = '1') THEN
awlen_cntr_r <= awlen_cntr_r - ONE AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
w_last_c <= '1' WHEN (awlen_cntr_r = "00000000" AND S_AXI_WVALID = '1') ELSE '0';
dec_alen_c <= (incr_addr_c OR w_last_c);
---------------------------------------------------------------------------
-- Generation of bvalid counter for outstanding transactions
---------------------------------------------------------------------------
P_b_valid_os_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_count_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- bvalid_count_r generation
IF (bvalid_c = '1' AND bvalid_r = '1' AND S_AXI_BREADY = '1') THEN
bvalid_count_r <= bvalid_count_r AFTER FLOP_DELAY;
ELSIF (bvalid_c = '1') THEN
bvalid_count_r <= bvalid_count_r + "01" AFTER FLOP_DELAY;
ELSIF (bvalid_r = '1' AND S_AXI_BREADY = '1' AND bvalid_count_r /= "0") THEN
bvalid_count_r <= bvalid_count_r - "01" AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_os_r ;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is used
---------------------------------------------------------------------------
gaxi_bvalid_id_r:IF (C_HAS_AXI_ID = 1) GENERATE
SIGNAL bvalid_d1_c : std_logic := '0';
BEGIN
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
bvalid_d1_c <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
--external bvalid signal generation
IF (bvalid_d1_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_id_r;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is not used
---------------------------------------------------------------------------
gaxi_bvalid_noid_r:IF (C_HAS_AXI_ID = 0) GENERATE
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
--external bvalid signal generation
IF (bvalid_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_noid_r;
---------------------------------------------------------------------------
-- Generation of Bready timeout
---------------------------------------------------------------------------
P_brdy_tout_c: PROCESS (bvalid_count_r)
BEGIN
-- bready_timeout_c generation
IF(conv_integer(bvalid_count_r) = C_AXI_OS_WR-1) THEN
bready_timeout_c <= '1';
ELSE
bready_timeout_c <= '0';
END IF;
END PROCESS P_brdy_tout_c;
---------------------------------------------------------------------------
-- Generation of BID
---------------------------------------------------------------------------
gaxi_bid_gen:IF (C_HAS_AXI_ID = 1) GENERATE
P_bid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
bvalid_wr_cnt_r <= (OTHERS => '0');
bvalid_rd_cnt_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- STORE AWID IN AN ARRAY
IF(bvalid_c = '1') THEN
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + "01";
END IF;
-- GENERATE BID FROM AWID ARRAY
bvalid_rd_cnt_r <= bvalid_rd_cnt_c AFTER FLOP_DELAY;
S_AXI_BID <= axi_bid_array(conv_integer(bvalid_rd_cnt_c));
END IF;
END PROCESS P_bid_gen;
bvalid_rd_cnt_c <= bvalid_rd_cnt_r + "01" WHEN (bvalid_r = '1' AND S_AXI_BREADY = '1') ELSE bvalid_rd_cnt_r;
---------------------------------------------------------------------------
-- Storing AWID for generation of BID
---------------------------------------------------------------------------
P_awid_reg:PROCESS (S_ACLK)
BEGIN
IF (S_ACLK'event AND S_ACLK='1') THEN
IF(aw_ready_r = '1' AND S_AXI_AWVALID = '1') THEN
axi_bid_array(conv_integer(bvalid_wr_cnt_r)) <= S_AXI_AWID;
END IF;
END IF;
END PROCESS P_awid_reg;
END GENERATE gaxi_bid_gen;
S_AXI_BVALID <= bvalid_r;
S_AXI_AWREADY <= aw_ready_r;
END axi_write_wrap_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity write_netlist is
GENERIC(
C_AXI_TYPE : integer
);
port (
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_AWVALID : in STD_LOGIC := '0';
S_AXI_WVALID : in STD_LOGIC := '0';
S_AXI_BREADY : in STD_LOGIC := '0';
w_last_c : in STD_LOGIC := '0';
bready_timeout_c : in STD_LOGIC := '0';
aw_ready_r : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_WR_EN : out STD_LOGIC;
addr_en_c : out STD_LOGIC;
incr_addr_c : out STD_LOGIC;
bvalid_c : out STD_LOGIC
);
end write_netlist;
architecture STRUCTURE of write_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
BEGIN
---------------------------------------------------------------------------
-- AXI LITE
---------------------------------------------------------------------------
gbeh_axi_lite_sm: IF (C_AXI_TYPE = 0 ) GENERATE
signal w_ready_r_7 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSignal_bvalid_c : STD_LOGIC;
signal NlwRenamedSignal_incr_addr_c : STD_LOGIC;
signal present_state_FSM_FFd3_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal present_state_FSM_FFd1_15 : STD_LOGIC;
signal present_state_FSM_FFd4_16 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd4_In1_21 : STD_LOGIC;
signal Mmux_aw_ready_c : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
S_AXI_WREADY <= w_ready_r_7;
S_AXI_BVALID <= NlwRenamedSignal_incr_addr_c;
S_AXI_WR_EN <= NlwRenamedSignal_bvalid_c;
incr_addr_c <= NlwRenamedSignal_incr_addr_c;
bvalid_c <= NlwRenamedSignal_bvalid_c;
NlwRenamedSignal_incr_addr_c <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_7
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_16
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_13
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_15
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000055554440"
)
port map (
I0 => S_AXI_WVALID,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => '0',
O => present_state_FSM_FFd3_In
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"0000000088880800"
)
port map (
I0 => S_AXI_AWVALID,
I1 => S_AXI_WVALID,
I2 => bready_timeout_c,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => present_state_FSM_FFd2_In
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAA2000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_WVALID,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => addr_en_c
);
Mmux_w_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"F5F07570F5F05500"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => w_ready_c
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd3_13,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd1_15,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_14,
I2 => present_state_FSM_FFd3_13,
I3 => '0',
I4 => '0',
I5 => '0',
O => NlwRenamedSignal_bvalid_c
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"2F0F27072F0F2200"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => present_state_FSM_FFd4_In1_21
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_In1_21,
I3 => '0',
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_aw_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"7535753575305500"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => S_AXI_WVALID,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => present_state_FSM_FFd2_14,
O => Mmux_aw_ready_c(0)
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => Mmux_aw_ready_c(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => aw_ready_c
);
END GENERATE gbeh_axi_lite_sm;
---------------------------------------------------------------------------
-- AXI FULL
---------------------------------------------------------------------------
gbeh_axi_full_sm: IF (C_AXI_TYPE = 1 ) GENERATE
signal w_ready_r_8 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSig_OI_bvalid_c : STD_LOGIC;
signal present_state_FSM_FFd1_16 : STD_LOGIC;
signal present_state_FSM_FFd4_17 : STD_LOGIC;
signal present_state_FSM_FFd3_18 : STD_LOGIC;
signal present_state_FSM_FFd2_19 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd2_In1_24 : STD_LOGIC;
signal present_state_FSM_FFd4_In1_25 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal N4 : STD_LOGIC;
begin
S_AXI_WREADY <= w_ready_r_8;
bvalid_c <= NlwRenamedSig_OI_bvalid_c;
S_AXI_BVALID <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_8
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_17
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_18
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_19
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_16
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000000005540"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd4_17,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd3_In
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"BF3FBB33AF0FAA00"
)
port map (
I0 => S_AXI_BREADY,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd1_16,
I4 => present_state_FSM_FFd4_17,
I5 => NlwRenamedSig_OI_bvalid_c,
O => aw_ready_c
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"AAAAAAAA20000000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_19,
I3 => S_AXI_WVALID,
I4 => w_last_c,
I5 => present_state_FSM_FFd4_17,
O => addr_en_c
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_19,
I2 => present_state_FSM_FFd3_18,
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_WR_EN
);
Mmux_incr_addr_c_0_1 : STATE_LOGIC
generic map(
INIT => X"0000000000002220"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => incr_addr_c
);
Mmux_aw_ready_c_0_11 : STATE_LOGIC
generic map(
INIT => X"0000000000008880"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => NlwRenamedSig_OI_bvalid_c
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"000000000000D5C0"
)
port map (
I0 => w_last_c,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd4_17,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd2_In1_24
);
present_state_FSM_FFd2_In2 : STATE_LOGIC
generic map(
INIT => X"FFFFAAAA08AAAAAA"
)
port map (
I0 => present_state_FSM_FFd2_19,
I1 => S_AXI_AWVALID,
I2 => bready_timeout_c,
I3 => w_last_c,
I4 => S_AXI_WVALID,
I5 => present_state_FSM_FFd2_In1_24,
O => present_state_FSM_FFd2_In
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"00C0004000C00000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => w_last_c,
I2 => S_AXI_WVALID,
I3 => bready_timeout_c,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => present_state_FSM_FFd4_In1_25
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88F8"
)
port map (
I0 => present_state_FSM_FFd1_16,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_17,
I3 => S_AXI_AWVALID,
I4 => present_state_FSM_FFd4_In1_25,
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_w_ready_c_0_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => w_last_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_w_ready_c_0_Q : STATE_LOGIC
generic map(
INIT => X"FABAFABAFAAAF000"
)
port map (
I0 => N2,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd4_17,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => w_ready_c
);
Mmux_aw_ready_c_0_11_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => bready_timeout_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => w_last_c,
I1 => N4,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => present_state_FSM_FFd1_16,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
END GENERATE gbeh_axi_full_sm;
end STRUCTURE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--AXI Behavioral Model entities
ENTITY blk_mem_axi_read_wrapper_beh is
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
port (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END blk_mem_axi_read_wrapper_beh;
architecture blk_mem_axi_read_wrapper_beh_arch of blk_mem_axi_read_wrapper_beh is
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_WRITE_WIDTH_A=8,0,
if_then_else((C_WRITE_WIDTH_A=16),1,
if_then_else((C_WRITE_WIDTH_A=32),2,
if_then_else((C_WRITE_WIDTH_A=64),3,
if_then_else((C_WRITE_WIDTH_A=128),4,
if_then_else((C_WRITE_WIDTH_A=256),5,0))))));
SIGNAL ar_id_r : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
SIGNAL addr_en_c : std_logic := '0';
SIGNAL rd_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL single_trans_c : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL mux_sel_c : std_logic := '0';
SIGNAL r_last_c : std_logic := '0';
SIGNAL r_last_int_c : std_logic := '0';
SIGNAL arlen_int_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL arlen_cntr : std_logic_vector(7 DOWNTO 0) := ONE;
SIGNAL arburst_int_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL arburst_int_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL araddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),C_AXI_ARADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL total_bytes : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
SIGNAL wrap_base_addr_r : integer := 0;
SIGNAL wrap_boundary_r : integer := 0;
SIGNAL arlen_int_c : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes_c : integer := 0;
SIGNAL wrap_base_addr_c : integer := 0;
SIGNAL wrap_boundary_c : integer := 0;
SIGNAL araddr_out : std_logic_vector(C_ADDRB_WIDTH-1 downto 0) := (OTHERS => '0');
COMPONENT read_netlist
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_INCR_ADDR : OUT std_logic := '0';
S_AXI_ADDR_EN : OUT std_logic := '0';
S_AXI_SINGLE_TRANS : OUT std_logic := '0';
S_AXI_MUX_SEL : OUT std_logic := '0';
S_AXI_R_LAST : OUT std_logic := '0';
S_AXI_R_LAST_INT : IN std_logic := '0';
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT read_netlist;
BEGIN
dec_alen_c <= incr_addr_c OR r_last_int_c;
axi_read_fsm : read_netlist
GENERIC MAP(
C_AXI_TYPE => 1,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
S_AXI_INCR_ADDR => incr_addr_c,
S_AXI_ADDR_EN => addr_en_c,
S_AXI_SINGLE_TRANS => single_trans_c,
S_AXI_MUX_SEL => mux_sel_c,
S_AXI_R_LAST => r_last_c,
S_AXI_R_LAST_INT => r_last_int_c,
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN => rd_en_c
);
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(arlen_int_r)+1);
wrap_base_addr_r <= (conv_integer(araddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary_r <= wrap_base_addr_r+total_bytes;
---- combinatorial from interface
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARSIZE,"000"));
arlen_int_c <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
total_bytes_c <= conv_integer(num_of_bytes_c)*(conv_integer(arlen_int_c)+1);
wrap_base_addr_c <= (conv_integer(S_AXI_ARADDR)/if_then_else(total_bytes_c=0,1,total_bytes_c))*(total_bytes_c);
wrap_boundary_c <= wrap_base_addr_c+total_bytes_c;
arburst_int_c <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARBURST,"01");
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
araddr_reg <= (OTHERS => '0');
arburst_int_r <= (OTHERS => '0');
num_of_bytes_r <= 0;
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (incr_addr_c = '1' AND addr_en_c = '1' AND single_trans_c = '0') THEN
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
IF (arburst_int_c = "10") THEN
IF(conv_integer(S_AXI_ARADDR) = (wrap_boundary_c-num_of_bytes_c)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_c,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (arburst_int_c = "01" OR arburst_int_c = "11") THEN
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (addr_en_c = '1') THEN
araddr_reg <= S_AXI_ARADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
ELSIF (incr_addr_c = '1') THEN
IF (arburst_int_r = "10") THEN
IF(conv_integer(araddr_reg) = (wrap_boundary_r-num_of_bytes_r)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_r,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
ELSIF (arburst_int_r = "01" OR arburst_int_r = "11") THEN
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
araddr_out <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),araddr_reg(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),araddr_reg);
--------------------------------------------------------------------------
-- Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
--------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF S_ARESETN = '1' THEN
arlen_cntr <= ONE;
arlen_int_r <= (OTHERS => '0');
ELSIF S_ACLK'event AND S_ACLK = '1' THEN
IF (addr_en_c = '1' AND dec_alen_c = '1' AND single_trans_c = '0') THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= S_AXI_ARLEN - ONE AFTER FLOP_DELAY;
ELSIF addr_en_c = '1' THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
ELSIF dec_alen_c = '1' THEN
arlen_cntr <= arlen_cntr - ONE AFTER FLOP_DELAY;
ELSE
arlen_cntr <= arlen_cntr AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
r_last_int_c <= '1' WHEN (arlen_cntr = "00000000" AND S_AXI_RREADY = '1') ELSE '0' ;
--------------------------------------------------------------------------
-- AXI FULL FSM
-- Mux Selection of ARADDR
-- ARADDR is driven out from the read fsm based on the mux_sel_c
-- Based on mux_sel either ARADDR is given out or the latched ARADDR is
-- given out to BRAM
--------------------------------------------------------------------------
P_araddr_mux: PROCESS (mux_sel_c,S_AXI_ARADDR,araddr_out)
BEGIN
IF (mux_sel_c = '0') THEN
S_AXI_ARADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARADDR(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),S_AXI_ARADDR);
ELSE
S_AXI_ARADDR_OUT <= araddr_out;
END IF;
END PROCESS P_araddr_mux;
--------------------------------------------------------------------------
-- Assign output signals - AXI FULL FSM
--------------------------------------------------------------------------
S_AXI_RD_EN <= rd_en_c;
grid: IF (C_HAS_AXI_ID = 1) GENERATE
P_rid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
S_AXI_RID <= (OTHERS => '0');
ar_id_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
IF (addr_en_c = '1' AND rd_en_c = '1') THEN
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
ELSIF (addr_en_c = '1' AND rd_en_c = '0') THEN
ar_id_r <= S_AXI_ARID;
ELSIF (rd_en_c = '1') THEN
S_AXI_RID <= ar_id_r;
END IF;
END IF;
END PROCESS P_rid_gen;
END GENERATE grid;
END blk_mem_axi_read_wrapper_beh_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity read_netlist is
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_R_LAST_INT : in STD_LOGIC := '0';
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_ARVALID : in STD_LOGIC := '0';
S_AXI_RREADY : in STD_LOGIC := '0';
S_AXI_INCR_ADDR : out STD_LOGIC;
S_AXI_ADDR_EN : out STD_LOGIC;
S_AXI_SINGLE_TRANS : out STD_LOGIC;
S_AXI_MUX_SEL : out STD_LOGIC;
S_AXI_R_LAST : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RLAST : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RD_EN : out STD_LOGIC;
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end read_netlist;
architecture STRUCTURE of read_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
signal present_state_FSM_FFd1_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_r_15 : STD_LOGIC;
signal gaxi_full_sm_ar_ready_r_16 : STD_LOGIC;
signal gaxi_full_sm_r_last_r_17 : STD_LOGIC;
signal NlwRenamedSig_OI_gaxi_full_sm_r_valid_r : STD_LOGIC;
signal gaxi_full_sm_r_valid_c : STD_LOGIC;
signal S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o : STD_LOGIC;
signal gaxi_full_sm_ar_ready_c : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_c : STD_LOGIC;
signal NlwRenamedSig_OI_S_AXI_R_LAST : STD_LOGIC;
signal S_AXI_ARLEN_7_GND_8_o_equal_1_o : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal Mmux_S_AXI_R_LAST13 : STD_LOGIC;
signal N01 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal Mmux_gaxi_full_sm_ar_ready_c11 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N8 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N13 : STD_LOGIC;
begin
S_AXI_R_LAST <= NlwRenamedSig_OI_S_AXI_R_LAST;
S_AXI_ARREADY <= gaxi_full_sm_ar_ready_r_16;
S_AXI_RLAST <= gaxi_full_sm_r_last_r_17;
S_AXI_RVALID <= NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
gaxi_full_sm_outstanding_read_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_outstanding_read_c,
Q => gaxi_full_sm_outstanding_read_r_15
);
gaxi_full_sm_r_valid_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => gaxi_full_sm_r_valid_c,
Q => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r
);
gaxi_full_sm_ar_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_ar_ready_c,
Q => gaxi_full_sm_ar_ready_r_16
);
gaxi_full_sm_r_last_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => NlwRenamedSig_OI_S_AXI_R_LAST,
Q => gaxi_full_sm_r_last_r_17
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_13
);
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 : STATE_LOGIC
generic map(
INIT => X"000000000000000B"
)
port map (
I0 => S_AXI_RREADY,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o
);
Mmux_S_AXI_SINGLE_TRANS11 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_SINGLE_TRANS
);
Mmux_S_AXI_ADDR_EN11 : STATE_LOGIC
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_ADDR_EN
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"ECEE2022EEEE2022"
)
port map (
I0 => S_AXI_ARVALID,
I1 => present_state_FSM_FFd1_13,
I2 => S_AXI_RREADY,
I3 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I4 => present_state_FSM_FFd2_14,
I5 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
O => present_state_FSM_FFd2_In
);
Mmux_S_AXI_R_LAST131 : STATE_LOGIC
generic map(
INIT => X"0000000044440444"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_RREADY,
I5 => '0',
O => Mmux_S_AXI_R_LAST13
);
Mmux_S_AXI_INCR_ADDR11 : STATE_LOGIC
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => S_AXI_R_LAST_INT,
I1 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => Mmux_S_AXI_R_LAST13,
O => S_AXI_INCR_ADDR
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000FE"
)
port map (
I0 => S_AXI_ARLEN(2),
I1 => S_AXI_ARLEN(1),
I2 => S_AXI_ARLEN(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => N01
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q : STATE_LOGIC
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => S_AXI_ARLEN(7),
I1 => S_AXI_ARLEN(6),
I2 => S_AXI_ARLEN(5),
I3 => S_AXI_ARLEN(4),
I4 => S_AXI_ARLEN(3),
I5 => N01,
O => S_AXI_ARLEN_7_GND_8_o_equal_1_o
);
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_gaxi_full_sm_outstanding_read_c1 : STATE_LOGIC
generic map(
INIT => X"0020000002200200"
)
port map (
I0 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd1_13,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => N2,
O => gaxi_full_sm_outstanding_read_c
);
Mmux_gaxi_full_sm_ar_ready_c12 : STATE_LOGIC
generic map(
INIT => X"0000000000004555"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => '0',
I5 => '0',
O => Mmux_gaxi_full_sm_ar_ready_c11
);
Mmux_S_AXI_R_LAST11_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000EF"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
Mmux_S_AXI_R_LAST11 : STATE_LOGIC
generic map(
INIT => X"FCAAFC0A00AA000A"
)
port map (
I0 => S_AXI_ARVALID,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => N4,
I5 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
O => gaxi_full_sm_r_valid_c
);
S_AXI_MUX_SEL1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAAAA08"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => '0',
O => S_AXI_MUX_SEL
);
Mmux_S_AXI_RD_EN11 : STATE_LOGIC
generic map(
INIT => X"F3F3F755A2A2A200"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => gaxi_full_sm_outstanding_read_r_15,
I4 => present_state_FSM_FFd2_14,
I5 => S_AXI_ARVALID,
O => S_AXI_RD_EN
);
present_state_FSM_FFd1_In3 : beh_muxf7
port map (
I0 => N8,
I1 => N9,
S => present_state_FSM_FFd1_13,
O => present_state_FSM_FFd1_In
);
present_state_FSM_FFd1_In3_F : STATE_LOGIC
generic map(
INIT => X"000000005410F4F0"
)
port map (
I0 => S_AXI_RREADY,
I1 => present_state_FSM_FFd2_14,
I2 => S_AXI_ARVALID,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => '0',
O => N8
);
present_state_FSM_FFd1_In3_G : STATE_LOGIC
generic map(
INIT => X"0000000072FF7272"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N9
);
Mmux_gaxi_full_sm_ar_ready_c14 : beh_muxf7
port map (
I0 => N10,
I1 => N11,
S => present_state_FSM_FFd1_13,
O => gaxi_full_sm_ar_ready_c
);
Mmux_gaxi_full_sm_ar_ready_c14_F : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88A8"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => Mmux_gaxi_full_sm_ar_ready_c11,
I5 => '0',
O => N10
);
Mmux_gaxi_full_sm_ar_ready_c14_G : STATE_LOGIC
generic map(
INIT => X"000000008D008D8D"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N11
);
Mmux_S_AXI_R_LAST1 : beh_muxf7
port map (
I0 => N12,
I1 => N13,
S => present_state_FSM_FFd1_13,
O => NlwRenamedSig_OI_S_AXI_R_LAST
);
Mmux_S_AXI_R_LAST1_F : STATE_LOGIC
generic map(
INIT => X"0000000088088888"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N12
);
Mmux_S_AXI_R_LAST1_G : STATE_LOGIC
generic map(
INIT => X"00000000E400E4E4"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => S_AXI_R_LAST_INT,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N13
);
end STRUCTURE;
-------------------------------------------------------------------------------
-- Output Register Stage Entity
--
-- This module builds the output register stages of the memory. This module is
-- instantiated in the main memory module (blk_mem_gen_v8_3_1) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_output_stage IS
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_output_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6" and "virtex6l".
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
-- C_HAS_RST : Determines the presence of the RST port
-- C_RSTRAM : Determines if special reset behavior is used
-- C_RST_PRIORITY : Determines the priority between CE and SR
-- C_INIT_VAL : Initialization value
-- C_HAS_EN : Determines the presence of the EN port
-- C_HAS_REGCE : Determines the presence of the REGCE port
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
-- of the RAM primitive
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- NUM_STAGES : Determines the number of output stages
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE output_stage_behavioral OF blk_mem_gen_v8_3_1_output_stage IS
--*******************************************************
-- Functions used in the output stage ARCHITECTURE
--*******************************************************
-- Calculate num_reg_stages
FUNCTION get_num_reg_stages(NUM_STAGES: INTEGER) RETURN INTEGER IS
VARIABLE num_reg_stages : INTEGER := 0;
BEGIN
IF (NUM_STAGES = 0) THEN
num_reg_stages := 0;
ELSE
num_reg_stages := NUM_STAGES - 1;
END IF;
RETURN num_reg_stages;
END get_num_reg_stages;
-- Check if the INTEGER is zero or non-zero
FUNCTION int_to_bit(input: INTEGER) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = 0) THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END int_to_bit;
-- Constants
CONSTANT HAS_EN : STD_LOGIC := int_to_bit(C_HAS_EN);
CONSTANT HAS_REGCE : STD_LOGIC := int_to_bit(C_HAS_REGCE);
CONSTANT HAS_RST : STD_LOGIC := int_to_bit(C_HAS_RST);
CONSTANT REG_STAGES : INTEGER := get_num_reg_stages(NUM_STAGES);
-- Pipeline array
TYPE reg_data_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
TYPE reg_ecc_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC;
TYPE reg_eccaddr_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
CONSTANT REG_INIT : reg_data_array := (OTHERS => init_val);
SIGNAL out_regs : reg_data_array := REG_INIT;
SIGNAL sbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL dbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL rdaddrecc_regs: reg_eccaddr_array := (OTHERS => (OTHERS => '0'));
-- Internal signals
SIGNAL en_i : STD_LOGIC;
SIGNAL regce_i : STD_LOGIC;
SIGNAL rst_i : STD_LOGIC;
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := init_val;
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL DIN : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL RDADDRECC_IN : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ;
SIGNAL SBITERR_IN : STD_LOGIC := '0';
SIGNAL DBITERR_IN : STD_LOGIC := '0';
BEGIN
--***********************************************************************
-- Assign internal signals. This effectively wires off optional inputs.
--***********************************************************************
-- Internal enable for output registers is tied to user EN or '1' depending
-- on parameters
en_i <= EN OR (NOT HAS_EN);
-- Internal register enable for output registers is tied to user REGCE, EN
-- or '1' depending on parameters
regce_i <= (HAS_REGCE AND REGCE)
OR ((NOT HAS_REGCE) AND en_i);
-- Internal SRR is tied to user RST or '0' depending on parameters
rst_i <= RST AND HAS_RST;
--***************************************************************************
-- NUM_STAGES = 0 (No output registers. RAM only)
--***************************************************************************
zero_stages: IF (NUM_STAGES = 0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE zero_stages;
NO_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 0) GENERATE
DIN <= DIN_I;
RDADDRECC_IN <= RDADDRECC_IN_I;
SBITERR_IN <= SBITERR_IN_I;
DBITERR_IN <= DBITERR_IN_I;
END GENERATE NO_ECC_PIPE_REG;
WITH_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(ECCPIPECE = '1') THEN
DIN <= DIN_I AFTER FLOP_DELAY;
RDADDRECC_IN <= RDADDRECC_IN_I AFTER FLOP_DELAY;
SBITERR_IN <= SBITERR_IN_I AFTER FLOP_DELAY;
DBITERR_IN <= DBITERR_IN_I AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS;
END GENERATE WITH_ECC_PIPE_REG;
--***************************************************************************
-- NUM_STAGES = 1
-- (Mem Output Reg only or Mux Output Reg only)
--***************************************************************************
-- Possible valid combinations:
-- Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
-- +-----------------------------------------+
-- | C_RSTRAM_* | Reset Behavior |
-- +----------------+------------------------+
-- | 0 | Normal Behavior |
-- +----------------+------------------------+
-- | 1 | Special Behavior |
-- +----------------+------------------------+
--
-- Normal = REGCE gates reset, as in the case of all Virtex families and all
-- spartan families with the exception of S3ADSP and S6.
-- Special = EN gates reset, as in the case of S3ADSP and S6.
one_stage_norm: IF (NUM_STAGES = 1 AND
(C_RSTRAM=0 OR (C_RSTRAM=1 AND (C_XDEVICEFAMILY/="spartan3adsp" AND C_XDEVICEFAMILY/="aspartan3adsp")) OR
C_HAS_MEM_OUTPUT_REGS=0 OR C_HAS_RST=0)) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i = '1' AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
END IF;--CLK
END PROCESS;
END GENERATE one_stage_norm;
-- Special Reset Behavior for S6 and S3ADSP
one_stage_splbhv: IF (NUM_STAGES=1 AND C_RSTRAM=1 AND (C_XDEVICEFAMILY ="spartan3adsp" OR C_XDEVICEFAMILY ="aspartan3adsp"))
GENERATE
DOUT <= dout_i;
SBITERR <= '0';
DBITERR <= '0';
RDADDRECC <= (OTHERS => '0');
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (rst_i='1' AND en_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
ELSIF (regce_i='1' AND rst_i/='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE one_stage_splbhv;
--****************************************************************************
-- NUM_STAGES > 1
-- Mem Output Reg + Mux Output Reg
-- or
-- Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
-- or
-- Mux Pipeline Stages (>0) + Mux Output Reg
--****************************************************************************
multi_stage: IF (NUM_STAGES > 1) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i='1'AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
IF (en_i='1') THEN
-- Shift the data through the output stages
FOR i IN 1 TO REG_STAGES-1 LOOP
out_regs(i) <= out_regs(i-1) AFTER FLOP_DELAY;
sbiterr_regs(i) <= sbiterr_regs(i-1) AFTER FLOP_DELAY;
dbiterr_regs(i) <= dbiterr_regs(i-1) AFTER FLOP_DELAY;
rdaddrecc_regs(i) <= rdaddrecc_regs(i-1) AFTER FLOP_DELAY;
END LOOP;
out_regs(0) <= DIN;
sbiterr_regs(0) <= SBITERR_IN;
dbiterr_regs(0) <= DBITERR_IN;
rdaddrecc_regs(0) <= RDADDRECC_IN;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE multi_stage;
END output_stage_behavioral;
-------------------------------------------------------------------------------
-- SoftECC Output Register Stage Entity
-- This module builds the softecc output register stages. This module is
-- instantiated in the memory module (blk_mem_gen_v8_3_1_mem_module) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ;
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- of the RAM primitive
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE softecc_output_reg_stage_behavioral OF blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
-- Internal signals
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
--***************************************************************************
-- NO OUTPUT STAGES
--***************************************************************************
no_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE no_output_stage;
--****************************************************************************
-- WITH OUTPUT STAGE
--****************************************************************************
has_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END PROCESS;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
END GENERATE has_output_stage;
END softecc_output_reg_stage_behavioral;
--******************************************************************************
-- Main Memory module
--
-- This module is the behavioral model which implements the RAM
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
ENTITY blk_mem_gen_v8_3_1_mem_module IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_mem_module;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE mem_module_behavioral OF blk_mem_gen_v8_3_1_mem_module IS
--****************************************
-- min/max constant functions
--****************************************
-- get_max
----------
function SLV_TO_INT(SLV: in std_logic_vector
) return integer is
variable int : integer;
begin
int := 0;
for i in SLV'high downto SLV'low loop
int := int * 2;
if SLV(i) = '1' then
int := int + 1;
end if;
end loop;
return int;
end;
FUNCTION get_max(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a > b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-- get_min
----------
FUNCTION get_min(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
--***************************************************************
-- convert write_mode from STRING type for use in case statement
--***************************************************************
FUNCTION write_mode_to_vector(mode: STRING) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF (mode = "NO_CHANGE") THEN
RETURN "10";
ELSIF (mode = "READ_FIRST") THEN
RETURN "01";
ELSE
RETURN "00"; -- WRITE_FIRST
END IF;
END FUNCTION;
--***************************************************************
-- convert hex STRING to STD_LOGIC_VECTOR
--***************************************************************
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
--***************************************************************
-- locally derived constants to determine memory shape
--***************************************************************
CONSTANT MIN_WIDTH_A : INTEGER := get_min(C_WRITE_WIDTH_A, C_READ_WIDTH_A);
CONSTANT MIN_WIDTH_B : INTEGER := get_min(C_WRITE_WIDTH_B,C_READ_WIDTH_B);
CONSTANT MIN_WIDTH : INTEGER := get_min(MIN_WIDTH_A, MIN_WIDTH_B);
CONSTANT MAX_DEPTH_A : INTEGER := get_max(C_WRITE_DEPTH_A, C_READ_DEPTH_A);
CONSTANT MAX_DEPTH_B : INTEGER := get_max(C_WRITE_DEPTH_B, C_READ_DEPTH_B);
CONSTANT MAX_DEPTH : INTEGER := get_max(MAX_DEPTH_A, MAX_DEPTH_B);
TYPE int_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF std_logic_vector(C_WRITE_WIDTH_A-1 DOWNTO 0);
TYPE mem_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC_VECTOR(MIN_WIDTH-1 DOWNTO 0);
TYPE ecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
TYPE softecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
--***************************************************************
-- memory initialization function
--***************************************************************
IMPURE FUNCTION init_memory(DEFAULT_DATA :
STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
write_width_a : INTEGER;
depth : INTEGER;
width : INTEGER)
RETURN mem_array IS
VARIABLE init_return : mem_array := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(write_width_a-1 DOWNTO 0);
VARIABLE int_mem_vector : int_array:= (OTHERS => (OTHERS => '0'));
VARIABLE file_buffer : LINE;
VARIABLE i : INTEGER := 0;
VARIABLE j : INTEGER;
VARIABLE k : INTEGER;
VARIABLE ignore_line : BOOLEAN := false;
VARIABLE good_data : BOOLEAN := false;
VARIABLE char_tmp : CHARACTER;
VARIABLE index : INTEGER;
variable init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable data : std_logic_vector(255 downto 0) := (others => '0');
variable inside_init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable k_slv : std_logic_vector(31 downto 0) := (others => '0');
variable i_slv : std_logic_vector(31 downto 0) := (others => '0');
VARIABLE disp_line : line := null;
variable open_status : file_open_status;
variable input_initf_tmp : mem_array ;
variable input_initf : mem_array := (others => (others => '0'));
file int_infile : text;
variable data_line, data_line_tmp, out_data_line : line;
variable slv_width : integer;
VARIABLE d_l : LINE;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
index := 0;
FOR i IN 0 TO depth-1 LOOP
FOR j IN 0 TO width-1 LOOP
init_return(i)(j) := DEFAULT_DATA(index);
index := (index + 1) MOD C_WRITE_WIDTH_A;
END LOOP;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, file_buffer);
read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO write_width_a-1 LOOP
IF (j MOD width = 0 AND j /= 0) THEN
i := i + 1;
END IF;
init_return(i)(j MOD width) := bit_to_sl(mem_vector(j));
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
--Display output message indicating that the behavioral model is done
--initializing
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator data initialization complete." SEVERITY NOTE;
if (C_USE_BRAM_BLOCK = 1) then
--Display output message indicating that the behavioral model is being
--initialized
-- Read in the .mem file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_INIT_FILE /= "NONE") then
file_open(open_status, int_infile, C_INIT_FILE, read_mode);
while not endfile(int_infile) loop
readline(int_infile, data_line);
while (data_line /= null and data_line'length > 0) loop
if (data_line(data_line'low to data_line'low + 1) = "//") then
deallocate(data_line);
elsif ((data_line(data_line'low to data_line'low + 1) = "/*") and (data_line(data_line'high-1 to data_line'high) = "*/")) then
deallocate(data_line);
elsif (data_line(data_line'low to data_line'low + 1) = "/*") then
deallocate(data_line);
ignore_line := true;
elsif (ignore_line = true and data_line(data_line'high-1 to data_line'high) = "*/") then
deallocate(data_line);
ignore_line := false;
elsif (ignore_line = false and data_line(data_line'low) = '@') then
read(data_line, char_tmp);
hread(data_line, init_addr_slv, good_data);
i := SLV_TO_INT(init_addr_slv);
elsif (ignore_line = false) then
hread(data_line, input_initf_tmp(i), good_data);
init_return(i)(write_width_a - 1 downto 0) := input_initf_tmp(i)(write_width_a - 1 downto 0);
if (good_data = true) then
i := i + 1;
end if;
else
deallocate(data_line);
end if;
end loop;
end loop;
file_close(int_infile);
END IF;
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- memory type constants
--***************************************************************
CONSTANT MEM_TYPE_SP_RAM : INTEGER := 0;
CONSTANT MEM_TYPE_SDP_RAM : INTEGER := 1;
CONSTANT MEM_TYPE_TDP_RAM : INTEGER := 2;
CONSTANT MEM_TYPE_SP_ROM : INTEGER := 3;
CONSTANT MEM_TYPE_DP_ROM : INTEGER := 4;
--***************************************************************
-- memory configuration constant functions
--***************************************************************
--get_single_port
-----------------
FUNCTION get_single_port(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_RAM OR mem_type=MEM_TYPE_SP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_single_port;
--get_is_rom
--------------
FUNCTION get_is_rom(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_ROM OR mem_type=MEM_TYPE_DP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_is_rom;
--get_has_a_write
------------------
FUNCTION get_has_a_write(IS_ROM : INTEGER) RETURN INTEGER IS
BEGIN
IF (IS_ROM=0) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_a_write;
--get_has_b_write
------------------
FUNCTION get_has_b_write(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_TDP_RAM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_write;
--get_has_a_read
------------------
FUNCTION get_has_a_read(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SDP_RAM) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_a_read;
--get_has_b_read
------------------
FUNCTION get_has_b_read(SINGLE_PORT : INTEGER) RETURN INTEGER IS
BEGIN
IF (SINGLE_PORT=1) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_b_read;
--get_has_b_port
------------------
FUNCTION get_has_b_port(HAS_B_READ : INTEGER;
HAS_B_WRITE : INTEGER)
RETURN INTEGER IS
BEGIN
IF (HAS_B_READ=1 OR HAS_B_WRITE=1) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_port;
--get_num_output_stages
-----------------------
FUNCTION get_num_output_stages(has_mem_output_regs : INTEGER;
has_mux_output_regs : INTEGER;
mux_pipeline_stages : INTEGER)
RETURN INTEGER IS
VARIABLE actual_mux_pipeline_stages : INTEGER;
BEGIN
-- Mux pipeline stages can be non-zero only when there is a mux
-- output register.
IF (has_mux_output_regs=1) THEN
actual_mux_pipeline_stages := mux_pipeline_stages;
ELSE
actual_mux_pipeline_stages := 0;
END IF;
RETURN has_mem_output_regs+actual_mux_pipeline_stages+has_mux_output_regs;
END get_num_output_stages;
--***************************************************************************
-- Component declaration of the VARIABLE depth output register stage
--***************************************************************************
COMPONENT blk_mem_gen_v8_3_1_output_stage
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
EN : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
ECCPIPECE : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_output_stage;
COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************************************
-- locally derived constants to assist memory access
--******************************************************
CONSTANT WRITE_WIDTH_RATIO_A : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_A : INTEGER := C_READ_WIDTH_A/MIN_WIDTH;
CONSTANT WRITE_WIDTH_RATIO_B : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_B : INTEGER := C_READ_WIDTH_B/MIN_WIDTH;
--******************************************************
-- To modify the LSBs of the 'wider' data to the actual
-- address value
--******************************************************
CONSTANT WRITE_ADDR_A_DIV : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH_A;
CONSTANT READ_ADDR_A_DIV : INTEGER := C_READ_WIDTH_A/MIN_WIDTH_A;
CONSTANT WRITE_ADDR_B_DIV : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH_B;
CONSTANT READ_ADDR_B_DIV : INTEGER := C_READ_WIDTH_B/MIN_WIDTH_B;
--******************************************************
-- FUNCTION : log2roundup
--******************************************************
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
--******************************************************
-- Other constants and signals
--******************************************************
CONSTANT COLL_DELAY : TIME := 100 ps;
-- default data vector
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_DEFAULT_DATA,
C_WRITE_WIDTH_A);
CONSTANT CHKBIT_WIDTH : INTEGER := if_then_else(C_WRITE_WIDTH_A>57,8,if_then_else(C_WRITE_WIDTH_A>26,7,if_then_else(C_WRITE_WIDTH_A>11,6,if_then_else(C_WRITE_WIDTH_A>4,5,if_then_else(C_WRITE_WIDTH_A<5,4,0)))));
-- the init memory SIGNAL
SIGNAL memory_i : mem_array;
SIGNAL doublebit_error_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0);
SIGNAL current_contents_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
-- write mode constants
CONSTANT WRITE_MODE_A : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_A);
CONSTANT WRITE_MODE_B : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_B);
CONSTANT WRITE_MODES : STD_LOGIC_VECTOR(3 DOWNTO 0) :=
WRITE_MODE_A & WRITE_MODE_B;
-- reset values
CONSTANT INITA_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITA_VAL,
C_READ_WIDTH_A);
CONSTANT INITB_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITB_VAL,
C_READ_WIDTH_B);
-- memory output 'latches'
SIGNAL memory_out_a : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0) :=
INITA_VAL;
SIGNAL memory_out_b : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) :=
INITB_VAL;
SIGNAL sbiterr_in : STD_LOGIC := '0';
SIGNAL sbiterr_sdp : STD_LOGIC := '0';
SIGNAL dbiterr_in : STD_LOGIC := '0';
SIGNAL dbiterr_sdp : STD_LOGIC := '0';
SIGNAL rdaddrecc_in : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_sdp : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL doutb_i : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i : STD_LOGIC := '0';
SIGNAL dbiterr_i : STD_LOGIC := '0';
-- memory configuration constants
-----------------------------------------------
CONSTANT SINGLE_PORT : INTEGER := get_single_port(C_MEM_TYPE);
CONSTANT IS_ROM : INTEGER := get_is_rom(C_MEM_TYPE);
CONSTANT HAS_A_WRITE : INTEGER := get_has_a_write(IS_ROM);
CONSTANT HAS_B_WRITE : INTEGER := get_has_b_write(C_MEM_TYPE);
CONSTANT HAS_A_READ : INTEGER := get_has_a_read(C_MEM_TYPE);
CONSTANT HAS_B_READ : INTEGER := get_has_b_read(SINGLE_PORT);
CONSTANT HAS_B_PORT : INTEGER := get_has_b_port(HAS_B_READ, HAS_B_WRITE);
CONSTANT NUM_OUTPUT_STAGES_A : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_A,
C_MUX_PIPELINE_STAGES);
CONSTANT NUM_OUTPUT_STAGES_B : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES);
CONSTANT WEA0 : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT WEB0 : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-----------------------------------------------------------------------------
-- DEBUG CONTROL
-- DEBUG=0 : Debug output OFF
-- DEBUG=1 : Some debug info printed
-----------------------------------------------------------------------------
CONSTANT DEBUG : INTEGER := 0;
-- internal signals
-----------------------------------------------
SIGNAL ena_i : STD_LOGIC;
SIGNAL enb_i : STD_LOGIC;
SIGNAL reseta_i : STD_LOGIC;
SIGNAL resetb_i : STD_LOGIC;
SIGNAL wea_i : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL web_i : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL rea_i : STD_LOGIC;
SIGNAL reb_i : STD_LOGIC;
SIGNAL message_complete : BOOLEAN := false;
SIGNAL rsta_outp_stage : STD_LOGIC := '0';
SIGNAL rstb_outp_stage : STD_LOGIC := '0';
--*********************************************************
--FUNCTION : Collision check
--*********************************************************
FUNCTION collision_check (addr_a :
STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
iswrite_a : BOOLEAN;
addr_b :
STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
iswrite_b : BOOLEAN)
RETURN BOOLEAN IS
VARIABLE c_aw_bw : INTEGER;
VARIABLE c_aw_br : INTEGER;
VARIABLE c_ar_bw : INTEGER;
VARIABLE write_addr_a_width : INTEGER;
VARIABLE read_addr_a_width : INTEGER;
VARIABLE write_addr_b_width : INTEGER;
VARIABLE read_addr_b_width : INTEGER;
BEGIN
c_aw_bw := 0;
c_aw_br := 0;
c_ar_bw := 0;
-- Determine the effective address widths FOR each of the 4 ports
write_addr_a_width := C_ADDRA_WIDTH-log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width := C_ADDRA_WIDTH-log2roundup(READ_ADDR_A_DIV);
write_addr_b_width := C_ADDRB_WIDTH-log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width := C_ADDRB_WIDTH-log2roundup(READ_ADDR_B_DIV);
--Look FOR a write-write collision. In order FOR a write-write
--collision to exist, both ports must have a write transaction.
IF (iswrite_a AND iswrite_b) THEN
IF (write_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_a and iswrite_b
--If the B port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_a) THEN
IF (write_addr_a_width > read_addr_b_width) THEN
--read_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_b_width
--Once both are scaled to read_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
END IF; --width
END IF; --iswrite_a
--If the A port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_b) THEN
IF (read_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
ELSE
--read_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_a_width
--Once both are scaled to read_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_b
RETURN (c_aw_bw=1 OR c_aw_br=1 OR c_ar_bw=1);
END FUNCTION collision_check;
BEGIN -- Architecture
-----------------------------------------------------------------------------
-- SOFTECC and ECC SBITERR/DBITERR Outputs
-- The ECC Behavior is modeled by the behavioral models only for Virtex-6.
-- The SOFTECC Behavior is modeled by the behavioral models for Spartan-6.
-- For Virtex-5, these outputs will be tied to 0.
-----------------------------------------------------------------------------
SBITERR <= sbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_sdp WHEN (((C_FAMILY="virtex7") AND C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
-----------------------------------------------
-- This effectively wires off optional inputs
-----------------------------------------------
ena_i <= ENA WHEN (C_HAS_ENA=1) ELSE '1';
enb_i <= ENB WHEN (C_HAS_ENB=1 AND HAS_B_PORT=1) ELSE '1';
-- We are doing an "AND" operation of WEA and ENA and passing to Enbale pin of BRAM when built-in ECC is enabled,
-- what this means is that the write operation happens only when both WEA and ENA are high.
wea_i <= WEA WHEN (HAS_A_WRITE=1 AND ena_i='1') ELSE WEA0;
-- wea_i <= (OTHERS => '1') WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=1 AND ENA = '1') ELSE -- Use_ENA_pin
-- WEA WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=0) ELSE -- Always_enabled
-- WEA WHEN (HAS_A_WRITE=1 AND ena_i='1' AND C_USE_ECC = 0) ELSE
-- WEA0;
web_i <= WEB WHEN (HAS_B_WRITE=1 AND enb_i='1') ELSE WEB0;
rea_i <= ena_i WHEN (HAS_A_READ=1) ELSE '0';
reb_i <= enb_i WHEN (HAS_B_READ=1) ELSE '0';
-- these signals reset the memory latches
-- For the special reset behaviors in some of the families, the C_RSTRAM
-- attribute of the corresponding port is used to indicate if the latch is
-- reset or not.
reseta_i <= RSTA WHEN
((C_HAS_RSTA=1 AND NUM_OUTPUT_STAGES_A=0) OR
(C_HAS_RSTA=1 AND C_RSTRAM_A=1))
ELSE '0';
resetb_i <= RSTB WHEN
((C_HAS_RSTB=1 AND NUM_OUTPUT_STAGES_B=0) OR
(C_HAS_RSTB=1 AND C_RSTRAM_B=1) )
ELSE '0';
--***************************************************************************
-- This is the main PROCESS which includes the memory VARIABLE and the read
-- and write procedures. It also schedules read and write operations
--***************************************************************************
PROCESS (CLKA, CLKB,rea_i,reb_i,reseta_i,resetb_i)
-- Initialize the init memory array
------------------------------------
VARIABLE memory : mem_array := init_memory(DEFAULT_DATA,
C_WRITE_WIDTH_A,
MAX_DEPTH,
MIN_WIDTH);
-- Initialize the mem memory array
------------------------------------
VARIABLE softecc_sbiterr_arr : softecc_err_array;
VARIABLE softecc_dbiterr_arr : softecc_err_array;
VARIABLE sbiterr_arr : ecc_err_array;
VARIABLE dbiterr_arr : ecc_err_array;
CONSTANT doublebit_lsb : STD_LOGIC_VECTOR (1 DOWNTO 0):="11";
CONSTANT doublebit_msb : STD_LOGIC_VECTOR (C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 DOWNTO 0):= (OTHERS => '0');
VARIABLE doublebit_error : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0) := doublebit_msb & doublebit_lsb ;
VARIABLE current_contents_var : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
--***********************************
-- procedures to access the memory
--***********************************
-- write_a
----------
PROCEDURE write_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
inj_sbiterr : IN STD_LOGIC;
inj_dbiterr : IN STD_LOGIC) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
VARIABLE message : LINE;
VARIABLE errbit_current_contents : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
-- Block Memory Generator non-cycle-accurate message
ASSERT (message_complete) REPORT "Block Memory Generator module is using a behavioral model FOR simulation which will not precisely model memory collision behavior."
SEVERITY NOTE;
message_complete <= true;
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_A_DIV);
IF (address_i >= C_WRITE_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range FOR A Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEA = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_A + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEA_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Insert double bit errors:
IF (C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
current_contents(0) := NOT(current_contents(0));
current_contents(1) := NOT(current_contents(1));
--current_contents(0) := NOT(current_contents(30));
--current_contents(1) := NOT(current_contents(62));
END IF;
END IF;
-- Insert double bit errors:
IF (C_USE_SOFTECC=1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 downto 2) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 downto 0);
doublebit_error(0) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1);
doublebit_error(1) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-2);
current_contents := current_contents XOR doublebit_error(C_WRITE_WIDTH_A-1 DOWNTO 0);
END IF;
END IF;
IF(DEBUG=1) THEN
current_contents_var := current_contents; --for debugging current
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_A + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
-- Store address at which error is injected:
IF ((C_FAMILY = "virtex7") AND C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
sbiterr_arr(address_i) := '1';
ELSE
sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
dbiterr_arr(address_i) := '1';
ELSE
dbiterr_arr(address_i) := '0';
END IF;
END IF;
-- Store address at which softecc error is injected:
IF (C_USE_SOFTECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
softecc_sbiterr_arr(address_i) := '1';
ELSE
softecc_sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
softecc_dbiterr_arr(address_i) := '1';
ELSE
softecc_dbiterr_arr(address_i) := '0';
END IF;
END IF;
END IF;
END PROCEDURE;
-- write_b
----------
PROCEDURE write_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_B_DIV);
IF (address_i >= C_WRITE_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEB = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_B + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEB_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_B + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
END IF;
END PROCEDURE;
-- read_a
----------
PROCEDURE read_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_A_DIV);
IF (address_i >= C_READ_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for A Read"
SEVERITY WARNING;
END IF;
memory_out_a <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_A-1 LOOP
memory_out_a(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_A + i) AFTER FLOP_DELAY;
END LOOP;
END IF;
END IF;
END PROCEDURE;
-- read_b
----------
PROCEDURE read_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_B_DIV);
IF (address_i >= C_READ_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Read"
SEVERITY WARNING;
END IF;
memory_out_b <= (OTHERS => 'X') AFTER FLOP_DELAY;
sbiterr_in <= 'X' AFTER FLOP_DELAY;
dbiterr_in <= 'X' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_B-1 LOOP
memory_out_b(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_B + i) AFTER FLOP_DELAY;
END LOOP;
--assert sbiterr and dbiterr signals
IF ((C_FAMILY="virtex7") AND C_USE_ECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
--assert softecc sbiterr and dbiterr signals
ELSIF (C_USE_SOFTECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (softecc_sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (softecc_dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
END IF;
END IF;
END IF;
END PROCEDURE;
-- reset_a
----------
PROCEDURE reset_a
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
-- reset_b
----------
PROCEDURE reset_b
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
BEGIN -- begin the main PROCESS
--***************************************************************************
-- These are the main blocks which schedule read and write operations
-- Note that the reset priority feature at the latch stage is only supported
-- for Spartan-6. For other families, the default priority at the latch stage
-- is "CE"
--***************************************************************************
-- Synchronous clocks: schedule port operations with respect to both
-- write operating modes
IF (C_COMMON_CLK=1) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODES IS
WHEN "0000" => -- write_first write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "0100" => -- read_first write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "0001" => -- write_first read_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0101" => --read_first read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0010" => -- write_first no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0110" => -- read_first no_change
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1000" => -- no_change write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "1001" => -- no_change read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1010" => -- no_change no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Synchronous clocks
-- Asynchronous clocks: port operation is independent
IF (C_COMMON_CLK=0) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODE_A IS
WHEN "00" => -- write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN "01" => -- read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "10" => -- no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
IF (CLKB='1' AND CLKB'EVENT) THEN
CASE WRITE_MODE_B IS
WHEN "00" => -- write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "01" => -- read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "10" => -- no_change
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Asynchronous clocks
-- Assign the memory VARIABLE to the user_visible memory_i SIGNAL
IF(DEBUG=1) THEN
memory_i <= memory;
doublebit_error_i <= doublebit_error;
current_contents_i <= current_contents_var;
END IF;
END PROCESS;
--********************************************************************
-- Instantiate the VARIABLE depth output stage
--********************************************************************
-- Port A
rsta_outp_stage <= RSTA and not sleep;
rstb_outp_stage <= RSTB and not sleep;
reg_a : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTA,
C_RSTRAM => C_RSTRAM_A,
C_RST_PRIORITY => C_RST_PRIORITY_A,
init_val => INITA_VAL,
C_HAS_EN => C_HAS_ENA,
C_HAS_REGCE => C_HAS_REGCEA,
C_DATA_WIDTH => C_READ_WIDTH_A,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_A,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_A,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKA,
RST => rsta_outp_stage, --RSTA,
EN => ENA,
REGCE => REGCEA,
DIN_I => memory_out_a,
DOUT => DOUTA,
SBITERR_IN_I => '0',
DBITERR_IN_I => '0',
SBITERR => OPEN,
DBITERR => OPEN,
RDADDRECC_IN_I => (OTHERS => '0'),
ECCPIPECE => '0',
RDADDRECC => OPEN
);
-- Port B
reg_b : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTB,
C_RSTRAM => C_RSTRAM_B,
C_RST_PRIORITY => C_RST_PRIORITY_B,
init_val => INITB_VAL,
C_HAS_EN => C_HAS_ENB,
C_HAS_REGCE => C_HAS_REGCEB,
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_B,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKB,
RST => rstb_outp_stage,--RSTB,
EN => ENB,
REGCE => REGCEB,
DIN_I => memory_out_b,
DOUT => doutb_i,
SBITERR_IN_I => sbiterr_in,
DBITERR_IN_I => dbiterr_in,
SBITERR => sbiterr_i,
DBITERR => dbiterr_i,
RDADDRECC_IN_I => rdaddrecc_in,
ECCPIPECE => ECCPIPECE,
RDADDRECC => rdaddrecc_i
);
--********************************************************************
-- Instantiate the input / Output Register stages
--********************************************************************
output_reg_stage: blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC MAP(
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP(
CLK => CLKB,
DIN => doutb_i,
DOUT => DOUTB,
SBITERR_IN => sbiterr_i,
DBITERR_IN => dbiterr_i,
SBITERR => sbiterr_sdp,
DBITERR => dbiterr_sdp,
RDADDRECC_IN => rdaddrecc_i,
RDADDRECC => rdaddrecc_sdp
);
--*********************************
-- Synchronous collision checks
--*********************************
sync_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=1) GENERATE
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
-- collision detect
VARIABLE is_collision : BOOLEAN;
VARIABLE message : LINE;
BEGIN
IF (CLKA='1' AND CLKA'EVENT) THEN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision := false;
END IF;
-- If the write port is in READ_FIRST mode, there is no collision
IF (C_WRITE_MODE_A="READ_FIRST" AND wea_i/=WEA0 AND web_i=WEB0) THEN
is_collision := false;
END IF;
IF (C_WRITE_MODE_B="READ_FIRST" AND web_i/=WEB0 AND wea_i=WEA0) THEN
is_collision := false;
END IF;
-- Only flag if one of the accesses is a write
IF (is_collision AND (wea_i/=WEA0 OR web_i/=WEB0)) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END IF;
END PROCESS;
END GENERATE;
--*********************************
-- Asynchronous collision checks
--*********************************
async_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=0) GENERATE
SIGNAL addra_delay : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL wea_delay : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL ena_delay : STD_LOGIC;
SIGNAL addrb_delay : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
SIGNAL web_delay : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL enb_delay : STD_LOGIC;
BEGIN
-- Delay A and B addresses in order to mimic setup/hold times
PROCESS (ADDRA, wea_i, ena_i, ADDRB, web_i, enb_i)
BEGIN
addra_delay <= ADDRA AFTER COLL_DELAY;
wea_delay <= wea_i AFTER COLL_DELAY;
ena_delay <= ena_i AFTER COLL_DELAY;
addrb_delay <= ADDRB AFTER COLL_DELAY;
web_delay <= web_i AFTER COLL_DELAY;
enb_delay <= enb_i AFTER COLL_DELAY;
END PROCESS;
-- Do the checks w/rt A
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_a : BOOLEAN;
VARIABLE is_collision_delay_a : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_a := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_a := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_delay_a := collision_check(ADDRA,
wea_i/=WEA0,
addrb_delay,
web_delay/=WEB0);
ELSE
is_collision_delay_a := false;
END IF;
-- Only flag if B access is a write
IF (is_collision_a AND web_i/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_a AND web_delay/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, addrb_delay);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
-- Do the checks w/rt B
PROCESS (CLKB)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_b : BOOLEAN;
VARIABLE is_collision_delay_b : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA) /= 'X') THEN
is_collision_b := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_b := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(addra_delay) /= 'X') THEN
is_collision_delay_b := collision_check(addra_delay,
wea_delay/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_delay_b := false;
END IF;
-- Only flag if A access is a write
-- Modified condition checking (is_collision_b AND WEA0_i=/WEA0) to fix CR526228
IF (is_collision_b AND wea_i/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_b AND wea_delay/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, addra_delay);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
END GENERATE;
END mem_module_behavioral;
--******************************************************************************
-- Top module that wraps SoftECC Input register stage and the main memory module
--
-- This module is the top-level of behavioral model
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1 IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_CTRL_ECC_ALGO : STRING := "NONE";
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
--C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_SLEEP_PIN : INTEGER := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
PORT (
clka : IN STD_LOGIC := '0';
rsta : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '1';
regcea : IN STD_LOGIC := '1';
wea : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addra : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
dina : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
douta : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
clkb : IN STD_LOGIC := '0';
rstb : IN STD_LOGIC := '0';
enb : IN STD_LOGIC := '1';
regceb : IN STD_LOGIC := '1';
web : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addrb : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
dinb : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
doutb : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
injectsbiterr : IN STD_LOGIC := '0';
injectdbiterr : IN STD_LOGIC := '0';
sbiterr : OUT STD_LOGIC := '0';
dbiterr : OUT STD_LOGIC := '0';
rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : in std_logic := '0';
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic := '0';
rstb_busy : out std_logic := '0';
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
s_aclk : IN STD_LOGIC := '0';
s_aresetn : IN STD_LOGIC := '0';
-- axi full/lite slave Write (write side)
s_axi_awid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid : IN STD_LOGIC := '0';
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast : IN STD_LOGIC := '0';
s_axi_wvalid : IN STD_LOGIC := '0';
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC := '0';
-- axi full/lite slave Read (Write side)
s_axi_arid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid : IN STD_LOGIC := '0';
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_rdata : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC := '0';
-- axi full/lite sideband Signals
s_axi_injectsbiterr : IN STD_LOGIC := '0';
s_axi_injectdbiterr : IN STD_LOGIC := '0';
s_axi_sbiterr : OUT STD_LOGIC := '0';
s_axi_dbiterr : OUT STD_LOGIC := '0';
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END blk_mem_gen_v8_3_1;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE behavioral OF blk_mem_gen_v8_3_1 IS
COMPONENT blk_mem_gen_v8_3_1_mem_module
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_mem_module;
COMPONENT blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_axi_regs_fwd_v8_3;
COMPONENT blk_mem_axi_read_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT blk_mem_axi_read_wrapper_beh;
COMPONENT blk_mem_axi_write_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END COMPONENT blk_mem_axi_write_wrapper_beh;
CONSTANT FLOP_DELAY : TIME := 100 ps;
SIGNAL rsta_in : STD_LOGIC := '1';
SIGNAL ena_in : STD_LOGIC := '1';
SIGNAL regcea_in : STD_LOGIC := '1';
SIGNAL wea_in : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL addra_in : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL dina_in : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL injectsbiterr_in : STD_LOGIC := '0';
SIGNAL injectdbiterr_in : STD_LOGIC := '0';
-----------------------------------------------------------------------------
-- FUNCTION: toLowerCaseChar
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
-----------------------------------------------------------------------------
FUNCTION toLowerCaseChar(
char : character )
RETURN character IS
BEGIN
-- If char is not an upper case letter then return char
IF char<'A' OR char>'Z' THEN
RETURN char;
END IF;
-- Otherwise map char to its corresponding lower case character and
-- RETURN that
CASE char IS
WHEN 'A' => RETURN 'a';
WHEN 'B' => RETURN 'b';
WHEN 'C' => RETURN 'c';
WHEN 'D' => RETURN 'd';
WHEN 'E' => RETURN 'e';
WHEN 'F' => RETURN 'f';
WHEN 'G' => RETURN 'g';
WHEN 'H' => RETURN 'h';
WHEN 'I' => RETURN 'i';
WHEN 'J' => RETURN 'j';
WHEN 'K' => RETURN 'k';
WHEN 'L' => RETURN 'l';
WHEN 'M' => RETURN 'm';
WHEN 'N' => RETURN 'n';
WHEN 'O' => RETURN 'o';
WHEN 'P' => RETURN 'p';
WHEN 'Q' => RETURN 'q';
WHEN 'R' => RETURN 'r';
WHEN 'S' => RETURN 's';
WHEN 'T' => RETURN 't';
WHEN 'U' => RETURN 'u';
WHEN 'V' => RETURN 'v';
WHEN 'W' => RETURN 'w';
WHEN 'X' => RETURN 'x';
WHEN 'Y' => RETURN 'y';
WHEN 'Z' => RETURN 'z';
WHEN OTHERS => RETURN char;
END CASE;
END toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
FUNCTION equalIgnoreCase(
str1 : STRING;
str2 : STRING )
RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str2'left TO str1'right LOOP
IF NOT (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equalIgnoreCase;
-----------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
----------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
----------------------------------------------------------------------------
-- FUNCTION : log2roundup
----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
CONSTANT lower_limit : INTEGER := 1;
CONSTANT upper_limit : INTEGER := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
-----------------------------------------------------------------------------
-- FUNCTION : divroundup
-- Returns the ceiling value of the division
-- Data_value - the quantity to be divided, dividend
-- Divisor - the value to divide the data_value by
-----------------------------------------------------------------------------
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
SIGNAL s_axi_awaddr_out_c : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_araddr_out_c : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_wr_en_c : STD_LOGIC := '0';
SIGNAL s_axi_rd_en_c : STD_LOGIC := '0';
SIGNAL s_aresetn_a_c : STD_LOGIC := '0';
--**************************************************************************
-- AXI PARAMETERS
CONSTANT AXI_FULL_MEMORY_SLAVE : integer := if_then_else((C_AXI_SLAVE_TYPE = 0 AND C_AXI_TYPE = 1),1,0);
CONSTANT C_AXI_ADDR_WIDTH_MSB : integer := C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
CONSTANT C_AXI_ADDR_WIDTH : integer := C_AXI_ADDR_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT LOWER_BOUND_VAL : integer := if_then_else((log2roundup(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT C_AXI_ADDR_WIDTH_LSB : integer := if_then_else((AXI_FULL_MEMORY_SLAVE = 1),0,LOWER_BOUND_VAL);
CONSTANT C_AXI_OS_WR : integer := 2;
-- SAFETY LOGIC related Signals
SIGNAL RSTA_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_A : STD_LOGIC := '0';
SIGNAL RSTB_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_B : STD_LOGIC := '0';
SIGNAL ENA_dly : STD_LOGIC := '0';
SIGNAL ENA_dly_D : STD_LOGIC := '0';
SIGNAL ENB_dly : STD_LOGIC := '0';
SIGNAL ENB_dly_D : STD_LOGIC := '0';
SIGNAL RSTA_I_SAFE : STD_LOGIC := '0';
SIGNAL RSTB_I_SAFE : STD_LOGIC := '0';
SIGNAL ENA_I_SAFE : STD_LOGIC := '0';
SIGNAL ENB_I_SAFE : STD_LOGIC := '0';
SIGNAL ram_rstram_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstram_b_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_b_busy : STD_LOGIC := '0';
SIGNAL ENA_dly_reg : STD_LOGIC := '0';
SIGNAL ENB_dly_reg : STD_LOGIC := '0';
SIGNAL ENA_dly_reg_D : STD_LOGIC := '0';
SIGNAL ENB_dly_reg_D : STD_LOGIC := '0';
--**************************************************************************
BEGIN -- Architecture
--*************************************************************************
-- NO INPUT STAGE
--*************************************************************************
no_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=0) GENERATE
rsta_in <= RSTA;
ena_in <= ENA;
regcea_in <= REGCEA;
wea_in <= WEA;
addra_in <= ADDRA;
dina_in <= DINA;
injectsbiterr_in <= INJECTSBITERR;
injectdbiterr_in <= INJECTDBITERR;
END GENERATE no_input_stage;
--**************************************************************************
-- WITH INPUT STAGE
--**************************************************************************
has_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=1) GENERATE
PROCESS (CLKA)
BEGIN
IF (CLKA'EVENT AND CLKA = '1') THEN
rsta_in <= RSTA AFTER FLOP_DELAY;
ena_in <= ENA AFTER FLOP_DELAY;
regcea_in <= REGCEA AFTER FLOP_DELAY;
wea_in <= WEA AFTER FLOP_DELAY;
addra_in <= ADDRA AFTER FLOP_DELAY;
dina_in <= DINA AFTER FLOP_DELAY;
injectsbiterr_in <= INJECTSBITERR AFTER FLOP_DELAY;
injectdbiterr_in <= INJECTDBITERR AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE has_input_stage;
--**************************************************************************
-- NO SAFETY LOGIC
--**************************************************************************
NO_SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 0) GENERATE
ENA_I_SAFE <= ena_in;
ENB_I_SAFE <= ENB;
RSTA_I_SAFE <= rsta_in;
RSTB_I_SAFE <= RSTB;
END GENERATE NO_SAFETY_CKT_GEN;
--**************************************************************************
-- SAFETY LOGIC
--**************************************************************************
SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 1) GENERATE
-- RESET SAFETY LOGIC Generation
-- POR Generation
------------------------------------------------------------------------------
-- Power-ON Reset Generation
------------------------------------------------------------------------------
RST_SHFT_LOGIC_A : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
RSTA_SHFT_REG(4 DOWNTO 0) <= RSTA_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_A;
POR_RSTA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
POR_A <= RSTA_SHFT_REG(4) xor RSTA_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTA_GEN;
RST_SHFT_LOGIC_B : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
RSTB_SHFT_REG(4 DOWNTO 0) <= RSTB_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_B;
POR_RSTB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
POR_B <= RSTB_SHFT_REG(4) xor RSTB_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTB_GEN;
-----------------------------------------------------------------------------
-- Fix for the AR42571
-----------------------------------------------------------------------------
-- Reset Generation
-----------------------------------------------------------------------------
RSTA_I_SAFE <= rsta_in OR POR_A;
SPRAM_RST: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_I_SAFE <= '0';
END GENERATE SPRAM_RST;
nSPRAM_RST: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_I_SAFE <= RSTB OR POR_B;
END GENERATE nSPRAM_RST;
-----------------------------------------------------------------------------
-- RSTA/B_BUSY Generation
-----------------------------------------------------------------------------
RSTA_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
ram_rstram_a_busy <= rsta_in OR ENA_dly OR ENA_dly_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstram_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_NO_REG;
RSTA_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
ram_rstreg_a_busy <= rsta_in OR ENA_dly OR ENA_dly_reg_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstreg_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_WITH_REG;
SPRAM_RST_BUSY: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_BUSY <= '0';
END GENERATE SPRAM_RST_BUSY;
nSPRAM_RST_BUSY: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
ram_rstram_b_busy <= RSTB OR ENB_dly OR ENB_dly_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstram_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_NO_REG;
RSTB_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
ram_rstreg_b_busy <= RSTB OR ENB_dly OR ENB_dly_reg_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstreg_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_WITH_REG;
END GENERATE nSPRAM_RST_BUSY;
-----------------------------------------------------------------------------
-- ENA/ENB Generation
-----------------------------------------------------------------------------
ENA_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly <= rsta_in AFTER FLOP_DELAY;
ENA_dly_D <= ENA_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_D OR ena_in;
END GENERATE ENA_NO_REG;
ENA_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly_reg <= rsta_in AFTER FLOP_DELAY;
ENA_dly_reg_D <= ENA_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_reg_D OR ena_in;
END GENERATE ENA_WITH_REG;
SPRAM_ENB: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
ENB_I_SAFE <= '0';
END GENERATE SPRAM_ENB;
nSPRAM_ENB: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
ENB_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly <= RSTB AFTER FLOP_DELAY;
ENB_dly_D <= ENB_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_D OR ENB;
END GENERATE ENB_NO_REG;
ENB_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly_reg <= RSTB AFTER FLOP_DELAY;
ENB_dly_reg_D <= ENB_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_reg_D OR ENB;
END GENERATE ENB_WITH_REG;
END GENERATE nSPRAM_ENB;
END GENERATE SAFETY_CKT_GEN;
--**************************************************************************
-- NATIVE MEMORY MODULE INSTANCE
--**************************************************************************
native_mem_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 0) GENERATE
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,--rsta_in,
ENA => ENA_I_SAFE,--ena_in,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in,
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => RDADDRECC
);
END GENERATE native_mem_module;
--**************************************************************************
-- NATIVE MEMORY MAPPED MODULE INSTANCE
--**************************************************************************
native_mem_map_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 1) GENERATE
--**************************************************************************
-- NATIVE MEMORY MAPPED PARAMETERS
CONSTANT C_ADDRA_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_A);
CONSTANT C_ADDRB_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_B);
CONSTANT C_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
CONSTANT C_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
CONSTANT C_MEM_MAP_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_MSB;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT MEM_MAP_LOWER_BOUND_VAL_A : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT MEM_MAP_LOWER_BOUND_VAL_B : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_B,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_B,8)));
CONSTANT C_MEM_MAP_ADDRA_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_A;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_B;
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH_ACTUAL-1 DOWNTO 0) := (OTHERS => '0');
--**************************************************************************
BEGIN
RDADDRECC(C_ADDRB_WIDTH-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_MSB) <= (OTHERS => '0');
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB) <= rdaddrecc_i;
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_LSB-1 DOWNTO 0) <= (OTHERS => '0');
mem_map_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH_ACTUAL,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH_ACTUAL,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,
ENA => ENA_I_SAFE,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in(C_MEM_MAP_ADDRA_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRA_WIDTH_LSB),
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB),
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => rdaddrecc_i
);
END GENERATE native_mem_map_module;
--****************************************************************************
-- AXI MEMORY MODULE INSTANCE
--****************************************************************************
axi_mem_module: IF (C_INTERFACE_TYPE = 1) GENERATE
SIGNAL s_axi_rid_c : STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rdata_c : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rresp_c : STD_LOGIC_VECTOR(2-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rlast_c : STD_LOGIC := '0';
SIGNAL s_axi_rvalid_c : STD_LOGIC := '0';
SIGNAL s_axi_rready_c : STD_LOGIC := '0';
SIGNAL regceb_c : STD_LOGIC := '0';
BEGIN
s_aresetn_a_c <= NOT S_ARESETN;
S_AXI_BRESP <= (OTHERS => '0');
s_axi_rresp_c <= (OTHERS => '0');
no_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 0 AND C_HAS_MUX_OUTPUT_REGS_B = 0 ) GENERATE
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RLAST <= s_axi_rlast_c;
S_AXI_RVALID <= s_axi_rvalid_c;
S_AXI_RID <= s_axi_rid_c;
S_AXI_RRESP <= s_axi_rresp_c;
s_axi_rready_c <= S_AXI_RREADY;
END GENERATE no_regs;
has_regs_fwd: IF (C_HAS_MUX_OUTPUT_REGS_B = 1 OR C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
CONSTANT C_AXI_PAYLOAD : INTEGER := if_then_else((C_HAS_MUX_OUTPUT_REGS_B = 1),C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3,C_AXI_ID_WIDTH+3);
SIGNAL s_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
has_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
regceb_c <= s_axi_rvalid_c AND s_axi_rready_c;
END GENERATE has_regceb;
no_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 0) GENERATE
regceb_c <= REGCEB;
END GENERATE no_regceb;
only_core_op_regs: IF (C_HAS_MUX_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rdata_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RDATA <= m_axi_payload_c(C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_core_op_regs;
only_emb_op_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_emb_op_regs;
axi_regs_inst : blk_mem_axi_regs_fwd_v8_3
GENERIC MAP(
C_DATA_WIDTH => C_AXI_PAYLOAD
)
PORT MAP (
ACLK => S_ACLK,
ARESET => s_aresetn_a_c,
S_VALID => s_axi_rvalid_c,
S_READY => s_axi_rready_c,
S_PAYLOAD_DATA => s_axi_payload_c,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY,
M_PAYLOAD_DATA => m_axi_payload_c
);
END GENERATE has_regs_fwd;
axi_wr_fsm : blk_mem_axi_write_wrapper_beh
GENERIC MAP(
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_AXI_AWADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_WDATA_WIDTH => C_WRITE_WIDTH_A,
C_AXI_OS_WR => C_AXI_OS_WR
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Slave Write Interface
S_AXI_AWADDR => S_AXI_AWADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_AWLEN => S_AXI_AWLEN,
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BID => S_AXI_BID,
-- Signals for BRAM interface
S_AXI_AWADDR_OUT =>s_axi_awaddr_out_c,
S_AXI_WR_EN =>s_axi_wr_en_c
);
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => 1, -- For AXI, Read Enable is always C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => 1, -- For AXI C_USE_BYTE_WEA is always 1,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => 1, -- For AXI, Read Enable is always C_HAS_ENB,
C_HAS_REGCEB => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_BYTE_WEB => 1, -- For AXI C_USE_BYTE_WEB is always 1,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => 0, --For AXI, Primitive Registers A is not supported C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => 0,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
--Port A:
CLKA => S_AClk,
RSTA => s_aresetn_a_c,
ENA => s_axi_wr_en_c,
REGCEA => regcea_in,
WEA => S_AXI_WSTRB,
ADDRA => s_axi_awaddr_out_c,
DINA => S_AXI_WDATA,
DOUTA => DOUTA,
--Port B:
CLKB => S_AClk,
RSTB => s_aresetn_a_c,
ENB => s_axi_rd_en_c,
REGCEB => regceb_c,
WEB => (OTHERS => '0'),
ADDRB => s_axi_araddr_out_c,
DINB => DINB,
DOUTB => s_axi_rdata_c,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => '0',
SLEEP => '0',
RDADDRECC => RDADDRECC
);
axi_rd_sm : blk_mem_axi_read_wrapper_beh
GENERIC MAP (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_PIPELINE_STAGES => 1,
C_AXI_ARADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_AClk,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Read Side
S_AXI_ARADDR => S_AXI_ARADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARSIZE => S_AXI_ARSIZE,
S_AXI_ARBURST => S_AXI_ARBURST,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => s_axi_rlast_c,
S_AXI_RVALID => s_axi_rvalid_c,
S_AXI_RREADY => s_axi_rready_c,
S_AXI_ARID => S_AXI_ARID,
S_AXI_RID => s_axi_rid_c,
-- AXI Full/Lite Read FSM Outputs
S_AXI_ARADDR_OUT => s_axi_araddr_out_c,
S_AXI_RD_EN => s_axi_rd_en_c
);
END GENERATE axi_mem_module;
END behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_clr is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_clr;
architecture beh_ff_clr_arch of beh_ff_clr is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(CLR, C)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_clr_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_ce is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_ce;
architecture beh_ff_ce_arch of beh_ff_ce is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, CLR)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
if (CE = '1') then
q_o <= D after 100 ps;
end if;
end if;
end process;
end beh_ff_ce_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_pre is
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end beh_ff_pre;
architecture beh_ff_pre_arch of beh_ff_pre is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, PRE)
begin
if (PRE = '1') then
q_o <= '1';
elsif (C' event and C = '1') then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_pre_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_muxf7 is
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end beh_muxf7;
architecture beh_muxf7_arch of beh_muxf7 is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
else
O <= I1;
end if;
end process;
end beh_muxf7_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity STATE_LOGIC is
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic := '0';
I0 : in std_logic := '0';
I1 : in std_logic := '0';
I2 : in std_logic := '0';
I3 : in std_logic := '0';
I4 : in std_logic := '0';
I5 : in std_logic := '0'
);
end STATE_LOGIC;
architecture STATE_LOGIC_arch of STATE_LOGIC is
constant INIT_reg : std_logic_vector(63 downto 0) := INIT;
begin
LUT_beh:process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
begin
I_reg := I5 & I4 & I3 & I2 & I1 & I0;
O <= INIT_reg(conv_integer(I_reg));
end process;
end STATE_LOGIC_arch;
|
-------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v8_3_1.vhd
--
-- Description:
-- This file is the VHDL behvarial model for the
-- Block Memory Generator Core.
--
-------------------------------------------------------------------------------
-- Author: Xilinx
--
-- History: January 11, 2006: Initial revision
-- June 11, 2007 : Added independent register stages for
-- Port A and Port B (IP1_Jm/v2.5)
-- August 28, 2007 : Added mux pipeline stages feature (IP2_Jm/v2.6)
-- April 07, 2009 : Added support for Spartan-6 and Virtex-6
-- features, including the following:
-- (i) error injection, detection and/or correction
-- (ii) reset priority
-- (iii) special reset behavior
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
ENTITY blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END ENTITY blk_mem_axi_regs_fwd_v8_3;
ARCHITECTURE axi_regs_fwd_arch OF blk_mem_axi_regs_fwd_v8_3 IS
SIGNAL STORAGE_DATA : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_READY_I : STD_LOGIC := '0';
SIGNAL M_VALID_I : STD_LOGIC := '0';
SIGNAL ARESET_D : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');-- Reset delay register
BEGIN
--assign local signal to its output signal
S_READY <= S_READY_I;
M_VALID <= M_VALID_I;
PROCESS(ACLK)
BEGIN
IF(ACLK'event AND ACLK = '1') THEN
ARESET_D <= ARESET_D(0) & ARESET;
END IF;
END PROCESS;
--Save payload data whenever we have a transaction on the slave side
PROCESS(ACLK, ARESET)
BEGIN
IF (ARESET = '1') THEN
STORAGE_DATA <= (OTHERS => '0');
ELSIF(ACLK'event AND ACLK = '1') THEN
IF(S_VALID = '1' AND S_READY_I = '1') THEN
STORAGE_DATA <= S_PAYLOAD_DATA;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= STORAGE_DATA;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
PROCESS(ACLK,ARESET)
BEGIN
IF (ARESET_D /= "00") THEN
M_VALID_I <= '0';
ELSIF(ACLK'event AND ACLK = '1') THEN
IF (S_VALID = '1') THEN
--Always set M_VALID_I when slave side is valid
M_VALID_I <= '1';
ELSIF (M_READY = '1') THEN
--Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= '0';
END IF;
END IF;
END PROCESS;
--Slave Ready is either when Master side drives M_READY or we have space in our storage data
S_READY_I <= (M_READY OR (NOT M_VALID_I)) AND NOT(OR_REDUCE(ARESET_D));
END axi_regs_fwd_arch;
-------------------------------------------------------------------------------
-- Description:
-- This is the behavioral model of write_wrapper for the
-- Block Memory Generator Core.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_axi_write_wrapper_beh IS
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END blk_mem_axi_write_wrapper_beh;
ARCHITECTURE axi_write_wrap_arch OF blk_mem_axi_write_wrapper_beh IS
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_AXI_WDATA_WIDTH=8,0,
if_then_else((C_AXI_WDATA_WIDTH=16),1,
if_then_else((C_AXI_WDATA_WIDTH=32),2,
if_then_else((C_AXI_WDATA_WIDTH=64),3,
if_then_else((C_AXI_WDATA_WIDTH=128),4,
if_then_else((C_AXI_WDATA_WIDTH=256),5,0))))));
SIGNAL bvalid_c : std_logic := '0';
SIGNAL bready_timeout_c : std_logic := '0';
SIGNAL bvalid_rd_cnt_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_r : std_logic := '0';
SIGNAL bvalid_count_r : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL awaddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
C_AXI_AWADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL bvalid_wr_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_rd_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_last_c : std_logic := '0';
SIGNAL addr_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL aw_ready_r : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL awlen_cntr_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1');
SIGNAL awlen_int : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL awburst_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes : integer := 0;
SIGNAL wrap_boundary : integer := 0;
SIGNAL wrap_base_addr : integer := 0;
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
-- Array to store BIDs
TYPE id_array IS ARRAY (3 DOWNTO 0) OF std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
SIGNAL axi_bid_array : id_array := (others => (others => '0'));
COMPONENT write_netlist
GENERIC(
C_AXI_TYPE : integer
);
PORT(
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
S_AXI_AWVALID : IN std_logic;
aw_ready_r : OUT std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN std_logic;
S_AXI_WR_EN : OUT std_logic;
w_last_c : IN std_logic;
bready_timeout_c : IN std_logic;
addr_en_c : OUT std_logic;
incr_addr_c : OUT std_logic;
bvalid_c : OUT std_logic
);
END COMPONENT write_netlist;
BEGIN
---------------------------------------
--AXI WRITE FSM COMPONENT INSTANTIATION
---------------------------------------
axi_wr_fsm : write_netlist
GENERIC MAP (
C_AXI_TYPE => C_AXI_TYPE
)
PORT MAP (
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
S_AXI_AWVALID => S_AXI_AWVALID,
aw_ready_r => aw_ready_r,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BVALID => OPEN,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_WR_EN => S_AXI_WR_EN,
w_last_c => w_last_c,
bready_timeout_c => bready_timeout_c,
addr_en_c => addr_en_c,
incr_addr_c => incr_addr_c,
bvalid_c => bvalid_c
);
--Wrap Address boundary calculation
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWSIZE,"000"));
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(awlen_int)+1);
wrap_base_addr <= (conv_integer(awaddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary <= wrap_base_addr+total_bytes;
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awaddr_reg <= (OTHERS => '0');
num_of_bytes_r <= 0;
awburst_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awaddr_reg <= S_AXI_AWADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWBURST,"01");
ELSIF (incr_addr_c = '1') THEN
IF (awburst_int = "10") THEN
IF(conv_integer(awaddr_reg) = (wrap_boundary-num_of_bytes_r)) THEN
awaddr_reg <= conv_std_logic_vector(wrap_base_addr,C_AXI_AWADDR_WIDTH);
ELSE
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
ELSIF (awburst_int = "01" OR awburst_int = "11") THEN
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
S_AXI_AWADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
awaddr_reg(C_AXI_AWADDR_WIDTH-1 DOWNTO C_RANGE),awaddr_reg);
---------------------------------------------------------------------------
-- AXI wlast generation
---------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awlen_cntr_r <= (OTHERS => '1');
awlen_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awlen_int <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
awlen_cntr_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
ELSIF (dec_alen_c = '1') THEN
awlen_cntr_r <= awlen_cntr_r - ONE AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
w_last_c <= '1' WHEN (awlen_cntr_r = "00000000" AND S_AXI_WVALID = '1') ELSE '0';
dec_alen_c <= (incr_addr_c OR w_last_c);
---------------------------------------------------------------------------
-- Generation of bvalid counter for outstanding transactions
---------------------------------------------------------------------------
P_b_valid_os_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_count_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- bvalid_count_r generation
IF (bvalid_c = '1' AND bvalid_r = '1' AND S_AXI_BREADY = '1') THEN
bvalid_count_r <= bvalid_count_r AFTER FLOP_DELAY;
ELSIF (bvalid_c = '1') THEN
bvalid_count_r <= bvalid_count_r + "01" AFTER FLOP_DELAY;
ELSIF (bvalid_r = '1' AND S_AXI_BREADY = '1' AND bvalid_count_r /= "0") THEN
bvalid_count_r <= bvalid_count_r - "01" AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_os_r ;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is used
---------------------------------------------------------------------------
gaxi_bvalid_id_r:IF (C_HAS_AXI_ID = 1) GENERATE
SIGNAL bvalid_d1_c : std_logic := '0';
BEGIN
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
bvalid_d1_c <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
--external bvalid signal generation
IF (bvalid_d1_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_id_r;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is not used
---------------------------------------------------------------------------
gaxi_bvalid_noid_r:IF (C_HAS_AXI_ID = 0) GENERATE
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
--external bvalid signal generation
IF (bvalid_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_noid_r;
---------------------------------------------------------------------------
-- Generation of Bready timeout
---------------------------------------------------------------------------
P_brdy_tout_c: PROCESS (bvalid_count_r)
BEGIN
-- bready_timeout_c generation
IF(conv_integer(bvalid_count_r) = C_AXI_OS_WR-1) THEN
bready_timeout_c <= '1';
ELSE
bready_timeout_c <= '0';
END IF;
END PROCESS P_brdy_tout_c;
---------------------------------------------------------------------------
-- Generation of BID
---------------------------------------------------------------------------
gaxi_bid_gen:IF (C_HAS_AXI_ID = 1) GENERATE
P_bid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
bvalid_wr_cnt_r <= (OTHERS => '0');
bvalid_rd_cnt_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- STORE AWID IN AN ARRAY
IF(bvalid_c = '1') THEN
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + "01";
END IF;
-- GENERATE BID FROM AWID ARRAY
bvalid_rd_cnt_r <= bvalid_rd_cnt_c AFTER FLOP_DELAY;
S_AXI_BID <= axi_bid_array(conv_integer(bvalid_rd_cnt_c));
END IF;
END PROCESS P_bid_gen;
bvalid_rd_cnt_c <= bvalid_rd_cnt_r + "01" WHEN (bvalid_r = '1' AND S_AXI_BREADY = '1') ELSE bvalid_rd_cnt_r;
---------------------------------------------------------------------------
-- Storing AWID for generation of BID
---------------------------------------------------------------------------
P_awid_reg:PROCESS (S_ACLK)
BEGIN
IF (S_ACLK'event AND S_ACLK='1') THEN
IF(aw_ready_r = '1' AND S_AXI_AWVALID = '1') THEN
axi_bid_array(conv_integer(bvalid_wr_cnt_r)) <= S_AXI_AWID;
END IF;
END IF;
END PROCESS P_awid_reg;
END GENERATE gaxi_bid_gen;
S_AXI_BVALID <= bvalid_r;
S_AXI_AWREADY <= aw_ready_r;
END axi_write_wrap_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity write_netlist is
GENERIC(
C_AXI_TYPE : integer
);
port (
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_AWVALID : in STD_LOGIC := '0';
S_AXI_WVALID : in STD_LOGIC := '0';
S_AXI_BREADY : in STD_LOGIC := '0';
w_last_c : in STD_LOGIC := '0';
bready_timeout_c : in STD_LOGIC := '0';
aw_ready_r : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_WR_EN : out STD_LOGIC;
addr_en_c : out STD_LOGIC;
incr_addr_c : out STD_LOGIC;
bvalid_c : out STD_LOGIC
);
end write_netlist;
architecture STRUCTURE of write_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
BEGIN
---------------------------------------------------------------------------
-- AXI LITE
---------------------------------------------------------------------------
gbeh_axi_lite_sm: IF (C_AXI_TYPE = 0 ) GENERATE
signal w_ready_r_7 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSignal_bvalid_c : STD_LOGIC;
signal NlwRenamedSignal_incr_addr_c : STD_LOGIC;
signal present_state_FSM_FFd3_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal present_state_FSM_FFd1_15 : STD_LOGIC;
signal present_state_FSM_FFd4_16 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd4_In1_21 : STD_LOGIC;
signal Mmux_aw_ready_c : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
S_AXI_WREADY <= w_ready_r_7;
S_AXI_BVALID <= NlwRenamedSignal_incr_addr_c;
S_AXI_WR_EN <= NlwRenamedSignal_bvalid_c;
incr_addr_c <= NlwRenamedSignal_incr_addr_c;
bvalid_c <= NlwRenamedSignal_bvalid_c;
NlwRenamedSignal_incr_addr_c <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_7
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_16
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_13
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_15
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000055554440"
)
port map (
I0 => S_AXI_WVALID,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => '0',
O => present_state_FSM_FFd3_In
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"0000000088880800"
)
port map (
I0 => S_AXI_AWVALID,
I1 => S_AXI_WVALID,
I2 => bready_timeout_c,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => present_state_FSM_FFd2_In
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAA2000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_WVALID,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => addr_en_c
);
Mmux_w_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"F5F07570F5F05500"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => w_ready_c
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd3_13,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd1_15,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_14,
I2 => present_state_FSM_FFd3_13,
I3 => '0',
I4 => '0',
I5 => '0',
O => NlwRenamedSignal_bvalid_c
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"2F0F27072F0F2200"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => present_state_FSM_FFd4_In1_21
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_In1_21,
I3 => '0',
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_aw_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"7535753575305500"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => S_AXI_WVALID,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => present_state_FSM_FFd2_14,
O => Mmux_aw_ready_c(0)
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => Mmux_aw_ready_c(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => aw_ready_c
);
END GENERATE gbeh_axi_lite_sm;
---------------------------------------------------------------------------
-- AXI FULL
---------------------------------------------------------------------------
gbeh_axi_full_sm: IF (C_AXI_TYPE = 1 ) GENERATE
signal w_ready_r_8 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSig_OI_bvalid_c : STD_LOGIC;
signal present_state_FSM_FFd1_16 : STD_LOGIC;
signal present_state_FSM_FFd4_17 : STD_LOGIC;
signal present_state_FSM_FFd3_18 : STD_LOGIC;
signal present_state_FSM_FFd2_19 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd2_In1_24 : STD_LOGIC;
signal present_state_FSM_FFd4_In1_25 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal N4 : STD_LOGIC;
begin
S_AXI_WREADY <= w_ready_r_8;
bvalid_c <= NlwRenamedSig_OI_bvalid_c;
S_AXI_BVALID <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_8
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_17
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_18
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_19
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_16
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000000005540"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd4_17,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd3_In
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"BF3FBB33AF0FAA00"
)
port map (
I0 => S_AXI_BREADY,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd1_16,
I4 => present_state_FSM_FFd4_17,
I5 => NlwRenamedSig_OI_bvalid_c,
O => aw_ready_c
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"AAAAAAAA20000000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_19,
I3 => S_AXI_WVALID,
I4 => w_last_c,
I5 => present_state_FSM_FFd4_17,
O => addr_en_c
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_19,
I2 => present_state_FSM_FFd3_18,
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_WR_EN
);
Mmux_incr_addr_c_0_1 : STATE_LOGIC
generic map(
INIT => X"0000000000002220"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => incr_addr_c
);
Mmux_aw_ready_c_0_11 : STATE_LOGIC
generic map(
INIT => X"0000000000008880"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => NlwRenamedSig_OI_bvalid_c
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"000000000000D5C0"
)
port map (
I0 => w_last_c,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd4_17,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd2_In1_24
);
present_state_FSM_FFd2_In2 : STATE_LOGIC
generic map(
INIT => X"FFFFAAAA08AAAAAA"
)
port map (
I0 => present_state_FSM_FFd2_19,
I1 => S_AXI_AWVALID,
I2 => bready_timeout_c,
I3 => w_last_c,
I4 => S_AXI_WVALID,
I5 => present_state_FSM_FFd2_In1_24,
O => present_state_FSM_FFd2_In
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"00C0004000C00000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => w_last_c,
I2 => S_AXI_WVALID,
I3 => bready_timeout_c,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => present_state_FSM_FFd4_In1_25
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88F8"
)
port map (
I0 => present_state_FSM_FFd1_16,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_17,
I3 => S_AXI_AWVALID,
I4 => present_state_FSM_FFd4_In1_25,
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_w_ready_c_0_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => w_last_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_w_ready_c_0_Q : STATE_LOGIC
generic map(
INIT => X"FABAFABAFAAAF000"
)
port map (
I0 => N2,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd4_17,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => w_ready_c
);
Mmux_aw_ready_c_0_11_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => bready_timeout_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => w_last_c,
I1 => N4,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => present_state_FSM_FFd1_16,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
END GENERATE gbeh_axi_full_sm;
end STRUCTURE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--AXI Behavioral Model entities
ENTITY blk_mem_axi_read_wrapper_beh is
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
port (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END blk_mem_axi_read_wrapper_beh;
architecture blk_mem_axi_read_wrapper_beh_arch of blk_mem_axi_read_wrapper_beh is
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_WRITE_WIDTH_A=8,0,
if_then_else((C_WRITE_WIDTH_A=16),1,
if_then_else((C_WRITE_WIDTH_A=32),2,
if_then_else((C_WRITE_WIDTH_A=64),3,
if_then_else((C_WRITE_WIDTH_A=128),4,
if_then_else((C_WRITE_WIDTH_A=256),5,0))))));
SIGNAL ar_id_r : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
SIGNAL addr_en_c : std_logic := '0';
SIGNAL rd_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL single_trans_c : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL mux_sel_c : std_logic := '0';
SIGNAL r_last_c : std_logic := '0';
SIGNAL r_last_int_c : std_logic := '0';
SIGNAL arlen_int_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL arlen_cntr : std_logic_vector(7 DOWNTO 0) := ONE;
SIGNAL arburst_int_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL arburst_int_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL araddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),C_AXI_ARADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL total_bytes : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
SIGNAL wrap_base_addr_r : integer := 0;
SIGNAL wrap_boundary_r : integer := 0;
SIGNAL arlen_int_c : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes_c : integer := 0;
SIGNAL wrap_base_addr_c : integer := 0;
SIGNAL wrap_boundary_c : integer := 0;
SIGNAL araddr_out : std_logic_vector(C_ADDRB_WIDTH-1 downto 0) := (OTHERS => '0');
COMPONENT read_netlist
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_INCR_ADDR : OUT std_logic := '0';
S_AXI_ADDR_EN : OUT std_logic := '0';
S_AXI_SINGLE_TRANS : OUT std_logic := '0';
S_AXI_MUX_SEL : OUT std_logic := '0';
S_AXI_R_LAST : OUT std_logic := '0';
S_AXI_R_LAST_INT : IN std_logic := '0';
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT read_netlist;
BEGIN
dec_alen_c <= incr_addr_c OR r_last_int_c;
axi_read_fsm : read_netlist
GENERIC MAP(
C_AXI_TYPE => 1,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
S_AXI_INCR_ADDR => incr_addr_c,
S_AXI_ADDR_EN => addr_en_c,
S_AXI_SINGLE_TRANS => single_trans_c,
S_AXI_MUX_SEL => mux_sel_c,
S_AXI_R_LAST => r_last_c,
S_AXI_R_LAST_INT => r_last_int_c,
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN => rd_en_c
);
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(arlen_int_r)+1);
wrap_base_addr_r <= (conv_integer(araddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary_r <= wrap_base_addr_r+total_bytes;
---- combinatorial from interface
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARSIZE,"000"));
arlen_int_c <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
total_bytes_c <= conv_integer(num_of_bytes_c)*(conv_integer(arlen_int_c)+1);
wrap_base_addr_c <= (conv_integer(S_AXI_ARADDR)/if_then_else(total_bytes_c=0,1,total_bytes_c))*(total_bytes_c);
wrap_boundary_c <= wrap_base_addr_c+total_bytes_c;
arburst_int_c <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARBURST,"01");
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
araddr_reg <= (OTHERS => '0');
arburst_int_r <= (OTHERS => '0');
num_of_bytes_r <= 0;
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (incr_addr_c = '1' AND addr_en_c = '1' AND single_trans_c = '0') THEN
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
IF (arburst_int_c = "10") THEN
IF(conv_integer(S_AXI_ARADDR) = (wrap_boundary_c-num_of_bytes_c)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_c,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (arburst_int_c = "01" OR arburst_int_c = "11") THEN
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (addr_en_c = '1') THEN
araddr_reg <= S_AXI_ARADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
ELSIF (incr_addr_c = '1') THEN
IF (arburst_int_r = "10") THEN
IF(conv_integer(araddr_reg) = (wrap_boundary_r-num_of_bytes_r)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_r,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
ELSIF (arburst_int_r = "01" OR arburst_int_r = "11") THEN
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
araddr_out <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),araddr_reg(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),araddr_reg);
--------------------------------------------------------------------------
-- Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
--------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF S_ARESETN = '1' THEN
arlen_cntr <= ONE;
arlen_int_r <= (OTHERS => '0');
ELSIF S_ACLK'event AND S_ACLK = '1' THEN
IF (addr_en_c = '1' AND dec_alen_c = '1' AND single_trans_c = '0') THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= S_AXI_ARLEN - ONE AFTER FLOP_DELAY;
ELSIF addr_en_c = '1' THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
ELSIF dec_alen_c = '1' THEN
arlen_cntr <= arlen_cntr - ONE AFTER FLOP_DELAY;
ELSE
arlen_cntr <= arlen_cntr AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
r_last_int_c <= '1' WHEN (arlen_cntr = "00000000" AND S_AXI_RREADY = '1') ELSE '0' ;
--------------------------------------------------------------------------
-- AXI FULL FSM
-- Mux Selection of ARADDR
-- ARADDR is driven out from the read fsm based on the mux_sel_c
-- Based on mux_sel either ARADDR is given out or the latched ARADDR is
-- given out to BRAM
--------------------------------------------------------------------------
P_araddr_mux: PROCESS (mux_sel_c,S_AXI_ARADDR,araddr_out)
BEGIN
IF (mux_sel_c = '0') THEN
S_AXI_ARADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARADDR(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),S_AXI_ARADDR);
ELSE
S_AXI_ARADDR_OUT <= araddr_out;
END IF;
END PROCESS P_araddr_mux;
--------------------------------------------------------------------------
-- Assign output signals - AXI FULL FSM
--------------------------------------------------------------------------
S_AXI_RD_EN <= rd_en_c;
grid: IF (C_HAS_AXI_ID = 1) GENERATE
P_rid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
S_AXI_RID <= (OTHERS => '0');
ar_id_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
IF (addr_en_c = '1' AND rd_en_c = '1') THEN
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
ELSIF (addr_en_c = '1' AND rd_en_c = '0') THEN
ar_id_r <= S_AXI_ARID;
ELSIF (rd_en_c = '1') THEN
S_AXI_RID <= ar_id_r;
END IF;
END IF;
END PROCESS P_rid_gen;
END GENERATE grid;
END blk_mem_axi_read_wrapper_beh_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity read_netlist is
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_R_LAST_INT : in STD_LOGIC := '0';
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_ARVALID : in STD_LOGIC := '0';
S_AXI_RREADY : in STD_LOGIC := '0';
S_AXI_INCR_ADDR : out STD_LOGIC;
S_AXI_ADDR_EN : out STD_LOGIC;
S_AXI_SINGLE_TRANS : out STD_LOGIC;
S_AXI_MUX_SEL : out STD_LOGIC;
S_AXI_R_LAST : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RLAST : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RD_EN : out STD_LOGIC;
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end read_netlist;
architecture STRUCTURE of read_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
signal present_state_FSM_FFd1_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_r_15 : STD_LOGIC;
signal gaxi_full_sm_ar_ready_r_16 : STD_LOGIC;
signal gaxi_full_sm_r_last_r_17 : STD_LOGIC;
signal NlwRenamedSig_OI_gaxi_full_sm_r_valid_r : STD_LOGIC;
signal gaxi_full_sm_r_valid_c : STD_LOGIC;
signal S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o : STD_LOGIC;
signal gaxi_full_sm_ar_ready_c : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_c : STD_LOGIC;
signal NlwRenamedSig_OI_S_AXI_R_LAST : STD_LOGIC;
signal S_AXI_ARLEN_7_GND_8_o_equal_1_o : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal Mmux_S_AXI_R_LAST13 : STD_LOGIC;
signal N01 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal Mmux_gaxi_full_sm_ar_ready_c11 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N8 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N13 : STD_LOGIC;
begin
S_AXI_R_LAST <= NlwRenamedSig_OI_S_AXI_R_LAST;
S_AXI_ARREADY <= gaxi_full_sm_ar_ready_r_16;
S_AXI_RLAST <= gaxi_full_sm_r_last_r_17;
S_AXI_RVALID <= NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
gaxi_full_sm_outstanding_read_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_outstanding_read_c,
Q => gaxi_full_sm_outstanding_read_r_15
);
gaxi_full_sm_r_valid_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => gaxi_full_sm_r_valid_c,
Q => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r
);
gaxi_full_sm_ar_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_ar_ready_c,
Q => gaxi_full_sm_ar_ready_r_16
);
gaxi_full_sm_r_last_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => NlwRenamedSig_OI_S_AXI_R_LAST,
Q => gaxi_full_sm_r_last_r_17
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_13
);
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 : STATE_LOGIC
generic map(
INIT => X"000000000000000B"
)
port map (
I0 => S_AXI_RREADY,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o
);
Mmux_S_AXI_SINGLE_TRANS11 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_SINGLE_TRANS
);
Mmux_S_AXI_ADDR_EN11 : STATE_LOGIC
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_ADDR_EN
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"ECEE2022EEEE2022"
)
port map (
I0 => S_AXI_ARVALID,
I1 => present_state_FSM_FFd1_13,
I2 => S_AXI_RREADY,
I3 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I4 => present_state_FSM_FFd2_14,
I5 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
O => present_state_FSM_FFd2_In
);
Mmux_S_AXI_R_LAST131 : STATE_LOGIC
generic map(
INIT => X"0000000044440444"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_RREADY,
I5 => '0',
O => Mmux_S_AXI_R_LAST13
);
Mmux_S_AXI_INCR_ADDR11 : STATE_LOGIC
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => S_AXI_R_LAST_INT,
I1 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => Mmux_S_AXI_R_LAST13,
O => S_AXI_INCR_ADDR
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000FE"
)
port map (
I0 => S_AXI_ARLEN(2),
I1 => S_AXI_ARLEN(1),
I2 => S_AXI_ARLEN(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => N01
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q : STATE_LOGIC
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => S_AXI_ARLEN(7),
I1 => S_AXI_ARLEN(6),
I2 => S_AXI_ARLEN(5),
I3 => S_AXI_ARLEN(4),
I4 => S_AXI_ARLEN(3),
I5 => N01,
O => S_AXI_ARLEN_7_GND_8_o_equal_1_o
);
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_gaxi_full_sm_outstanding_read_c1 : STATE_LOGIC
generic map(
INIT => X"0020000002200200"
)
port map (
I0 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd1_13,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => N2,
O => gaxi_full_sm_outstanding_read_c
);
Mmux_gaxi_full_sm_ar_ready_c12 : STATE_LOGIC
generic map(
INIT => X"0000000000004555"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => '0',
I5 => '0',
O => Mmux_gaxi_full_sm_ar_ready_c11
);
Mmux_S_AXI_R_LAST11_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000EF"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
Mmux_S_AXI_R_LAST11 : STATE_LOGIC
generic map(
INIT => X"FCAAFC0A00AA000A"
)
port map (
I0 => S_AXI_ARVALID,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => N4,
I5 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
O => gaxi_full_sm_r_valid_c
);
S_AXI_MUX_SEL1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAAAA08"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => '0',
O => S_AXI_MUX_SEL
);
Mmux_S_AXI_RD_EN11 : STATE_LOGIC
generic map(
INIT => X"F3F3F755A2A2A200"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => gaxi_full_sm_outstanding_read_r_15,
I4 => present_state_FSM_FFd2_14,
I5 => S_AXI_ARVALID,
O => S_AXI_RD_EN
);
present_state_FSM_FFd1_In3 : beh_muxf7
port map (
I0 => N8,
I1 => N9,
S => present_state_FSM_FFd1_13,
O => present_state_FSM_FFd1_In
);
present_state_FSM_FFd1_In3_F : STATE_LOGIC
generic map(
INIT => X"000000005410F4F0"
)
port map (
I0 => S_AXI_RREADY,
I1 => present_state_FSM_FFd2_14,
I2 => S_AXI_ARVALID,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => '0',
O => N8
);
present_state_FSM_FFd1_In3_G : STATE_LOGIC
generic map(
INIT => X"0000000072FF7272"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N9
);
Mmux_gaxi_full_sm_ar_ready_c14 : beh_muxf7
port map (
I0 => N10,
I1 => N11,
S => present_state_FSM_FFd1_13,
O => gaxi_full_sm_ar_ready_c
);
Mmux_gaxi_full_sm_ar_ready_c14_F : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88A8"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => Mmux_gaxi_full_sm_ar_ready_c11,
I5 => '0',
O => N10
);
Mmux_gaxi_full_sm_ar_ready_c14_G : STATE_LOGIC
generic map(
INIT => X"000000008D008D8D"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N11
);
Mmux_S_AXI_R_LAST1 : beh_muxf7
port map (
I0 => N12,
I1 => N13,
S => present_state_FSM_FFd1_13,
O => NlwRenamedSig_OI_S_AXI_R_LAST
);
Mmux_S_AXI_R_LAST1_F : STATE_LOGIC
generic map(
INIT => X"0000000088088888"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N12
);
Mmux_S_AXI_R_LAST1_G : STATE_LOGIC
generic map(
INIT => X"00000000E400E4E4"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => S_AXI_R_LAST_INT,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N13
);
end STRUCTURE;
-------------------------------------------------------------------------------
-- Output Register Stage Entity
--
-- This module builds the output register stages of the memory. This module is
-- instantiated in the main memory module (blk_mem_gen_v8_3_1) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_output_stage IS
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_output_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6" and "virtex6l".
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
-- C_HAS_RST : Determines the presence of the RST port
-- C_RSTRAM : Determines if special reset behavior is used
-- C_RST_PRIORITY : Determines the priority between CE and SR
-- C_INIT_VAL : Initialization value
-- C_HAS_EN : Determines the presence of the EN port
-- C_HAS_REGCE : Determines the presence of the REGCE port
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
-- of the RAM primitive
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- NUM_STAGES : Determines the number of output stages
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE output_stage_behavioral OF blk_mem_gen_v8_3_1_output_stage IS
--*******************************************************
-- Functions used in the output stage ARCHITECTURE
--*******************************************************
-- Calculate num_reg_stages
FUNCTION get_num_reg_stages(NUM_STAGES: INTEGER) RETURN INTEGER IS
VARIABLE num_reg_stages : INTEGER := 0;
BEGIN
IF (NUM_STAGES = 0) THEN
num_reg_stages := 0;
ELSE
num_reg_stages := NUM_STAGES - 1;
END IF;
RETURN num_reg_stages;
END get_num_reg_stages;
-- Check if the INTEGER is zero or non-zero
FUNCTION int_to_bit(input: INTEGER) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = 0) THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END int_to_bit;
-- Constants
CONSTANT HAS_EN : STD_LOGIC := int_to_bit(C_HAS_EN);
CONSTANT HAS_REGCE : STD_LOGIC := int_to_bit(C_HAS_REGCE);
CONSTANT HAS_RST : STD_LOGIC := int_to_bit(C_HAS_RST);
CONSTANT REG_STAGES : INTEGER := get_num_reg_stages(NUM_STAGES);
-- Pipeline array
TYPE reg_data_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
TYPE reg_ecc_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC;
TYPE reg_eccaddr_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
CONSTANT REG_INIT : reg_data_array := (OTHERS => init_val);
SIGNAL out_regs : reg_data_array := REG_INIT;
SIGNAL sbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL dbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL rdaddrecc_regs: reg_eccaddr_array := (OTHERS => (OTHERS => '0'));
-- Internal signals
SIGNAL en_i : STD_LOGIC;
SIGNAL regce_i : STD_LOGIC;
SIGNAL rst_i : STD_LOGIC;
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := init_val;
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL DIN : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL RDADDRECC_IN : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ;
SIGNAL SBITERR_IN : STD_LOGIC := '0';
SIGNAL DBITERR_IN : STD_LOGIC := '0';
BEGIN
--***********************************************************************
-- Assign internal signals. This effectively wires off optional inputs.
--***********************************************************************
-- Internal enable for output registers is tied to user EN or '1' depending
-- on parameters
en_i <= EN OR (NOT HAS_EN);
-- Internal register enable for output registers is tied to user REGCE, EN
-- or '1' depending on parameters
regce_i <= (HAS_REGCE AND REGCE)
OR ((NOT HAS_REGCE) AND en_i);
-- Internal SRR is tied to user RST or '0' depending on parameters
rst_i <= RST AND HAS_RST;
--***************************************************************************
-- NUM_STAGES = 0 (No output registers. RAM only)
--***************************************************************************
zero_stages: IF (NUM_STAGES = 0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE zero_stages;
NO_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 0) GENERATE
DIN <= DIN_I;
RDADDRECC_IN <= RDADDRECC_IN_I;
SBITERR_IN <= SBITERR_IN_I;
DBITERR_IN <= DBITERR_IN_I;
END GENERATE NO_ECC_PIPE_REG;
WITH_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(ECCPIPECE = '1') THEN
DIN <= DIN_I AFTER FLOP_DELAY;
RDADDRECC_IN <= RDADDRECC_IN_I AFTER FLOP_DELAY;
SBITERR_IN <= SBITERR_IN_I AFTER FLOP_DELAY;
DBITERR_IN <= DBITERR_IN_I AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS;
END GENERATE WITH_ECC_PIPE_REG;
--***************************************************************************
-- NUM_STAGES = 1
-- (Mem Output Reg only or Mux Output Reg only)
--***************************************************************************
-- Possible valid combinations:
-- Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
-- +-----------------------------------------+
-- | C_RSTRAM_* | Reset Behavior |
-- +----------------+------------------------+
-- | 0 | Normal Behavior |
-- +----------------+------------------------+
-- | 1 | Special Behavior |
-- +----------------+------------------------+
--
-- Normal = REGCE gates reset, as in the case of all Virtex families and all
-- spartan families with the exception of S3ADSP and S6.
-- Special = EN gates reset, as in the case of S3ADSP and S6.
one_stage_norm: IF (NUM_STAGES = 1 AND
(C_RSTRAM=0 OR (C_RSTRAM=1 AND (C_XDEVICEFAMILY/="spartan3adsp" AND C_XDEVICEFAMILY/="aspartan3adsp")) OR
C_HAS_MEM_OUTPUT_REGS=0 OR C_HAS_RST=0)) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i = '1' AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
END IF;--CLK
END PROCESS;
END GENERATE one_stage_norm;
-- Special Reset Behavior for S6 and S3ADSP
one_stage_splbhv: IF (NUM_STAGES=1 AND C_RSTRAM=1 AND (C_XDEVICEFAMILY ="spartan3adsp" OR C_XDEVICEFAMILY ="aspartan3adsp"))
GENERATE
DOUT <= dout_i;
SBITERR <= '0';
DBITERR <= '0';
RDADDRECC <= (OTHERS => '0');
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (rst_i='1' AND en_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
ELSIF (regce_i='1' AND rst_i/='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE one_stage_splbhv;
--****************************************************************************
-- NUM_STAGES > 1
-- Mem Output Reg + Mux Output Reg
-- or
-- Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
-- or
-- Mux Pipeline Stages (>0) + Mux Output Reg
--****************************************************************************
multi_stage: IF (NUM_STAGES > 1) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i='1'AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
IF (en_i='1') THEN
-- Shift the data through the output stages
FOR i IN 1 TO REG_STAGES-1 LOOP
out_regs(i) <= out_regs(i-1) AFTER FLOP_DELAY;
sbiterr_regs(i) <= sbiterr_regs(i-1) AFTER FLOP_DELAY;
dbiterr_regs(i) <= dbiterr_regs(i-1) AFTER FLOP_DELAY;
rdaddrecc_regs(i) <= rdaddrecc_regs(i-1) AFTER FLOP_DELAY;
END LOOP;
out_regs(0) <= DIN;
sbiterr_regs(0) <= SBITERR_IN;
dbiterr_regs(0) <= DBITERR_IN;
rdaddrecc_regs(0) <= RDADDRECC_IN;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE multi_stage;
END output_stage_behavioral;
-------------------------------------------------------------------------------
-- SoftECC Output Register Stage Entity
-- This module builds the softecc output register stages. This module is
-- instantiated in the memory module (blk_mem_gen_v8_3_1_mem_module) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ;
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- of the RAM primitive
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE softecc_output_reg_stage_behavioral OF blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
-- Internal signals
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
--***************************************************************************
-- NO OUTPUT STAGES
--***************************************************************************
no_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE no_output_stage;
--****************************************************************************
-- WITH OUTPUT STAGE
--****************************************************************************
has_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END PROCESS;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
END GENERATE has_output_stage;
END softecc_output_reg_stage_behavioral;
--******************************************************************************
-- Main Memory module
--
-- This module is the behavioral model which implements the RAM
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
ENTITY blk_mem_gen_v8_3_1_mem_module IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_mem_module;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE mem_module_behavioral OF blk_mem_gen_v8_3_1_mem_module IS
--****************************************
-- min/max constant functions
--****************************************
-- get_max
----------
function SLV_TO_INT(SLV: in std_logic_vector
) return integer is
variable int : integer;
begin
int := 0;
for i in SLV'high downto SLV'low loop
int := int * 2;
if SLV(i) = '1' then
int := int + 1;
end if;
end loop;
return int;
end;
FUNCTION get_max(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a > b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-- get_min
----------
FUNCTION get_min(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
--***************************************************************
-- convert write_mode from STRING type for use in case statement
--***************************************************************
FUNCTION write_mode_to_vector(mode: STRING) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF (mode = "NO_CHANGE") THEN
RETURN "10";
ELSIF (mode = "READ_FIRST") THEN
RETURN "01";
ELSE
RETURN "00"; -- WRITE_FIRST
END IF;
END FUNCTION;
--***************************************************************
-- convert hex STRING to STD_LOGIC_VECTOR
--***************************************************************
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
--***************************************************************
-- locally derived constants to determine memory shape
--***************************************************************
CONSTANT MIN_WIDTH_A : INTEGER := get_min(C_WRITE_WIDTH_A, C_READ_WIDTH_A);
CONSTANT MIN_WIDTH_B : INTEGER := get_min(C_WRITE_WIDTH_B,C_READ_WIDTH_B);
CONSTANT MIN_WIDTH : INTEGER := get_min(MIN_WIDTH_A, MIN_WIDTH_B);
CONSTANT MAX_DEPTH_A : INTEGER := get_max(C_WRITE_DEPTH_A, C_READ_DEPTH_A);
CONSTANT MAX_DEPTH_B : INTEGER := get_max(C_WRITE_DEPTH_B, C_READ_DEPTH_B);
CONSTANT MAX_DEPTH : INTEGER := get_max(MAX_DEPTH_A, MAX_DEPTH_B);
TYPE int_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF std_logic_vector(C_WRITE_WIDTH_A-1 DOWNTO 0);
TYPE mem_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC_VECTOR(MIN_WIDTH-1 DOWNTO 0);
TYPE ecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
TYPE softecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
--***************************************************************
-- memory initialization function
--***************************************************************
IMPURE FUNCTION init_memory(DEFAULT_DATA :
STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
write_width_a : INTEGER;
depth : INTEGER;
width : INTEGER)
RETURN mem_array IS
VARIABLE init_return : mem_array := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(write_width_a-1 DOWNTO 0);
VARIABLE int_mem_vector : int_array:= (OTHERS => (OTHERS => '0'));
VARIABLE file_buffer : LINE;
VARIABLE i : INTEGER := 0;
VARIABLE j : INTEGER;
VARIABLE k : INTEGER;
VARIABLE ignore_line : BOOLEAN := false;
VARIABLE good_data : BOOLEAN := false;
VARIABLE char_tmp : CHARACTER;
VARIABLE index : INTEGER;
variable init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable data : std_logic_vector(255 downto 0) := (others => '0');
variable inside_init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable k_slv : std_logic_vector(31 downto 0) := (others => '0');
variable i_slv : std_logic_vector(31 downto 0) := (others => '0');
VARIABLE disp_line : line := null;
variable open_status : file_open_status;
variable input_initf_tmp : mem_array ;
variable input_initf : mem_array := (others => (others => '0'));
file int_infile : text;
variable data_line, data_line_tmp, out_data_line : line;
variable slv_width : integer;
VARIABLE d_l : LINE;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
index := 0;
FOR i IN 0 TO depth-1 LOOP
FOR j IN 0 TO width-1 LOOP
init_return(i)(j) := DEFAULT_DATA(index);
index := (index + 1) MOD C_WRITE_WIDTH_A;
END LOOP;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, file_buffer);
read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO write_width_a-1 LOOP
IF (j MOD width = 0 AND j /= 0) THEN
i := i + 1;
END IF;
init_return(i)(j MOD width) := bit_to_sl(mem_vector(j));
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
--Display output message indicating that the behavioral model is done
--initializing
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator data initialization complete." SEVERITY NOTE;
if (C_USE_BRAM_BLOCK = 1) then
--Display output message indicating that the behavioral model is being
--initialized
-- Read in the .mem file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_INIT_FILE /= "NONE") then
file_open(open_status, int_infile, C_INIT_FILE, read_mode);
while not endfile(int_infile) loop
readline(int_infile, data_line);
while (data_line /= null and data_line'length > 0) loop
if (data_line(data_line'low to data_line'low + 1) = "//") then
deallocate(data_line);
elsif ((data_line(data_line'low to data_line'low + 1) = "/*") and (data_line(data_line'high-1 to data_line'high) = "*/")) then
deallocate(data_line);
elsif (data_line(data_line'low to data_line'low + 1) = "/*") then
deallocate(data_line);
ignore_line := true;
elsif (ignore_line = true and data_line(data_line'high-1 to data_line'high) = "*/") then
deallocate(data_line);
ignore_line := false;
elsif (ignore_line = false and data_line(data_line'low) = '@') then
read(data_line, char_tmp);
hread(data_line, init_addr_slv, good_data);
i := SLV_TO_INT(init_addr_slv);
elsif (ignore_line = false) then
hread(data_line, input_initf_tmp(i), good_data);
init_return(i)(write_width_a - 1 downto 0) := input_initf_tmp(i)(write_width_a - 1 downto 0);
if (good_data = true) then
i := i + 1;
end if;
else
deallocate(data_line);
end if;
end loop;
end loop;
file_close(int_infile);
END IF;
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- memory type constants
--***************************************************************
CONSTANT MEM_TYPE_SP_RAM : INTEGER := 0;
CONSTANT MEM_TYPE_SDP_RAM : INTEGER := 1;
CONSTANT MEM_TYPE_TDP_RAM : INTEGER := 2;
CONSTANT MEM_TYPE_SP_ROM : INTEGER := 3;
CONSTANT MEM_TYPE_DP_ROM : INTEGER := 4;
--***************************************************************
-- memory configuration constant functions
--***************************************************************
--get_single_port
-----------------
FUNCTION get_single_port(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_RAM OR mem_type=MEM_TYPE_SP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_single_port;
--get_is_rom
--------------
FUNCTION get_is_rom(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_ROM OR mem_type=MEM_TYPE_DP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_is_rom;
--get_has_a_write
------------------
FUNCTION get_has_a_write(IS_ROM : INTEGER) RETURN INTEGER IS
BEGIN
IF (IS_ROM=0) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_a_write;
--get_has_b_write
------------------
FUNCTION get_has_b_write(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_TDP_RAM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_write;
--get_has_a_read
------------------
FUNCTION get_has_a_read(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SDP_RAM) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_a_read;
--get_has_b_read
------------------
FUNCTION get_has_b_read(SINGLE_PORT : INTEGER) RETURN INTEGER IS
BEGIN
IF (SINGLE_PORT=1) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_b_read;
--get_has_b_port
------------------
FUNCTION get_has_b_port(HAS_B_READ : INTEGER;
HAS_B_WRITE : INTEGER)
RETURN INTEGER IS
BEGIN
IF (HAS_B_READ=1 OR HAS_B_WRITE=1) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_port;
--get_num_output_stages
-----------------------
FUNCTION get_num_output_stages(has_mem_output_regs : INTEGER;
has_mux_output_regs : INTEGER;
mux_pipeline_stages : INTEGER)
RETURN INTEGER IS
VARIABLE actual_mux_pipeline_stages : INTEGER;
BEGIN
-- Mux pipeline stages can be non-zero only when there is a mux
-- output register.
IF (has_mux_output_regs=1) THEN
actual_mux_pipeline_stages := mux_pipeline_stages;
ELSE
actual_mux_pipeline_stages := 0;
END IF;
RETURN has_mem_output_regs+actual_mux_pipeline_stages+has_mux_output_regs;
END get_num_output_stages;
--***************************************************************************
-- Component declaration of the VARIABLE depth output register stage
--***************************************************************************
COMPONENT blk_mem_gen_v8_3_1_output_stage
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
EN : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
ECCPIPECE : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_output_stage;
COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************************************
-- locally derived constants to assist memory access
--******************************************************
CONSTANT WRITE_WIDTH_RATIO_A : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_A : INTEGER := C_READ_WIDTH_A/MIN_WIDTH;
CONSTANT WRITE_WIDTH_RATIO_B : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_B : INTEGER := C_READ_WIDTH_B/MIN_WIDTH;
--******************************************************
-- To modify the LSBs of the 'wider' data to the actual
-- address value
--******************************************************
CONSTANT WRITE_ADDR_A_DIV : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH_A;
CONSTANT READ_ADDR_A_DIV : INTEGER := C_READ_WIDTH_A/MIN_WIDTH_A;
CONSTANT WRITE_ADDR_B_DIV : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH_B;
CONSTANT READ_ADDR_B_DIV : INTEGER := C_READ_WIDTH_B/MIN_WIDTH_B;
--******************************************************
-- FUNCTION : log2roundup
--******************************************************
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
--******************************************************
-- Other constants and signals
--******************************************************
CONSTANT COLL_DELAY : TIME := 100 ps;
-- default data vector
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_DEFAULT_DATA,
C_WRITE_WIDTH_A);
CONSTANT CHKBIT_WIDTH : INTEGER := if_then_else(C_WRITE_WIDTH_A>57,8,if_then_else(C_WRITE_WIDTH_A>26,7,if_then_else(C_WRITE_WIDTH_A>11,6,if_then_else(C_WRITE_WIDTH_A>4,5,if_then_else(C_WRITE_WIDTH_A<5,4,0)))));
-- the init memory SIGNAL
SIGNAL memory_i : mem_array;
SIGNAL doublebit_error_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0);
SIGNAL current_contents_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
-- write mode constants
CONSTANT WRITE_MODE_A : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_A);
CONSTANT WRITE_MODE_B : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_B);
CONSTANT WRITE_MODES : STD_LOGIC_VECTOR(3 DOWNTO 0) :=
WRITE_MODE_A & WRITE_MODE_B;
-- reset values
CONSTANT INITA_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITA_VAL,
C_READ_WIDTH_A);
CONSTANT INITB_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITB_VAL,
C_READ_WIDTH_B);
-- memory output 'latches'
SIGNAL memory_out_a : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0) :=
INITA_VAL;
SIGNAL memory_out_b : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) :=
INITB_VAL;
SIGNAL sbiterr_in : STD_LOGIC := '0';
SIGNAL sbiterr_sdp : STD_LOGIC := '0';
SIGNAL dbiterr_in : STD_LOGIC := '0';
SIGNAL dbiterr_sdp : STD_LOGIC := '0';
SIGNAL rdaddrecc_in : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_sdp : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL doutb_i : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i : STD_LOGIC := '0';
SIGNAL dbiterr_i : STD_LOGIC := '0';
-- memory configuration constants
-----------------------------------------------
CONSTANT SINGLE_PORT : INTEGER := get_single_port(C_MEM_TYPE);
CONSTANT IS_ROM : INTEGER := get_is_rom(C_MEM_TYPE);
CONSTANT HAS_A_WRITE : INTEGER := get_has_a_write(IS_ROM);
CONSTANT HAS_B_WRITE : INTEGER := get_has_b_write(C_MEM_TYPE);
CONSTANT HAS_A_READ : INTEGER := get_has_a_read(C_MEM_TYPE);
CONSTANT HAS_B_READ : INTEGER := get_has_b_read(SINGLE_PORT);
CONSTANT HAS_B_PORT : INTEGER := get_has_b_port(HAS_B_READ, HAS_B_WRITE);
CONSTANT NUM_OUTPUT_STAGES_A : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_A,
C_MUX_PIPELINE_STAGES);
CONSTANT NUM_OUTPUT_STAGES_B : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES);
CONSTANT WEA0 : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT WEB0 : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-----------------------------------------------------------------------------
-- DEBUG CONTROL
-- DEBUG=0 : Debug output OFF
-- DEBUG=1 : Some debug info printed
-----------------------------------------------------------------------------
CONSTANT DEBUG : INTEGER := 0;
-- internal signals
-----------------------------------------------
SIGNAL ena_i : STD_LOGIC;
SIGNAL enb_i : STD_LOGIC;
SIGNAL reseta_i : STD_LOGIC;
SIGNAL resetb_i : STD_LOGIC;
SIGNAL wea_i : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL web_i : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL rea_i : STD_LOGIC;
SIGNAL reb_i : STD_LOGIC;
SIGNAL message_complete : BOOLEAN := false;
SIGNAL rsta_outp_stage : STD_LOGIC := '0';
SIGNAL rstb_outp_stage : STD_LOGIC := '0';
--*********************************************************
--FUNCTION : Collision check
--*********************************************************
FUNCTION collision_check (addr_a :
STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
iswrite_a : BOOLEAN;
addr_b :
STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
iswrite_b : BOOLEAN)
RETURN BOOLEAN IS
VARIABLE c_aw_bw : INTEGER;
VARIABLE c_aw_br : INTEGER;
VARIABLE c_ar_bw : INTEGER;
VARIABLE write_addr_a_width : INTEGER;
VARIABLE read_addr_a_width : INTEGER;
VARIABLE write_addr_b_width : INTEGER;
VARIABLE read_addr_b_width : INTEGER;
BEGIN
c_aw_bw := 0;
c_aw_br := 0;
c_ar_bw := 0;
-- Determine the effective address widths FOR each of the 4 ports
write_addr_a_width := C_ADDRA_WIDTH-log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width := C_ADDRA_WIDTH-log2roundup(READ_ADDR_A_DIV);
write_addr_b_width := C_ADDRB_WIDTH-log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width := C_ADDRB_WIDTH-log2roundup(READ_ADDR_B_DIV);
--Look FOR a write-write collision. In order FOR a write-write
--collision to exist, both ports must have a write transaction.
IF (iswrite_a AND iswrite_b) THEN
IF (write_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_a and iswrite_b
--If the B port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_a) THEN
IF (write_addr_a_width > read_addr_b_width) THEN
--read_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_b_width
--Once both are scaled to read_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
END IF; --width
END IF; --iswrite_a
--If the A port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_b) THEN
IF (read_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
ELSE
--read_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_a_width
--Once both are scaled to read_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_b
RETURN (c_aw_bw=1 OR c_aw_br=1 OR c_ar_bw=1);
END FUNCTION collision_check;
BEGIN -- Architecture
-----------------------------------------------------------------------------
-- SOFTECC and ECC SBITERR/DBITERR Outputs
-- The ECC Behavior is modeled by the behavioral models only for Virtex-6.
-- The SOFTECC Behavior is modeled by the behavioral models for Spartan-6.
-- For Virtex-5, these outputs will be tied to 0.
-----------------------------------------------------------------------------
SBITERR <= sbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_sdp WHEN (((C_FAMILY="virtex7") AND C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
-----------------------------------------------
-- This effectively wires off optional inputs
-----------------------------------------------
ena_i <= ENA WHEN (C_HAS_ENA=1) ELSE '1';
enb_i <= ENB WHEN (C_HAS_ENB=1 AND HAS_B_PORT=1) ELSE '1';
-- We are doing an "AND" operation of WEA and ENA and passing to Enbale pin of BRAM when built-in ECC is enabled,
-- what this means is that the write operation happens only when both WEA and ENA are high.
wea_i <= WEA WHEN (HAS_A_WRITE=1 AND ena_i='1') ELSE WEA0;
-- wea_i <= (OTHERS => '1') WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=1 AND ENA = '1') ELSE -- Use_ENA_pin
-- WEA WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=0) ELSE -- Always_enabled
-- WEA WHEN (HAS_A_WRITE=1 AND ena_i='1' AND C_USE_ECC = 0) ELSE
-- WEA0;
web_i <= WEB WHEN (HAS_B_WRITE=1 AND enb_i='1') ELSE WEB0;
rea_i <= ena_i WHEN (HAS_A_READ=1) ELSE '0';
reb_i <= enb_i WHEN (HAS_B_READ=1) ELSE '0';
-- these signals reset the memory latches
-- For the special reset behaviors in some of the families, the C_RSTRAM
-- attribute of the corresponding port is used to indicate if the latch is
-- reset or not.
reseta_i <= RSTA WHEN
((C_HAS_RSTA=1 AND NUM_OUTPUT_STAGES_A=0) OR
(C_HAS_RSTA=1 AND C_RSTRAM_A=1))
ELSE '0';
resetb_i <= RSTB WHEN
((C_HAS_RSTB=1 AND NUM_OUTPUT_STAGES_B=0) OR
(C_HAS_RSTB=1 AND C_RSTRAM_B=1) )
ELSE '0';
--***************************************************************************
-- This is the main PROCESS which includes the memory VARIABLE and the read
-- and write procedures. It also schedules read and write operations
--***************************************************************************
PROCESS (CLKA, CLKB,rea_i,reb_i,reseta_i,resetb_i)
-- Initialize the init memory array
------------------------------------
VARIABLE memory : mem_array := init_memory(DEFAULT_DATA,
C_WRITE_WIDTH_A,
MAX_DEPTH,
MIN_WIDTH);
-- Initialize the mem memory array
------------------------------------
VARIABLE softecc_sbiterr_arr : softecc_err_array;
VARIABLE softecc_dbiterr_arr : softecc_err_array;
VARIABLE sbiterr_arr : ecc_err_array;
VARIABLE dbiterr_arr : ecc_err_array;
CONSTANT doublebit_lsb : STD_LOGIC_VECTOR (1 DOWNTO 0):="11";
CONSTANT doublebit_msb : STD_LOGIC_VECTOR (C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 DOWNTO 0):= (OTHERS => '0');
VARIABLE doublebit_error : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0) := doublebit_msb & doublebit_lsb ;
VARIABLE current_contents_var : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
--***********************************
-- procedures to access the memory
--***********************************
-- write_a
----------
PROCEDURE write_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
inj_sbiterr : IN STD_LOGIC;
inj_dbiterr : IN STD_LOGIC) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
VARIABLE message : LINE;
VARIABLE errbit_current_contents : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
-- Block Memory Generator non-cycle-accurate message
ASSERT (message_complete) REPORT "Block Memory Generator module is using a behavioral model FOR simulation which will not precisely model memory collision behavior."
SEVERITY NOTE;
message_complete <= true;
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_A_DIV);
IF (address_i >= C_WRITE_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range FOR A Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEA = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_A + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEA_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Insert double bit errors:
IF (C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
current_contents(0) := NOT(current_contents(0));
current_contents(1) := NOT(current_contents(1));
--current_contents(0) := NOT(current_contents(30));
--current_contents(1) := NOT(current_contents(62));
END IF;
END IF;
-- Insert double bit errors:
IF (C_USE_SOFTECC=1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 downto 2) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 downto 0);
doublebit_error(0) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1);
doublebit_error(1) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-2);
current_contents := current_contents XOR doublebit_error(C_WRITE_WIDTH_A-1 DOWNTO 0);
END IF;
END IF;
IF(DEBUG=1) THEN
current_contents_var := current_contents; --for debugging current
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_A + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
-- Store address at which error is injected:
IF ((C_FAMILY = "virtex7") AND C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
sbiterr_arr(address_i) := '1';
ELSE
sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
dbiterr_arr(address_i) := '1';
ELSE
dbiterr_arr(address_i) := '0';
END IF;
END IF;
-- Store address at which softecc error is injected:
IF (C_USE_SOFTECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
softecc_sbiterr_arr(address_i) := '1';
ELSE
softecc_sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
softecc_dbiterr_arr(address_i) := '1';
ELSE
softecc_dbiterr_arr(address_i) := '0';
END IF;
END IF;
END IF;
END PROCEDURE;
-- write_b
----------
PROCEDURE write_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_B_DIV);
IF (address_i >= C_WRITE_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEB = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_B + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEB_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_B + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
END IF;
END PROCEDURE;
-- read_a
----------
PROCEDURE read_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_A_DIV);
IF (address_i >= C_READ_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for A Read"
SEVERITY WARNING;
END IF;
memory_out_a <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_A-1 LOOP
memory_out_a(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_A + i) AFTER FLOP_DELAY;
END LOOP;
END IF;
END IF;
END PROCEDURE;
-- read_b
----------
PROCEDURE read_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_B_DIV);
IF (address_i >= C_READ_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Read"
SEVERITY WARNING;
END IF;
memory_out_b <= (OTHERS => 'X') AFTER FLOP_DELAY;
sbiterr_in <= 'X' AFTER FLOP_DELAY;
dbiterr_in <= 'X' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_B-1 LOOP
memory_out_b(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_B + i) AFTER FLOP_DELAY;
END LOOP;
--assert sbiterr and dbiterr signals
IF ((C_FAMILY="virtex7") AND C_USE_ECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
--assert softecc sbiterr and dbiterr signals
ELSIF (C_USE_SOFTECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (softecc_sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (softecc_dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
END IF;
END IF;
END IF;
END PROCEDURE;
-- reset_a
----------
PROCEDURE reset_a
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
-- reset_b
----------
PROCEDURE reset_b
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
BEGIN -- begin the main PROCESS
--***************************************************************************
-- These are the main blocks which schedule read and write operations
-- Note that the reset priority feature at the latch stage is only supported
-- for Spartan-6. For other families, the default priority at the latch stage
-- is "CE"
--***************************************************************************
-- Synchronous clocks: schedule port operations with respect to both
-- write operating modes
IF (C_COMMON_CLK=1) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODES IS
WHEN "0000" => -- write_first write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "0100" => -- read_first write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "0001" => -- write_first read_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0101" => --read_first read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0010" => -- write_first no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0110" => -- read_first no_change
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1000" => -- no_change write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "1001" => -- no_change read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1010" => -- no_change no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Synchronous clocks
-- Asynchronous clocks: port operation is independent
IF (C_COMMON_CLK=0) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODE_A IS
WHEN "00" => -- write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN "01" => -- read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "10" => -- no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
IF (CLKB='1' AND CLKB'EVENT) THEN
CASE WRITE_MODE_B IS
WHEN "00" => -- write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "01" => -- read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "10" => -- no_change
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Asynchronous clocks
-- Assign the memory VARIABLE to the user_visible memory_i SIGNAL
IF(DEBUG=1) THEN
memory_i <= memory;
doublebit_error_i <= doublebit_error;
current_contents_i <= current_contents_var;
END IF;
END PROCESS;
--********************************************************************
-- Instantiate the VARIABLE depth output stage
--********************************************************************
-- Port A
rsta_outp_stage <= RSTA and not sleep;
rstb_outp_stage <= RSTB and not sleep;
reg_a : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTA,
C_RSTRAM => C_RSTRAM_A,
C_RST_PRIORITY => C_RST_PRIORITY_A,
init_val => INITA_VAL,
C_HAS_EN => C_HAS_ENA,
C_HAS_REGCE => C_HAS_REGCEA,
C_DATA_WIDTH => C_READ_WIDTH_A,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_A,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_A,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKA,
RST => rsta_outp_stage, --RSTA,
EN => ENA,
REGCE => REGCEA,
DIN_I => memory_out_a,
DOUT => DOUTA,
SBITERR_IN_I => '0',
DBITERR_IN_I => '0',
SBITERR => OPEN,
DBITERR => OPEN,
RDADDRECC_IN_I => (OTHERS => '0'),
ECCPIPECE => '0',
RDADDRECC => OPEN
);
-- Port B
reg_b : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTB,
C_RSTRAM => C_RSTRAM_B,
C_RST_PRIORITY => C_RST_PRIORITY_B,
init_val => INITB_VAL,
C_HAS_EN => C_HAS_ENB,
C_HAS_REGCE => C_HAS_REGCEB,
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_B,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKB,
RST => rstb_outp_stage,--RSTB,
EN => ENB,
REGCE => REGCEB,
DIN_I => memory_out_b,
DOUT => doutb_i,
SBITERR_IN_I => sbiterr_in,
DBITERR_IN_I => dbiterr_in,
SBITERR => sbiterr_i,
DBITERR => dbiterr_i,
RDADDRECC_IN_I => rdaddrecc_in,
ECCPIPECE => ECCPIPECE,
RDADDRECC => rdaddrecc_i
);
--********************************************************************
-- Instantiate the input / Output Register stages
--********************************************************************
output_reg_stage: blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC MAP(
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP(
CLK => CLKB,
DIN => doutb_i,
DOUT => DOUTB,
SBITERR_IN => sbiterr_i,
DBITERR_IN => dbiterr_i,
SBITERR => sbiterr_sdp,
DBITERR => dbiterr_sdp,
RDADDRECC_IN => rdaddrecc_i,
RDADDRECC => rdaddrecc_sdp
);
--*********************************
-- Synchronous collision checks
--*********************************
sync_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=1) GENERATE
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
-- collision detect
VARIABLE is_collision : BOOLEAN;
VARIABLE message : LINE;
BEGIN
IF (CLKA='1' AND CLKA'EVENT) THEN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision := false;
END IF;
-- If the write port is in READ_FIRST mode, there is no collision
IF (C_WRITE_MODE_A="READ_FIRST" AND wea_i/=WEA0 AND web_i=WEB0) THEN
is_collision := false;
END IF;
IF (C_WRITE_MODE_B="READ_FIRST" AND web_i/=WEB0 AND wea_i=WEA0) THEN
is_collision := false;
END IF;
-- Only flag if one of the accesses is a write
IF (is_collision AND (wea_i/=WEA0 OR web_i/=WEB0)) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END IF;
END PROCESS;
END GENERATE;
--*********************************
-- Asynchronous collision checks
--*********************************
async_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=0) GENERATE
SIGNAL addra_delay : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL wea_delay : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL ena_delay : STD_LOGIC;
SIGNAL addrb_delay : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
SIGNAL web_delay : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL enb_delay : STD_LOGIC;
BEGIN
-- Delay A and B addresses in order to mimic setup/hold times
PROCESS (ADDRA, wea_i, ena_i, ADDRB, web_i, enb_i)
BEGIN
addra_delay <= ADDRA AFTER COLL_DELAY;
wea_delay <= wea_i AFTER COLL_DELAY;
ena_delay <= ena_i AFTER COLL_DELAY;
addrb_delay <= ADDRB AFTER COLL_DELAY;
web_delay <= web_i AFTER COLL_DELAY;
enb_delay <= enb_i AFTER COLL_DELAY;
END PROCESS;
-- Do the checks w/rt A
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_a : BOOLEAN;
VARIABLE is_collision_delay_a : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_a := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_a := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_delay_a := collision_check(ADDRA,
wea_i/=WEA0,
addrb_delay,
web_delay/=WEB0);
ELSE
is_collision_delay_a := false;
END IF;
-- Only flag if B access is a write
IF (is_collision_a AND web_i/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_a AND web_delay/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, addrb_delay);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
-- Do the checks w/rt B
PROCESS (CLKB)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_b : BOOLEAN;
VARIABLE is_collision_delay_b : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA) /= 'X') THEN
is_collision_b := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_b := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(addra_delay) /= 'X') THEN
is_collision_delay_b := collision_check(addra_delay,
wea_delay/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_delay_b := false;
END IF;
-- Only flag if A access is a write
-- Modified condition checking (is_collision_b AND WEA0_i=/WEA0) to fix CR526228
IF (is_collision_b AND wea_i/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_b AND wea_delay/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, addra_delay);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
END GENERATE;
END mem_module_behavioral;
--******************************************************************************
-- Top module that wraps SoftECC Input register stage and the main memory module
--
-- This module is the top-level of behavioral model
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1 IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_CTRL_ECC_ALGO : STRING := "NONE";
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
--C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_SLEEP_PIN : INTEGER := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
PORT (
clka : IN STD_LOGIC := '0';
rsta : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '1';
regcea : IN STD_LOGIC := '1';
wea : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addra : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
dina : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
douta : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
clkb : IN STD_LOGIC := '0';
rstb : IN STD_LOGIC := '0';
enb : IN STD_LOGIC := '1';
regceb : IN STD_LOGIC := '1';
web : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addrb : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
dinb : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
doutb : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
injectsbiterr : IN STD_LOGIC := '0';
injectdbiterr : IN STD_LOGIC := '0';
sbiterr : OUT STD_LOGIC := '0';
dbiterr : OUT STD_LOGIC := '0';
rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : in std_logic := '0';
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic := '0';
rstb_busy : out std_logic := '0';
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
s_aclk : IN STD_LOGIC := '0';
s_aresetn : IN STD_LOGIC := '0';
-- axi full/lite slave Write (write side)
s_axi_awid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid : IN STD_LOGIC := '0';
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast : IN STD_LOGIC := '0';
s_axi_wvalid : IN STD_LOGIC := '0';
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC := '0';
-- axi full/lite slave Read (Write side)
s_axi_arid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid : IN STD_LOGIC := '0';
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_rdata : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC := '0';
-- axi full/lite sideband Signals
s_axi_injectsbiterr : IN STD_LOGIC := '0';
s_axi_injectdbiterr : IN STD_LOGIC := '0';
s_axi_sbiterr : OUT STD_LOGIC := '0';
s_axi_dbiterr : OUT STD_LOGIC := '0';
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END blk_mem_gen_v8_3_1;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE behavioral OF blk_mem_gen_v8_3_1 IS
COMPONENT blk_mem_gen_v8_3_1_mem_module
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_mem_module;
COMPONENT blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_axi_regs_fwd_v8_3;
COMPONENT blk_mem_axi_read_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT blk_mem_axi_read_wrapper_beh;
COMPONENT blk_mem_axi_write_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END COMPONENT blk_mem_axi_write_wrapper_beh;
CONSTANT FLOP_DELAY : TIME := 100 ps;
SIGNAL rsta_in : STD_LOGIC := '1';
SIGNAL ena_in : STD_LOGIC := '1';
SIGNAL regcea_in : STD_LOGIC := '1';
SIGNAL wea_in : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL addra_in : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL dina_in : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL injectsbiterr_in : STD_LOGIC := '0';
SIGNAL injectdbiterr_in : STD_LOGIC := '0';
-----------------------------------------------------------------------------
-- FUNCTION: toLowerCaseChar
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
-----------------------------------------------------------------------------
FUNCTION toLowerCaseChar(
char : character )
RETURN character IS
BEGIN
-- If char is not an upper case letter then return char
IF char<'A' OR char>'Z' THEN
RETURN char;
END IF;
-- Otherwise map char to its corresponding lower case character and
-- RETURN that
CASE char IS
WHEN 'A' => RETURN 'a';
WHEN 'B' => RETURN 'b';
WHEN 'C' => RETURN 'c';
WHEN 'D' => RETURN 'd';
WHEN 'E' => RETURN 'e';
WHEN 'F' => RETURN 'f';
WHEN 'G' => RETURN 'g';
WHEN 'H' => RETURN 'h';
WHEN 'I' => RETURN 'i';
WHEN 'J' => RETURN 'j';
WHEN 'K' => RETURN 'k';
WHEN 'L' => RETURN 'l';
WHEN 'M' => RETURN 'm';
WHEN 'N' => RETURN 'n';
WHEN 'O' => RETURN 'o';
WHEN 'P' => RETURN 'p';
WHEN 'Q' => RETURN 'q';
WHEN 'R' => RETURN 'r';
WHEN 'S' => RETURN 's';
WHEN 'T' => RETURN 't';
WHEN 'U' => RETURN 'u';
WHEN 'V' => RETURN 'v';
WHEN 'W' => RETURN 'w';
WHEN 'X' => RETURN 'x';
WHEN 'Y' => RETURN 'y';
WHEN 'Z' => RETURN 'z';
WHEN OTHERS => RETURN char;
END CASE;
END toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
FUNCTION equalIgnoreCase(
str1 : STRING;
str2 : STRING )
RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str2'left TO str1'right LOOP
IF NOT (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equalIgnoreCase;
-----------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
----------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
----------------------------------------------------------------------------
-- FUNCTION : log2roundup
----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
CONSTANT lower_limit : INTEGER := 1;
CONSTANT upper_limit : INTEGER := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
-----------------------------------------------------------------------------
-- FUNCTION : divroundup
-- Returns the ceiling value of the division
-- Data_value - the quantity to be divided, dividend
-- Divisor - the value to divide the data_value by
-----------------------------------------------------------------------------
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
SIGNAL s_axi_awaddr_out_c : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_araddr_out_c : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_wr_en_c : STD_LOGIC := '0';
SIGNAL s_axi_rd_en_c : STD_LOGIC := '0';
SIGNAL s_aresetn_a_c : STD_LOGIC := '0';
--**************************************************************************
-- AXI PARAMETERS
CONSTANT AXI_FULL_MEMORY_SLAVE : integer := if_then_else((C_AXI_SLAVE_TYPE = 0 AND C_AXI_TYPE = 1),1,0);
CONSTANT C_AXI_ADDR_WIDTH_MSB : integer := C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
CONSTANT C_AXI_ADDR_WIDTH : integer := C_AXI_ADDR_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT LOWER_BOUND_VAL : integer := if_then_else((log2roundup(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT C_AXI_ADDR_WIDTH_LSB : integer := if_then_else((AXI_FULL_MEMORY_SLAVE = 1),0,LOWER_BOUND_VAL);
CONSTANT C_AXI_OS_WR : integer := 2;
-- SAFETY LOGIC related Signals
SIGNAL RSTA_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_A : STD_LOGIC := '0';
SIGNAL RSTB_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_B : STD_LOGIC := '0';
SIGNAL ENA_dly : STD_LOGIC := '0';
SIGNAL ENA_dly_D : STD_LOGIC := '0';
SIGNAL ENB_dly : STD_LOGIC := '0';
SIGNAL ENB_dly_D : STD_LOGIC := '0';
SIGNAL RSTA_I_SAFE : STD_LOGIC := '0';
SIGNAL RSTB_I_SAFE : STD_LOGIC := '0';
SIGNAL ENA_I_SAFE : STD_LOGIC := '0';
SIGNAL ENB_I_SAFE : STD_LOGIC := '0';
SIGNAL ram_rstram_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstram_b_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_b_busy : STD_LOGIC := '0';
SIGNAL ENA_dly_reg : STD_LOGIC := '0';
SIGNAL ENB_dly_reg : STD_LOGIC := '0';
SIGNAL ENA_dly_reg_D : STD_LOGIC := '0';
SIGNAL ENB_dly_reg_D : STD_LOGIC := '0';
--**************************************************************************
BEGIN -- Architecture
--*************************************************************************
-- NO INPUT STAGE
--*************************************************************************
no_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=0) GENERATE
rsta_in <= RSTA;
ena_in <= ENA;
regcea_in <= REGCEA;
wea_in <= WEA;
addra_in <= ADDRA;
dina_in <= DINA;
injectsbiterr_in <= INJECTSBITERR;
injectdbiterr_in <= INJECTDBITERR;
END GENERATE no_input_stage;
--**************************************************************************
-- WITH INPUT STAGE
--**************************************************************************
has_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=1) GENERATE
PROCESS (CLKA)
BEGIN
IF (CLKA'EVENT AND CLKA = '1') THEN
rsta_in <= RSTA AFTER FLOP_DELAY;
ena_in <= ENA AFTER FLOP_DELAY;
regcea_in <= REGCEA AFTER FLOP_DELAY;
wea_in <= WEA AFTER FLOP_DELAY;
addra_in <= ADDRA AFTER FLOP_DELAY;
dina_in <= DINA AFTER FLOP_DELAY;
injectsbiterr_in <= INJECTSBITERR AFTER FLOP_DELAY;
injectdbiterr_in <= INJECTDBITERR AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE has_input_stage;
--**************************************************************************
-- NO SAFETY LOGIC
--**************************************************************************
NO_SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 0) GENERATE
ENA_I_SAFE <= ena_in;
ENB_I_SAFE <= ENB;
RSTA_I_SAFE <= rsta_in;
RSTB_I_SAFE <= RSTB;
END GENERATE NO_SAFETY_CKT_GEN;
--**************************************************************************
-- SAFETY LOGIC
--**************************************************************************
SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 1) GENERATE
-- RESET SAFETY LOGIC Generation
-- POR Generation
------------------------------------------------------------------------------
-- Power-ON Reset Generation
------------------------------------------------------------------------------
RST_SHFT_LOGIC_A : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
RSTA_SHFT_REG(4 DOWNTO 0) <= RSTA_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_A;
POR_RSTA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
POR_A <= RSTA_SHFT_REG(4) xor RSTA_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTA_GEN;
RST_SHFT_LOGIC_B : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
RSTB_SHFT_REG(4 DOWNTO 0) <= RSTB_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_B;
POR_RSTB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
POR_B <= RSTB_SHFT_REG(4) xor RSTB_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTB_GEN;
-----------------------------------------------------------------------------
-- Fix for the AR42571
-----------------------------------------------------------------------------
-- Reset Generation
-----------------------------------------------------------------------------
RSTA_I_SAFE <= rsta_in OR POR_A;
SPRAM_RST: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_I_SAFE <= '0';
END GENERATE SPRAM_RST;
nSPRAM_RST: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_I_SAFE <= RSTB OR POR_B;
END GENERATE nSPRAM_RST;
-----------------------------------------------------------------------------
-- RSTA/B_BUSY Generation
-----------------------------------------------------------------------------
RSTA_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
ram_rstram_a_busy <= rsta_in OR ENA_dly OR ENA_dly_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstram_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_NO_REG;
RSTA_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
ram_rstreg_a_busy <= rsta_in OR ENA_dly OR ENA_dly_reg_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstreg_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_WITH_REG;
SPRAM_RST_BUSY: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_BUSY <= '0';
END GENERATE SPRAM_RST_BUSY;
nSPRAM_RST_BUSY: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
ram_rstram_b_busy <= RSTB OR ENB_dly OR ENB_dly_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstram_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_NO_REG;
RSTB_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
ram_rstreg_b_busy <= RSTB OR ENB_dly OR ENB_dly_reg_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstreg_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_WITH_REG;
END GENERATE nSPRAM_RST_BUSY;
-----------------------------------------------------------------------------
-- ENA/ENB Generation
-----------------------------------------------------------------------------
ENA_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly <= rsta_in AFTER FLOP_DELAY;
ENA_dly_D <= ENA_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_D OR ena_in;
END GENERATE ENA_NO_REG;
ENA_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly_reg <= rsta_in AFTER FLOP_DELAY;
ENA_dly_reg_D <= ENA_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_reg_D OR ena_in;
END GENERATE ENA_WITH_REG;
SPRAM_ENB: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
ENB_I_SAFE <= '0';
END GENERATE SPRAM_ENB;
nSPRAM_ENB: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
ENB_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly <= RSTB AFTER FLOP_DELAY;
ENB_dly_D <= ENB_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_D OR ENB;
END GENERATE ENB_NO_REG;
ENB_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly_reg <= RSTB AFTER FLOP_DELAY;
ENB_dly_reg_D <= ENB_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_reg_D OR ENB;
END GENERATE ENB_WITH_REG;
END GENERATE nSPRAM_ENB;
END GENERATE SAFETY_CKT_GEN;
--**************************************************************************
-- NATIVE MEMORY MODULE INSTANCE
--**************************************************************************
native_mem_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 0) GENERATE
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,--rsta_in,
ENA => ENA_I_SAFE,--ena_in,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in,
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => RDADDRECC
);
END GENERATE native_mem_module;
--**************************************************************************
-- NATIVE MEMORY MAPPED MODULE INSTANCE
--**************************************************************************
native_mem_map_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 1) GENERATE
--**************************************************************************
-- NATIVE MEMORY MAPPED PARAMETERS
CONSTANT C_ADDRA_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_A);
CONSTANT C_ADDRB_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_B);
CONSTANT C_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
CONSTANT C_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
CONSTANT C_MEM_MAP_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_MSB;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT MEM_MAP_LOWER_BOUND_VAL_A : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT MEM_MAP_LOWER_BOUND_VAL_B : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_B,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_B,8)));
CONSTANT C_MEM_MAP_ADDRA_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_A;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_B;
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH_ACTUAL-1 DOWNTO 0) := (OTHERS => '0');
--**************************************************************************
BEGIN
RDADDRECC(C_ADDRB_WIDTH-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_MSB) <= (OTHERS => '0');
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB) <= rdaddrecc_i;
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_LSB-1 DOWNTO 0) <= (OTHERS => '0');
mem_map_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH_ACTUAL,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH_ACTUAL,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,
ENA => ENA_I_SAFE,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in(C_MEM_MAP_ADDRA_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRA_WIDTH_LSB),
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB),
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => rdaddrecc_i
);
END GENERATE native_mem_map_module;
--****************************************************************************
-- AXI MEMORY MODULE INSTANCE
--****************************************************************************
axi_mem_module: IF (C_INTERFACE_TYPE = 1) GENERATE
SIGNAL s_axi_rid_c : STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rdata_c : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rresp_c : STD_LOGIC_VECTOR(2-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rlast_c : STD_LOGIC := '0';
SIGNAL s_axi_rvalid_c : STD_LOGIC := '0';
SIGNAL s_axi_rready_c : STD_LOGIC := '0';
SIGNAL regceb_c : STD_LOGIC := '0';
BEGIN
s_aresetn_a_c <= NOT S_ARESETN;
S_AXI_BRESP <= (OTHERS => '0');
s_axi_rresp_c <= (OTHERS => '0');
no_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 0 AND C_HAS_MUX_OUTPUT_REGS_B = 0 ) GENERATE
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RLAST <= s_axi_rlast_c;
S_AXI_RVALID <= s_axi_rvalid_c;
S_AXI_RID <= s_axi_rid_c;
S_AXI_RRESP <= s_axi_rresp_c;
s_axi_rready_c <= S_AXI_RREADY;
END GENERATE no_regs;
has_regs_fwd: IF (C_HAS_MUX_OUTPUT_REGS_B = 1 OR C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
CONSTANT C_AXI_PAYLOAD : INTEGER := if_then_else((C_HAS_MUX_OUTPUT_REGS_B = 1),C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3,C_AXI_ID_WIDTH+3);
SIGNAL s_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
has_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
regceb_c <= s_axi_rvalid_c AND s_axi_rready_c;
END GENERATE has_regceb;
no_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 0) GENERATE
regceb_c <= REGCEB;
END GENERATE no_regceb;
only_core_op_regs: IF (C_HAS_MUX_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rdata_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RDATA <= m_axi_payload_c(C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_core_op_regs;
only_emb_op_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_emb_op_regs;
axi_regs_inst : blk_mem_axi_regs_fwd_v8_3
GENERIC MAP(
C_DATA_WIDTH => C_AXI_PAYLOAD
)
PORT MAP (
ACLK => S_ACLK,
ARESET => s_aresetn_a_c,
S_VALID => s_axi_rvalid_c,
S_READY => s_axi_rready_c,
S_PAYLOAD_DATA => s_axi_payload_c,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY,
M_PAYLOAD_DATA => m_axi_payload_c
);
END GENERATE has_regs_fwd;
axi_wr_fsm : blk_mem_axi_write_wrapper_beh
GENERIC MAP(
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_AXI_AWADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_WDATA_WIDTH => C_WRITE_WIDTH_A,
C_AXI_OS_WR => C_AXI_OS_WR
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Slave Write Interface
S_AXI_AWADDR => S_AXI_AWADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_AWLEN => S_AXI_AWLEN,
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BID => S_AXI_BID,
-- Signals for BRAM interface
S_AXI_AWADDR_OUT =>s_axi_awaddr_out_c,
S_AXI_WR_EN =>s_axi_wr_en_c
);
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => 1, -- For AXI, Read Enable is always C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => 1, -- For AXI C_USE_BYTE_WEA is always 1,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => 1, -- For AXI, Read Enable is always C_HAS_ENB,
C_HAS_REGCEB => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_BYTE_WEB => 1, -- For AXI C_USE_BYTE_WEB is always 1,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => 0, --For AXI, Primitive Registers A is not supported C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => 0,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
--Port A:
CLKA => S_AClk,
RSTA => s_aresetn_a_c,
ENA => s_axi_wr_en_c,
REGCEA => regcea_in,
WEA => S_AXI_WSTRB,
ADDRA => s_axi_awaddr_out_c,
DINA => S_AXI_WDATA,
DOUTA => DOUTA,
--Port B:
CLKB => S_AClk,
RSTB => s_aresetn_a_c,
ENB => s_axi_rd_en_c,
REGCEB => regceb_c,
WEB => (OTHERS => '0'),
ADDRB => s_axi_araddr_out_c,
DINB => DINB,
DOUTB => s_axi_rdata_c,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => '0',
SLEEP => '0',
RDADDRECC => RDADDRECC
);
axi_rd_sm : blk_mem_axi_read_wrapper_beh
GENERIC MAP (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_PIPELINE_STAGES => 1,
C_AXI_ARADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_AClk,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Read Side
S_AXI_ARADDR => S_AXI_ARADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARSIZE => S_AXI_ARSIZE,
S_AXI_ARBURST => S_AXI_ARBURST,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => s_axi_rlast_c,
S_AXI_RVALID => s_axi_rvalid_c,
S_AXI_RREADY => s_axi_rready_c,
S_AXI_ARID => S_AXI_ARID,
S_AXI_RID => s_axi_rid_c,
-- AXI Full/Lite Read FSM Outputs
S_AXI_ARADDR_OUT => s_axi_araddr_out_c,
S_AXI_RD_EN => s_axi_rd_en_c
);
END GENERATE axi_mem_module;
END behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_clr is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_clr;
architecture beh_ff_clr_arch of beh_ff_clr is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(CLR, C)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_clr_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_ce is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_ce;
architecture beh_ff_ce_arch of beh_ff_ce is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, CLR)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
if (CE = '1') then
q_o <= D after 100 ps;
end if;
end if;
end process;
end beh_ff_ce_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_pre is
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end beh_ff_pre;
architecture beh_ff_pre_arch of beh_ff_pre is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, PRE)
begin
if (PRE = '1') then
q_o <= '1';
elsif (C' event and C = '1') then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_pre_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_muxf7 is
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end beh_muxf7;
architecture beh_muxf7_arch of beh_muxf7 is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
else
O <= I1;
end if;
end process;
end beh_muxf7_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity STATE_LOGIC is
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic := '0';
I0 : in std_logic := '0';
I1 : in std_logic := '0';
I2 : in std_logic := '0';
I3 : in std_logic := '0';
I4 : in std_logic := '0';
I5 : in std_logic := '0'
);
end STATE_LOGIC;
architecture STATE_LOGIC_arch of STATE_LOGIC is
constant INIT_reg : std_logic_vector(63 downto 0) := INIT;
begin
LUT_beh:process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
begin
I_reg := I5 & I4 & I3 & I2 & I1 & I0;
O <= INIT_reg(conv_integer(I_reg));
end process;
end STATE_LOGIC_arch;
|
-------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v8_3_1.vhd
--
-- Description:
-- This file is the VHDL behvarial model for the
-- Block Memory Generator Core.
--
-------------------------------------------------------------------------------
-- Author: Xilinx
--
-- History: January 11, 2006: Initial revision
-- June 11, 2007 : Added independent register stages for
-- Port A and Port B (IP1_Jm/v2.5)
-- August 28, 2007 : Added mux pipeline stages feature (IP2_Jm/v2.6)
-- April 07, 2009 : Added support for Spartan-6 and Virtex-6
-- features, including the following:
-- (i) error injection, detection and/or correction
-- (ii) reset priority
-- (iii) special reset behavior
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
ENTITY blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END ENTITY blk_mem_axi_regs_fwd_v8_3;
ARCHITECTURE axi_regs_fwd_arch OF blk_mem_axi_regs_fwd_v8_3 IS
SIGNAL STORAGE_DATA : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_READY_I : STD_LOGIC := '0';
SIGNAL M_VALID_I : STD_LOGIC := '0';
SIGNAL ARESET_D : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');-- Reset delay register
BEGIN
--assign local signal to its output signal
S_READY <= S_READY_I;
M_VALID <= M_VALID_I;
PROCESS(ACLK)
BEGIN
IF(ACLK'event AND ACLK = '1') THEN
ARESET_D <= ARESET_D(0) & ARESET;
END IF;
END PROCESS;
--Save payload data whenever we have a transaction on the slave side
PROCESS(ACLK, ARESET)
BEGIN
IF (ARESET = '1') THEN
STORAGE_DATA <= (OTHERS => '0');
ELSIF(ACLK'event AND ACLK = '1') THEN
IF(S_VALID = '1' AND S_READY_I = '1') THEN
STORAGE_DATA <= S_PAYLOAD_DATA;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= STORAGE_DATA;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
PROCESS(ACLK,ARESET)
BEGIN
IF (ARESET_D /= "00") THEN
M_VALID_I <= '0';
ELSIF(ACLK'event AND ACLK = '1') THEN
IF (S_VALID = '1') THEN
--Always set M_VALID_I when slave side is valid
M_VALID_I <= '1';
ELSIF (M_READY = '1') THEN
--Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= '0';
END IF;
END IF;
END PROCESS;
--Slave Ready is either when Master side drives M_READY or we have space in our storage data
S_READY_I <= (M_READY OR (NOT M_VALID_I)) AND NOT(OR_REDUCE(ARESET_D));
END axi_regs_fwd_arch;
-------------------------------------------------------------------------------
-- Description:
-- This is the behavioral model of write_wrapper for the
-- Block Memory Generator Core.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_axi_write_wrapper_beh IS
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END blk_mem_axi_write_wrapper_beh;
ARCHITECTURE axi_write_wrap_arch OF blk_mem_axi_write_wrapper_beh IS
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_AXI_WDATA_WIDTH=8,0,
if_then_else((C_AXI_WDATA_WIDTH=16),1,
if_then_else((C_AXI_WDATA_WIDTH=32),2,
if_then_else((C_AXI_WDATA_WIDTH=64),3,
if_then_else((C_AXI_WDATA_WIDTH=128),4,
if_then_else((C_AXI_WDATA_WIDTH=256),5,0))))));
SIGNAL bvalid_c : std_logic := '0';
SIGNAL bready_timeout_c : std_logic := '0';
SIGNAL bvalid_rd_cnt_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_r : std_logic := '0';
SIGNAL bvalid_count_r : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL awaddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
C_AXI_AWADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL bvalid_wr_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_rd_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_last_c : std_logic := '0';
SIGNAL addr_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL aw_ready_r : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL awlen_cntr_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1');
SIGNAL awlen_int : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL awburst_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes : integer := 0;
SIGNAL wrap_boundary : integer := 0;
SIGNAL wrap_base_addr : integer := 0;
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
-- Array to store BIDs
TYPE id_array IS ARRAY (3 DOWNTO 0) OF std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
SIGNAL axi_bid_array : id_array := (others => (others => '0'));
COMPONENT write_netlist
GENERIC(
C_AXI_TYPE : integer
);
PORT(
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
S_AXI_AWVALID : IN std_logic;
aw_ready_r : OUT std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN std_logic;
S_AXI_WR_EN : OUT std_logic;
w_last_c : IN std_logic;
bready_timeout_c : IN std_logic;
addr_en_c : OUT std_logic;
incr_addr_c : OUT std_logic;
bvalid_c : OUT std_logic
);
END COMPONENT write_netlist;
BEGIN
---------------------------------------
--AXI WRITE FSM COMPONENT INSTANTIATION
---------------------------------------
axi_wr_fsm : write_netlist
GENERIC MAP (
C_AXI_TYPE => C_AXI_TYPE
)
PORT MAP (
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
S_AXI_AWVALID => S_AXI_AWVALID,
aw_ready_r => aw_ready_r,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BVALID => OPEN,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_WR_EN => S_AXI_WR_EN,
w_last_c => w_last_c,
bready_timeout_c => bready_timeout_c,
addr_en_c => addr_en_c,
incr_addr_c => incr_addr_c,
bvalid_c => bvalid_c
);
--Wrap Address boundary calculation
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWSIZE,"000"));
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(awlen_int)+1);
wrap_base_addr <= (conv_integer(awaddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary <= wrap_base_addr+total_bytes;
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awaddr_reg <= (OTHERS => '0');
num_of_bytes_r <= 0;
awburst_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awaddr_reg <= S_AXI_AWADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWBURST,"01");
ELSIF (incr_addr_c = '1') THEN
IF (awburst_int = "10") THEN
IF(conv_integer(awaddr_reg) = (wrap_boundary-num_of_bytes_r)) THEN
awaddr_reg <= conv_std_logic_vector(wrap_base_addr,C_AXI_AWADDR_WIDTH);
ELSE
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
ELSIF (awburst_int = "01" OR awburst_int = "11") THEN
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
S_AXI_AWADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
awaddr_reg(C_AXI_AWADDR_WIDTH-1 DOWNTO C_RANGE),awaddr_reg);
---------------------------------------------------------------------------
-- AXI wlast generation
---------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awlen_cntr_r <= (OTHERS => '1');
awlen_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awlen_int <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
awlen_cntr_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
ELSIF (dec_alen_c = '1') THEN
awlen_cntr_r <= awlen_cntr_r - ONE AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
w_last_c <= '1' WHEN (awlen_cntr_r = "00000000" AND S_AXI_WVALID = '1') ELSE '0';
dec_alen_c <= (incr_addr_c OR w_last_c);
---------------------------------------------------------------------------
-- Generation of bvalid counter for outstanding transactions
---------------------------------------------------------------------------
P_b_valid_os_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_count_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- bvalid_count_r generation
IF (bvalid_c = '1' AND bvalid_r = '1' AND S_AXI_BREADY = '1') THEN
bvalid_count_r <= bvalid_count_r AFTER FLOP_DELAY;
ELSIF (bvalid_c = '1') THEN
bvalid_count_r <= bvalid_count_r + "01" AFTER FLOP_DELAY;
ELSIF (bvalid_r = '1' AND S_AXI_BREADY = '1' AND bvalid_count_r /= "0") THEN
bvalid_count_r <= bvalid_count_r - "01" AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_os_r ;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is used
---------------------------------------------------------------------------
gaxi_bvalid_id_r:IF (C_HAS_AXI_ID = 1) GENERATE
SIGNAL bvalid_d1_c : std_logic := '0';
BEGIN
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
bvalid_d1_c <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
--external bvalid signal generation
IF (bvalid_d1_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_id_r;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is not used
---------------------------------------------------------------------------
gaxi_bvalid_noid_r:IF (C_HAS_AXI_ID = 0) GENERATE
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
--external bvalid signal generation
IF (bvalid_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_noid_r;
---------------------------------------------------------------------------
-- Generation of Bready timeout
---------------------------------------------------------------------------
P_brdy_tout_c: PROCESS (bvalid_count_r)
BEGIN
-- bready_timeout_c generation
IF(conv_integer(bvalid_count_r) = C_AXI_OS_WR-1) THEN
bready_timeout_c <= '1';
ELSE
bready_timeout_c <= '0';
END IF;
END PROCESS P_brdy_tout_c;
---------------------------------------------------------------------------
-- Generation of BID
---------------------------------------------------------------------------
gaxi_bid_gen:IF (C_HAS_AXI_ID = 1) GENERATE
P_bid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
bvalid_wr_cnt_r <= (OTHERS => '0');
bvalid_rd_cnt_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- STORE AWID IN AN ARRAY
IF(bvalid_c = '1') THEN
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + "01";
END IF;
-- GENERATE BID FROM AWID ARRAY
bvalid_rd_cnt_r <= bvalid_rd_cnt_c AFTER FLOP_DELAY;
S_AXI_BID <= axi_bid_array(conv_integer(bvalid_rd_cnt_c));
END IF;
END PROCESS P_bid_gen;
bvalid_rd_cnt_c <= bvalid_rd_cnt_r + "01" WHEN (bvalid_r = '1' AND S_AXI_BREADY = '1') ELSE bvalid_rd_cnt_r;
---------------------------------------------------------------------------
-- Storing AWID for generation of BID
---------------------------------------------------------------------------
P_awid_reg:PROCESS (S_ACLK)
BEGIN
IF (S_ACLK'event AND S_ACLK='1') THEN
IF(aw_ready_r = '1' AND S_AXI_AWVALID = '1') THEN
axi_bid_array(conv_integer(bvalid_wr_cnt_r)) <= S_AXI_AWID;
END IF;
END IF;
END PROCESS P_awid_reg;
END GENERATE gaxi_bid_gen;
S_AXI_BVALID <= bvalid_r;
S_AXI_AWREADY <= aw_ready_r;
END axi_write_wrap_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity write_netlist is
GENERIC(
C_AXI_TYPE : integer
);
port (
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_AWVALID : in STD_LOGIC := '0';
S_AXI_WVALID : in STD_LOGIC := '0';
S_AXI_BREADY : in STD_LOGIC := '0';
w_last_c : in STD_LOGIC := '0';
bready_timeout_c : in STD_LOGIC := '0';
aw_ready_r : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_WR_EN : out STD_LOGIC;
addr_en_c : out STD_LOGIC;
incr_addr_c : out STD_LOGIC;
bvalid_c : out STD_LOGIC
);
end write_netlist;
architecture STRUCTURE of write_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
BEGIN
---------------------------------------------------------------------------
-- AXI LITE
---------------------------------------------------------------------------
gbeh_axi_lite_sm: IF (C_AXI_TYPE = 0 ) GENERATE
signal w_ready_r_7 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSignal_bvalid_c : STD_LOGIC;
signal NlwRenamedSignal_incr_addr_c : STD_LOGIC;
signal present_state_FSM_FFd3_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal present_state_FSM_FFd1_15 : STD_LOGIC;
signal present_state_FSM_FFd4_16 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd4_In1_21 : STD_LOGIC;
signal Mmux_aw_ready_c : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
S_AXI_WREADY <= w_ready_r_7;
S_AXI_BVALID <= NlwRenamedSignal_incr_addr_c;
S_AXI_WR_EN <= NlwRenamedSignal_bvalid_c;
incr_addr_c <= NlwRenamedSignal_incr_addr_c;
bvalid_c <= NlwRenamedSignal_bvalid_c;
NlwRenamedSignal_incr_addr_c <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_7
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_16
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_13
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_15
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000055554440"
)
port map (
I0 => S_AXI_WVALID,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => '0',
O => present_state_FSM_FFd3_In
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"0000000088880800"
)
port map (
I0 => S_AXI_AWVALID,
I1 => S_AXI_WVALID,
I2 => bready_timeout_c,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => present_state_FSM_FFd2_In
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAA2000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_WVALID,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => addr_en_c
);
Mmux_w_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"F5F07570F5F05500"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => w_ready_c
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd3_13,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd1_15,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_14,
I2 => present_state_FSM_FFd3_13,
I3 => '0',
I4 => '0',
I5 => '0',
O => NlwRenamedSignal_bvalid_c
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"2F0F27072F0F2200"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => present_state_FSM_FFd4_In1_21
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_In1_21,
I3 => '0',
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_aw_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"7535753575305500"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => S_AXI_WVALID,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => present_state_FSM_FFd2_14,
O => Mmux_aw_ready_c(0)
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => Mmux_aw_ready_c(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => aw_ready_c
);
END GENERATE gbeh_axi_lite_sm;
---------------------------------------------------------------------------
-- AXI FULL
---------------------------------------------------------------------------
gbeh_axi_full_sm: IF (C_AXI_TYPE = 1 ) GENERATE
signal w_ready_r_8 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSig_OI_bvalid_c : STD_LOGIC;
signal present_state_FSM_FFd1_16 : STD_LOGIC;
signal present_state_FSM_FFd4_17 : STD_LOGIC;
signal present_state_FSM_FFd3_18 : STD_LOGIC;
signal present_state_FSM_FFd2_19 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd2_In1_24 : STD_LOGIC;
signal present_state_FSM_FFd4_In1_25 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal N4 : STD_LOGIC;
begin
S_AXI_WREADY <= w_ready_r_8;
bvalid_c <= NlwRenamedSig_OI_bvalid_c;
S_AXI_BVALID <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_8
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_17
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_18
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_19
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_16
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000000005540"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd4_17,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd3_In
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"BF3FBB33AF0FAA00"
)
port map (
I0 => S_AXI_BREADY,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd1_16,
I4 => present_state_FSM_FFd4_17,
I5 => NlwRenamedSig_OI_bvalid_c,
O => aw_ready_c
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"AAAAAAAA20000000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_19,
I3 => S_AXI_WVALID,
I4 => w_last_c,
I5 => present_state_FSM_FFd4_17,
O => addr_en_c
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_19,
I2 => present_state_FSM_FFd3_18,
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_WR_EN
);
Mmux_incr_addr_c_0_1 : STATE_LOGIC
generic map(
INIT => X"0000000000002220"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => incr_addr_c
);
Mmux_aw_ready_c_0_11 : STATE_LOGIC
generic map(
INIT => X"0000000000008880"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => NlwRenamedSig_OI_bvalid_c
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"000000000000D5C0"
)
port map (
I0 => w_last_c,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd4_17,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd2_In1_24
);
present_state_FSM_FFd2_In2 : STATE_LOGIC
generic map(
INIT => X"FFFFAAAA08AAAAAA"
)
port map (
I0 => present_state_FSM_FFd2_19,
I1 => S_AXI_AWVALID,
I2 => bready_timeout_c,
I3 => w_last_c,
I4 => S_AXI_WVALID,
I5 => present_state_FSM_FFd2_In1_24,
O => present_state_FSM_FFd2_In
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"00C0004000C00000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => w_last_c,
I2 => S_AXI_WVALID,
I3 => bready_timeout_c,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => present_state_FSM_FFd4_In1_25
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88F8"
)
port map (
I0 => present_state_FSM_FFd1_16,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_17,
I3 => S_AXI_AWVALID,
I4 => present_state_FSM_FFd4_In1_25,
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_w_ready_c_0_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => w_last_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_w_ready_c_0_Q : STATE_LOGIC
generic map(
INIT => X"FABAFABAFAAAF000"
)
port map (
I0 => N2,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd4_17,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => w_ready_c
);
Mmux_aw_ready_c_0_11_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => bready_timeout_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => w_last_c,
I1 => N4,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => present_state_FSM_FFd1_16,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
END GENERATE gbeh_axi_full_sm;
end STRUCTURE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--AXI Behavioral Model entities
ENTITY blk_mem_axi_read_wrapper_beh is
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
port (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END blk_mem_axi_read_wrapper_beh;
architecture blk_mem_axi_read_wrapper_beh_arch of blk_mem_axi_read_wrapper_beh is
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_WRITE_WIDTH_A=8,0,
if_then_else((C_WRITE_WIDTH_A=16),1,
if_then_else((C_WRITE_WIDTH_A=32),2,
if_then_else((C_WRITE_WIDTH_A=64),3,
if_then_else((C_WRITE_WIDTH_A=128),4,
if_then_else((C_WRITE_WIDTH_A=256),5,0))))));
SIGNAL ar_id_r : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
SIGNAL addr_en_c : std_logic := '0';
SIGNAL rd_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL single_trans_c : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL mux_sel_c : std_logic := '0';
SIGNAL r_last_c : std_logic := '0';
SIGNAL r_last_int_c : std_logic := '0';
SIGNAL arlen_int_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL arlen_cntr : std_logic_vector(7 DOWNTO 0) := ONE;
SIGNAL arburst_int_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL arburst_int_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL araddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),C_AXI_ARADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL total_bytes : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
SIGNAL wrap_base_addr_r : integer := 0;
SIGNAL wrap_boundary_r : integer := 0;
SIGNAL arlen_int_c : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes_c : integer := 0;
SIGNAL wrap_base_addr_c : integer := 0;
SIGNAL wrap_boundary_c : integer := 0;
SIGNAL araddr_out : std_logic_vector(C_ADDRB_WIDTH-1 downto 0) := (OTHERS => '0');
COMPONENT read_netlist
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_INCR_ADDR : OUT std_logic := '0';
S_AXI_ADDR_EN : OUT std_logic := '0';
S_AXI_SINGLE_TRANS : OUT std_logic := '0';
S_AXI_MUX_SEL : OUT std_logic := '0';
S_AXI_R_LAST : OUT std_logic := '0';
S_AXI_R_LAST_INT : IN std_logic := '0';
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT read_netlist;
BEGIN
dec_alen_c <= incr_addr_c OR r_last_int_c;
axi_read_fsm : read_netlist
GENERIC MAP(
C_AXI_TYPE => 1,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
S_AXI_INCR_ADDR => incr_addr_c,
S_AXI_ADDR_EN => addr_en_c,
S_AXI_SINGLE_TRANS => single_trans_c,
S_AXI_MUX_SEL => mux_sel_c,
S_AXI_R_LAST => r_last_c,
S_AXI_R_LAST_INT => r_last_int_c,
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN => rd_en_c
);
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(arlen_int_r)+1);
wrap_base_addr_r <= (conv_integer(araddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary_r <= wrap_base_addr_r+total_bytes;
---- combinatorial from interface
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARSIZE,"000"));
arlen_int_c <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
total_bytes_c <= conv_integer(num_of_bytes_c)*(conv_integer(arlen_int_c)+1);
wrap_base_addr_c <= (conv_integer(S_AXI_ARADDR)/if_then_else(total_bytes_c=0,1,total_bytes_c))*(total_bytes_c);
wrap_boundary_c <= wrap_base_addr_c+total_bytes_c;
arburst_int_c <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARBURST,"01");
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
araddr_reg <= (OTHERS => '0');
arburst_int_r <= (OTHERS => '0');
num_of_bytes_r <= 0;
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (incr_addr_c = '1' AND addr_en_c = '1' AND single_trans_c = '0') THEN
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
IF (arburst_int_c = "10") THEN
IF(conv_integer(S_AXI_ARADDR) = (wrap_boundary_c-num_of_bytes_c)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_c,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (arburst_int_c = "01" OR arburst_int_c = "11") THEN
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (addr_en_c = '1') THEN
araddr_reg <= S_AXI_ARADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
ELSIF (incr_addr_c = '1') THEN
IF (arburst_int_r = "10") THEN
IF(conv_integer(araddr_reg) = (wrap_boundary_r-num_of_bytes_r)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_r,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
ELSIF (arburst_int_r = "01" OR arburst_int_r = "11") THEN
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
araddr_out <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),araddr_reg(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),araddr_reg);
--------------------------------------------------------------------------
-- Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
--------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF S_ARESETN = '1' THEN
arlen_cntr <= ONE;
arlen_int_r <= (OTHERS => '0');
ELSIF S_ACLK'event AND S_ACLK = '1' THEN
IF (addr_en_c = '1' AND dec_alen_c = '1' AND single_trans_c = '0') THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= S_AXI_ARLEN - ONE AFTER FLOP_DELAY;
ELSIF addr_en_c = '1' THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
ELSIF dec_alen_c = '1' THEN
arlen_cntr <= arlen_cntr - ONE AFTER FLOP_DELAY;
ELSE
arlen_cntr <= arlen_cntr AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
r_last_int_c <= '1' WHEN (arlen_cntr = "00000000" AND S_AXI_RREADY = '1') ELSE '0' ;
--------------------------------------------------------------------------
-- AXI FULL FSM
-- Mux Selection of ARADDR
-- ARADDR is driven out from the read fsm based on the mux_sel_c
-- Based on mux_sel either ARADDR is given out or the latched ARADDR is
-- given out to BRAM
--------------------------------------------------------------------------
P_araddr_mux: PROCESS (mux_sel_c,S_AXI_ARADDR,araddr_out)
BEGIN
IF (mux_sel_c = '0') THEN
S_AXI_ARADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARADDR(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),S_AXI_ARADDR);
ELSE
S_AXI_ARADDR_OUT <= araddr_out;
END IF;
END PROCESS P_araddr_mux;
--------------------------------------------------------------------------
-- Assign output signals - AXI FULL FSM
--------------------------------------------------------------------------
S_AXI_RD_EN <= rd_en_c;
grid: IF (C_HAS_AXI_ID = 1) GENERATE
P_rid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
S_AXI_RID <= (OTHERS => '0');
ar_id_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
IF (addr_en_c = '1' AND rd_en_c = '1') THEN
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
ELSIF (addr_en_c = '1' AND rd_en_c = '0') THEN
ar_id_r <= S_AXI_ARID;
ELSIF (rd_en_c = '1') THEN
S_AXI_RID <= ar_id_r;
END IF;
END IF;
END PROCESS P_rid_gen;
END GENERATE grid;
END blk_mem_axi_read_wrapper_beh_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity read_netlist is
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_R_LAST_INT : in STD_LOGIC := '0';
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_ARVALID : in STD_LOGIC := '0';
S_AXI_RREADY : in STD_LOGIC := '0';
S_AXI_INCR_ADDR : out STD_LOGIC;
S_AXI_ADDR_EN : out STD_LOGIC;
S_AXI_SINGLE_TRANS : out STD_LOGIC;
S_AXI_MUX_SEL : out STD_LOGIC;
S_AXI_R_LAST : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RLAST : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RD_EN : out STD_LOGIC;
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end read_netlist;
architecture STRUCTURE of read_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
signal present_state_FSM_FFd1_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_r_15 : STD_LOGIC;
signal gaxi_full_sm_ar_ready_r_16 : STD_LOGIC;
signal gaxi_full_sm_r_last_r_17 : STD_LOGIC;
signal NlwRenamedSig_OI_gaxi_full_sm_r_valid_r : STD_LOGIC;
signal gaxi_full_sm_r_valid_c : STD_LOGIC;
signal S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o : STD_LOGIC;
signal gaxi_full_sm_ar_ready_c : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_c : STD_LOGIC;
signal NlwRenamedSig_OI_S_AXI_R_LAST : STD_LOGIC;
signal S_AXI_ARLEN_7_GND_8_o_equal_1_o : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal Mmux_S_AXI_R_LAST13 : STD_LOGIC;
signal N01 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal Mmux_gaxi_full_sm_ar_ready_c11 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N8 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N13 : STD_LOGIC;
begin
S_AXI_R_LAST <= NlwRenamedSig_OI_S_AXI_R_LAST;
S_AXI_ARREADY <= gaxi_full_sm_ar_ready_r_16;
S_AXI_RLAST <= gaxi_full_sm_r_last_r_17;
S_AXI_RVALID <= NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
gaxi_full_sm_outstanding_read_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_outstanding_read_c,
Q => gaxi_full_sm_outstanding_read_r_15
);
gaxi_full_sm_r_valid_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => gaxi_full_sm_r_valid_c,
Q => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r
);
gaxi_full_sm_ar_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_ar_ready_c,
Q => gaxi_full_sm_ar_ready_r_16
);
gaxi_full_sm_r_last_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => NlwRenamedSig_OI_S_AXI_R_LAST,
Q => gaxi_full_sm_r_last_r_17
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_13
);
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 : STATE_LOGIC
generic map(
INIT => X"000000000000000B"
)
port map (
I0 => S_AXI_RREADY,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o
);
Mmux_S_AXI_SINGLE_TRANS11 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_SINGLE_TRANS
);
Mmux_S_AXI_ADDR_EN11 : STATE_LOGIC
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_ADDR_EN
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"ECEE2022EEEE2022"
)
port map (
I0 => S_AXI_ARVALID,
I1 => present_state_FSM_FFd1_13,
I2 => S_AXI_RREADY,
I3 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I4 => present_state_FSM_FFd2_14,
I5 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
O => present_state_FSM_FFd2_In
);
Mmux_S_AXI_R_LAST131 : STATE_LOGIC
generic map(
INIT => X"0000000044440444"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_RREADY,
I5 => '0',
O => Mmux_S_AXI_R_LAST13
);
Mmux_S_AXI_INCR_ADDR11 : STATE_LOGIC
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => S_AXI_R_LAST_INT,
I1 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => Mmux_S_AXI_R_LAST13,
O => S_AXI_INCR_ADDR
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000FE"
)
port map (
I0 => S_AXI_ARLEN(2),
I1 => S_AXI_ARLEN(1),
I2 => S_AXI_ARLEN(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => N01
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q : STATE_LOGIC
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => S_AXI_ARLEN(7),
I1 => S_AXI_ARLEN(6),
I2 => S_AXI_ARLEN(5),
I3 => S_AXI_ARLEN(4),
I4 => S_AXI_ARLEN(3),
I5 => N01,
O => S_AXI_ARLEN_7_GND_8_o_equal_1_o
);
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_gaxi_full_sm_outstanding_read_c1 : STATE_LOGIC
generic map(
INIT => X"0020000002200200"
)
port map (
I0 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd1_13,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => N2,
O => gaxi_full_sm_outstanding_read_c
);
Mmux_gaxi_full_sm_ar_ready_c12 : STATE_LOGIC
generic map(
INIT => X"0000000000004555"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => '0',
I5 => '0',
O => Mmux_gaxi_full_sm_ar_ready_c11
);
Mmux_S_AXI_R_LAST11_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000EF"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
Mmux_S_AXI_R_LAST11 : STATE_LOGIC
generic map(
INIT => X"FCAAFC0A00AA000A"
)
port map (
I0 => S_AXI_ARVALID,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => N4,
I5 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
O => gaxi_full_sm_r_valid_c
);
S_AXI_MUX_SEL1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAAAA08"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => '0',
O => S_AXI_MUX_SEL
);
Mmux_S_AXI_RD_EN11 : STATE_LOGIC
generic map(
INIT => X"F3F3F755A2A2A200"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => gaxi_full_sm_outstanding_read_r_15,
I4 => present_state_FSM_FFd2_14,
I5 => S_AXI_ARVALID,
O => S_AXI_RD_EN
);
present_state_FSM_FFd1_In3 : beh_muxf7
port map (
I0 => N8,
I1 => N9,
S => present_state_FSM_FFd1_13,
O => present_state_FSM_FFd1_In
);
present_state_FSM_FFd1_In3_F : STATE_LOGIC
generic map(
INIT => X"000000005410F4F0"
)
port map (
I0 => S_AXI_RREADY,
I1 => present_state_FSM_FFd2_14,
I2 => S_AXI_ARVALID,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => '0',
O => N8
);
present_state_FSM_FFd1_In3_G : STATE_LOGIC
generic map(
INIT => X"0000000072FF7272"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N9
);
Mmux_gaxi_full_sm_ar_ready_c14 : beh_muxf7
port map (
I0 => N10,
I1 => N11,
S => present_state_FSM_FFd1_13,
O => gaxi_full_sm_ar_ready_c
);
Mmux_gaxi_full_sm_ar_ready_c14_F : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88A8"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => Mmux_gaxi_full_sm_ar_ready_c11,
I5 => '0',
O => N10
);
Mmux_gaxi_full_sm_ar_ready_c14_G : STATE_LOGIC
generic map(
INIT => X"000000008D008D8D"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N11
);
Mmux_S_AXI_R_LAST1 : beh_muxf7
port map (
I0 => N12,
I1 => N13,
S => present_state_FSM_FFd1_13,
O => NlwRenamedSig_OI_S_AXI_R_LAST
);
Mmux_S_AXI_R_LAST1_F : STATE_LOGIC
generic map(
INIT => X"0000000088088888"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N12
);
Mmux_S_AXI_R_LAST1_G : STATE_LOGIC
generic map(
INIT => X"00000000E400E4E4"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => S_AXI_R_LAST_INT,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N13
);
end STRUCTURE;
-------------------------------------------------------------------------------
-- Output Register Stage Entity
--
-- This module builds the output register stages of the memory. This module is
-- instantiated in the main memory module (blk_mem_gen_v8_3_1) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_output_stage IS
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_output_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6" and "virtex6l".
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
-- C_HAS_RST : Determines the presence of the RST port
-- C_RSTRAM : Determines if special reset behavior is used
-- C_RST_PRIORITY : Determines the priority between CE and SR
-- C_INIT_VAL : Initialization value
-- C_HAS_EN : Determines the presence of the EN port
-- C_HAS_REGCE : Determines the presence of the REGCE port
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
-- of the RAM primitive
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- NUM_STAGES : Determines the number of output stages
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE output_stage_behavioral OF blk_mem_gen_v8_3_1_output_stage IS
--*******************************************************
-- Functions used in the output stage ARCHITECTURE
--*******************************************************
-- Calculate num_reg_stages
FUNCTION get_num_reg_stages(NUM_STAGES: INTEGER) RETURN INTEGER IS
VARIABLE num_reg_stages : INTEGER := 0;
BEGIN
IF (NUM_STAGES = 0) THEN
num_reg_stages := 0;
ELSE
num_reg_stages := NUM_STAGES - 1;
END IF;
RETURN num_reg_stages;
END get_num_reg_stages;
-- Check if the INTEGER is zero or non-zero
FUNCTION int_to_bit(input: INTEGER) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = 0) THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END int_to_bit;
-- Constants
CONSTANT HAS_EN : STD_LOGIC := int_to_bit(C_HAS_EN);
CONSTANT HAS_REGCE : STD_LOGIC := int_to_bit(C_HAS_REGCE);
CONSTANT HAS_RST : STD_LOGIC := int_to_bit(C_HAS_RST);
CONSTANT REG_STAGES : INTEGER := get_num_reg_stages(NUM_STAGES);
-- Pipeline array
TYPE reg_data_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
TYPE reg_ecc_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC;
TYPE reg_eccaddr_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
CONSTANT REG_INIT : reg_data_array := (OTHERS => init_val);
SIGNAL out_regs : reg_data_array := REG_INIT;
SIGNAL sbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL dbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL rdaddrecc_regs: reg_eccaddr_array := (OTHERS => (OTHERS => '0'));
-- Internal signals
SIGNAL en_i : STD_LOGIC;
SIGNAL regce_i : STD_LOGIC;
SIGNAL rst_i : STD_LOGIC;
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := init_val;
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL DIN : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL RDADDRECC_IN : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ;
SIGNAL SBITERR_IN : STD_LOGIC := '0';
SIGNAL DBITERR_IN : STD_LOGIC := '0';
BEGIN
--***********************************************************************
-- Assign internal signals. This effectively wires off optional inputs.
--***********************************************************************
-- Internal enable for output registers is tied to user EN or '1' depending
-- on parameters
en_i <= EN OR (NOT HAS_EN);
-- Internal register enable for output registers is tied to user REGCE, EN
-- or '1' depending on parameters
regce_i <= (HAS_REGCE AND REGCE)
OR ((NOT HAS_REGCE) AND en_i);
-- Internal SRR is tied to user RST or '0' depending on parameters
rst_i <= RST AND HAS_RST;
--***************************************************************************
-- NUM_STAGES = 0 (No output registers. RAM only)
--***************************************************************************
zero_stages: IF (NUM_STAGES = 0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE zero_stages;
NO_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 0) GENERATE
DIN <= DIN_I;
RDADDRECC_IN <= RDADDRECC_IN_I;
SBITERR_IN <= SBITERR_IN_I;
DBITERR_IN <= DBITERR_IN_I;
END GENERATE NO_ECC_PIPE_REG;
WITH_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(ECCPIPECE = '1') THEN
DIN <= DIN_I AFTER FLOP_DELAY;
RDADDRECC_IN <= RDADDRECC_IN_I AFTER FLOP_DELAY;
SBITERR_IN <= SBITERR_IN_I AFTER FLOP_DELAY;
DBITERR_IN <= DBITERR_IN_I AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS;
END GENERATE WITH_ECC_PIPE_REG;
--***************************************************************************
-- NUM_STAGES = 1
-- (Mem Output Reg only or Mux Output Reg only)
--***************************************************************************
-- Possible valid combinations:
-- Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
-- +-----------------------------------------+
-- | C_RSTRAM_* | Reset Behavior |
-- +----------------+------------------------+
-- | 0 | Normal Behavior |
-- +----------------+------------------------+
-- | 1 | Special Behavior |
-- +----------------+------------------------+
--
-- Normal = REGCE gates reset, as in the case of all Virtex families and all
-- spartan families with the exception of S3ADSP and S6.
-- Special = EN gates reset, as in the case of S3ADSP and S6.
one_stage_norm: IF (NUM_STAGES = 1 AND
(C_RSTRAM=0 OR (C_RSTRAM=1 AND (C_XDEVICEFAMILY/="spartan3adsp" AND C_XDEVICEFAMILY/="aspartan3adsp")) OR
C_HAS_MEM_OUTPUT_REGS=0 OR C_HAS_RST=0)) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i = '1' AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
END IF;--CLK
END PROCESS;
END GENERATE one_stage_norm;
-- Special Reset Behavior for S6 and S3ADSP
one_stage_splbhv: IF (NUM_STAGES=1 AND C_RSTRAM=1 AND (C_XDEVICEFAMILY ="spartan3adsp" OR C_XDEVICEFAMILY ="aspartan3adsp"))
GENERATE
DOUT <= dout_i;
SBITERR <= '0';
DBITERR <= '0';
RDADDRECC <= (OTHERS => '0');
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (rst_i='1' AND en_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
ELSIF (regce_i='1' AND rst_i/='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE one_stage_splbhv;
--****************************************************************************
-- NUM_STAGES > 1
-- Mem Output Reg + Mux Output Reg
-- or
-- Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
-- or
-- Mux Pipeline Stages (>0) + Mux Output Reg
--****************************************************************************
multi_stage: IF (NUM_STAGES > 1) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i='1'AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
IF (en_i='1') THEN
-- Shift the data through the output stages
FOR i IN 1 TO REG_STAGES-1 LOOP
out_regs(i) <= out_regs(i-1) AFTER FLOP_DELAY;
sbiterr_regs(i) <= sbiterr_regs(i-1) AFTER FLOP_DELAY;
dbiterr_regs(i) <= dbiterr_regs(i-1) AFTER FLOP_DELAY;
rdaddrecc_regs(i) <= rdaddrecc_regs(i-1) AFTER FLOP_DELAY;
END LOOP;
out_regs(0) <= DIN;
sbiterr_regs(0) <= SBITERR_IN;
dbiterr_regs(0) <= DBITERR_IN;
rdaddrecc_regs(0) <= RDADDRECC_IN;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE multi_stage;
END output_stage_behavioral;
-------------------------------------------------------------------------------
-- SoftECC Output Register Stage Entity
-- This module builds the softecc output register stages. This module is
-- instantiated in the memory module (blk_mem_gen_v8_3_1_mem_module) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ;
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- of the RAM primitive
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE softecc_output_reg_stage_behavioral OF blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
-- Internal signals
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
--***************************************************************************
-- NO OUTPUT STAGES
--***************************************************************************
no_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE no_output_stage;
--****************************************************************************
-- WITH OUTPUT STAGE
--****************************************************************************
has_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END PROCESS;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
END GENERATE has_output_stage;
END softecc_output_reg_stage_behavioral;
--******************************************************************************
-- Main Memory module
--
-- This module is the behavioral model which implements the RAM
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
ENTITY blk_mem_gen_v8_3_1_mem_module IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_mem_module;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE mem_module_behavioral OF blk_mem_gen_v8_3_1_mem_module IS
--****************************************
-- min/max constant functions
--****************************************
-- get_max
----------
function SLV_TO_INT(SLV: in std_logic_vector
) return integer is
variable int : integer;
begin
int := 0;
for i in SLV'high downto SLV'low loop
int := int * 2;
if SLV(i) = '1' then
int := int + 1;
end if;
end loop;
return int;
end;
FUNCTION get_max(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a > b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-- get_min
----------
FUNCTION get_min(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
--***************************************************************
-- convert write_mode from STRING type for use in case statement
--***************************************************************
FUNCTION write_mode_to_vector(mode: STRING) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF (mode = "NO_CHANGE") THEN
RETURN "10";
ELSIF (mode = "READ_FIRST") THEN
RETURN "01";
ELSE
RETURN "00"; -- WRITE_FIRST
END IF;
END FUNCTION;
--***************************************************************
-- convert hex STRING to STD_LOGIC_VECTOR
--***************************************************************
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
--***************************************************************
-- locally derived constants to determine memory shape
--***************************************************************
CONSTANT MIN_WIDTH_A : INTEGER := get_min(C_WRITE_WIDTH_A, C_READ_WIDTH_A);
CONSTANT MIN_WIDTH_B : INTEGER := get_min(C_WRITE_WIDTH_B,C_READ_WIDTH_B);
CONSTANT MIN_WIDTH : INTEGER := get_min(MIN_WIDTH_A, MIN_WIDTH_B);
CONSTANT MAX_DEPTH_A : INTEGER := get_max(C_WRITE_DEPTH_A, C_READ_DEPTH_A);
CONSTANT MAX_DEPTH_B : INTEGER := get_max(C_WRITE_DEPTH_B, C_READ_DEPTH_B);
CONSTANT MAX_DEPTH : INTEGER := get_max(MAX_DEPTH_A, MAX_DEPTH_B);
TYPE int_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF std_logic_vector(C_WRITE_WIDTH_A-1 DOWNTO 0);
TYPE mem_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC_VECTOR(MIN_WIDTH-1 DOWNTO 0);
TYPE ecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
TYPE softecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
--***************************************************************
-- memory initialization function
--***************************************************************
IMPURE FUNCTION init_memory(DEFAULT_DATA :
STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
write_width_a : INTEGER;
depth : INTEGER;
width : INTEGER)
RETURN mem_array IS
VARIABLE init_return : mem_array := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(write_width_a-1 DOWNTO 0);
VARIABLE int_mem_vector : int_array:= (OTHERS => (OTHERS => '0'));
VARIABLE file_buffer : LINE;
VARIABLE i : INTEGER := 0;
VARIABLE j : INTEGER;
VARIABLE k : INTEGER;
VARIABLE ignore_line : BOOLEAN := false;
VARIABLE good_data : BOOLEAN := false;
VARIABLE char_tmp : CHARACTER;
VARIABLE index : INTEGER;
variable init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable data : std_logic_vector(255 downto 0) := (others => '0');
variable inside_init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable k_slv : std_logic_vector(31 downto 0) := (others => '0');
variable i_slv : std_logic_vector(31 downto 0) := (others => '0');
VARIABLE disp_line : line := null;
variable open_status : file_open_status;
variable input_initf_tmp : mem_array ;
variable input_initf : mem_array := (others => (others => '0'));
file int_infile : text;
variable data_line, data_line_tmp, out_data_line : line;
variable slv_width : integer;
VARIABLE d_l : LINE;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
index := 0;
FOR i IN 0 TO depth-1 LOOP
FOR j IN 0 TO width-1 LOOP
init_return(i)(j) := DEFAULT_DATA(index);
index := (index + 1) MOD C_WRITE_WIDTH_A;
END LOOP;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, file_buffer);
read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO write_width_a-1 LOOP
IF (j MOD width = 0 AND j /= 0) THEN
i := i + 1;
END IF;
init_return(i)(j MOD width) := bit_to_sl(mem_vector(j));
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
--Display output message indicating that the behavioral model is done
--initializing
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator data initialization complete." SEVERITY NOTE;
if (C_USE_BRAM_BLOCK = 1) then
--Display output message indicating that the behavioral model is being
--initialized
-- Read in the .mem file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_INIT_FILE /= "NONE") then
file_open(open_status, int_infile, C_INIT_FILE, read_mode);
while not endfile(int_infile) loop
readline(int_infile, data_line);
while (data_line /= null and data_line'length > 0) loop
if (data_line(data_line'low to data_line'low + 1) = "//") then
deallocate(data_line);
elsif ((data_line(data_line'low to data_line'low + 1) = "/*") and (data_line(data_line'high-1 to data_line'high) = "*/")) then
deallocate(data_line);
elsif (data_line(data_line'low to data_line'low + 1) = "/*") then
deallocate(data_line);
ignore_line := true;
elsif (ignore_line = true and data_line(data_line'high-1 to data_line'high) = "*/") then
deallocate(data_line);
ignore_line := false;
elsif (ignore_line = false and data_line(data_line'low) = '@') then
read(data_line, char_tmp);
hread(data_line, init_addr_slv, good_data);
i := SLV_TO_INT(init_addr_slv);
elsif (ignore_line = false) then
hread(data_line, input_initf_tmp(i), good_data);
init_return(i)(write_width_a - 1 downto 0) := input_initf_tmp(i)(write_width_a - 1 downto 0);
if (good_data = true) then
i := i + 1;
end if;
else
deallocate(data_line);
end if;
end loop;
end loop;
file_close(int_infile);
END IF;
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- memory type constants
--***************************************************************
CONSTANT MEM_TYPE_SP_RAM : INTEGER := 0;
CONSTANT MEM_TYPE_SDP_RAM : INTEGER := 1;
CONSTANT MEM_TYPE_TDP_RAM : INTEGER := 2;
CONSTANT MEM_TYPE_SP_ROM : INTEGER := 3;
CONSTANT MEM_TYPE_DP_ROM : INTEGER := 4;
--***************************************************************
-- memory configuration constant functions
--***************************************************************
--get_single_port
-----------------
FUNCTION get_single_port(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_RAM OR mem_type=MEM_TYPE_SP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_single_port;
--get_is_rom
--------------
FUNCTION get_is_rom(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_ROM OR mem_type=MEM_TYPE_DP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_is_rom;
--get_has_a_write
------------------
FUNCTION get_has_a_write(IS_ROM : INTEGER) RETURN INTEGER IS
BEGIN
IF (IS_ROM=0) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_a_write;
--get_has_b_write
------------------
FUNCTION get_has_b_write(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_TDP_RAM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_write;
--get_has_a_read
------------------
FUNCTION get_has_a_read(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SDP_RAM) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_a_read;
--get_has_b_read
------------------
FUNCTION get_has_b_read(SINGLE_PORT : INTEGER) RETURN INTEGER IS
BEGIN
IF (SINGLE_PORT=1) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_b_read;
--get_has_b_port
------------------
FUNCTION get_has_b_port(HAS_B_READ : INTEGER;
HAS_B_WRITE : INTEGER)
RETURN INTEGER IS
BEGIN
IF (HAS_B_READ=1 OR HAS_B_WRITE=1) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_port;
--get_num_output_stages
-----------------------
FUNCTION get_num_output_stages(has_mem_output_regs : INTEGER;
has_mux_output_regs : INTEGER;
mux_pipeline_stages : INTEGER)
RETURN INTEGER IS
VARIABLE actual_mux_pipeline_stages : INTEGER;
BEGIN
-- Mux pipeline stages can be non-zero only when there is a mux
-- output register.
IF (has_mux_output_regs=1) THEN
actual_mux_pipeline_stages := mux_pipeline_stages;
ELSE
actual_mux_pipeline_stages := 0;
END IF;
RETURN has_mem_output_regs+actual_mux_pipeline_stages+has_mux_output_regs;
END get_num_output_stages;
--***************************************************************************
-- Component declaration of the VARIABLE depth output register stage
--***************************************************************************
COMPONENT blk_mem_gen_v8_3_1_output_stage
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
EN : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
ECCPIPECE : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_output_stage;
COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************************************
-- locally derived constants to assist memory access
--******************************************************
CONSTANT WRITE_WIDTH_RATIO_A : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_A : INTEGER := C_READ_WIDTH_A/MIN_WIDTH;
CONSTANT WRITE_WIDTH_RATIO_B : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_B : INTEGER := C_READ_WIDTH_B/MIN_WIDTH;
--******************************************************
-- To modify the LSBs of the 'wider' data to the actual
-- address value
--******************************************************
CONSTANT WRITE_ADDR_A_DIV : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH_A;
CONSTANT READ_ADDR_A_DIV : INTEGER := C_READ_WIDTH_A/MIN_WIDTH_A;
CONSTANT WRITE_ADDR_B_DIV : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH_B;
CONSTANT READ_ADDR_B_DIV : INTEGER := C_READ_WIDTH_B/MIN_WIDTH_B;
--******************************************************
-- FUNCTION : log2roundup
--******************************************************
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
--******************************************************
-- Other constants and signals
--******************************************************
CONSTANT COLL_DELAY : TIME := 100 ps;
-- default data vector
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_DEFAULT_DATA,
C_WRITE_WIDTH_A);
CONSTANT CHKBIT_WIDTH : INTEGER := if_then_else(C_WRITE_WIDTH_A>57,8,if_then_else(C_WRITE_WIDTH_A>26,7,if_then_else(C_WRITE_WIDTH_A>11,6,if_then_else(C_WRITE_WIDTH_A>4,5,if_then_else(C_WRITE_WIDTH_A<5,4,0)))));
-- the init memory SIGNAL
SIGNAL memory_i : mem_array;
SIGNAL doublebit_error_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0);
SIGNAL current_contents_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
-- write mode constants
CONSTANT WRITE_MODE_A : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_A);
CONSTANT WRITE_MODE_B : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_B);
CONSTANT WRITE_MODES : STD_LOGIC_VECTOR(3 DOWNTO 0) :=
WRITE_MODE_A & WRITE_MODE_B;
-- reset values
CONSTANT INITA_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITA_VAL,
C_READ_WIDTH_A);
CONSTANT INITB_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITB_VAL,
C_READ_WIDTH_B);
-- memory output 'latches'
SIGNAL memory_out_a : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0) :=
INITA_VAL;
SIGNAL memory_out_b : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) :=
INITB_VAL;
SIGNAL sbiterr_in : STD_LOGIC := '0';
SIGNAL sbiterr_sdp : STD_LOGIC := '0';
SIGNAL dbiterr_in : STD_LOGIC := '0';
SIGNAL dbiterr_sdp : STD_LOGIC := '0';
SIGNAL rdaddrecc_in : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_sdp : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL doutb_i : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i : STD_LOGIC := '0';
SIGNAL dbiterr_i : STD_LOGIC := '0';
-- memory configuration constants
-----------------------------------------------
CONSTANT SINGLE_PORT : INTEGER := get_single_port(C_MEM_TYPE);
CONSTANT IS_ROM : INTEGER := get_is_rom(C_MEM_TYPE);
CONSTANT HAS_A_WRITE : INTEGER := get_has_a_write(IS_ROM);
CONSTANT HAS_B_WRITE : INTEGER := get_has_b_write(C_MEM_TYPE);
CONSTANT HAS_A_READ : INTEGER := get_has_a_read(C_MEM_TYPE);
CONSTANT HAS_B_READ : INTEGER := get_has_b_read(SINGLE_PORT);
CONSTANT HAS_B_PORT : INTEGER := get_has_b_port(HAS_B_READ, HAS_B_WRITE);
CONSTANT NUM_OUTPUT_STAGES_A : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_A,
C_MUX_PIPELINE_STAGES);
CONSTANT NUM_OUTPUT_STAGES_B : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES);
CONSTANT WEA0 : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT WEB0 : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-----------------------------------------------------------------------------
-- DEBUG CONTROL
-- DEBUG=0 : Debug output OFF
-- DEBUG=1 : Some debug info printed
-----------------------------------------------------------------------------
CONSTANT DEBUG : INTEGER := 0;
-- internal signals
-----------------------------------------------
SIGNAL ena_i : STD_LOGIC;
SIGNAL enb_i : STD_LOGIC;
SIGNAL reseta_i : STD_LOGIC;
SIGNAL resetb_i : STD_LOGIC;
SIGNAL wea_i : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL web_i : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL rea_i : STD_LOGIC;
SIGNAL reb_i : STD_LOGIC;
SIGNAL message_complete : BOOLEAN := false;
SIGNAL rsta_outp_stage : STD_LOGIC := '0';
SIGNAL rstb_outp_stage : STD_LOGIC := '0';
--*********************************************************
--FUNCTION : Collision check
--*********************************************************
FUNCTION collision_check (addr_a :
STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
iswrite_a : BOOLEAN;
addr_b :
STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
iswrite_b : BOOLEAN)
RETURN BOOLEAN IS
VARIABLE c_aw_bw : INTEGER;
VARIABLE c_aw_br : INTEGER;
VARIABLE c_ar_bw : INTEGER;
VARIABLE write_addr_a_width : INTEGER;
VARIABLE read_addr_a_width : INTEGER;
VARIABLE write_addr_b_width : INTEGER;
VARIABLE read_addr_b_width : INTEGER;
BEGIN
c_aw_bw := 0;
c_aw_br := 0;
c_ar_bw := 0;
-- Determine the effective address widths FOR each of the 4 ports
write_addr_a_width := C_ADDRA_WIDTH-log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width := C_ADDRA_WIDTH-log2roundup(READ_ADDR_A_DIV);
write_addr_b_width := C_ADDRB_WIDTH-log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width := C_ADDRB_WIDTH-log2roundup(READ_ADDR_B_DIV);
--Look FOR a write-write collision. In order FOR a write-write
--collision to exist, both ports must have a write transaction.
IF (iswrite_a AND iswrite_b) THEN
IF (write_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_a and iswrite_b
--If the B port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_a) THEN
IF (write_addr_a_width > read_addr_b_width) THEN
--read_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_b_width
--Once both are scaled to read_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
END IF; --width
END IF; --iswrite_a
--If the A port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_b) THEN
IF (read_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
ELSE
--read_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_a_width
--Once both are scaled to read_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_b
RETURN (c_aw_bw=1 OR c_aw_br=1 OR c_ar_bw=1);
END FUNCTION collision_check;
BEGIN -- Architecture
-----------------------------------------------------------------------------
-- SOFTECC and ECC SBITERR/DBITERR Outputs
-- The ECC Behavior is modeled by the behavioral models only for Virtex-6.
-- The SOFTECC Behavior is modeled by the behavioral models for Spartan-6.
-- For Virtex-5, these outputs will be tied to 0.
-----------------------------------------------------------------------------
SBITERR <= sbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_sdp WHEN (((C_FAMILY="virtex7") AND C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
-----------------------------------------------
-- This effectively wires off optional inputs
-----------------------------------------------
ena_i <= ENA WHEN (C_HAS_ENA=1) ELSE '1';
enb_i <= ENB WHEN (C_HAS_ENB=1 AND HAS_B_PORT=1) ELSE '1';
-- We are doing an "AND" operation of WEA and ENA and passing to Enbale pin of BRAM when built-in ECC is enabled,
-- what this means is that the write operation happens only when both WEA and ENA are high.
wea_i <= WEA WHEN (HAS_A_WRITE=1 AND ena_i='1') ELSE WEA0;
-- wea_i <= (OTHERS => '1') WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=1 AND ENA = '1') ELSE -- Use_ENA_pin
-- WEA WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=0) ELSE -- Always_enabled
-- WEA WHEN (HAS_A_WRITE=1 AND ena_i='1' AND C_USE_ECC = 0) ELSE
-- WEA0;
web_i <= WEB WHEN (HAS_B_WRITE=1 AND enb_i='1') ELSE WEB0;
rea_i <= ena_i WHEN (HAS_A_READ=1) ELSE '0';
reb_i <= enb_i WHEN (HAS_B_READ=1) ELSE '0';
-- these signals reset the memory latches
-- For the special reset behaviors in some of the families, the C_RSTRAM
-- attribute of the corresponding port is used to indicate if the latch is
-- reset or not.
reseta_i <= RSTA WHEN
((C_HAS_RSTA=1 AND NUM_OUTPUT_STAGES_A=0) OR
(C_HAS_RSTA=1 AND C_RSTRAM_A=1))
ELSE '0';
resetb_i <= RSTB WHEN
((C_HAS_RSTB=1 AND NUM_OUTPUT_STAGES_B=0) OR
(C_HAS_RSTB=1 AND C_RSTRAM_B=1) )
ELSE '0';
--***************************************************************************
-- This is the main PROCESS which includes the memory VARIABLE and the read
-- and write procedures. It also schedules read and write operations
--***************************************************************************
PROCESS (CLKA, CLKB,rea_i,reb_i,reseta_i,resetb_i)
-- Initialize the init memory array
------------------------------------
VARIABLE memory : mem_array := init_memory(DEFAULT_DATA,
C_WRITE_WIDTH_A,
MAX_DEPTH,
MIN_WIDTH);
-- Initialize the mem memory array
------------------------------------
VARIABLE softecc_sbiterr_arr : softecc_err_array;
VARIABLE softecc_dbiterr_arr : softecc_err_array;
VARIABLE sbiterr_arr : ecc_err_array;
VARIABLE dbiterr_arr : ecc_err_array;
CONSTANT doublebit_lsb : STD_LOGIC_VECTOR (1 DOWNTO 0):="11";
CONSTANT doublebit_msb : STD_LOGIC_VECTOR (C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 DOWNTO 0):= (OTHERS => '0');
VARIABLE doublebit_error : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0) := doublebit_msb & doublebit_lsb ;
VARIABLE current_contents_var : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
--***********************************
-- procedures to access the memory
--***********************************
-- write_a
----------
PROCEDURE write_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
inj_sbiterr : IN STD_LOGIC;
inj_dbiterr : IN STD_LOGIC) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
VARIABLE message : LINE;
VARIABLE errbit_current_contents : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
-- Block Memory Generator non-cycle-accurate message
ASSERT (message_complete) REPORT "Block Memory Generator module is using a behavioral model FOR simulation which will not precisely model memory collision behavior."
SEVERITY NOTE;
message_complete <= true;
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_A_DIV);
IF (address_i >= C_WRITE_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range FOR A Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEA = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_A + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEA_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Insert double bit errors:
IF (C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
current_contents(0) := NOT(current_contents(0));
current_contents(1) := NOT(current_contents(1));
--current_contents(0) := NOT(current_contents(30));
--current_contents(1) := NOT(current_contents(62));
END IF;
END IF;
-- Insert double bit errors:
IF (C_USE_SOFTECC=1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 downto 2) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 downto 0);
doublebit_error(0) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1);
doublebit_error(1) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-2);
current_contents := current_contents XOR doublebit_error(C_WRITE_WIDTH_A-1 DOWNTO 0);
END IF;
END IF;
IF(DEBUG=1) THEN
current_contents_var := current_contents; --for debugging current
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_A + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
-- Store address at which error is injected:
IF ((C_FAMILY = "virtex7") AND C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
sbiterr_arr(address_i) := '1';
ELSE
sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
dbiterr_arr(address_i) := '1';
ELSE
dbiterr_arr(address_i) := '0';
END IF;
END IF;
-- Store address at which softecc error is injected:
IF (C_USE_SOFTECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
softecc_sbiterr_arr(address_i) := '1';
ELSE
softecc_sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
softecc_dbiterr_arr(address_i) := '1';
ELSE
softecc_dbiterr_arr(address_i) := '0';
END IF;
END IF;
END IF;
END PROCEDURE;
-- write_b
----------
PROCEDURE write_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_B_DIV);
IF (address_i >= C_WRITE_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEB = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_B + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEB_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_B + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
END IF;
END PROCEDURE;
-- read_a
----------
PROCEDURE read_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_A_DIV);
IF (address_i >= C_READ_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for A Read"
SEVERITY WARNING;
END IF;
memory_out_a <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_A-1 LOOP
memory_out_a(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_A + i) AFTER FLOP_DELAY;
END LOOP;
END IF;
END IF;
END PROCEDURE;
-- read_b
----------
PROCEDURE read_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_B_DIV);
IF (address_i >= C_READ_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Read"
SEVERITY WARNING;
END IF;
memory_out_b <= (OTHERS => 'X') AFTER FLOP_DELAY;
sbiterr_in <= 'X' AFTER FLOP_DELAY;
dbiterr_in <= 'X' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_B-1 LOOP
memory_out_b(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_B + i) AFTER FLOP_DELAY;
END LOOP;
--assert sbiterr and dbiterr signals
IF ((C_FAMILY="virtex7") AND C_USE_ECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
--assert softecc sbiterr and dbiterr signals
ELSIF (C_USE_SOFTECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (softecc_sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (softecc_dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
END IF;
END IF;
END IF;
END PROCEDURE;
-- reset_a
----------
PROCEDURE reset_a
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
-- reset_b
----------
PROCEDURE reset_b
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
BEGIN -- begin the main PROCESS
--***************************************************************************
-- These are the main blocks which schedule read and write operations
-- Note that the reset priority feature at the latch stage is only supported
-- for Spartan-6. For other families, the default priority at the latch stage
-- is "CE"
--***************************************************************************
-- Synchronous clocks: schedule port operations with respect to both
-- write operating modes
IF (C_COMMON_CLK=1) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODES IS
WHEN "0000" => -- write_first write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "0100" => -- read_first write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "0001" => -- write_first read_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0101" => --read_first read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0010" => -- write_first no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0110" => -- read_first no_change
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1000" => -- no_change write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "1001" => -- no_change read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1010" => -- no_change no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Synchronous clocks
-- Asynchronous clocks: port operation is independent
IF (C_COMMON_CLK=0) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODE_A IS
WHEN "00" => -- write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN "01" => -- read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "10" => -- no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
IF (CLKB='1' AND CLKB'EVENT) THEN
CASE WRITE_MODE_B IS
WHEN "00" => -- write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "01" => -- read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "10" => -- no_change
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Asynchronous clocks
-- Assign the memory VARIABLE to the user_visible memory_i SIGNAL
IF(DEBUG=1) THEN
memory_i <= memory;
doublebit_error_i <= doublebit_error;
current_contents_i <= current_contents_var;
END IF;
END PROCESS;
--********************************************************************
-- Instantiate the VARIABLE depth output stage
--********************************************************************
-- Port A
rsta_outp_stage <= RSTA and not sleep;
rstb_outp_stage <= RSTB and not sleep;
reg_a : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTA,
C_RSTRAM => C_RSTRAM_A,
C_RST_PRIORITY => C_RST_PRIORITY_A,
init_val => INITA_VAL,
C_HAS_EN => C_HAS_ENA,
C_HAS_REGCE => C_HAS_REGCEA,
C_DATA_WIDTH => C_READ_WIDTH_A,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_A,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_A,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKA,
RST => rsta_outp_stage, --RSTA,
EN => ENA,
REGCE => REGCEA,
DIN_I => memory_out_a,
DOUT => DOUTA,
SBITERR_IN_I => '0',
DBITERR_IN_I => '0',
SBITERR => OPEN,
DBITERR => OPEN,
RDADDRECC_IN_I => (OTHERS => '0'),
ECCPIPECE => '0',
RDADDRECC => OPEN
);
-- Port B
reg_b : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTB,
C_RSTRAM => C_RSTRAM_B,
C_RST_PRIORITY => C_RST_PRIORITY_B,
init_val => INITB_VAL,
C_HAS_EN => C_HAS_ENB,
C_HAS_REGCE => C_HAS_REGCEB,
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_B,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKB,
RST => rstb_outp_stage,--RSTB,
EN => ENB,
REGCE => REGCEB,
DIN_I => memory_out_b,
DOUT => doutb_i,
SBITERR_IN_I => sbiterr_in,
DBITERR_IN_I => dbiterr_in,
SBITERR => sbiterr_i,
DBITERR => dbiterr_i,
RDADDRECC_IN_I => rdaddrecc_in,
ECCPIPECE => ECCPIPECE,
RDADDRECC => rdaddrecc_i
);
--********************************************************************
-- Instantiate the input / Output Register stages
--********************************************************************
output_reg_stage: blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC MAP(
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP(
CLK => CLKB,
DIN => doutb_i,
DOUT => DOUTB,
SBITERR_IN => sbiterr_i,
DBITERR_IN => dbiterr_i,
SBITERR => sbiterr_sdp,
DBITERR => dbiterr_sdp,
RDADDRECC_IN => rdaddrecc_i,
RDADDRECC => rdaddrecc_sdp
);
--*********************************
-- Synchronous collision checks
--*********************************
sync_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=1) GENERATE
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
-- collision detect
VARIABLE is_collision : BOOLEAN;
VARIABLE message : LINE;
BEGIN
IF (CLKA='1' AND CLKA'EVENT) THEN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision := false;
END IF;
-- If the write port is in READ_FIRST mode, there is no collision
IF (C_WRITE_MODE_A="READ_FIRST" AND wea_i/=WEA0 AND web_i=WEB0) THEN
is_collision := false;
END IF;
IF (C_WRITE_MODE_B="READ_FIRST" AND web_i/=WEB0 AND wea_i=WEA0) THEN
is_collision := false;
END IF;
-- Only flag if one of the accesses is a write
IF (is_collision AND (wea_i/=WEA0 OR web_i/=WEB0)) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END IF;
END PROCESS;
END GENERATE;
--*********************************
-- Asynchronous collision checks
--*********************************
async_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=0) GENERATE
SIGNAL addra_delay : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL wea_delay : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL ena_delay : STD_LOGIC;
SIGNAL addrb_delay : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
SIGNAL web_delay : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL enb_delay : STD_LOGIC;
BEGIN
-- Delay A and B addresses in order to mimic setup/hold times
PROCESS (ADDRA, wea_i, ena_i, ADDRB, web_i, enb_i)
BEGIN
addra_delay <= ADDRA AFTER COLL_DELAY;
wea_delay <= wea_i AFTER COLL_DELAY;
ena_delay <= ena_i AFTER COLL_DELAY;
addrb_delay <= ADDRB AFTER COLL_DELAY;
web_delay <= web_i AFTER COLL_DELAY;
enb_delay <= enb_i AFTER COLL_DELAY;
END PROCESS;
-- Do the checks w/rt A
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_a : BOOLEAN;
VARIABLE is_collision_delay_a : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_a := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_a := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_delay_a := collision_check(ADDRA,
wea_i/=WEA0,
addrb_delay,
web_delay/=WEB0);
ELSE
is_collision_delay_a := false;
END IF;
-- Only flag if B access is a write
IF (is_collision_a AND web_i/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_a AND web_delay/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, addrb_delay);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
-- Do the checks w/rt B
PROCESS (CLKB)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_b : BOOLEAN;
VARIABLE is_collision_delay_b : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA) /= 'X') THEN
is_collision_b := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_b := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(addra_delay) /= 'X') THEN
is_collision_delay_b := collision_check(addra_delay,
wea_delay/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_delay_b := false;
END IF;
-- Only flag if A access is a write
-- Modified condition checking (is_collision_b AND WEA0_i=/WEA0) to fix CR526228
IF (is_collision_b AND wea_i/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_b AND wea_delay/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, addra_delay);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
END GENERATE;
END mem_module_behavioral;
--******************************************************************************
-- Top module that wraps SoftECC Input register stage and the main memory module
--
-- This module is the top-level of behavioral model
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1 IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_CTRL_ECC_ALGO : STRING := "NONE";
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
--C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_SLEEP_PIN : INTEGER := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
PORT (
clka : IN STD_LOGIC := '0';
rsta : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '1';
regcea : IN STD_LOGIC := '1';
wea : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addra : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
dina : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
douta : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
clkb : IN STD_LOGIC := '0';
rstb : IN STD_LOGIC := '0';
enb : IN STD_LOGIC := '1';
regceb : IN STD_LOGIC := '1';
web : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addrb : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
dinb : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
doutb : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
injectsbiterr : IN STD_LOGIC := '0';
injectdbiterr : IN STD_LOGIC := '0';
sbiterr : OUT STD_LOGIC := '0';
dbiterr : OUT STD_LOGIC := '0';
rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : in std_logic := '0';
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic := '0';
rstb_busy : out std_logic := '0';
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
s_aclk : IN STD_LOGIC := '0';
s_aresetn : IN STD_LOGIC := '0';
-- axi full/lite slave Write (write side)
s_axi_awid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid : IN STD_LOGIC := '0';
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast : IN STD_LOGIC := '0';
s_axi_wvalid : IN STD_LOGIC := '0';
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC := '0';
-- axi full/lite slave Read (Write side)
s_axi_arid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid : IN STD_LOGIC := '0';
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_rdata : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC := '0';
-- axi full/lite sideband Signals
s_axi_injectsbiterr : IN STD_LOGIC := '0';
s_axi_injectdbiterr : IN STD_LOGIC := '0';
s_axi_sbiterr : OUT STD_LOGIC := '0';
s_axi_dbiterr : OUT STD_LOGIC := '0';
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END blk_mem_gen_v8_3_1;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE behavioral OF blk_mem_gen_v8_3_1 IS
COMPONENT blk_mem_gen_v8_3_1_mem_module
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_mem_module;
COMPONENT blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_axi_regs_fwd_v8_3;
COMPONENT blk_mem_axi_read_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT blk_mem_axi_read_wrapper_beh;
COMPONENT blk_mem_axi_write_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END COMPONENT blk_mem_axi_write_wrapper_beh;
CONSTANT FLOP_DELAY : TIME := 100 ps;
SIGNAL rsta_in : STD_LOGIC := '1';
SIGNAL ena_in : STD_LOGIC := '1';
SIGNAL regcea_in : STD_LOGIC := '1';
SIGNAL wea_in : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL addra_in : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL dina_in : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL injectsbiterr_in : STD_LOGIC := '0';
SIGNAL injectdbiterr_in : STD_LOGIC := '0';
-----------------------------------------------------------------------------
-- FUNCTION: toLowerCaseChar
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
-----------------------------------------------------------------------------
FUNCTION toLowerCaseChar(
char : character )
RETURN character IS
BEGIN
-- If char is not an upper case letter then return char
IF char<'A' OR char>'Z' THEN
RETURN char;
END IF;
-- Otherwise map char to its corresponding lower case character and
-- RETURN that
CASE char IS
WHEN 'A' => RETURN 'a';
WHEN 'B' => RETURN 'b';
WHEN 'C' => RETURN 'c';
WHEN 'D' => RETURN 'd';
WHEN 'E' => RETURN 'e';
WHEN 'F' => RETURN 'f';
WHEN 'G' => RETURN 'g';
WHEN 'H' => RETURN 'h';
WHEN 'I' => RETURN 'i';
WHEN 'J' => RETURN 'j';
WHEN 'K' => RETURN 'k';
WHEN 'L' => RETURN 'l';
WHEN 'M' => RETURN 'm';
WHEN 'N' => RETURN 'n';
WHEN 'O' => RETURN 'o';
WHEN 'P' => RETURN 'p';
WHEN 'Q' => RETURN 'q';
WHEN 'R' => RETURN 'r';
WHEN 'S' => RETURN 's';
WHEN 'T' => RETURN 't';
WHEN 'U' => RETURN 'u';
WHEN 'V' => RETURN 'v';
WHEN 'W' => RETURN 'w';
WHEN 'X' => RETURN 'x';
WHEN 'Y' => RETURN 'y';
WHEN 'Z' => RETURN 'z';
WHEN OTHERS => RETURN char;
END CASE;
END toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
FUNCTION equalIgnoreCase(
str1 : STRING;
str2 : STRING )
RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str2'left TO str1'right LOOP
IF NOT (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equalIgnoreCase;
-----------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
----------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
----------------------------------------------------------------------------
-- FUNCTION : log2roundup
----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
CONSTANT lower_limit : INTEGER := 1;
CONSTANT upper_limit : INTEGER := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
-----------------------------------------------------------------------------
-- FUNCTION : divroundup
-- Returns the ceiling value of the division
-- Data_value - the quantity to be divided, dividend
-- Divisor - the value to divide the data_value by
-----------------------------------------------------------------------------
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
SIGNAL s_axi_awaddr_out_c : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_araddr_out_c : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_wr_en_c : STD_LOGIC := '0';
SIGNAL s_axi_rd_en_c : STD_LOGIC := '0';
SIGNAL s_aresetn_a_c : STD_LOGIC := '0';
--**************************************************************************
-- AXI PARAMETERS
CONSTANT AXI_FULL_MEMORY_SLAVE : integer := if_then_else((C_AXI_SLAVE_TYPE = 0 AND C_AXI_TYPE = 1),1,0);
CONSTANT C_AXI_ADDR_WIDTH_MSB : integer := C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
CONSTANT C_AXI_ADDR_WIDTH : integer := C_AXI_ADDR_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT LOWER_BOUND_VAL : integer := if_then_else((log2roundup(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT C_AXI_ADDR_WIDTH_LSB : integer := if_then_else((AXI_FULL_MEMORY_SLAVE = 1),0,LOWER_BOUND_VAL);
CONSTANT C_AXI_OS_WR : integer := 2;
-- SAFETY LOGIC related Signals
SIGNAL RSTA_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_A : STD_LOGIC := '0';
SIGNAL RSTB_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_B : STD_LOGIC := '0';
SIGNAL ENA_dly : STD_LOGIC := '0';
SIGNAL ENA_dly_D : STD_LOGIC := '0';
SIGNAL ENB_dly : STD_LOGIC := '0';
SIGNAL ENB_dly_D : STD_LOGIC := '0';
SIGNAL RSTA_I_SAFE : STD_LOGIC := '0';
SIGNAL RSTB_I_SAFE : STD_LOGIC := '0';
SIGNAL ENA_I_SAFE : STD_LOGIC := '0';
SIGNAL ENB_I_SAFE : STD_LOGIC := '0';
SIGNAL ram_rstram_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstram_b_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_b_busy : STD_LOGIC := '0';
SIGNAL ENA_dly_reg : STD_LOGIC := '0';
SIGNAL ENB_dly_reg : STD_LOGIC := '0';
SIGNAL ENA_dly_reg_D : STD_LOGIC := '0';
SIGNAL ENB_dly_reg_D : STD_LOGIC := '0';
--**************************************************************************
BEGIN -- Architecture
--*************************************************************************
-- NO INPUT STAGE
--*************************************************************************
no_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=0) GENERATE
rsta_in <= RSTA;
ena_in <= ENA;
regcea_in <= REGCEA;
wea_in <= WEA;
addra_in <= ADDRA;
dina_in <= DINA;
injectsbiterr_in <= INJECTSBITERR;
injectdbiterr_in <= INJECTDBITERR;
END GENERATE no_input_stage;
--**************************************************************************
-- WITH INPUT STAGE
--**************************************************************************
has_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=1) GENERATE
PROCESS (CLKA)
BEGIN
IF (CLKA'EVENT AND CLKA = '1') THEN
rsta_in <= RSTA AFTER FLOP_DELAY;
ena_in <= ENA AFTER FLOP_DELAY;
regcea_in <= REGCEA AFTER FLOP_DELAY;
wea_in <= WEA AFTER FLOP_DELAY;
addra_in <= ADDRA AFTER FLOP_DELAY;
dina_in <= DINA AFTER FLOP_DELAY;
injectsbiterr_in <= INJECTSBITERR AFTER FLOP_DELAY;
injectdbiterr_in <= INJECTDBITERR AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE has_input_stage;
--**************************************************************************
-- NO SAFETY LOGIC
--**************************************************************************
NO_SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 0) GENERATE
ENA_I_SAFE <= ena_in;
ENB_I_SAFE <= ENB;
RSTA_I_SAFE <= rsta_in;
RSTB_I_SAFE <= RSTB;
END GENERATE NO_SAFETY_CKT_GEN;
--**************************************************************************
-- SAFETY LOGIC
--**************************************************************************
SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 1) GENERATE
-- RESET SAFETY LOGIC Generation
-- POR Generation
------------------------------------------------------------------------------
-- Power-ON Reset Generation
------------------------------------------------------------------------------
RST_SHFT_LOGIC_A : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
RSTA_SHFT_REG(4 DOWNTO 0) <= RSTA_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_A;
POR_RSTA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
POR_A <= RSTA_SHFT_REG(4) xor RSTA_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTA_GEN;
RST_SHFT_LOGIC_B : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
RSTB_SHFT_REG(4 DOWNTO 0) <= RSTB_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_B;
POR_RSTB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
POR_B <= RSTB_SHFT_REG(4) xor RSTB_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTB_GEN;
-----------------------------------------------------------------------------
-- Fix for the AR42571
-----------------------------------------------------------------------------
-- Reset Generation
-----------------------------------------------------------------------------
RSTA_I_SAFE <= rsta_in OR POR_A;
SPRAM_RST: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_I_SAFE <= '0';
END GENERATE SPRAM_RST;
nSPRAM_RST: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_I_SAFE <= RSTB OR POR_B;
END GENERATE nSPRAM_RST;
-----------------------------------------------------------------------------
-- RSTA/B_BUSY Generation
-----------------------------------------------------------------------------
RSTA_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
ram_rstram_a_busy <= rsta_in OR ENA_dly OR ENA_dly_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstram_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_NO_REG;
RSTA_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
ram_rstreg_a_busy <= rsta_in OR ENA_dly OR ENA_dly_reg_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstreg_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_WITH_REG;
SPRAM_RST_BUSY: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_BUSY <= '0';
END GENERATE SPRAM_RST_BUSY;
nSPRAM_RST_BUSY: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
ram_rstram_b_busy <= RSTB OR ENB_dly OR ENB_dly_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstram_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_NO_REG;
RSTB_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
ram_rstreg_b_busy <= RSTB OR ENB_dly OR ENB_dly_reg_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstreg_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_WITH_REG;
END GENERATE nSPRAM_RST_BUSY;
-----------------------------------------------------------------------------
-- ENA/ENB Generation
-----------------------------------------------------------------------------
ENA_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly <= rsta_in AFTER FLOP_DELAY;
ENA_dly_D <= ENA_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_D OR ena_in;
END GENERATE ENA_NO_REG;
ENA_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly_reg <= rsta_in AFTER FLOP_DELAY;
ENA_dly_reg_D <= ENA_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_reg_D OR ena_in;
END GENERATE ENA_WITH_REG;
SPRAM_ENB: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
ENB_I_SAFE <= '0';
END GENERATE SPRAM_ENB;
nSPRAM_ENB: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
ENB_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly <= RSTB AFTER FLOP_DELAY;
ENB_dly_D <= ENB_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_D OR ENB;
END GENERATE ENB_NO_REG;
ENB_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly_reg <= RSTB AFTER FLOP_DELAY;
ENB_dly_reg_D <= ENB_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_reg_D OR ENB;
END GENERATE ENB_WITH_REG;
END GENERATE nSPRAM_ENB;
END GENERATE SAFETY_CKT_GEN;
--**************************************************************************
-- NATIVE MEMORY MODULE INSTANCE
--**************************************************************************
native_mem_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 0) GENERATE
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,--rsta_in,
ENA => ENA_I_SAFE,--ena_in,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in,
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => RDADDRECC
);
END GENERATE native_mem_module;
--**************************************************************************
-- NATIVE MEMORY MAPPED MODULE INSTANCE
--**************************************************************************
native_mem_map_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 1) GENERATE
--**************************************************************************
-- NATIVE MEMORY MAPPED PARAMETERS
CONSTANT C_ADDRA_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_A);
CONSTANT C_ADDRB_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_B);
CONSTANT C_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
CONSTANT C_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
CONSTANT C_MEM_MAP_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_MSB;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT MEM_MAP_LOWER_BOUND_VAL_A : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT MEM_MAP_LOWER_BOUND_VAL_B : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_B,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_B,8)));
CONSTANT C_MEM_MAP_ADDRA_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_A;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_B;
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH_ACTUAL-1 DOWNTO 0) := (OTHERS => '0');
--**************************************************************************
BEGIN
RDADDRECC(C_ADDRB_WIDTH-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_MSB) <= (OTHERS => '0');
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB) <= rdaddrecc_i;
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_LSB-1 DOWNTO 0) <= (OTHERS => '0');
mem_map_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH_ACTUAL,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH_ACTUAL,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,
ENA => ENA_I_SAFE,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in(C_MEM_MAP_ADDRA_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRA_WIDTH_LSB),
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB),
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => rdaddrecc_i
);
END GENERATE native_mem_map_module;
--****************************************************************************
-- AXI MEMORY MODULE INSTANCE
--****************************************************************************
axi_mem_module: IF (C_INTERFACE_TYPE = 1) GENERATE
SIGNAL s_axi_rid_c : STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rdata_c : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rresp_c : STD_LOGIC_VECTOR(2-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rlast_c : STD_LOGIC := '0';
SIGNAL s_axi_rvalid_c : STD_LOGIC := '0';
SIGNAL s_axi_rready_c : STD_LOGIC := '0';
SIGNAL regceb_c : STD_LOGIC := '0';
BEGIN
s_aresetn_a_c <= NOT S_ARESETN;
S_AXI_BRESP <= (OTHERS => '0');
s_axi_rresp_c <= (OTHERS => '0');
no_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 0 AND C_HAS_MUX_OUTPUT_REGS_B = 0 ) GENERATE
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RLAST <= s_axi_rlast_c;
S_AXI_RVALID <= s_axi_rvalid_c;
S_AXI_RID <= s_axi_rid_c;
S_AXI_RRESP <= s_axi_rresp_c;
s_axi_rready_c <= S_AXI_RREADY;
END GENERATE no_regs;
has_regs_fwd: IF (C_HAS_MUX_OUTPUT_REGS_B = 1 OR C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
CONSTANT C_AXI_PAYLOAD : INTEGER := if_then_else((C_HAS_MUX_OUTPUT_REGS_B = 1),C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3,C_AXI_ID_WIDTH+3);
SIGNAL s_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
has_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
regceb_c <= s_axi_rvalid_c AND s_axi_rready_c;
END GENERATE has_regceb;
no_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 0) GENERATE
regceb_c <= REGCEB;
END GENERATE no_regceb;
only_core_op_regs: IF (C_HAS_MUX_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rdata_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RDATA <= m_axi_payload_c(C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_core_op_regs;
only_emb_op_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_emb_op_regs;
axi_regs_inst : blk_mem_axi_regs_fwd_v8_3
GENERIC MAP(
C_DATA_WIDTH => C_AXI_PAYLOAD
)
PORT MAP (
ACLK => S_ACLK,
ARESET => s_aresetn_a_c,
S_VALID => s_axi_rvalid_c,
S_READY => s_axi_rready_c,
S_PAYLOAD_DATA => s_axi_payload_c,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY,
M_PAYLOAD_DATA => m_axi_payload_c
);
END GENERATE has_regs_fwd;
axi_wr_fsm : blk_mem_axi_write_wrapper_beh
GENERIC MAP(
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_AXI_AWADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_WDATA_WIDTH => C_WRITE_WIDTH_A,
C_AXI_OS_WR => C_AXI_OS_WR
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Slave Write Interface
S_AXI_AWADDR => S_AXI_AWADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_AWLEN => S_AXI_AWLEN,
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BID => S_AXI_BID,
-- Signals for BRAM interface
S_AXI_AWADDR_OUT =>s_axi_awaddr_out_c,
S_AXI_WR_EN =>s_axi_wr_en_c
);
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => 1, -- For AXI, Read Enable is always C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => 1, -- For AXI C_USE_BYTE_WEA is always 1,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => 1, -- For AXI, Read Enable is always C_HAS_ENB,
C_HAS_REGCEB => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_BYTE_WEB => 1, -- For AXI C_USE_BYTE_WEB is always 1,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => 0, --For AXI, Primitive Registers A is not supported C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => 0,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
--Port A:
CLKA => S_AClk,
RSTA => s_aresetn_a_c,
ENA => s_axi_wr_en_c,
REGCEA => regcea_in,
WEA => S_AXI_WSTRB,
ADDRA => s_axi_awaddr_out_c,
DINA => S_AXI_WDATA,
DOUTA => DOUTA,
--Port B:
CLKB => S_AClk,
RSTB => s_aresetn_a_c,
ENB => s_axi_rd_en_c,
REGCEB => regceb_c,
WEB => (OTHERS => '0'),
ADDRB => s_axi_araddr_out_c,
DINB => DINB,
DOUTB => s_axi_rdata_c,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => '0',
SLEEP => '0',
RDADDRECC => RDADDRECC
);
axi_rd_sm : blk_mem_axi_read_wrapper_beh
GENERIC MAP (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_PIPELINE_STAGES => 1,
C_AXI_ARADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_AClk,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Read Side
S_AXI_ARADDR => S_AXI_ARADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARSIZE => S_AXI_ARSIZE,
S_AXI_ARBURST => S_AXI_ARBURST,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => s_axi_rlast_c,
S_AXI_RVALID => s_axi_rvalid_c,
S_AXI_RREADY => s_axi_rready_c,
S_AXI_ARID => S_AXI_ARID,
S_AXI_RID => s_axi_rid_c,
-- AXI Full/Lite Read FSM Outputs
S_AXI_ARADDR_OUT => s_axi_araddr_out_c,
S_AXI_RD_EN => s_axi_rd_en_c
);
END GENERATE axi_mem_module;
END behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_clr is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_clr;
architecture beh_ff_clr_arch of beh_ff_clr is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(CLR, C)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_clr_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_ce is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_ce;
architecture beh_ff_ce_arch of beh_ff_ce is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, CLR)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
if (CE = '1') then
q_o <= D after 100 ps;
end if;
end if;
end process;
end beh_ff_ce_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_pre is
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end beh_ff_pre;
architecture beh_ff_pre_arch of beh_ff_pre is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, PRE)
begin
if (PRE = '1') then
q_o <= '1';
elsif (C' event and C = '1') then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_pre_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_muxf7 is
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end beh_muxf7;
architecture beh_muxf7_arch of beh_muxf7 is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
else
O <= I1;
end if;
end process;
end beh_muxf7_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity STATE_LOGIC is
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic := '0';
I0 : in std_logic := '0';
I1 : in std_logic := '0';
I2 : in std_logic := '0';
I3 : in std_logic := '0';
I4 : in std_logic := '0';
I5 : in std_logic := '0'
);
end STATE_LOGIC;
architecture STATE_LOGIC_arch of STATE_LOGIC is
constant INIT_reg : std_logic_vector(63 downto 0) := INIT;
begin
LUT_beh:process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
begin
I_reg := I5 & I4 & I3 & I2 & I1 & I0;
O <= INIT_reg(conv_integer(I_reg));
end process;
end STATE_LOGIC_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2036.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02036ent IS
END c07s02b04x00p01n01i02036ent;
ARCHITECTURE c07s02b04x00p01n01i02036arch OF c07s02b04x00p01n01i02036ent IS
BEGIN
TESTING: PROCESS
variable BOOLV : BOOLEAN := FALSE;
BEGIN
BOOLV := BOOLV + BOOLV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02036 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02036arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2036.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02036ent IS
END c07s02b04x00p01n01i02036ent;
ARCHITECTURE c07s02b04x00p01n01i02036arch OF c07s02b04x00p01n01i02036ent IS
BEGIN
TESTING: PROCESS
variable BOOLV : BOOLEAN := FALSE;
BEGIN
BOOLV := BOOLV + BOOLV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02036 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02036arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2036.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02036ent IS
END c07s02b04x00p01n01i02036ent;
ARCHITECTURE c07s02b04x00p01n01i02036arch OF c07s02b04x00p01n01i02036ent IS
BEGIN
TESTING: PROCESS
variable BOOLV : BOOLEAN := FALSE;
BEGIN
BOOLV := BOOLV + BOOLV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02036 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02036arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.mem_bus_master_bfm_pkg.all;
library std;
use std.textio.all;
entity mem_bus_master_bfm is
generic (
g_name : string );
port (
clock : in std_logic;
req : out t_mem_req := c_mem_req_init;
resp : in t_mem_resp );
end mem_bus_master_bfm;
architecture bfm of mem_bus_master_bfm is
shared variable this : p_mem_bus_master_bfm_object := null;
signal bound : boolean := false;
type t_state is (idle, wait_for_rack, wait_for_data);
signal state : t_state := idle;
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_mem_bus_master_bfm(g_name, this);
bound <= true;
wait;
end process;
process
procedure check_command is
begin
if this.command = e_mem_read then
req.tag <= this.tag;
req.address <= this.address;
req.request <= '1';
req.read_writen <= '1';
state <= wait_for_data;
elsif this.command = e_mem_write then
req.tag <= this.tag;
req.address <= this.address;
req.request <= '1';
req.read_writen <= '0';
req.data <= this.data;
state <= wait_for_rack;
else
req.request <= '0';
req.data <= (others => '1');
req.address <= (others => '1');
state <= idle;
end if;
end procedure;
begin
wait until rising_edge(clock);
case state is
when idle =>
req <= c_mem_req_init;
req.data <= (others => '1');
req.address <= (others => '1');
if bound then
check_command;
end if;
when wait_for_rack =>
if resp.rack='1' then
this.command := e_mem_none;
wait for 2*this.poll_time;
check_command;
end if;
when wait_for_data =>
if resp.rack='1' then
req.request <= '0';
req.address <= (others => '1');
end if;
if to_integer(unsigned(resp.dack_tag)) /= 0 then
this.data := resp.data;
this.command := e_mem_none;
wait for 2*this.poll_time;
check_command;
end if;
when others =>
null;
end case;
end process;
end bfm;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.mem_bus_master_bfm_pkg.all;
library std;
use std.textio.all;
entity mem_bus_master_bfm is
generic (
g_name : string );
port (
clock : in std_logic;
req : out t_mem_req := c_mem_req_init;
resp : in t_mem_resp );
end mem_bus_master_bfm;
architecture bfm of mem_bus_master_bfm is
shared variable this : p_mem_bus_master_bfm_object := null;
signal bound : boolean := false;
type t_state is (idle, wait_for_rack, wait_for_data);
signal state : t_state := idle;
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_mem_bus_master_bfm(g_name, this);
bound <= true;
wait;
end process;
process
procedure check_command is
begin
if this.command = e_mem_read then
req.tag <= this.tag;
req.address <= this.address;
req.request <= '1';
req.read_writen <= '1';
state <= wait_for_data;
elsif this.command = e_mem_write then
req.tag <= this.tag;
req.address <= this.address;
req.request <= '1';
req.read_writen <= '0';
req.data <= this.data;
state <= wait_for_rack;
else
req.request <= '0';
req.data <= (others => '1');
req.address <= (others => '1');
state <= idle;
end if;
end procedure;
begin
wait until rising_edge(clock);
case state is
when idle =>
req <= c_mem_req_init;
req.data <= (others => '1');
req.address <= (others => '1');
if bound then
check_command;
end if;
when wait_for_rack =>
if resp.rack='1' then
this.command := e_mem_none;
wait for 2*this.poll_time;
check_command;
end if;
when wait_for_data =>
if resp.rack='1' then
req.request <= '0';
req.address <= (others => '1');
end if;
if to_integer(unsigned(resp.dack_tag)) /= 0 then
this.data := resp.data;
this.command := e_mem_none;
wait for 2*this.poll_time;
check_command;
end if;
when others =>
null;
end case;
end process;
end bfm;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.mem_bus_master_bfm_pkg.all;
library std;
use std.textio.all;
entity mem_bus_master_bfm is
generic (
g_name : string );
port (
clock : in std_logic;
req : out t_mem_req := c_mem_req_init;
resp : in t_mem_resp );
end mem_bus_master_bfm;
architecture bfm of mem_bus_master_bfm is
shared variable this : p_mem_bus_master_bfm_object := null;
signal bound : boolean := false;
type t_state is (idle, wait_for_rack, wait_for_data);
signal state : t_state := idle;
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_mem_bus_master_bfm(g_name, this);
bound <= true;
wait;
end process;
process
procedure check_command is
begin
if this.command = e_mem_read then
req.tag <= this.tag;
req.address <= this.address;
req.request <= '1';
req.read_writen <= '1';
state <= wait_for_data;
elsif this.command = e_mem_write then
req.tag <= this.tag;
req.address <= this.address;
req.request <= '1';
req.read_writen <= '0';
req.data <= this.data;
state <= wait_for_rack;
else
req.request <= '0';
req.data <= (others => '1');
req.address <= (others => '1');
state <= idle;
end if;
end procedure;
begin
wait until rising_edge(clock);
case state is
when idle =>
req <= c_mem_req_init;
req.data <= (others => '1');
req.address <= (others => '1');
if bound then
check_command;
end if;
when wait_for_rack =>
if resp.rack='1' then
this.command := e_mem_none;
wait for 2*this.poll_time;
check_command;
end if;
when wait_for_data =>
if resp.rack='1' then
req.request <= '0';
req.address <= (others => '1');
end if;
if to_integer(unsigned(resp.dack_tag)) /= 0 then
this.data := resp.data;
this.command := e_mem_none;
wait for 2*this.poll_time;
check_command;
end if;
when others =>
null;
end case;
end process;
end bfm;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.mem_bus_master_bfm_pkg.all;
library std;
use std.textio.all;
entity mem_bus_master_bfm is
generic (
g_name : string );
port (
clock : in std_logic;
req : out t_mem_req := c_mem_req_init;
resp : in t_mem_resp );
end mem_bus_master_bfm;
architecture bfm of mem_bus_master_bfm is
shared variable this : p_mem_bus_master_bfm_object := null;
signal bound : boolean := false;
type t_state is (idle, wait_for_rack, wait_for_data);
signal state : t_state := idle;
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_mem_bus_master_bfm(g_name, this);
bound <= true;
wait;
end process;
process
procedure check_command is
begin
if this.command = e_mem_read then
req.tag <= this.tag;
req.address <= this.address;
req.request <= '1';
req.read_writen <= '1';
state <= wait_for_data;
elsif this.command = e_mem_write then
req.tag <= this.tag;
req.address <= this.address;
req.request <= '1';
req.read_writen <= '0';
req.data <= this.data;
state <= wait_for_rack;
else
req.request <= '0';
req.data <= (others => '1');
req.address <= (others => '1');
state <= idle;
end if;
end procedure;
begin
wait until rising_edge(clock);
case state is
when idle =>
req <= c_mem_req_init;
req.data <= (others => '1');
req.address <= (others => '1');
if bound then
check_command;
end if;
when wait_for_rack =>
if resp.rack='1' then
this.command := e_mem_none;
wait for 2*this.poll_time;
check_command;
end if;
when wait_for_data =>
if resp.rack='1' then
req.request <= '0';
req.address <= (others => '1');
end if;
if to_integer(unsigned(resp.dack_tag)) /= 0 then
this.data := resp.data;
this.command := e_mem_none;
wait for 2*this.poll_time;
check_command;
end if;
when others =>
null;
end case;
end process;
end bfm;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.mem_bus_master_bfm_pkg.all;
library std;
use std.textio.all;
entity mem_bus_master_bfm is
generic (
g_name : string );
port (
clock : in std_logic;
req : out t_mem_req := c_mem_req_init;
resp : in t_mem_resp );
end mem_bus_master_bfm;
architecture bfm of mem_bus_master_bfm is
shared variable this : p_mem_bus_master_bfm_object := null;
signal bound : boolean := false;
type t_state is (idle, wait_for_rack, wait_for_data);
signal state : t_state := idle;
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_mem_bus_master_bfm(g_name, this);
bound <= true;
wait;
end process;
process
procedure check_command is
begin
if this.command = e_mem_read then
req.tag <= this.tag;
req.address <= this.address;
req.request <= '1';
req.read_writen <= '1';
state <= wait_for_data;
elsif this.command = e_mem_write then
req.tag <= this.tag;
req.address <= this.address;
req.request <= '1';
req.read_writen <= '0';
req.data <= this.data;
state <= wait_for_rack;
else
req.request <= '0';
req.data <= (others => '1');
req.address <= (others => '1');
state <= idle;
end if;
end procedure;
begin
wait until rising_edge(clock);
case state is
when idle =>
req <= c_mem_req_init;
req.data <= (others => '1');
req.address <= (others => '1');
if bound then
check_command;
end if;
when wait_for_rack =>
if resp.rack='1' then
this.command := e_mem_none;
wait for 2*this.poll_time;
check_command;
end if;
when wait_for_data =>
if resp.rack='1' then
req.request <= '0';
req.address <= (others => '1');
end if;
if to_integer(unsigned(resp.dack_tag)) /= 0 then
this.data := resp.data;
this.command := e_mem_none;
wait for 2*this.poll_time;
check_command;
end if;
when others =>
null;
end case;
end process;
end bfm;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: tap_altera
-- File: tap_altera_gen.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: Altera TAP controllers wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altera_mf_components.all;
use altera_mf.sld_virtual_jtag;
-- pragma translate_on
entity altera_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of altera_tap is
signal ir0 : std_logic_vector(7 downto 0);
component sld_virtual_jtag
generic (
--lpm_hint : string := "UNUSED";
--lpm_type : string := "sld_virtual_jtag";
sld_auto_instance_index : string := "NO";
sld_instance_index : natural := 0;
sld_ir_width : natural := 1;
sld_sim_action : string := "UNUSED"
--sld_sim_n_scan : natural := 0;
--sld_sim_total_length : natural := 0
);
port(
ir_in : out std_logic_vector(sld_ir_width-1 downto 0);
ir_out : in std_logic_vector(sld_ir_width-1 downto 0);
jtag_state_cdr : out std_logic;
jtag_state_cir : out std_logic;
jtag_state_e1dr : out std_logic;
jtag_state_e1ir : out std_logic;
jtag_state_e2dr : out std_logic;
jtag_state_e2ir : out std_logic;
jtag_state_pdr : out std_logic;
jtag_state_pir : out std_logic;
jtag_state_rti : out std_logic;
jtag_state_sdr : out std_logic;
jtag_state_sdrs : out std_logic;
jtag_state_sir : out std_logic;
jtag_state_sirs : out std_logic;
jtag_state_tlr : out std_logic;
jtag_state_udr : out std_logic;
jtag_state_uir : out std_logic;
tck : out std_logic;
tdi : out std_logic;
tdo : in std_logic;
tms : out std_logic;
virtual_state_cdr : out std_logic;
virtual_state_cir : out std_logic;
virtual_state_e1dr : out std_logic;
virtual_state_e2dr : out std_logic;
virtual_state_pdr : out std_logic;
virtual_state_sdr : out std_logic;
virtual_state_udr : out std_logic;
virtual_state_uir : out std_logic
);
end component;
begin
tapo_capt <= '0'; tapo_upd <= '0'; tapo_rst <= '0';
tapo_xsel1 <= '0'; tapo_xsel2 <= '0';
u0 : sld_virtual_jtag
generic map (sld_ir_width => 8,
sld_auto_instance_index => "NO",
sld_instance_index => 0)
port map (ir_in => tapo_inst,
ir_out => ir0,
jtag_state_cdr => open,
jtag_state_cir => open,
jtag_state_e1dr => open,
jtag_state_e1ir => open,
jtag_state_e2dr => open,
jtag_state_e2ir => open,
jtag_state_pdr => open,
jtag_state_pir => open,
jtag_state_rti => open,
jtag_state_sdr => open,
jtag_state_sdrs => open,
jtag_state_sir => open,
jtag_state_sirs => open,
jtag_state_tlr => open,
jtag_state_udr => open,
jtag_state_uir => open,
tck => tapo_tck,
tdi => tapo_tdi,
tdo => tapi_tdo1,
tms => open,
virtual_state_cdr => open,
virtual_state_cir => open,
virtual_state_e1dr => open,
virtual_state_e2dr => open,
virtual_state_pdr => open,
virtual_state_sdr => tapo_shft,
virtual_state_udr => open,
virtual_state_uir => open);
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: tap_altera
-- File: tap_altera_gen.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: Altera TAP controllers wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altera_mf_components.all;
use altera_mf.sld_virtual_jtag;
-- pragma translate_on
entity altera_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of altera_tap is
signal ir0 : std_logic_vector(7 downto 0);
component sld_virtual_jtag
generic (
--lpm_hint : string := "UNUSED";
--lpm_type : string := "sld_virtual_jtag";
sld_auto_instance_index : string := "NO";
sld_instance_index : natural := 0;
sld_ir_width : natural := 1;
sld_sim_action : string := "UNUSED"
--sld_sim_n_scan : natural := 0;
--sld_sim_total_length : natural := 0
);
port(
ir_in : out std_logic_vector(sld_ir_width-1 downto 0);
ir_out : in std_logic_vector(sld_ir_width-1 downto 0);
jtag_state_cdr : out std_logic;
jtag_state_cir : out std_logic;
jtag_state_e1dr : out std_logic;
jtag_state_e1ir : out std_logic;
jtag_state_e2dr : out std_logic;
jtag_state_e2ir : out std_logic;
jtag_state_pdr : out std_logic;
jtag_state_pir : out std_logic;
jtag_state_rti : out std_logic;
jtag_state_sdr : out std_logic;
jtag_state_sdrs : out std_logic;
jtag_state_sir : out std_logic;
jtag_state_sirs : out std_logic;
jtag_state_tlr : out std_logic;
jtag_state_udr : out std_logic;
jtag_state_uir : out std_logic;
tck : out std_logic;
tdi : out std_logic;
tdo : in std_logic;
tms : out std_logic;
virtual_state_cdr : out std_logic;
virtual_state_cir : out std_logic;
virtual_state_e1dr : out std_logic;
virtual_state_e2dr : out std_logic;
virtual_state_pdr : out std_logic;
virtual_state_sdr : out std_logic;
virtual_state_udr : out std_logic;
virtual_state_uir : out std_logic
);
end component;
begin
tapo_capt <= '0'; tapo_upd <= '0'; tapo_rst <= '0';
tapo_xsel1 <= '0'; tapo_xsel2 <= '0';
u0 : sld_virtual_jtag
generic map (sld_ir_width => 8,
sld_auto_instance_index => "NO",
sld_instance_index => 0)
port map (ir_in => tapo_inst,
ir_out => ir0,
jtag_state_cdr => open,
jtag_state_cir => open,
jtag_state_e1dr => open,
jtag_state_e1ir => open,
jtag_state_e2dr => open,
jtag_state_e2ir => open,
jtag_state_pdr => open,
jtag_state_pir => open,
jtag_state_rti => open,
jtag_state_sdr => open,
jtag_state_sdrs => open,
jtag_state_sir => open,
jtag_state_sirs => open,
jtag_state_tlr => open,
jtag_state_udr => open,
jtag_state_uir => open,
tck => tapo_tck,
tdi => tapo_tdi,
tdo => tapi_tdo1,
tms => open,
virtual_state_cdr => open,
virtual_state_cir => open,
virtual_state_e1dr => open,
virtual_state_e2dr => open,
virtual_state_pdr => open,
virtual_state_sdr => tapo_shft,
virtual_state_udr => open,
virtual_state_uir => open);
end;
|
constant SPIFSMLength : integer := 1295;
constant SPIFSMCfg : std_logic_vector(SPIFSMLength-1 downto 0) := "00001001110000010000000000010000000000000000000000001010101000000000100000000110000110000000000010000011100100000000100000000000000000010001000000000000000100000000000000100100011000000000001000000010000000010100010000000000000001000100000000110010000000000000000010001100000010100001100000000000010000011000000100101001000000000000100010000000000011001010000000100000000100100000000110001000000000000001001010000000100100001000000000100000010100000001010010100000000001000001111100000000000000000000000000000000111110000000000000000000000000000000011111000000000000000000000000000000001111100000000000000000000000000000000111110000000000000000000000000000000011111000000000000000000000000000000001111100000000000000000000000000000000111110000000000000000000000000000000011111000000000000000000000000000000001111100000000000000000000000000000000111110000000000000000000000000000000000001111100000000000000000000000000000000000011111000000000000000000000000000000000000111110000000000000000000000000000000000001111100000000000000000000000000000000000011111000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000111110000000000000000000000000000000000000000000011111000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000";
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1138.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p05n02i01138ent IS
END c06s05b00x00p05n02i01138ent;
ARCHITECTURE c06s05b00x00p05n02i01138arch OF c06s05b00x00p05n02i01138ent IS
signal T1 : boolean;
BEGIN
TESTING: PROCESS
variable B : Bit_vector (1 to 10) := B"01010_10101";
BEGIN
if B(1 to 2) = B"01" then
T1 <= TRUE;
else
T1 <= FALSE;
end if;
wait for 1 ns;
assert NOT(T1=TRUE)
report "***PASSED TEST: c06s05b00x00p05n02i01138"
severity NOTE;
assert (T1=TRUE)
report "***FAILED TEST: c06s05b00x00p05n02i01138 - The prefix and the discrete range of the slice is not correctly evaluated."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p05n02i01138arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1138.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p05n02i01138ent IS
END c06s05b00x00p05n02i01138ent;
ARCHITECTURE c06s05b00x00p05n02i01138arch OF c06s05b00x00p05n02i01138ent IS
signal T1 : boolean;
BEGIN
TESTING: PROCESS
variable B : Bit_vector (1 to 10) := B"01010_10101";
BEGIN
if B(1 to 2) = B"01" then
T1 <= TRUE;
else
T1 <= FALSE;
end if;
wait for 1 ns;
assert NOT(T1=TRUE)
report "***PASSED TEST: c06s05b00x00p05n02i01138"
severity NOTE;
assert (T1=TRUE)
report "***FAILED TEST: c06s05b00x00p05n02i01138 - The prefix and the discrete range of the slice is not correctly evaluated."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p05n02i01138arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1138.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p05n02i01138ent IS
END c06s05b00x00p05n02i01138ent;
ARCHITECTURE c06s05b00x00p05n02i01138arch OF c06s05b00x00p05n02i01138ent IS
signal T1 : boolean;
BEGIN
TESTING: PROCESS
variable B : Bit_vector (1 to 10) := B"01010_10101";
BEGIN
if B(1 to 2) = B"01" then
T1 <= TRUE;
else
T1 <= FALSE;
end if;
wait for 1 ns;
assert NOT(T1=TRUE)
report "***PASSED TEST: c06s05b00x00p05n02i01138"
severity NOTE;
assert (T1=TRUE)
report "***FAILED TEST: c06s05b00x00p05n02i01138 - The prefix and the discrete range of the slice is not correctly evaluated."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p05n02i01138arch;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Loop_loop_height_eOg_rom is
generic(
dwidth : integer := 8;
awidth : integer := 8;
mem_size : integer := 256
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
addr2 : in std_logic_vector(awidth-1 downto 0);
ce2 : in std_logic;
q2 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of Loop_loop_height_eOg_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
signal addr2_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem0 : mem_array := (
0 => "00000000", 1 => "00000011", 2 => "00000100", 3 => "00000110",
4 => "00001000", 5 => "00001010", 6 => "00001011", 7 => "00001101",
8 => "00001110", 9 => "00010000", 10 => "00010001", 11 => "00010011",
12 => "00010100", 13 => "00010101", 14 => "00010111", 15 => "00011000",
16 => "00011001", 17 => "00011011", 18 => "00011100", 19 => "00011101",
20 => "00011111", 21 => "00100000", 22 => "00100001", 23 => "00100010",
24 => "00100100", 25 => "00100101", 26 => "00100110", 27 => "00100111",
28 => "00101000", 29 => "00101010", 30 => "00101011", 31 => "00101100",
32 => "00101101", 33 => "00101110", 34 => "00110000", 35 => "00110001",
36 => "00110010", 37 => "00110011", 38 => "00110100", 39 => "00110101",
40 => "00110110", 41 => "00111000", 42 => "00111001", 43 => "00111010",
44 => "00111011", 45 => "00111100", 46 => "00111101", 47 => "00111110",
48 => "00111111", 49 => "01000001", 50 => "01000010", 51 => "01000011",
52 => "01000100", 53 => "01000101", 54 => "01000110", 55 => "01000111",
56 => "01001000", 57 => "01001001", 58 => "01001010", 59 => "01001011",
60 => "01001100", 61 => "01001101", 62 => "01001110", 63 => "01010000",
64 => "01010001", 65 => "01010010", 66 => "01010011", 67 => "01010100",
68 => "01010101", 69 => "01010110", 70 => "01010111", 71 => "01011000",
72 => "01011001", 73 => "01011010", 74 => "01011011", 75 => "01011100",
76 => "01011101", 77 => "01011110", 78 => "01011111", 79 => "01100000",
80 => "01100001", 81 => "01100010", 82 => "01100011", 83 => "01100100",
84 => "01100101", 85 => "01100110", 86 => "01100111", 87 => "01101000",
88 => "01101001", 89 => "01101010", 90 => "01101011", 91 => "01101100",
92 => "01101101", 93 => "01101110", 94 => "01101111", 95 => "01110000",
96 => "01110001", 97 => "01110010", 98 => "01110011", 99 => "01110100",
100 => "01110101", 101 => "01110110", 102 => "01110111", 103 => "01111000",
104 => "01111001", 105 => "01111010", 106 => "01111011", 107 => "01111100",
108 => "01111101", 109 => "01111110", 110 => "01111111", 111 to 112=> "10000000",
113 => "10000001", 114 => "10000010", 115 => "10000011", 116 => "10000100",
117 => "10000101", 118 => "10000110", 119 => "10000111", 120 => "10001000",
121 => "10001001", 122 => "10001010", 123 => "10001011", 124 => "10001100",
125 => "10001101", 126 => "10001110", 127 => "10001111", 128 => "10010000",
129 to 130=> "10010001", 131 => "10010010", 132 => "10010011", 133 => "10010100",
134 => "10010101", 135 => "10010110", 136 => "10010111", 137 => "10011000",
138 => "10011001", 139 => "10011010", 140 => "10011011", 141 => "10011100",
142 to 143=> "10011101", 144 => "10011110", 145 => "10011111", 146 => "10100000",
147 => "10100001", 148 => "10100010", 149 => "10100011", 150 => "10100100",
151 => "10100101", 152 => "10100110", 153 => "10100111", 154 to 155=> "10101000",
156 => "10101001", 157 => "10101010", 158 => "10101011", 159 => "10101100",
160 => "10101101", 161 => "10101110", 162 => "10101111", 163 => "10110000",
164 to 165=> "10110001", 166 => "10110010", 167 => "10110011", 168 => "10110100",
169 => "10110101", 170 => "10110110", 171 => "10110111", 172 => "10111000",
173 to 174=> "10111001", 175 => "10111010", 176 => "10111011", 177 => "10111100",
178 => "10111101", 179 => "10111110", 180 => "10111111", 181 => "11000000",
182 to 183=> "11000001", 184 => "11000010", 185 => "11000011", 186 => "11000100",
187 => "11000101", 188 => "11000110", 189 => "11000111", 190 to 191=> "11001000",
192 => "11001001", 193 => "11001010", 194 => "11001011", 195 => "11001100",
196 => "11001101", 197 => "11001110", 198 to 199=> "11001111", 200 => "11010000",
201 => "11010001", 202 => "11010010", 203 => "11010011", 204 => "11010100",
205 to 206=> "11010101", 207 => "11010110", 208 => "11010111", 209 => "11011000",
210 => "11011001", 211 => "11011010", 212 to 213=> "11011011", 214 => "11011100",
215 => "11011101", 216 => "11011110", 217 => "11011111", 218 => "11100000",
219 to 220=> "11100001", 221 => "11100010", 222 => "11100011", 223 => "11100100",
224 => "11100101", 225 => "11100110", 226 to 227=> "11100111", 228 => "11101000",
229 => "11101001", 230 => "11101010", 231 => "11101011", 232 => "11101100",
233 to 234=> "11101101", 235 => "11101110", 236 => "11101111", 237 => "11110000",
238 => "11110001", 239 to 240=> "11110010", 241 => "11110011", 242 => "11110100",
243 => "11110101", 244 => "11110110", 245 to 246=> "11110111", 247 => "11111000",
248 => "11111001", 249 => "11111010", 250 => "11111011", 251 to 252=> "11111100",
253 => "11111101", 254 => "11111110", 255 => "11111111" );
signal mem1 : mem_array := (
0 => "00000000", 1 => "00000011", 2 => "00000100", 3 => "00000110",
4 => "00001000", 5 => "00001010", 6 => "00001011", 7 => "00001101",
8 => "00001110", 9 => "00010000", 10 => "00010001", 11 => "00010011",
12 => "00010100", 13 => "00010101", 14 => "00010111", 15 => "00011000",
16 => "00011001", 17 => "00011011", 18 => "00011100", 19 => "00011101",
20 => "00011111", 21 => "00100000", 22 => "00100001", 23 => "00100010",
24 => "00100100", 25 => "00100101", 26 => "00100110", 27 => "00100111",
28 => "00101000", 29 => "00101010", 30 => "00101011", 31 => "00101100",
32 => "00101101", 33 => "00101110", 34 => "00110000", 35 => "00110001",
36 => "00110010", 37 => "00110011", 38 => "00110100", 39 => "00110101",
40 => "00110110", 41 => "00111000", 42 => "00111001", 43 => "00111010",
44 => "00111011", 45 => "00111100", 46 => "00111101", 47 => "00111110",
48 => "00111111", 49 => "01000001", 50 => "01000010", 51 => "01000011",
52 => "01000100", 53 => "01000101", 54 => "01000110", 55 => "01000111",
56 => "01001000", 57 => "01001001", 58 => "01001010", 59 => "01001011",
60 => "01001100", 61 => "01001101", 62 => "01001110", 63 => "01010000",
64 => "01010001", 65 => "01010010", 66 => "01010011", 67 => "01010100",
68 => "01010101", 69 => "01010110", 70 => "01010111", 71 => "01011000",
72 => "01011001", 73 => "01011010", 74 => "01011011", 75 => "01011100",
76 => "01011101", 77 => "01011110", 78 => "01011111", 79 => "01100000",
80 => "01100001", 81 => "01100010", 82 => "01100011", 83 => "01100100",
84 => "01100101", 85 => "01100110", 86 => "01100111", 87 => "01101000",
88 => "01101001", 89 => "01101010", 90 => "01101011", 91 => "01101100",
92 => "01101101", 93 => "01101110", 94 => "01101111", 95 => "01110000",
96 => "01110001", 97 => "01110010", 98 => "01110011", 99 => "01110100",
100 => "01110101", 101 => "01110110", 102 => "01110111", 103 => "01111000",
104 => "01111001", 105 => "01111010", 106 => "01111011", 107 => "01111100",
108 => "01111101", 109 => "01111110", 110 => "01111111", 111 to 112=> "10000000",
113 => "10000001", 114 => "10000010", 115 => "10000011", 116 => "10000100",
117 => "10000101", 118 => "10000110", 119 => "10000111", 120 => "10001000",
121 => "10001001", 122 => "10001010", 123 => "10001011", 124 => "10001100",
125 => "10001101", 126 => "10001110", 127 => "10001111", 128 => "10010000",
129 to 130=> "10010001", 131 => "10010010", 132 => "10010011", 133 => "10010100",
134 => "10010101", 135 => "10010110", 136 => "10010111", 137 => "10011000",
138 => "10011001", 139 => "10011010", 140 => "10011011", 141 => "10011100",
142 to 143=> "10011101", 144 => "10011110", 145 => "10011111", 146 => "10100000",
147 => "10100001", 148 => "10100010", 149 => "10100011", 150 => "10100100",
151 => "10100101", 152 => "10100110", 153 => "10100111", 154 to 155=> "10101000",
156 => "10101001", 157 => "10101010", 158 => "10101011", 159 => "10101100",
160 => "10101101", 161 => "10101110", 162 => "10101111", 163 => "10110000",
164 to 165=> "10110001", 166 => "10110010", 167 => "10110011", 168 => "10110100",
169 => "10110101", 170 => "10110110", 171 => "10110111", 172 => "10111000",
173 to 174=> "10111001", 175 => "10111010", 176 => "10111011", 177 => "10111100",
178 => "10111101", 179 => "10111110", 180 => "10111111", 181 => "11000000",
182 to 183=> "11000001", 184 => "11000010", 185 => "11000011", 186 => "11000100",
187 => "11000101", 188 => "11000110", 189 => "11000111", 190 to 191=> "11001000",
192 => "11001001", 193 => "11001010", 194 => "11001011", 195 => "11001100",
196 => "11001101", 197 => "11001110", 198 to 199=> "11001111", 200 => "11010000",
201 => "11010001", 202 => "11010010", 203 => "11010011", 204 => "11010100",
205 to 206=> "11010101", 207 => "11010110", 208 => "11010111", 209 => "11011000",
210 => "11011001", 211 => "11011010", 212 to 213=> "11011011", 214 => "11011100",
215 => "11011101", 216 => "11011110", 217 => "11011111", 218 => "11100000",
219 to 220=> "11100001", 221 => "11100010", 222 => "11100011", 223 => "11100100",
224 => "11100101", 225 => "11100110", 226 to 227=> "11100111", 228 => "11101000",
229 => "11101001", 230 => "11101010", 231 => "11101011", 232 => "11101100",
233 to 234=> "11101101", 235 => "11101110", 236 => "11101111", 237 => "11110000",
238 => "11110001", 239 to 240=> "11110010", 241 => "11110011", 242 => "11110100",
243 => "11110101", 244 => "11110110", 245 to 246=> "11110111", 247 => "11111000",
248 => "11111001", 249 => "11111010", 250 => "11111011", 251 to 252=> "11111100",
253 => "11111101", 254 => "11111110", 255 => "11111111" );
attribute syn_rom_style : string;
attribute syn_rom_style of mem0 : signal is "block_rom";
attribute syn_rom_style of mem1 : signal is "block_rom";
attribute ROM_STYLE : string;
attribute ROM_STYLE of mem0 : signal is "block";
attribute ROM_STYLE of mem1 : signal is "block";
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
memory_access_guard_2: process (addr2)
begin
addr2_tmp <= addr2;
--synthesis translate_off
if (CONV_INTEGER(addr2) > mem_size-1) then
addr2_tmp <= (others => '0');
else
addr2_tmp <= addr2;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem0(CONV_INTEGER(addr0_tmp));
end if;
if (ce1 = '1') then
q1 <= mem0(CONV_INTEGER(addr1_tmp));
end if;
if (ce2 = '1') then
q2 <= mem1(CONV_INTEGER(addr2_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity Loop_loop_height_eOg is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 256;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address2 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of Loop_loop_height_eOg is
component Loop_loop_height_eOg_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR;
addr2 : IN STD_LOGIC_VECTOR;
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR);
end component;
begin
Loop_loop_height_eOg_rom_U : component Loop_loop_height_eOg_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1,
addr2 => address2,
ce2 => ce2,
q2 => q2);
end architecture;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_fwft_64x1024_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_fwft_64x1024_top is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end fifo_fwft_64x1024_top;
architecture xilinx of fifo_fwft_64x1024_top is
SIGNAL clk_i : std_logic;
component fifo_fwft_64x1024 is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : fifo_fwft_64x1024 PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncfifo_2p
-- File: syncfifo_2p.vhd
-- Authors: Pascal Trotta
-- Andrea Gianarro - Cobham Gaisler AB
-- Description: Syncronous 2-port fifo with tech selection
-----------------------------------------------------------------------------
-- Notes: Generic fifo has the following features & limitations:
-- -almost full is driven only in write clock domain;
-- -almost empty is driven only in read clock domain;
-- -full and empty are driven in both clock domains;
-- -usedw is re-computed in each clock domain;
-- -in "first word fall through" mode rempty should be observed as data
-- valid signal, as the first word written into the FIFO immediately
-- appears on the output. If renable is asserted while empty='0', and
-- at the next read clock rising edge empty='1', then new read data is
-- not valid because fifo is empty. This does not apply in standard fifo
-- mode, i.e., when empty is asserted, the last read data is valid;
-- -it works also if rclk = wclk. With sepclk=0 synchronization stages
-- and gray encoder/decoder are not instantiated, since not necessary.
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use work.allmem.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
entity syncfifo_2p is
generic (
tech : integer := 0; -- target technology
abits : integer := 10; -- fifo address bits (actual fifo depth = 2**abits)
dbits : integer := 32; -- fifo data width
sepclk : integer := 1; -- 1 = asynchrounous read/write clocks, 0 = synchronous read/write clocks
pfull : integer := 100; -- almost full threshold (max 2**abits - 3)
pempty : integer := 10; -- almost empty threshold (min 2)
fwft : integer := 0 -- 1 = first word fall trough mode, 0 = standard mode
);
port (
rclk : in std_logic; -- read clock
rrstn : in std_logic; -- read clock domain synchronous reset
wrstn : in std_logic; -- write clock domain synchronous reset
renable : in std_logic; -- read enable
rfull : out std_logic; -- fifo full (synchronized in read clock domain)
rempty : out std_logic; -- fifo empty
aempty : out std_logic; -- fifo almost empty (depending on pempty threshold)
rusedw : out std_logic_vector(abits-1 downto 0); -- fifo used words (synchronized in read clock domain)
dataout : out std_logic_vector(dbits-1 downto 0); -- fifo data output
wclk : in std_logic; -- write clock
write : in std_logic; -- write enable
wfull : out std_logic; -- fifo full
afull : out std_logic; -- fifo almost full (depending on pfull threshold)
wempty : out std_logic; -- fifo empty (synchronized in write clock domain)
wusedw : out std_logic_vector(abits-1 downto 0); -- fifo used words (synchronized in write clock domain)
datain : in std_logic_vector(dbits-1 downto 0)); -- fifo data input
end;
architecture rtl of syncfifo_2p is
begin
-- Altera fifo
alt : if (tech = altera) or (tech = stratix1) or (tech = stratix2) or
(tech = stratix3) or (tech = stratix4) generate
x0 : altera_fifo_dp generic map (tech, abits, dbits)
port map (rclk, renable, rfull, rempty, rusedw, dataout, wclk,
write, wfull, wempty, wusedw, datain);
end generate;
-- generic FIFO implemented using syncram_2p component
inf : if (tech /= altera) and (tech /= stratix1) and (tech /= stratix2) and
(tech /= stratix3) and (tech /= stratix4) generate
x0: generic_fifo generic map (tech, abits, dbits, sepclk, pfull, pempty, fwft)
port map (rclk, rrstn, wrstn, renable, rfull, rempty, aempty, rusedw, dataout,
wclk, write, wfull, afull, wempty, wusedw, datain);
end generate;
-- pragma translate_off
nofifo : if (has_2pfifo(tech) = 0) and (has_2pram(tech) = 0) generate
x : process
begin
assert false report "syncfifo_2p: technology " & tech_table(tech) &
" not supported"
severity failure;
wait;
end process;
end generate;
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "syncfifo_2p: " & tost(2**abits) & "x" & tost(dbits) &
" (" & tech_table(tech) & ")"
severity note;
wait;
end process;
end generate;
-- pragma translate_on
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_sampler is
generic(
PIX_DEPTH : positive;
MAX_WIDTH : positive;
MAX_HEIGHT : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- avalon_mm_slave
stop_and_reset : in std_logic;
idle : out std_logic;
wait_irq_ack : out std_logic;
irq_en : in std_logic;
irq_ack : in std_logic;
snapshot : in std_logic;
get_frame_info : in std_logic;
frame_width : out std_logic_vector(bit_width(max(MAX_WIDTH, MAX_HEIGHT)) - 1 downto 0);
frame_height : out std_logic_vector(bit_width(max(MAX_WIDTH, MAX_HEIGHT)) - 1 downto 0);
-- synchronizer
frame_valid : in std_logic;
line_valid : in std_logic;
data_in : in std_logic_vector(PIX_DEPTH - 1 downto 0);
-- debayer / packer / fifo
valid_out : out std_logic;
data_out : out std_logic_vector(PIX_DEPTH - 1 downto 0);
start_of_frame_out : out std_logic;
end_of_frame_out : out std_logic;
-- fifo
fifo_overflow : in std_logic;
-- st_source
end_of_frame_in : in std_logic;
end_of_frame_in_ack : out std_logic
);
end entity cmos_sensor_input_sampler;
architecture rtl of cmos_sensor_input_sampler is
-- GFI = get_frame_info
-- SNPSHT = snapshot
type state_type is (STATE_IDLE,
STATE_WAIT_END_FRAME_GFI, STATE_WAIT_START_FRAME_GFI, STATE_DATA_SKIP, STATE_LINE_LINE_BLANK_OR_LINE_FRAME_BLANK_GFI,
STATE_WAIT_END_FRAME_SNPSHT, STATE_WAIT_START_FRAME_SNPSHT, STATE_START_OF_FRAME_OUT, STATE_DATA_VALID, STATE_LINE_LINE_BLANK_SNPSHT, STATE_END_OF_FRAME_OUT, STATE_WAIT_END_OF_FRAME_IN, STATE_END_OF_FRAME_IN_ACK,
STATE_WAIT_IRQ_ACK);
signal reg_state, next_reg_state : state_type;
signal reg_frame_width_config, next_reg_frame_width_config : unsigned(frame_width'range);
signal reg_frame_height_config, next_reg_frame_height_config : unsigned(frame_height'range);
signal reg_frame_width_counter, next_reg_frame_width_counter : unsigned(frame_width'range);
signal reg_frame_height_counter, next_reg_frame_height_counter : unsigned(frame_height'range);
signal reg_data_in, next_reg_data_in : std_logic_vector(data_in'range);
begin
process(clk, reset)
begin
if reset = '1' then
reg_state <= STATE_IDLE;
reg_frame_width_config <= (others => '0');
reg_frame_height_config <= (others => '0');
reg_frame_width_counter <= (others => '0');
reg_frame_height_counter <= (others => '0');
reg_data_in <= (others => '0');
elsif rising_edge(clk) then
if stop_and_reset = '1' then
reg_state <= STATE_IDLE;
reg_frame_width_config <= (others => '0');
reg_frame_height_config <= (others => '0');
reg_frame_width_counter <= (others => '0');
reg_frame_height_counter <= (others => '0');
reg_data_in <= (others => '0');
else
reg_state <= next_reg_state;
reg_frame_width_config <= next_reg_frame_width_config;
reg_frame_height_config <= next_reg_frame_height_config;
reg_frame_width_counter <= next_reg_frame_width_counter;
reg_frame_height_counter <= next_reg_frame_height_counter;
reg_data_in <= next_reg_data_in;
end if;
end if;
end process;
process(data_in, end_of_frame_in, fifo_overflow, frame_valid, get_frame_info, irq_ack, irq_en, line_valid, reg_data_in, reg_frame_height_config, reg_frame_height_counter, reg_frame_width_config, reg_frame_width_counter, reg_state, snapshot)
begin
idle <= '0';
wait_irq_ack <= '0';
frame_width <= std_logic_vector(reg_frame_width_config);
frame_height <= std_logic_vector(reg_frame_height_config);
valid_out <= '0';
data_out <= (others => '0');
start_of_frame_out <= '0';
end_of_frame_out <= '0';
end_of_frame_in_ack <= '0';
next_reg_state <= reg_state;
next_reg_frame_width_config <= reg_frame_width_config;
next_reg_frame_height_config <= reg_frame_height_config;
next_reg_frame_width_counter <= reg_frame_width_counter;
next_reg_frame_height_counter <= reg_frame_height_counter;
next_reg_data_in <= data_in;
case reg_state is
when STATE_IDLE =>
idle <= '1';
if get_frame_info = '1' then
if frame_valid = '0' then
next_reg_state <= STATE_WAIT_START_FRAME_GFI;
elsif frame_valid = '1' then
next_reg_state <= STATE_WAIT_END_FRAME_GFI;
end if;
elsif snapshot = '1' then
if frame_valid = '0' then
next_reg_state <= STATE_WAIT_START_FRAME_SNPSHT;
elsif frame_valid = '1' then
next_reg_state <= STATE_WAIT_END_FRAME_SNPSHT;
end if;
end if;
when STATE_WAIT_END_FRAME_GFI =>
if frame_valid = '0' then
next_reg_state <= STATE_WAIT_START_FRAME_GFI;
end if;
when STATE_WAIT_START_FRAME_GFI =>
if frame_valid = '1' and line_valid = '1' then
next_reg_state <= STATE_DATA_SKIP;
next_reg_frame_width_config <= to_unsigned(1, next_reg_frame_width_config'length);
next_reg_frame_height_config <= to_unsigned(1, next_reg_frame_height_config'length);
end if;
when STATE_DATA_SKIP =>
if frame_valid = '0' then
if line_valid = '0' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
end if;
elsif frame_valid = '1' then
if line_valid = '0' then
next_reg_state <= STATE_LINE_LINE_BLANK_OR_LINE_FRAME_BLANK_GFI;
elsif line_valid = '1' then
next_reg_frame_width_config <= reg_frame_width_config + 1;
end if;
end if;
when STATE_LINE_LINE_BLANK_OR_LINE_FRAME_BLANK_GFI =>
if frame_valid = '0' and line_valid = '0' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif frame_valid = '1' and line_valid = '1' then
next_reg_state <= STATE_DATA_SKIP;
next_reg_frame_width_config <= to_unsigned(1, next_reg_frame_width_config'length);
next_reg_frame_height_config <= reg_frame_height_config + 1;
end if;
when STATE_WAIT_END_FRAME_SNPSHT =>
if frame_valid = '0' then
next_reg_state <= STATE_WAIT_START_FRAME_SNPSHT;
end if;
when STATE_WAIT_START_FRAME_SNPSHT =>
if frame_valid = '1' and line_valid = '1' then
next_reg_state <= STATE_START_OF_FRAME_OUT;
next_reg_frame_width_counter <= to_unsigned(1, next_reg_frame_width_counter'length);
next_reg_frame_height_counter <= to_unsigned(1, next_reg_frame_height_counter'length);
end if;
when STATE_START_OF_FRAME_OUT =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
valid_out <= '1';
data_out <= reg_data_in;
start_of_frame_out <= '1';
if reg_frame_width_counter < reg_frame_width_config - 1 then
next_reg_state <= STATE_DATA_VALID;
next_reg_frame_width_counter <= reg_frame_width_counter + 1;
elsif reg_frame_width_counter = reg_frame_width_config - 1 then
if reg_frame_height_counter = reg_frame_height_config then
next_reg_state <= STATE_END_OF_FRAME_OUT;
end if;
end if;
end if;
when STATE_DATA_VALID =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
valid_out <= '1';
data_out <= reg_data_in;
next_reg_frame_width_counter <= reg_frame_width_counter + 1;
if reg_frame_height_counter < reg_frame_height_config then
if reg_frame_width_counter = reg_frame_width_config then
next_reg_state <= STATE_LINE_LINE_BLANK_SNPSHT;
end if;
elsif reg_frame_height_counter = reg_frame_height_config then
if reg_frame_width_counter = reg_frame_width_config - 1 then
next_reg_state <= STATE_END_OF_FRAME_OUT;
next_reg_frame_width_counter <= reg_frame_width_counter + 1;
end if;
end if;
end if;
when STATE_LINE_LINE_BLANK_SNPSHT =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
if frame_valid = '1' and line_valid = '1' then
next_reg_state <= STATE_DATA_VALID;
next_reg_frame_width_counter <= to_unsigned(1, next_reg_frame_width_counter'length);
next_reg_frame_height_counter <= reg_frame_height_counter + 1;
end if;
end if;
when STATE_END_OF_FRAME_OUT =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
valid_out <= '1';
data_out <= reg_data_in;
end_of_frame_out <= '1';
next_reg_state <= STATE_WAIT_END_OF_FRAME_IN;
end if;
when STATE_WAIT_END_OF_FRAME_IN =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
if end_of_frame_in = '1' then
next_reg_state <= STATE_END_OF_FRAME_IN_ACK;
end if;
end if;
when STATE_END_OF_FRAME_IN_ACK =>
end_of_frame_in_ack <= '1';
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
when STATE_WAIT_IRQ_ACK =>
wait_irq_ack <= '1';
if irq_ack = '1' then
next_reg_state <= STATE_IDLE;
end if;
end case;
end process;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_sampler is
generic(
PIX_DEPTH : positive;
MAX_WIDTH : positive;
MAX_HEIGHT : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- avalon_mm_slave
stop_and_reset : in std_logic;
idle : out std_logic;
wait_irq_ack : out std_logic;
irq_en : in std_logic;
irq_ack : in std_logic;
snapshot : in std_logic;
get_frame_info : in std_logic;
frame_width : out std_logic_vector(bit_width(max(MAX_WIDTH, MAX_HEIGHT)) - 1 downto 0);
frame_height : out std_logic_vector(bit_width(max(MAX_WIDTH, MAX_HEIGHT)) - 1 downto 0);
-- synchronizer
frame_valid : in std_logic;
line_valid : in std_logic;
data_in : in std_logic_vector(PIX_DEPTH - 1 downto 0);
-- debayer / packer / fifo
valid_out : out std_logic;
data_out : out std_logic_vector(PIX_DEPTH - 1 downto 0);
start_of_frame_out : out std_logic;
end_of_frame_out : out std_logic;
-- fifo
fifo_overflow : in std_logic;
-- st_source
end_of_frame_in : in std_logic;
end_of_frame_in_ack : out std_logic
);
end entity cmos_sensor_input_sampler;
architecture rtl of cmos_sensor_input_sampler is
-- GFI = get_frame_info
-- SNPSHT = snapshot
type state_type is (STATE_IDLE,
STATE_WAIT_END_FRAME_GFI, STATE_WAIT_START_FRAME_GFI, STATE_DATA_SKIP, STATE_LINE_LINE_BLANK_OR_LINE_FRAME_BLANK_GFI,
STATE_WAIT_END_FRAME_SNPSHT, STATE_WAIT_START_FRAME_SNPSHT, STATE_START_OF_FRAME_OUT, STATE_DATA_VALID, STATE_LINE_LINE_BLANK_SNPSHT, STATE_END_OF_FRAME_OUT, STATE_WAIT_END_OF_FRAME_IN, STATE_END_OF_FRAME_IN_ACK,
STATE_WAIT_IRQ_ACK);
signal reg_state, next_reg_state : state_type;
signal reg_frame_width_config, next_reg_frame_width_config : unsigned(frame_width'range);
signal reg_frame_height_config, next_reg_frame_height_config : unsigned(frame_height'range);
signal reg_frame_width_counter, next_reg_frame_width_counter : unsigned(frame_width'range);
signal reg_frame_height_counter, next_reg_frame_height_counter : unsigned(frame_height'range);
signal reg_data_in, next_reg_data_in : std_logic_vector(data_in'range);
begin
process(clk, reset)
begin
if reset = '1' then
reg_state <= STATE_IDLE;
reg_frame_width_config <= (others => '0');
reg_frame_height_config <= (others => '0');
reg_frame_width_counter <= (others => '0');
reg_frame_height_counter <= (others => '0');
reg_data_in <= (others => '0');
elsif rising_edge(clk) then
if stop_and_reset = '1' then
reg_state <= STATE_IDLE;
reg_frame_width_config <= (others => '0');
reg_frame_height_config <= (others => '0');
reg_frame_width_counter <= (others => '0');
reg_frame_height_counter <= (others => '0');
reg_data_in <= (others => '0');
else
reg_state <= next_reg_state;
reg_frame_width_config <= next_reg_frame_width_config;
reg_frame_height_config <= next_reg_frame_height_config;
reg_frame_width_counter <= next_reg_frame_width_counter;
reg_frame_height_counter <= next_reg_frame_height_counter;
reg_data_in <= next_reg_data_in;
end if;
end if;
end process;
process(data_in, end_of_frame_in, fifo_overflow, frame_valid, get_frame_info, irq_ack, irq_en, line_valid, reg_data_in, reg_frame_height_config, reg_frame_height_counter, reg_frame_width_config, reg_frame_width_counter, reg_state, snapshot)
begin
idle <= '0';
wait_irq_ack <= '0';
frame_width <= std_logic_vector(reg_frame_width_config);
frame_height <= std_logic_vector(reg_frame_height_config);
valid_out <= '0';
data_out <= (others => '0');
start_of_frame_out <= '0';
end_of_frame_out <= '0';
end_of_frame_in_ack <= '0';
next_reg_state <= reg_state;
next_reg_frame_width_config <= reg_frame_width_config;
next_reg_frame_height_config <= reg_frame_height_config;
next_reg_frame_width_counter <= reg_frame_width_counter;
next_reg_frame_height_counter <= reg_frame_height_counter;
next_reg_data_in <= data_in;
case reg_state is
when STATE_IDLE =>
idle <= '1';
if get_frame_info = '1' then
if frame_valid = '0' then
next_reg_state <= STATE_WAIT_START_FRAME_GFI;
elsif frame_valid = '1' then
next_reg_state <= STATE_WAIT_END_FRAME_GFI;
end if;
elsif snapshot = '1' then
if frame_valid = '0' then
next_reg_state <= STATE_WAIT_START_FRAME_SNPSHT;
elsif frame_valid = '1' then
next_reg_state <= STATE_WAIT_END_FRAME_SNPSHT;
end if;
end if;
when STATE_WAIT_END_FRAME_GFI =>
if frame_valid = '0' then
next_reg_state <= STATE_WAIT_START_FRAME_GFI;
end if;
when STATE_WAIT_START_FRAME_GFI =>
if frame_valid = '1' and line_valid = '1' then
next_reg_state <= STATE_DATA_SKIP;
next_reg_frame_width_config <= to_unsigned(1, next_reg_frame_width_config'length);
next_reg_frame_height_config <= to_unsigned(1, next_reg_frame_height_config'length);
end if;
when STATE_DATA_SKIP =>
if frame_valid = '0' then
if line_valid = '0' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
end if;
elsif frame_valid = '1' then
if line_valid = '0' then
next_reg_state <= STATE_LINE_LINE_BLANK_OR_LINE_FRAME_BLANK_GFI;
elsif line_valid = '1' then
next_reg_frame_width_config <= reg_frame_width_config + 1;
end if;
end if;
when STATE_LINE_LINE_BLANK_OR_LINE_FRAME_BLANK_GFI =>
if frame_valid = '0' and line_valid = '0' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif frame_valid = '1' and line_valid = '1' then
next_reg_state <= STATE_DATA_SKIP;
next_reg_frame_width_config <= to_unsigned(1, next_reg_frame_width_config'length);
next_reg_frame_height_config <= reg_frame_height_config + 1;
end if;
when STATE_WAIT_END_FRAME_SNPSHT =>
if frame_valid = '0' then
next_reg_state <= STATE_WAIT_START_FRAME_SNPSHT;
end if;
when STATE_WAIT_START_FRAME_SNPSHT =>
if frame_valid = '1' and line_valid = '1' then
next_reg_state <= STATE_START_OF_FRAME_OUT;
next_reg_frame_width_counter <= to_unsigned(1, next_reg_frame_width_counter'length);
next_reg_frame_height_counter <= to_unsigned(1, next_reg_frame_height_counter'length);
end if;
when STATE_START_OF_FRAME_OUT =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
valid_out <= '1';
data_out <= reg_data_in;
start_of_frame_out <= '1';
if reg_frame_width_counter < reg_frame_width_config - 1 then
next_reg_state <= STATE_DATA_VALID;
next_reg_frame_width_counter <= reg_frame_width_counter + 1;
elsif reg_frame_width_counter = reg_frame_width_config - 1 then
if reg_frame_height_counter = reg_frame_height_config then
next_reg_state <= STATE_END_OF_FRAME_OUT;
end if;
end if;
end if;
when STATE_DATA_VALID =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
valid_out <= '1';
data_out <= reg_data_in;
next_reg_frame_width_counter <= reg_frame_width_counter + 1;
if reg_frame_height_counter < reg_frame_height_config then
if reg_frame_width_counter = reg_frame_width_config then
next_reg_state <= STATE_LINE_LINE_BLANK_SNPSHT;
end if;
elsif reg_frame_height_counter = reg_frame_height_config then
if reg_frame_width_counter = reg_frame_width_config - 1 then
next_reg_state <= STATE_END_OF_FRAME_OUT;
next_reg_frame_width_counter <= reg_frame_width_counter + 1;
end if;
end if;
end if;
when STATE_LINE_LINE_BLANK_SNPSHT =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
if frame_valid = '1' and line_valid = '1' then
next_reg_state <= STATE_DATA_VALID;
next_reg_frame_width_counter <= to_unsigned(1, next_reg_frame_width_counter'length);
next_reg_frame_height_counter <= reg_frame_height_counter + 1;
end if;
end if;
when STATE_END_OF_FRAME_OUT =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
valid_out <= '1';
data_out <= reg_data_in;
end_of_frame_out <= '1';
next_reg_state <= STATE_WAIT_END_OF_FRAME_IN;
end if;
when STATE_WAIT_END_OF_FRAME_IN =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
if end_of_frame_in = '1' then
next_reg_state <= STATE_END_OF_FRAME_IN_ACK;
end if;
end if;
when STATE_END_OF_FRAME_IN_ACK =>
end_of_frame_in_ack <= '1';
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
when STATE_WAIT_IRQ_ACK =>
wait_irq_ack <= '1';
if irq_ack = '1' then
next_reg_state <= STATE_IDLE;
end if;
end case;
end process;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_sampler is
generic(
PIX_DEPTH : positive;
MAX_WIDTH : positive;
MAX_HEIGHT : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- avalon_mm_slave
stop_and_reset : in std_logic;
idle : out std_logic;
wait_irq_ack : out std_logic;
irq_en : in std_logic;
irq_ack : in std_logic;
snapshot : in std_logic;
get_frame_info : in std_logic;
frame_width : out std_logic_vector(bit_width(max(MAX_WIDTH, MAX_HEIGHT)) - 1 downto 0);
frame_height : out std_logic_vector(bit_width(max(MAX_WIDTH, MAX_HEIGHT)) - 1 downto 0);
-- synchronizer
frame_valid : in std_logic;
line_valid : in std_logic;
data_in : in std_logic_vector(PIX_DEPTH - 1 downto 0);
-- debayer / packer / fifo
valid_out : out std_logic;
data_out : out std_logic_vector(PIX_DEPTH - 1 downto 0);
start_of_frame_out : out std_logic;
end_of_frame_out : out std_logic;
-- fifo
fifo_overflow : in std_logic;
-- st_source
end_of_frame_in : in std_logic;
end_of_frame_in_ack : out std_logic
);
end entity cmos_sensor_input_sampler;
architecture rtl of cmos_sensor_input_sampler is
-- GFI = get_frame_info
-- SNPSHT = snapshot
type state_type is (STATE_IDLE,
STATE_WAIT_END_FRAME_GFI, STATE_WAIT_START_FRAME_GFI, STATE_DATA_SKIP, STATE_LINE_LINE_BLANK_OR_LINE_FRAME_BLANK_GFI,
STATE_WAIT_END_FRAME_SNPSHT, STATE_WAIT_START_FRAME_SNPSHT, STATE_START_OF_FRAME_OUT, STATE_DATA_VALID, STATE_LINE_LINE_BLANK_SNPSHT, STATE_END_OF_FRAME_OUT, STATE_WAIT_END_OF_FRAME_IN, STATE_END_OF_FRAME_IN_ACK,
STATE_WAIT_IRQ_ACK);
signal reg_state, next_reg_state : state_type;
signal reg_frame_width_config, next_reg_frame_width_config : unsigned(frame_width'range);
signal reg_frame_height_config, next_reg_frame_height_config : unsigned(frame_height'range);
signal reg_frame_width_counter, next_reg_frame_width_counter : unsigned(frame_width'range);
signal reg_frame_height_counter, next_reg_frame_height_counter : unsigned(frame_height'range);
signal reg_data_in, next_reg_data_in : std_logic_vector(data_in'range);
begin
process(clk, reset)
begin
if reset = '1' then
reg_state <= STATE_IDLE;
reg_frame_width_config <= (others => '0');
reg_frame_height_config <= (others => '0');
reg_frame_width_counter <= (others => '0');
reg_frame_height_counter <= (others => '0');
reg_data_in <= (others => '0');
elsif rising_edge(clk) then
if stop_and_reset = '1' then
reg_state <= STATE_IDLE;
reg_frame_width_config <= (others => '0');
reg_frame_height_config <= (others => '0');
reg_frame_width_counter <= (others => '0');
reg_frame_height_counter <= (others => '0');
reg_data_in <= (others => '0');
else
reg_state <= next_reg_state;
reg_frame_width_config <= next_reg_frame_width_config;
reg_frame_height_config <= next_reg_frame_height_config;
reg_frame_width_counter <= next_reg_frame_width_counter;
reg_frame_height_counter <= next_reg_frame_height_counter;
reg_data_in <= next_reg_data_in;
end if;
end if;
end process;
process(data_in, end_of_frame_in, fifo_overflow, frame_valid, get_frame_info, irq_ack, irq_en, line_valid, reg_data_in, reg_frame_height_config, reg_frame_height_counter, reg_frame_width_config, reg_frame_width_counter, reg_state, snapshot)
begin
idle <= '0';
wait_irq_ack <= '0';
frame_width <= std_logic_vector(reg_frame_width_config);
frame_height <= std_logic_vector(reg_frame_height_config);
valid_out <= '0';
data_out <= (others => '0');
start_of_frame_out <= '0';
end_of_frame_out <= '0';
end_of_frame_in_ack <= '0';
next_reg_state <= reg_state;
next_reg_frame_width_config <= reg_frame_width_config;
next_reg_frame_height_config <= reg_frame_height_config;
next_reg_frame_width_counter <= reg_frame_width_counter;
next_reg_frame_height_counter <= reg_frame_height_counter;
next_reg_data_in <= data_in;
case reg_state is
when STATE_IDLE =>
idle <= '1';
if get_frame_info = '1' then
if frame_valid = '0' then
next_reg_state <= STATE_WAIT_START_FRAME_GFI;
elsif frame_valid = '1' then
next_reg_state <= STATE_WAIT_END_FRAME_GFI;
end if;
elsif snapshot = '1' then
if frame_valid = '0' then
next_reg_state <= STATE_WAIT_START_FRAME_SNPSHT;
elsif frame_valid = '1' then
next_reg_state <= STATE_WAIT_END_FRAME_SNPSHT;
end if;
end if;
when STATE_WAIT_END_FRAME_GFI =>
if frame_valid = '0' then
next_reg_state <= STATE_WAIT_START_FRAME_GFI;
end if;
when STATE_WAIT_START_FRAME_GFI =>
if frame_valid = '1' and line_valid = '1' then
next_reg_state <= STATE_DATA_SKIP;
next_reg_frame_width_config <= to_unsigned(1, next_reg_frame_width_config'length);
next_reg_frame_height_config <= to_unsigned(1, next_reg_frame_height_config'length);
end if;
when STATE_DATA_SKIP =>
if frame_valid = '0' then
if line_valid = '0' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
end if;
elsif frame_valid = '1' then
if line_valid = '0' then
next_reg_state <= STATE_LINE_LINE_BLANK_OR_LINE_FRAME_BLANK_GFI;
elsif line_valid = '1' then
next_reg_frame_width_config <= reg_frame_width_config + 1;
end if;
end if;
when STATE_LINE_LINE_BLANK_OR_LINE_FRAME_BLANK_GFI =>
if frame_valid = '0' and line_valid = '0' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif frame_valid = '1' and line_valid = '1' then
next_reg_state <= STATE_DATA_SKIP;
next_reg_frame_width_config <= to_unsigned(1, next_reg_frame_width_config'length);
next_reg_frame_height_config <= reg_frame_height_config + 1;
end if;
when STATE_WAIT_END_FRAME_SNPSHT =>
if frame_valid = '0' then
next_reg_state <= STATE_WAIT_START_FRAME_SNPSHT;
end if;
when STATE_WAIT_START_FRAME_SNPSHT =>
if frame_valid = '1' and line_valid = '1' then
next_reg_state <= STATE_START_OF_FRAME_OUT;
next_reg_frame_width_counter <= to_unsigned(1, next_reg_frame_width_counter'length);
next_reg_frame_height_counter <= to_unsigned(1, next_reg_frame_height_counter'length);
end if;
when STATE_START_OF_FRAME_OUT =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
valid_out <= '1';
data_out <= reg_data_in;
start_of_frame_out <= '1';
if reg_frame_width_counter < reg_frame_width_config - 1 then
next_reg_state <= STATE_DATA_VALID;
next_reg_frame_width_counter <= reg_frame_width_counter + 1;
elsif reg_frame_width_counter = reg_frame_width_config - 1 then
if reg_frame_height_counter = reg_frame_height_config then
next_reg_state <= STATE_END_OF_FRAME_OUT;
end if;
end if;
end if;
when STATE_DATA_VALID =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
valid_out <= '1';
data_out <= reg_data_in;
next_reg_frame_width_counter <= reg_frame_width_counter + 1;
if reg_frame_height_counter < reg_frame_height_config then
if reg_frame_width_counter = reg_frame_width_config then
next_reg_state <= STATE_LINE_LINE_BLANK_SNPSHT;
end if;
elsif reg_frame_height_counter = reg_frame_height_config then
if reg_frame_width_counter = reg_frame_width_config - 1 then
next_reg_state <= STATE_END_OF_FRAME_OUT;
next_reg_frame_width_counter <= reg_frame_width_counter + 1;
end if;
end if;
end if;
when STATE_LINE_LINE_BLANK_SNPSHT =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
if frame_valid = '1' and line_valid = '1' then
next_reg_state <= STATE_DATA_VALID;
next_reg_frame_width_counter <= to_unsigned(1, next_reg_frame_width_counter'length);
next_reg_frame_height_counter <= reg_frame_height_counter + 1;
end if;
end if;
when STATE_END_OF_FRAME_OUT =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
valid_out <= '1';
data_out <= reg_data_in;
end_of_frame_out <= '1';
next_reg_state <= STATE_WAIT_END_OF_FRAME_IN;
end if;
when STATE_WAIT_END_OF_FRAME_IN =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
if end_of_frame_in = '1' then
next_reg_state <= STATE_END_OF_FRAME_IN_ACK;
end if;
end if;
when STATE_END_OF_FRAME_IN_ACK =>
end_of_frame_in_ack <= '1';
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
when STATE_WAIT_IRQ_ACK =>
wait_irq_ack <= '1';
if irq_ack = '1' then
next_reg_state <= STATE_IDLE;
end if;
end case;
end process;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_sampler is
generic(
PIX_DEPTH : positive;
MAX_WIDTH : positive;
MAX_HEIGHT : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- avalon_mm_slave
stop_and_reset : in std_logic;
idle : out std_logic;
wait_irq_ack : out std_logic;
irq_en : in std_logic;
irq_ack : in std_logic;
snapshot : in std_logic;
get_frame_info : in std_logic;
frame_width : out std_logic_vector(bit_width(max(MAX_WIDTH, MAX_HEIGHT)) - 1 downto 0);
frame_height : out std_logic_vector(bit_width(max(MAX_WIDTH, MAX_HEIGHT)) - 1 downto 0);
-- synchronizer
frame_valid : in std_logic;
line_valid : in std_logic;
data_in : in std_logic_vector(PIX_DEPTH - 1 downto 0);
-- debayer / packer / fifo
valid_out : out std_logic;
data_out : out std_logic_vector(PIX_DEPTH - 1 downto 0);
start_of_frame_out : out std_logic;
end_of_frame_out : out std_logic;
-- fifo
fifo_overflow : in std_logic;
-- st_source
end_of_frame_in : in std_logic;
end_of_frame_in_ack : out std_logic
);
end entity cmos_sensor_input_sampler;
architecture rtl of cmos_sensor_input_sampler is
-- GFI = get_frame_info
-- SNPSHT = snapshot
type state_type is (STATE_IDLE,
STATE_WAIT_END_FRAME_GFI, STATE_WAIT_START_FRAME_GFI, STATE_DATA_SKIP, STATE_LINE_LINE_BLANK_OR_LINE_FRAME_BLANK_GFI,
STATE_WAIT_END_FRAME_SNPSHT, STATE_WAIT_START_FRAME_SNPSHT, STATE_START_OF_FRAME_OUT, STATE_DATA_VALID, STATE_LINE_LINE_BLANK_SNPSHT, STATE_END_OF_FRAME_OUT, STATE_WAIT_END_OF_FRAME_IN, STATE_END_OF_FRAME_IN_ACK,
STATE_WAIT_IRQ_ACK);
signal reg_state, next_reg_state : state_type;
signal reg_frame_width_config, next_reg_frame_width_config : unsigned(frame_width'range);
signal reg_frame_height_config, next_reg_frame_height_config : unsigned(frame_height'range);
signal reg_frame_width_counter, next_reg_frame_width_counter : unsigned(frame_width'range);
signal reg_frame_height_counter, next_reg_frame_height_counter : unsigned(frame_height'range);
signal reg_data_in, next_reg_data_in : std_logic_vector(data_in'range);
begin
process(clk, reset)
begin
if reset = '1' then
reg_state <= STATE_IDLE;
reg_frame_width_config <= (others => '0');
reg_frame_height_config <= (others => '0');
reg_frame_width_counter <= (others => '0');
reg_frame_height_counter <= (others => '0');
reg_data_in <= (others => '0');
elsif rising_edge(clk) then
if stop_and_reset = '1' then
reg_state <= STATE_IDLE;
reg_frame_width_config <= (others => '0');
reg_frame_height_config <= (others => '0');
reg_frame_width_counter <= (others => '0');
reg_frame_height_counter <= (others => '0');
reg_data_in <= (others => '0');
else
reg_state <= next_reg_state;
reg_frame_width_config <= next_reg_frame_width_config;
reg_frame_height_config <= next_reg_frame_height_config;
reg_frame_width_counter <= next_reg_frame_width_counter;
reg_frame_height_counter <= next_reg_frame_height_counter;
reg_data_in <= next_reg_data_in;
end if;
end if;
end process;
process(data_in, end_of_frame_in, fifo_overflow, frame_valid, get_frame_info, irq_ack, irq_en, line_valid, reg_data_in, reg_frame_height_config, reg_frame_height_counter, reg_frame_width_config, reg_frame_width_counter, reg_state, snapshot)
begin
idle <= '0';
wait_irq_ack <= '0';
frame_width <= std_logic_vector(reg_frame_width_config);
frame_height <= std_logic_vector(reg_frame_height_config);
valid_out <= '0';
data_out <= (others => '0');
start_of_frame_out <= '0';
end_of_frame_out <= '0';
end_of_frame_in_ack <= '0';
next_reg_state <= reg_state;
next_reg_frame_width_config <= reg_frame_width_config;
next_reg_frame_height_config <= reg_frame_height_config;
next_reg_frame_width_counter <= reg_frame_width_counter;
next_reg_frame_height_counter <= reg_frame_height_counter;
next_reg_data_in <= data_in;
case reg_state is
when STATE_IDLE =>
idle <= '1';
if get_frame_info = '1' then
if frame_valid = '0' then
next_reg_state <= STATE_WAIT_START_FRAME_GFI;
elsif frame_valid = '1' then
next_reg_state <= STATE_WAIT_END_FRAME_GFI;
end if;
elsif snapshot = '1' then
if frame_valid = '0' then
next_reg_state <= STATE_WAIT_START_FRAME_SNPSHT;
elsif frame_valid = '1' then
next_reg_state <= STATE_WAIT_END_FRAME_SNPSHT;
end if;
end if;
when STATE_WAIT_END_FRAME_GFI =>
if frame_valid = '0' then
next_reg_state <= STATE_WAIT_START_FRAME_GFI;
end if;
when STATE_WAIT_START_FRAME_GFI =>
if frame_valid = '1' and line_valid = '1' then
next_reg_state <= STATE_DATA_SKIP;
next_reg_frame_width_config <= to_unsigned(1, next_reg_frame_width_config'length);
next_reg_frame_height_config <= to_unsigned(1, next_reg_frame_height_config'length);
end if;
when STATE_DATA_SKIP =>
if frame_valid = '0' then
if line_valid = '0' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
end if;
elsif frame_valid = '1' then
if line_valid = '0' then
next_reg_state <= STATE_LINE_LINE_BLANK_OR_LINE_FRAME_BLANK_GFI;
elsif line_valid = '1' then
next_reg_frame_width_config <= reg_frame_width_config + 1;
end if;
end if;
when STATE_LINE_LINE_BLANK_OR_LINE_FRAME_BLANK_GFI =>
if frame_valid = '0' and line_valid = '0' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif frame_valid = '1' and line_valid = '1' then
next_reg_state <= STATE_DATA_SKIP;
next_reg_frame_width_config <= to_unsigned(1, next_reg_frame_width_config'length);
next_reg_frame_height_config <= reg_frame_height_config + 1;
end if;
when STATE_WAIT_END_FRAME_SNPSHT =>
if frame_valid = '0' then
next_reg_state <= STATE_WAIT_START_FRAME_SNPSHT;
end if;
when STATE_WAIT_START_FRAME_SNPSHT =>
if frame_valid = '1' and line_valid = '1' then
next_reg_state <= STATE_START_OF_FRAME_OUT;
next_reg_frame_width_counter <= to_unsigned(1, next_reg_frame_width_counter'length);
next_reg_frame_height_counter <= to_unsigned(1, next_reg_frame_height_counter'length);
end if;
when STATE_START_OF_FRAME_OUT =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
valid_out <= '1';
data_out <= reg_data_in;
start_of_frame_out <= '1';
if reg_frame_width_counter < reg_frame_width_config - 1 then
next_reg_state <= STATE_DATA_VALID;
next_reg_frame_width_counter <= reg_frame_width_counter + 1;
elsif reg_frame_width_counter = reg_frame_width_config - 1 then
if reg_frame_height_counter = reg_frame_height_config then
next_reg_state <= STATE_END_OF_FRAME_OUT;
end if;
end if;
end if;
when STATE_DATA_VALID =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
valid_out <= '1';
data_out <= reg_data_in;
next_reg_frame_width_counter <= reg_frame_width_counter + 1;
if reg_frame_height_counter < reg_frame_height_config then
if reg_frame_width_counter = reg_frame_width_config then
next_reg_state <= STATE_LINE_LINE_BLANK_SNPSHT;
end if;
elsif reg_frame_height_counter = reg_frame_height_config then
if reg_frame_width_counter = reg_frame_width_config - 1 then
next_reg_state <= STATE_END_OF_FRAME_OUT;
next_reg_frame_width_counter <= reg_frame_width_counter + 1;
end if;
end if;
end if;
when STATE_LINE_LINE_BLANK_SNPSHT =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
if frame_valid = '1' and line_valid = '1' then
next_reg_state <= STATE_DATA_VALID;
next_reg_frame_width_counter <= to_unsigned(1, next_reg_frame_width_counter'length);
next_reg_frame_height_counter <= reg_frame_height_counter + 1;
end if;
end if;
when STATE_END_OF_FRAME_OUT =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
valid_out <= '1';
data_out <= reg_data_in;
end_of_frame_out <= '1';
next_reg_state <= STATE_WAIT_END_OF_FRAME_IN;
end if;
when STATE_WAIT_END_OF_FRAME_IN =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
if end_of_frame_in = '1' then
next_reg_state <= STATE_END_OF_FRAME_IN_ACK;
end if;
end if;
when STATE_END_OF_FRAME_IN_ACK =>
end_of_frame_in_ack <= '1';
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
when STATE_WAIT_IRQ_ACK =>
wait_irq_ack <= '1';
if irq_ack = '1' then
next_reg_state <= STATE_IDLE;
end if;
end case;
end process;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_sampler is
generic(
PIX_DEPTH : positive;
MAX_WIDTH : positive;
MAX_HEIGHT : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- avalon_mm_slave
stop_and_reset : in std_logic;
idle : out std_logic;
wait_irq_ack : out std_logic;
irq_en : in std_logic;
irq_ack : in std_logic;
snapshot : in std_logic;
get_frame_info : in std_logic;
frame_width : out std_logic_vector(bit_width(max(MAX_WIDTH, MAX_HEIGHT)) - 1 downto 0);
frame_height : out std_logic_vector(bit_width(max(MAX_WIDTH, MAX_HEIGHT)) - 1 downto 0);
-- synchronizer
frame_valid : in std_logic;
line_valid : in std_logic;
data_in : in std_logic_vector(PIX_DEPTH - 1 downto 0);
-- debayer / packer / fifo
valid_out : out std_logic;
data_out : out std_logic_vector(PIX_DEPTH - 1 downto 0);
start_of_frame_out : out std_logic;
end_of_frame_out : out std_logic;
-- fifo
fifo_overflow : in std_logic;
-- st_source
end_of_frame_in : in std_logic;
end_of_frame_in_ack : out std_logic
);
end entity cmos_sensor_input_sampler;
architecture rtl of cmos_sensor_input_sampler is
-- GFI = get_frame_info
-- SNPSHT = snapshot
type state_type is (STATE_IDLE,
STATE_WAIT_END_FRAME_GFI, STATE_WAIT_START_FRAME_GFI, STATE_DATA_SKIP, STATE_LINE_LINE_BLANK_OR_LINE_FRAME_BLANK_GFI,
STATE_WAIT_END_FRAME_SNPSHT, STATE_WAIT_START_FRAME_SNPSHT, STATE_START_OF_FRAME_OUT, STATE_DATA_VALID, STATE_LINE_LINE_BLANK_SNPSHT, STATE_END_OF_FRAME_OUT, STATE_WAIT_END_OF_FRAME_IN, STATE_END_OF_FRAME_IN_ACK,
STATE_WAIT_IRQ_ACK);
signal reg_state, next_reg_state : state_type;
signal reg_frame_width_config, next_reg_frame_width_config : unsigned(frame_width'range);
signal reg_frame_height_config, next_reg_frame_height_config : unsigned(frame_height'range);
signal reg_frame_width_counter, next_reg_frame_width_counter : unsigned(frame_width'range);
signal reg_frame_height_counter, next_reg_frame_height_counter : unsigned(frame_height'range);
signal reg_data_in, next_reg_data_in : std_logic_vector(data_in'range);
begin
process(clk, reset)
begin
if reset = '1' then
reg_state <= STATE_IDLE;
reg_frame_width_config <= (others => '0');
reg_frame_height_config <= (others => '0');
reg_frame_width_counter <= (others => '0');
reg_frame_height_counter <= (others => '0');
reg_data_in <= (others => '0');
elsif rising_edge(clk) then
if stop_and_reset = '1' then
reg_state <= STATE_IDLE;
reg_frame_width_config <= (others => '0');
reg_frame_height_config <= (others => '0');
reg_frame_width_counter <= (others => '0');
reg_frame_height_counter <= (others => '0');
reg_data_in <= (others => '0');
else
reg_state <= next_reg_state;
reg_frame_width_config <= next_reg_frame_width_config;
reg_frame_height_config <= next_reg_frame_height_config;
reg_frame_width_counter <= next_reg_frame_width_counter;
reg_frame_height_counter <= next_reg_frame_height_counter;
reg_data_in <= next_reg_data_in;
end if;
end if;
end process;
process(data_in, end_of_frame_in, fifo_overflow, frame_valid, get_frame_info, irq_ack, irq_en, line_valid, reg_data_in, reg_frame_height_config, reg_frame_height_counter, reg_frame_width_config, reg_frame_width_counter, reg_state, snapshot)
begin
idle <= '0';
wait_irq_ack <= '0';
frame_width <= std_logic_vector(reg_frame_width_config);
frame_height <= std_logic_vector(reg_frame_height_config);
valid_out <= '0';
data_out <= (others => '0');
start_of_frame_out <= '0';
end_of_frame_out <= '0';
end_of_frame_in_ack <= '0';
next_reg_state <= reg_state;
next_reg_frame_width_config <= reg_frame_width_config;
next_reg_frame_height_config <= reg_frame_height_config;
next_reg_frame_width_counter <= reg_frame_width_counter;
next_reg_frame_height_counter <= reg_frame_height_counter;
next_reg_data_in <= data_in;
case reg_state is
when STATE_IDLE =>
idle <= '1';
if get_frame_info = '1' then
if frame_valid = '0' then
next_reg_state <= STATE_WAIT_START_FRAME_GFI;
elsif frame_valid = '1' then
next_reg_state <= STATE_WAIT_END_FRAME_GFI;
end if;
elsif snapshot = '1' then
if frame_valid = '0' then
next_reg_state <= STATE_WAIT_START_FRAME_SNPSHT;
elsif frame_valid = '1' then
next_reg_state <= STATE_WAIT_END_FRAME_SNPSHT;
end if;
end if;
when STATE_WAIT_END_FRAME_GFI =>
if frame_valid = '0' then
next_reg_state <= STATE_WAIT_START_FRAME_GFI;
end if;
when STATE_WAIT_START_FRAME_GFI =>
if frame_valid = '1' and line_valid = '1' then
next_reg_state <= STATE_DATA_SKIP;
next_reg_frame_width_config <= to_unsigned(1, next_reg_frame_width_config'length);
next_reg_frame_height_config <= to_unsigned(1, next_reg_frame_height_config'length);
end if;
when STATE_DATA_SKIP =>
if frame_valid = '0' then
if line_valid = '0' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
end if;
elsif frame_valid = '1' then
if line_valid = '0' then
next_reg_state <= STATE_LINE_LINE_BLANK_OR_LINE_FRAME_BLANK_GFI;
elsif line_valid = '1' then
next_reg_frame_width_config <= reg_frame_width_config + 1;
end if;
end if;
when STATE_LINE_LINE_BLANK_OR_LINE_FRAME_BLANK_GFI =>
if frame_valid = '0' and line_valid = '0' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif frame_valid = '1' and line_valid = '1' then
next_reg_state <= STATE_DATA_SKIP;
next_reg_frame_width_config <= to_unsigned(1, next_reg_frame_width_config'length);
next_reg_frame_height_config <= reg_frame_height_config + 1;
end if;
when STATE_WAIT_END_FRAME_SNPSHT =>
if frame_valid = '0' then
next_reg_state <= STATE_WAIT_START_FRAME_SNPSHT;
end if;
when STATE_WAIT_START_FRAME_SNPSHT =>
if frame_valid = '1' and line_valid = '1' then
next_reg_state <= STATE_START_OF_FRAME_OUT;
next_reg_frame_width_counter <= to_unsigned(1, next_reg_frame_width_counter'length);
next_reg_frame_height_counter <= to_unsigned(1, next_reg_frame_height_counter'length);
end if;
when STATE_START_OF_FRAME_OUT =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
valid_out <= '1';
data_out <= reg_data_in;
start_of_frame_out <= '1';
if reg_frame_width_counter < reg_frame_width_config - 1 then
next_reg_state <= STATE_DATA_VALID;
next_reg_frame_width_counter <= reg_frame_width_counter + 1;
elsif reg_frame_width_counter = reg_frame_width_config - 1 then
if reg_frame_height_counter = reg_frame_height_config then
next_reg_state <= STATE_END_OF_FRAME_OUT;
end if;
end if;
end if;
when STATE_DATA_VALID =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
valid_out <= '1';
data_out <= reg_data_in;
next_reg_frame_width_counter <= reg_frame_width_counter + 1;
if reg_frame_height_counter < reg_frame_height_config then
if reg_frame_width_counter = reg_frame_width_config then
next_reg_state <= STATE_LINE_LINE_BLANK_SNPSHT;
end if;
elsif reg_frame_height_counter = reg_frame_height_config then
if reg_frame_width_counter = reg_frame_width_config - 1 then
next_reg_state <= STATE_END_OF_FRAME_OUT;
next_reg_frame_width_counter <= reg_frame_width_counter + 1;
end if;
end if;
end if;
when STATE_LINE_LINE_BLANK_SNPSHT =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
if frame_valid = '1' and line_valid = '1' then
next_reg_state <= STATE_DATA_VALID;
next_reg_frame_width_counter <= to_unsigned(1, next_reg_frame_width_counter'length);
next_reg_frame_height_counter <= reg_frame_height_counter + 1;
end if;
end if;
when STATE_END_OF_FRAME_OUT =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
valid_out <= '1';
data_out <= reg_data_in;
end_of_frame_out <= '1';
next_reg_state <= STATE_WAIT_END_OF_FRAME_IN;
end if;
when STATE_WAIT_END_OF_FRAME_IN =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
if end_of_frame_in = '1' then
next_reg_state <= STATE_END_OF_FRAME_IN_ACK;
end if;
end if;
when STATE_END_OF_FRAME_IN_ACK =>
end_of_frame_in_ack <= '1';
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
when STATE_WAIT_IRQ_ACK =>
wait_irq_ack <= '1';
if irq_ack = '1' then
next_reg_state <= STATE_IDLE;
end if;
end case;
end process;
end architecture rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: clkgen_xilinx.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Author: Richard Pender, Pender Electronic Design
-- Description: Clock generators for Virtex and Virtex-2 fpgas
------------------------------------------------------------------------------
------------------------------------------------------------------
-- Virtex5 clock generator ---------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
--use unisim.BUFGDLL;
use unisim.BUFGMUX;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_virtex5 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end;
architecture struct of clkgen_virtex5 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
-- component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
--constant CLKIN_PERIOD_ST : string := "20.0";
constant FREQ_MHZ : integer := freq/1000;
--attribute CLKIN_PERIOD : string;
--attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, lsdclk : std_logic;
signal clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r: std_logic;
signal dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
signal clk0B, clkint, pciclkint : std_logic;
begin
gnd <= '0';
clk <= clk_i when (CLK2XEN = 0) else clk_p;
clkn <= clk_m; clk2x <= clk_i2;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
-- x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
--pragma translate_off
assert false report "PCIDLL = 1 currently not supported for virtex5_clkgen"
severity failure;
--pragma translate_on
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
clk1xu <= clk_k;
clk2xu <= clk_x;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
bufg2 : BUFG port map (I => clk_l, O => clk_m);
buf34gen : if (CLK2XEN /= 0) generate
cs0 : if (clksel = 0) generate
bufg3 : BUFG port map (I => clk_n, O => clk_i2);
end generate;
cs1 : if (clksel /= 0) generate
bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
end generate;
bufg4 : BUFG port map (I => clk_o, O => clk_p);
end generate;
dll0rst <= not cgi.pllrst;
-- HMODE_dll0 : if (((FREQ_MHZ*clk_mul)/clk_div >= 140) or (FREQ_MHZ >= 120)) generate
-- dll0 : DCM
-- generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
-- DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH")
-- port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
-- PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
-- CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
-- end generate;
-- LMODE_dll0 : if not (((FREQ_MHZ*clk_mul)/clk_div >= 140) or (FREQ_MHZ >= 120)) generate
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
-- end generate;
clk2xgen : if (CLK2XEN /= 0) generate
-- HMODE_dll2x : if ((FREQ_MHZ*clk_mul)/clk_div >= 120) generate
-- dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
-- DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH")
-- port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
-- PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
-- CLK2X => clk_n, LOCKED => dll2xlock);
-- end generate;
-- LMODE_dll2x : if not ((FREQ_MHZ*clk_mul)/clk_div >= 120) generate
dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
CLK2X => clk_n, LOCKED => dll2xlock);
-- end generate;
rstdel2x : process (clk_i, dll0lock)
begin
if dll0lock = '0' then dll2xrst <= (others => '1');
elsif rising_edge(clk_i) then
dll2xrst <= dll2xrst(1 to 3) & '0';
end if;
end process;
end generate;
clk_sd1 : if (CLK2XEN = 0) generate
clk_i2 <= clk_x;
dll2xlock <= dll0lock;
clk_sd <= clk_i;
end generate;
clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
cgo.clklock <= dll1lock;
-- HMODE_dll1 : if ((FREQ_MHZ*clk_mul)/clk_div >= (120-60*(CLK2XEN/2))) generate
-- dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
-- DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH",
-- DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
-- port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
-- PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => lsdclk, --CLK2X => clk2x,
-- LOCKED => dll1lock);
-- end generate;
-- LMODE_dll1 : if not ((FREQ_MHZ*clk_mul)/clk_div >= (120-60*(CLK2XEN/2))) generate
dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW",
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => lsdclk, --CLK2X => clk2x,
LOCKED => dll1lock);
-- end generate;
bufgx : BUFG port map (I => lsdclk, O => sdclk);
rstdel : process (clk_sd, dll2xlock)
begin
if dll2xlock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_sd) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
sdclk <= clk_i;
cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
end generate;
sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
sdclk <= clk_i2;
cgo.clklock <= dll2xlock;
end generate;
cgo.pcilock <= '1';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_virtex5" & ": virtex-5 sdram/pci clock generator, version " & tost(VERSION),
"clkgen_virtex5" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
------------------------------------------------------------------
-- Virtex7 clock generator ---------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use UNISIM.vcomponents.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_virtex7 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
freq : integer := 200000 -- clock frequency in KHz
);
port (
clkin : in std_ulogic;
clk : out std_ulogic; -- main clock
clk90 : out std_ulogic; -- main clock 90deg
clkio : out std_ulogic; -- IO ref clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type
);
end;
architecture struct of clkgen_virtex7 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
----- component PLLE2_ADV -----
component PLLE2_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT : integer := 5;
CLKFBOUT_PHASE : real := 0.0;
CLKIN1_PERIOD : real := 0.0;
CLKIN2_PERIOD : real := 0.0;
CLKOUT0_DIVIDE : integer := 1;
CLKOUT0_DUTY_CYCLE : real := 0.5;
CLKOUT0_PHASE : real := 0.0;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.5;
CLKOUT1_PHASE : real := 0.0;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.5;
CLKOUT2_PHASE : real := 0.0;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.5;
CLKOUT3_PHASE : real := 0.0;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.5;
CLKOUT4_PHASE : real := 0.0;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.5;
CLKOUT5_PHASE : real := 0.0;
COMPENSATION : string := "ZHOLD";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.0;
REF_JITTER2 : real := 0.0;
STARTUP_WAIT : string := "FALSE"
);
port (
CLKFBOUT : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
DO : out std_logic_vector (15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
end component;
constant VERSION : integer := 1;
constant period : real := 1000000.0/real(freq);
constant clkio_div : integer := freq*clk_mul/200000;
signal CLKFBOUT : std_logic;
signal CLKFBIN : std_logic;
signal int_rst : std_logic;
signal clk_nobuf : std_logic;
signal clk90_nobuf : std_logic;
signal clkio_nobuf : std_logic;
begin
CLKFBIN <= CLKFBOUT;
int_rst <= not cgi.pllrst;
PLLE2_ADV_inst : PLLE2_ADV
generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => clk_mul, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
-- CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD => period,
CLKIN2_PERIOD => 0.0,
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
CLKOUT0_DIVIDE => clk_div,
CLKOUT1_DIVIDE => clk_div,
CLKOUT2_DIVIDE => clkio_div,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 90.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL
DIVCLK_DIVIDE => 1, -- Master division value (1-56)
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => 0.0,
REF_JITTER2 => 0.0,
STARTUP_WAIT => "TRUE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => clk_nobuf,
CLKOUT1 => clk90_nobuf,
CLKOUT2 => clkio_nobuf,
CLKOUT3 => OPEN,
CLKOUT4 => OPEN,
CLKOUT5 => OPEN,
-- DRP Ports: 16-bit (each) output: Dynamic reconfigration ports
DO => OPEN,
DRDY => OPEN,
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => CLKFBOUT,
-- Status Ports: 1-bit (each) output: PLL status ports
LOCKED => cgo.clklock,
-- Clock Inputs: 1-bit (each) input: Clock inputs
CLKIN1 => clkin,
CLKIN2 => '0',
-- Con trol Ports: 1-bit (each) input: PLL control ports
CLKINSEL => '1',
PWRDWN => '0',
RST => int_rst,
-- DRP Ports: 7-bit (each) input: Dynamic reconfigration ports
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => "0000000000000000",
DWE => '0',
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => CLKFBIN
);
cgo.pcilock <= '0';
bufgclk0 : BUFG port map (I => clk_nobuf, O => clk);
bufgclk90 : BUFG port map (I => clk90_nobuf, O => clk90);
bufgclkio : BUFG port map (I => clkio_nobuf, O => clkio);
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_virtex7" & ": virtex-7 sdram/pci clock generator, version " & tost(VERSION),
"clkgen_virtex7" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
-- pragma translate_on
entity clkand_unisim is
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkand_unisim is
component BUFGCE
port(
O : out STD_ULOGIC;
CE: in STD_ULOGIC;
I : in STD_ULOGIC
);
end component;
begin
buf : bufgce port map(I => i, CE => en, O => o);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
-- pragma translate_on
entity clkmux_unisim is
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkmux_unisim is
component bufgmux is
port(
i0, i1 : in std_ulogic;
s : in std_ulogic;
o : out std_ulogic);
end component;
signal sel0, sel1, cg0, cg1 : std_ulogic;
begin
buf : bufgmux port map(S => sel, I0 => i0, I1 => i1, O => o);
end architecture;
|
-------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- Description
-- Contains a testbench for the generic UART entity.
--
-- To Do:
-- -
--
-- Author(s):
-- - Magnus Rosenius, [email protected]
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Authors and OPENCORES.ORG
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- TestUart.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
use work.rio_common.all;
-------------------------------------------------------------------------------
-- Entity for TestUart.
-------------------------------------------------------------------------------
entity TestUart is
end entity;
-------------------------------------------------------------------------------
-- Architecture for TestUart.
-------------------------------------------------------------------------------
architecture TestUartImpl of TestUart is
component Uart is
generic(
DIVISOR_WIDTH : natural;
DATA_WIDTH : natural);
port(
clk : in std_logic;
areset_n : in std_logic;
divisor_i : in std_logic_vector(DIVISOR_WIDTH-1 downto 0);
serial_i : in std_logic;
serial_o : out std_logic;
empty_o : out std_logic;
read_i : in std_logic;
data_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
full_o : out std_logic;
write_i : in std_logic;
data_i : in std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal clk : std_logic;
signal areset_n : std_logic;
signal rxSerial : std_logic;
signal txSerial : std_logic;
signal rxEmpty : std_logic;
signal rxRead : std_logic;
signal rxData : std_logic_vector(7 downto 0);
signal txFull : std_logic;
signal txWrite : std_logic;
signal txData : std_logic_vector(7 downto 0);
begin
-----------------------------------------------------------------------------
-- Clock generation.
-----------------------------------------------------------------------------
ClockGenerator: process
begin
clk <= '0';
wait for 20 ns;
clk <= '1';
wait for 20 ns;
end process;
-----------------------------------------------------------------------------
-- Serial port emulator.
-----------------------------------------------------------------------------
TestDriver: process
procedure SerialSend(
constant data : in std_logic_vector(7 downto 0)) is
variable outgoing : std_logic_vector(9 downto 0);
begin
-- Create the complete transmission character.
outgoing(0) := '0';
for i in 0 to 7 loop
outgoing(i+1) := data(i);
end loop;
outgoing(9) := '1';
-- Send the character.
for i in 0 to 9 loop
txSerial <= outgoing(i);
wait for 500 ns;
end loop;
end procedure;
procedure SerialReceive(
constant data : in std_logic_vector(7 downto 0)) is
variable incomming : std_logic_vector(9 downto 0);
begin
-- Receive the character.
wait until rxSerial = '0';
incomming(0) := '0';
for i in 1 to 9 loop
wait for 500 ns;
incomming(i) := rxSerial;
end loop;
-- Check if the received character is expected.
assert (incomming(0) = '0') report "Start bit." severity error;
assert (incomming(8 downto 1) = data) report "Data bit" severity error;
assert (incomming(9) = '1') report "Stop bit." severity error;
end procedure;
begin
txSerial <= '1';
txWrite <= '0';
rxRead <= '0';
areset_n <= '0';
wait until clk'event and clk = '1';
wait until clk'event and clk = '1';
areset_n <= '1';
wait until clk'event and clk = '1';
wait until clk'event and clk = '1';
---------------------------------------------------------------------------
-- Send byte to uart.
---------------------------------------------------------------------------
SerialSend(x"55");
wait until rxEmpty = '0' and clk'event and clk = '1';
rxRead <= '1';
wait until clk'event and clk = '1';
rxRead <= '0';
wait until clk'event and clk = '1';
assert rxData = x"55" report "rxData" severity error;
SerialSend(x"62");
wait until rxEmpty = '0' and clk'event and clk = '1';
rxRead <= '1';
wait until clk'event and clk = '1';
rxRead <= '0';
wait until clk'event and clk = '1';
assert rxData = x"62" report "rxData" severity error;
wait until txFull = '0' and clk'event and clk = '1';
txWrite <= '1';
txData <= x"55";
wait until clk'event and clk = '1';
txWrite <= '0';
SerialReceive(x"55");
wait until txFull = '0' and clk'event and clk = '1';
txWrite <= '1';
txData <= x"62";
wait until clk'event and clk = '1';
txWrite <= '0';
SerialReceive(x"62");
-- REMARK: Formalize the tests and write more testcases...
---------------------------------------------------------------------------
-- Test completed.
---------------------------------------------------------------------------
TestEnd;
end process;
-----------------------------------------------------------------------------
-- Instantiate the uart.
-----------------------------------------------------------------------------
UartInst: Uart
generic map(DIVISOR_WIDTH=>4, DATA_WIDTH=>8)
port map(
clk=>clk, areset_n=>areset_n,
divisor_i=>"1011",
serial_i=>txSerial, serial_o=>rxSerial,
empty_o=>rxEmpty, read_i=>rxRead, data_o=>rxData,
full_o=>txFull, write_i=>txWrite, data_i=>txData);
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:30:49 06/24/2014
-- Design Name:
-- Module Name: buffer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity buffer is
end buffer;
architecture Behavioral of buffer is
begin
end Behavioral;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex2;
constant CFG_MEMTECH : integer := virtex2;
constant CFG_PADTECH : integer := virtex2;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex2;
constant CFG_CLKMUL : integer := (13);
constant CFG_CLKDIV : integer := (20);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 1;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000019#;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (90);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (256);
constant CFG_DDRSP_RSKEW : integer := (0);
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 1;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_dma_v7_1;
USE axi_dma_v7_1.axi_dma;
ENTITY system_axi_dma_0_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_axi_dma_0_0;
ARCHITECTURE system_axi_dma_0_0_arch OF system_axi_dma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_dma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_dma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_INCLUDE_SG : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_MICRO_DMA : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s2mm_sts_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_dma;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 MM2S_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
BEGIN
U0 : axi_dma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_MULTI_CHANNEL => 0,
C_NUM_MM2S_CHANNELS => 1,
C_NUM_S2MM_CHANNELS => 1,
C_INCLUDE_SG => 0,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 0,
C_SG_LENGTH_WIDTH => 23,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_MICRO_DMA => 0,
C_INCLUDE_MM2S => 1,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_BURST_SIZE => 16,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_S2MM => 1,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_BURST_SIZE => 16,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 0,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awready => '0',
m_axi_sg_wready => '0',
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_bvalid => '0',
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_cntrl_tready => '0',
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_sts_tkeep => X"F",
s_axis_s2mm_sts_tvalid => '0',
s_axis_s2mm_sts_tlast => '0',
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut,
axi_dma_tstvec => axi_dma_tstvec
);
END system_axi_dma_0_0_arch;
|
-- $Id: rlink_core.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rlink_core - syn
-- Description: rlink core with 9bit interface
--
-- Dependencies: comlib/crc8
--
-- Test bench: tb/tb_rlink_direct
-- tb/tb_rlink_serport
-- tb/tb_rlink_tba_ttcombo
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-12-04 343 12.1 M53d xc3s1000-4 155 322 0 199 s 8.9
-- 2010-06-06 302 11.4 L68 xc3s1000-4 151 323 0 197 s 8.9
-- 2010-04-03 274 11.4 L68 xc3s1000-4 148 313 0 190 s 8.0
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 147 321 0 197 s 8.3
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 3.1.3 now numeric_std clean
-- 2010-12-25 348 3.1.2 drop RL_FLUSH support, add RL_MONI for rlink_core;
-- 2010-12-24 347 3.1.1 rename: CP_*->RL->*
-- 2010-12-22 346 3.1 wblk dcrc error: send nak, transit to s_error now;
-- rename stat flags: [cd]crc->[cd]err, ioto->rbnak,
-- ioerr->rberr; '111' cmd now aborts via s_txnak and
-- sets cerr flag; set [cd]err on eop/nak aborts;
-- 2010-12-04 343 3.0 renamed rri_ -> rlink_; rbus V3 interface: use now
-- aval,re,we; add new states: s_rstart, s_wstart
-- 2010-06-20 308 2.6 use rbinit,rbreq,rbwe state flops to drive rb_mreq;
-- now nak on reserved cmd 111; use do_comma_abort();
-- 2010-06-18 306 2.5.1 rename rbus data fields to _rbf_
-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
-- 2010-06-03 299 2.1.2 drop unneeded unsigned casts; change init encoding
-- 2010-05-02 287 2.1.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- 2010-04-03 274 2.1 add CP_FLUSH output
-- 2009-07-12 233 2.0.1 remove snoopers
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2008-03-02 121 1.1.1 comment out snoopers
-- 2007-11-24 98 1.1 new internal init handling (addr=11111111)
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-09-15 82 1.0 Initial version, fully functional
-- 2007-06-17 58 0.5 First preliminary version
------------------------------------------------------------------------------
--
-- Overall protocol:
-- _idle : expect
-- sop -> _txsop (echo sop, , to _txsop, _rxcmd)
-- eop -> _txeop (send nak,eop , to _txnak, _txeop, _idle)
-- nak -> _txnak (silently ignore nak)
-- attn -> _txito (send ito , to _idle)
-- data -> _idle (silently ignore data)
-- _error: expect
-- sop -> _txnak (send nak , to _txnak, _error)
-- eop -> _txeop (echo eop , to _txeop, _idle)
-- nak -> _txnak (echo nak , to _txnak, _error)
-- attn -> _txito (silently ignore attn)
-- data -> _idle (silently ignore data)
-- _rxcmd: expect
-- sop -> _txnak (send nak , to _txnak, _error)
-- eop -> _txeop (echo eop , to _txeop, _idle)
-- nak -> _txnak (echo nak , to _txnak, _error)
-- attn -> _txito (silently ignore attn)
-- data -> _idle (decode command)
-- _rx...: expect
-- sop -> _txnak (send nak , to _txnak, _error)
-- eop -> _txnak (send nak,eop , to _txnak, _txeop, _idle)
-- nak -> _txnak (echo nak , to _txnak, _error)
-- attn -> _txito (silently ignore attn)
-- data -> _idle (decode data)
--
-- 7 supported commands:
--
-- 000 read reg (rreg):
-- rx: cmd addr ccrc
-- tx: cmd dl dh stat crc
-- seq: _rxcmd _rxaddr _rxccrc (_txcmd|_txnak)
-- _rstart _rreg _txdatl _txdath _txstat _txcrc -> _rxcmd
--
-- 001 read blk (rblk):
-- rx: cmd addr cnt ccrc
-- tx: cmd cnt dl dh ... stat crc
-- seq: _rxcmd _rxaddr _rxcnt _rxccrc (_txcmd|_txnak) _txcnt
-- {_rstart _rreg _txdatl _txdath _blk}*
-- _txstat _txcrc -> _rxcmd
--
-- 010 write reg (wreg):
-- rx: cmd addr dl dh ccrc
-- tx: cmd stat crc
-- seq: _rxcmd _rxaddr _rxdatl _rxdath _rxccrc (_txcmd|_txnak)
-- _wstart _wreg _txstat _txcrc -> _rxcmd
--
-- 011 write blk (wblk):
-- rx: cmd addr cnt ccrc dl dh ... dcrc
-- tx: cmd stat crc
-- seq: _rxcmd _rxaddr _rxcnt _rxccrc (_txcmd|_txnak)
-- {_rxdatl _rxdath _wstart _wreg _blk}*
-- _rxdcrc _txstat _txcrc -> (_rxcmd|_txnak)
--
-- 100 read stat (stat):
-- rx: cmd ccrc
-- tx: cmd ccmd dl dh stat crc
-- seq: _rxcmd _rxccrc (_txcmd|_txnak)
-- _txccmd _txdatl _txdath _txstat _txcrc -> _rxcmd
--
-- 101 read attn (attn):
-- rx: cmd ccrc
-- tx: cmd dl dh stat crc
-- seq: _rxcmd _rxccrc (_txcmd|_txnak)
-- _attn _txdatl _txdath _txstat _txcrc -> _rxcmd
--
-- 110 write init (init):
-- rx: cmd addr dl dh ccrc
-- tx: cmd stat crc
-- seq: _rxcmd _rxaddr _rxdatl _rxdath _rxccrc (_txcmd|_txnak)
-- _txstat _txcrc -> _rxcmd
-- like wreg, but no rp_we - rp_hold, just a 1 cycle rp_init pulse
--
-- 111 is currently not a legal command and causes a nak
-- seq: _txnak
--
-- The state bits nakcerr and nakderr determine whether cerr/derr is set
-- when s_txnak is entered. cerr is '1' during command receive, derr is '1'
-- during data wblk data receive phase:
-- nakcerr set in s_rxcmd (when command received, unless it's stat)
-- clr in s_txcmd (when wblk)
-- clr in s_txnak
-- clr in s_txcrc (for sucessful completion)
-- nakderr set in s_txcmd (when wblk)
-- clr in s_txnak
-- clr in s_txcrc (for sucessful completion)
--
-- The different rbus cycle types are encoded as:
--
-- init aval re we
-- 0 0 0 0 idle
-- 0 0 1 0 not allowed
-- 0 0 0 1 not allowed
-- 0 1 1 0 read
-- 0 1 0 1 write
-- 1 0 0 0 internal init
-- 1 0 0 1 external init
-- 1 0 1 0 not allowed
-- * * 1 1 not allowed
-- 1 1 * * not allowed
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.comlib.all;
use work.rblib.all;
use work.rlinklib.all;
entity rlink_core is -- rlink core with 9bit interface
generic (
ATOWIDTH : positive := 5; -- access timeout counter width
ITOWIDTH : positive := 6); -- idle timeout counter width
port (
CLK : in slbit; -- clock
CE_INT : in slbit := '0'; -- rri ito time unit clock enable
RESET : in slbit; -- reset
RL_DI : in slv9; -- rlink 9b: data in
RL_ENA : in slbit; -- rlink 9b: data enable
RL_BUSY : out slbit; -- rlink 9b: data busy
RL_DO : out slv9; -- rlink 9b: data out
RL_VAL : out slbit; -- rlink 9b: data valid
RL_HOLD : in slbit; -- rlink 9b: data hold
RL_MONI : out rl_moni_type; -- rlink: monitor port
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end entity rlink_core;
architecture syn of rlink_core is
type state_type is (
s_idle, -- s_idle: wait for sop
s_txito, -- s_txito: send timeout symbol
s_txsop, -- s_txsop: send sop
s_txnak, -- s_txnak: send nak
s_txeop, -- s_txeop: send eop
s_error, -- s_error: wait for eop
s_rxcmd, -- s_rxcmd: wait for cmd
s_rxaddr, -- s_rxaddr: wait for addr
s_rxdatl, -- s_rxdatl: wait for data low
s_rxdath, -- s_rxdath: wait for data high
s_rxcnt, -- s_rxcnt: wait for count
s_rxccrc, -- s_rxccrc: wait for command crc
s_txcmd, -- s_txcmd: send cmd
s_txcnt, -- s_txcnt: send cnt
s_rstart, -- s_rstart: start reg or blk read
s_rreg, -- s_rreg: do reg or blk read
s_txdatl, -- s_txdatl: send data low
s_txdath, -- s_txdath: send data high
s_wstart, -- s_wstart: start reg or blk write
s_wreg, -- s_wreg: do reg or blk write
s_blk, -- s_blk: block count handling
s_rxdcrc, -- s_rxdcrc: wait for data crc
s_attn, -- s_attn: handle attention flags
s_txccmd, -- s_txccmd: send last command
s_txstat, -- s_txstat: send status
s_txcrc -- s_txcrc: send crc
);
type regs_type is record
state : state_type; -- state
rcmd : slv8; -- received command
ccmd : slv8; -- current command
addr : slv8; -- register address
dil : slv8; -- input data, lsb
dih : slv8; -- input data, msb
dol : slv8; -- output data, lsb
doh : slv8; -- output data, msb
cnt : slv8; -- block transfer count
attn : slv16; -- attn mask
atocnt : slv(ATOWIDTH-1 downto 0); -- access timeout counter
itocnt : slv(ITOWIDTH-1 downto 0); -- idle timeout counter
itoval : slv(ITOWIDTH-1 downto 0); -- idle timeout value
itoena : slbit; -- idle timeout enable flag
anena : slbit; -- attn notification enable flag
andone : slbit; -- attn notification done
cerr : slbit; -- stat: command error
derr : slbit; -- stat: data error
rbnak: slbit; -- stat: rbus no ack or timeout
rberr : slbit; -- stat: rbus err bit set
nakeop : slbit; -- send eop after nak
nakcerr : slbit; -- set cerr after nak
nakderr : slbit; -- set derr after nak
rbinit : slbit; -- rbus init signal
rbaval : slbit; -- rbus aval signal
rbre : slbit; -- rbus re signal
rbwe : slbit; -- rbus we signal
moneop : slbit; -- rl_moni: eop send pulse
monattn : slbit; -- rl_moni: attn send pulse
monlamp : slbit; -- rl_moni: attn pending state
stat : slv3; -- external status flags
end record regs_type;
constant atocnt_init : slv(ATOWIDTH-1 downto 0) := (others=>'1');
constant itocnt_init : slv(ITOWIDTH-1 downto 0) := (others=>'0');
constant c_idle : slv4 := "0000";
constant c_sop : slv4 := "0001";
constant c_eop : slv4 := "0010";
constant c_nak : slv4 := "0011";
constant c_attn : slv4 := "0100";
constant regs_init : regs_type := (
s_idle, --
(others=>'0'), -- rcmd
(others=>'0'), -- ccmd
(others=>'0'), -- addr
(others=>'0'), -- dil
(others=>'0'), -- dih
(others=>'0'), -- dol
(others=>'0'), -- doh
(others=>'0'), -- cnt
(others=>'0'), -- attn
atocnt_init, -- atocnt
itocnt_init, -- itocnt
itocnt_init, -- itoval
'0', -- itoena
'0','0', -- anena, andone
'0','0','0','0', -- stat flags
'0','0','0', -- nakeop,nakcerr,nakderr
'0','0','0','0', -- rbinit,rbaval,rbre,rbwe
'0','0','0', -- moneop,monattn,monlamp
(others=>'0') -- stat
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal CRC_RESET : slbit := '0';
signal ICRC_ENA : slbit := '0';
signal OCRC_ENA : slbit := '0';
signal ICRC_OUT : slv8 := (others=>'0');
signal OCRC_OUT : slv8 := (others=>'0');
signal OCRC_IN : slv8 := (others=>'0');
begin
assert ITOWIDTH<=8
report "assert(ITOWIDTH<=8): max byte size ITO counter supported"
severity failure;
ICRC : crc8 -- crc generator for input data
port map (
CLK => CLK,
RESET => CRC_RESET,
ENA => ICRC_ENA,
DI => RL_DI(7 downto 0),
CRC => ICRC_OUT
);
OCRC : crc8 -- crc generator for output data
port map (
CLK => CLK,
RESET => CRC_RESET,
ENA => OCRC_ENA,
DI => OCRC_IN,
CRC => OCRC_OUT
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_INT, RL_DI, RL_ENA, RL_HOLD, RB_LAM,
RB_SRES, RB_STAT, ICRC_OUT, OCRC_OUT)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ival : slbit := '0';
variable ibusy : slbit := '0';
variable ido : slv9 := (others=>'0');
variable ato_go : slbit := '0';
variable ato_end : slbit := '0';
variable ito_go : slbit := '0';
variable ito_end : slbit := '0';
variable crcreset : slbit := '0';
variable icrcena : slbit := '0';
variable ocrcena : slbit := '0';
variable has_attn : slbit := '0';
variable snd_attn : slbit := '0';
variable idi8 : slv8 := (others=>'0');
variable is_comma : slbit := '0';
variable comma_typ : slv4 := "0000";
procedure do_comma_abort(nstate : inout state_type;
nnakeop : inout slbit;
comma_typ : in slv4) is
begin
if comma_typ=c_sop or comma_typ=c_eop or comma_typ=c_nak then
if comma_typ = c_eop then
nnakeop := '1';
end if;
nstate := s_txnak; -- next: send nak
end if;
end procedure do_comma_abort;
begin
r := R_REGS;
n := R_REGS;
idi8 := RL_DI(7 downto 0); -- get data part of RL_DI
is_comma := RL_DI(8); -- get comma marker
comma_typ := RL_DI(3 downto 0); -- get comma type
n.rbinit := '0'; -- clear rb(init|aval|re|we) by default
n.rbaval := '0'; -- they must always be set by the
n.rbre := '0'; -- 'previous state'
n.rbwe := '0'; --
n.moneop := '0'; -- default '0', only set by states
n.monattn := '0'; -- "
n.monlamp := '0'; --
ibusy := '1'; -- default is to hold input
ival := '0';
ido := (others=>'0');
crcreset := '0';
icrcena := '0';
ocrcena := '0';
for i in RB_LAM'range loop -- handle attention "LAM's"
if RB_LAM(i) = '1' then -- if LAM bit set
n.attn(i) := '1'; -- set attention bit
end if;
end loop;
has_attn := '0';
snd_attn := '0';
if unsigned(r.attn) /= 0 then -- is any of the attn bits set ?
has_attn := '1';
if r.anena='1' and r.andone='0' then -- is attn notification to be send ?
snd_attn := '1';
n.monlamp := '1'; -- set lamp flag in rl_moni
end if;
end if;
ato_go := '0'; -- default: keep access timeout in reset
ato_end := '0';
if unsigned(r.atocnt) = 0 then -- if access timeout count at zero
ato_end := '1'; -- signal expiration
end if;
ito_go := '0'; -- default: keep idle timeout in reset
ito_end := '0';
if unsigned(r.itocnt) = 0 then -- if idle timeout count at zero
ito_end := '1'; -- signal expiration
end if;
case r.state is
when s_idle => -- s_idle: wait for sop --------------
ito_go := '1'; -- idle timeout active
if snd_attn = '1' then -- if attn notification to be send
n.state := s_txito; -- next: send ito byte
else
ibusy := '0'; -- accept input
if RL_ENA = '1' then -- if input
if is_comma = '1' then -- if comma
case comma_typ is
when c_sop => -- if sop
crcreset := '1'; -- reset crc generators
n.state := s_txsop; -- next: echo it
when c_eop => -- if eop (unexpected)
n.nakeop := '1'; -- send nak,eop
n.state := s_txnak; -- next: send nak
when c_attn => -- if attn
n.state := s_txito; -- next: send ito byte
when others => null; -- other commas: silently ignore
end case;
else -- if normal data
n.state := s_idle; -- silently dropped
end if;
elsif (r.itoena='1' and -- if ito enable, expired and XSEC
ito_end='1' and CE_INT='1') then
n.state := s_txito; -- next: send ito byte
end if;
end if;
when s_txito => -- s_txito: send timeout symbol ------
if has_attn = '1' then
ido := c_rlink_dat_attn; -- if attn pending: send attn symbol
n.andone := '1';
else
ido := c_rlink_dat_idle; -- otherwise: send idle symbol
end if;
ival := '1';
if RL_HOLD = '0' then -- wait for accept
n.monattn := has_attn; -- signal on rl_moni
n.state := s_idle; -- next: wait for sop
end if;
when s_txsop => -- s_txsop: send sop -----------------
ido := c_rlink_dat_sop; -- send sop character
ival := '1';
if RL_HOLD = '0' then -- wait for accept
n.state := s_rxcmd; -- next: read first command
end if;
when s_txnak => -- s_txnak: send nak -----------------
ido := c_rlink_dat_nak; -- send nak character
ival := '1';
if RL_HOLD = '0' then -- wait for accept
n.nakeop := '0'; -- clear all 'do on nak' state flags
n.nakcerr := '0';
n.nakderr := '0';
if r.nakcerr = '1' then -- if setting cerr requested
n.cerr := '1'; -- do it
end if;
if r.nakderr = '1' then -- if settung derr requested
n.derr := '1'; -- do it
end if;
if r.nakeop = '1' then -- if eop after nak requested
n.state := s_txeop; -- next: send eop
else
n.state := s_error; -- next: error state, wait for eop
end if;
end if;
when s_txeop => -- s_txeop: send eop -----------------
ido := c_rlink_dat_eop; -- send eop character
ival := '1';
if RL_HOLD = '0' then -- wait for accept
n.moneop := '1'; -- signal on rl_moni
n.state := s_idle; -- next: idle state, wait for sop
end if;
when s_error => -- s_error: wait for eop -------------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
case comma_typ is
when c_sop => -- if sop (unexpected)
n.state := s_txnak; -- next: send nak
when c_eop => -- if eop
n.state := s_txeop; -- next: echo eop
when c_nak => -- if nak
n.state := s_txnak; -- next: echo nak
when others => null; -- other commas: silently ignore
end case;
else -- if normal data
n.state := s_error; -- silently dropped
end if;
end if;
when s_rxcmd => -- s_rxcmd: wait for cmd -------------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
case comma_typ is
when c_sop => -- if sop (unexpected)
n.state := s_txnak; -- next: send nak
when c_eop => -- if eop
n.state := s_txeop; -- next: echo eop
when c_nak => -- if nak
n.state := s_txnak; -- next: echo nak
when others => null; --other commas: silently ignore
end case;
else -- if not comma
icrcena := '1'; -- update input crc
n.rcmd := idi8; -- latch received command code
-- unless the command is stat
if RL_DI(c_rlink_cmd_rbf_code) /= c_rlink_cmd_stat then
n.nakcerr := '1'; -- set cerr on eop/nak abort
end if;
case RL_DI(c_rlink_cmd_rbf_code) is
when c_rlink_cmd_rreg |
c_rlink_cmd_rblk |
c_rlink_cmd_wreg |
c_rlink_cmd_wblk |
c_rlink_cmd_init => -- for commands needing addr(data)
n.state := s_rxaddr; -- next: read address
when c_rlink_cmd_stat |
c_rlink_cmd_attn => -- stat and attn commands
n.state := s_rxccrc; -- next: read command crc
when others =>
n.state := s_txnak; -- next: send nak
end case; -- rcmd,ccmd always hold good cmd
end if;
end if;
when s_rxaddr => -- s_rxaddr: wait for addr -----------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
do_comma_abort(n.state, n.nakeop, comma_typ);
else
icrcena := '1'; -- update input crc
n.addr := idi8; -- latch read address
case r.rcmd(c_rlink_cmd_rbf_code) is
when c_rlink_cmd_rreg => -- for rreg command
n.state := s_rxccrc; -- next: read command crc
when c_rlink_cmd_wreg |
c_rlink_cmd_init => -- for wreg, init command
n.state := s_rxdatl; -- next: read data lsb
when others => -- for rblk or wblk
n.state := s_rxcnt; -- next: read count
end case;
end if;
end if;
when s_rxdatl => -- s_rxdatl: wait for data low -------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
do_comma_abort(n.state, n.nakeop, comma_typ);
else
icrcena := '1'; -- update input crc
n.dil := idi8; -- latch data lsb part
n.state := s_rxdath; -- next: read data msb
end if;
end if;
when s_rxdath => -- s_rxdath: wait for data high ------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
do_comma_abort(n.state, n.nakeop, comma_typ);
else
icrcena := '1'; -- update input crc
n.dih := idi8; -- latch data msb part
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_wblk then -- if wblk
n.rbaval := '1'; -- prepare rbus cycle
n.state := s_wstart; -- next: start write reg
else -- otherwise
n.state := s_rxccrc; -- next: read command crc
end if;
end if;
end if;
when s_rxcnt => -- s_rxcnt: wait for count -----------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
do_comma_abort(n.state, n.nakeop, comma_typ);
else
icrcena := '1'; -- update input crc
n.cnt := idi8; -- latch count
n.state := s_rxccrc; -- next: read command crc
end if;
end if;
when s_rxccrc => -- s_rxccrc: wait for command crc ----
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
do_comma_abort(n.state, n.nakeop, comma_typ);
else
if idi8 /= ICRC_OUT then -- if crc error
-- unless the command is stat
if r.rcmd(c_rlink_cmd_rbf_code) /= c_rlink_cmd_stat then
n.cerr := '1'; -- set command error flag
end if;
n.state := s_txnak; -- next: send nak
else -- if crc ok
n.state := s_txcmd; -- next: echo command
end if;
end if;
end if;
when s_txcmd => -- s_txcmd: send cmd -----------------
ido := '0' & r.rcmd; -- send read command
ival := '1';
if RL_HOLD = '0' then -- wait for accept
ocrcena := '1'; -- update output crc
if r.rcmd(c_rlink_cmd_rbf_code) /= c_rlink_cmd_stat then --unless stat
n.ccmd := r.rcmd; -- latch current command in ccmd
n.stat := RB_STAT; -- latch external status bits
n.cerr := '0';
n.derr := '0';
n.rbnak := '0';
n.rberr := '0';
end if;
n.nakcerr := '0'; -- all command rx done up to here
case r.rcmd(c_rlink_cmd_rbf_code) is -- main command dispatcher
when c_rlink_cmd_rreg => -- rreg ----------------
n.rbaval := '1'; -- prepare rbus cycle
n.state := s_rstart; -- next: start read reg
when c_rlink_cmd_rblk => -- rblk ----------------
n.state := s_txcnt;
when c_rlink_cmd_wreg => -- wreg ----------------
n.rbaval := '1'; -- prepare rbus cycle
n.state := s_wstart; -- next: start write reg
when c_rlink_cmd_wblk => -- wblk ----------------
n.nakderr := '1'; -- set derr on eop/nak abort
n.state := s_rxdatl;
when c_rlink_cmd_stat => -- stat ----------------
n.state := s_txccmd;
when c_rlink_cmd_attn => -- attn ----------------
n.state := s_attn;
when c_rlink_cmd_init => -- init ----------------
n.rbinit := '1'; -- send init pulse
if r.addr(7 downto 3) = "11111" then -- is internal init
if r.addr(2 downto 0) = "111" then -- is rri init
n.anena := r.dih(c_rlink_iint_rbf_anena - 8);
n.itoena := r.dih(c_rlink_iint_rbf_itoena - 8);
n.itoval := r.dil(ITOWIDTH-1 downto 0);
-- note: itocnt will load in next
-- cycle because ito_go=0, so no
-- action required here
end if;
else -- is external init
n.rbwe := '1'; -- send init with we
end if;
n.state := s_txstat;
when others => -- '111' ---------------
n.state := s_txnak; -- send NAK on reserved command
end case;
end if;
when s_txcnt => -- s_txcnt: send cnt -----------------
ido := '0' & r.cnt; -- send cnt
ival := '1';
if RL_HOLD = '0' then -- wait for accept
ocrcena := '1'; -- update output crc
n.rbaval := '1'; -- prepare rbus cycle
n.state := s_rstart; -- next: start first read reg
end if;
when s_rstart => -- s_rstart: start reg or blk read ---
n.rbaval := '1'; -- start actual read cycle
n.rbre := '1';
n.state := s_rreg; -- next: reg read
when s_rreg => -- s_rreg: do reg or blk read --------
-- this state handles all rbus reads
ato_go := '1'; -- activate timeout counter
if RB_SRES.err = '1' then -- latch rbus error flag
n.rberr := '1';
end if;
n.doh := RB_SRES.dout(15 downto 8); -- latch data
n.dol := RB_SRES.dout( 7 downto 0);
n.stat := RB_STAT; -- latch external status bits
if RB_SRES.busy='0' or ato_end='1' then -- wait for non-busy or timeout
if RB_SRES.busy='1' and ato_end='1' then -- if timeout and still busy
n.rbnak := '1'; -- set rbus nak flag
elsif RB_SRES.ack = '0' then -- if non-busy and no ack
n.rbnak := '1'; -- set rbus nak flag
end if;
n.state := s_txdatl; -- next: send data lsb
else -- otherwise rbus read continues
n.rbaval := '1'; -- extend cycle
n.rbre := '1';
end if;
when s_txdatl => -- s_txdatl: send data low -----------
ido := '0' & r.dol; -- send data
ival := '1';
if RL_HOLD = '0' then -- wait for accept
ocrcena := '1'; -- update output crc
n.state := s_txdath; -- next: send data msb
end if;
when s_txdath => -- s_txdath: send data high
ido := '0' & r.doh; -- send data
ival := '1';
if RL_HOLD = '0' then -- wait for accept
ocrcena := '1'; -- update output crc
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_rblk then -- if rblk
n.state := s_blk; -- next: block count handling
else -- otherwise
n.state := s_txstat; -- next: send stat
end if;
end if;
when s_wstart => -- s_wstart: start reg or blk write --
n.rbaval := '1'; -- start actual write cycle
n.rbwe := '1';
n.state := s_wreg; -- next: reg write
when s_wreg => -- s_wreg: do reg or blk write -------
-- this state handles all rbus writes
ato_go := '1'; -- activate timeout counter
if RB_SRES.err = '1' then -- latch rbus error flag
n.rberr := '1';
end if;
n.stat := RB_STAT; -- latch external status bits
if RB_SRES.busy='0' or ato_end='1' then -- wait for non-busy or timeout
if RB_SRES.busy='1' and ato_end='1' then -- if timeout and still busy
n.rbnak := '1'; -- set rbus nak flag
elsif RB_SRES.ack='0' then -- if non-busy and no ack
n.rbnak := '1'; -- set rbus nak flag
end if;
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_wblk then -- if wblk
n.state := s_blk; -- next: block count handling
else -- otherwise
n.state := s_txstat; -- next: send stat
end if;
else -- otherwise rbus write continues
n.rbaval := '1'; -- extend cycle
n.rbwe := '1';
end if;
when s_blk => -- s_blk: block count handling -------
n.cnt := slv(unsigned(r.cnt) - 1);-- decrement transfer count
if unsigned(r.cnt) = 0 then -- if last transfer
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_rblk then -- if rblk
n.state := s_txstat; -- next: send stat
else -- otherwise
n.state := s_rxdcrc; -- next: read data crc
end if;
else -- otherwise more to transfer
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_rblk then -- if rblk
n.rbaval := '1'; -- prepare rbus cycle
n.state := s_rstart; -- next: start read blk
else -- otherwise
n.state := s_rxdatl; -- next: read data
end if;
end if;
when s_rxdcrc => -- s_rxdcrc: wait for data crc -------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
do_comma_abort(n.state, n.nakeop, comma_typ);
else
if idi8 /= ICRC_OUT then -- if crc error
n.derr := '1'; -- set data error flag
end if;
n.state := s_txstat; -- next: echo command
end if;
end if;
when s_attn => -- s_attn: handle attention flags ----
n.dol := r.attn(7 downto 0); -- move attention flags to do buffer
n.doh := r.attn(15 downto 8);
n.attn := RB_LAM; -- LAM in current cycle send next time
n.andone := '0'; -- reenable attn nofification
n.state := s_txdatl; -- next: send data lsb
when s_txccmd => -- s_txccmd: send last command
ido := '0' & r.ccmd; -- send last accepted command
ival := '1';
if RL_HOLD = '0' then -- wait for accept
ocrcena := '1'; -- update output crc
n.state := s_txdatl; -- next: send last data lsb
end if;
when s_txstat => -- s_txstat: send status -------------
ido := (others=>'0');
ido(c_rlink_stat_rbf_stat) := r.stat;
ido(c_rlink_stat_rbf_attn) := has_attn;
ido(c_rlink_stat_rbf_cerr) := r.cerr;
ido(c_rlink_stat_rbf_derr) := r.derr;
ido(c_rlink_stat_rbf_rbnak) := r.rbnak;
ido(c_rlink_stat_rbf_rberr) := r.rberr;
ival := '1';
if RL_HOLD ='0' then -- wait for accept
ocrcena := '1'; -- update output crc
n.state := s_txcrc; -- next: send crc
end if;
when s_txcrc => -- s_txcrc: send crc -----------------
ido := "0" & OCRC_OUT; -- send crc code
ival := '1';
if RL_HOLD = '0' then -- wait for accept
-- if dcrc seen in wblk
if r.rcmd(c_rlink_cmd_rbf_code)=c_rlink_cmd_wblk and r.derr='1' then
n.state := s_txnak; -- next: send nak
else -- otherwise
n.nakcerr := '0'; -- clear 'set on nak' requests
n.nakderr := '0';
n.state := s_rxcmd; -- next: read command or eop
end if;
end if;
when others => null; -- <> --------------------------------
end case;
if ato_go = '0' then -- handle access timeout counter
n.atocnt := atocnt_init; -- if ato_go=0, keep in reset
else
n.atocnt := slv(unsigned(r.atocnt) - 1);-- otherwise count down
end if;
if ito_go = '0' then -- handle idle timeout counter
n.itocnt := r.itoval; -- if ito_go=0, keep at start value
else
if CE_INT = '1' then
n.itocnt := slv(unsigned(r.itocnt) - 1);-- otherwise cnt dn every CE_INT
end if;
end if;
N_REGS <= n;
RL_BUSY <= ibusy;
RL_DO <= ido;
RL_VAL <= ival;
RL_MONI.eop <= r.moneop;
RL_MONI.attn <= r.monattn;
RL_MONI.lamp <= r.monlamp;
RB_MREQ <= rb_mreq_init;
RB_MREQ.aval <= r.rbaval;
RB_MREQ.re <= r.rbre;
RB_MREQ.we <= r.rbwe;
RB_MREQ.init <= r.rbinit;
RB_MREQ.addr <= r.addr;
RB_MREQ.din <= r.dih & r.dil;
CRC_RESET <= crcreset;
ICRC_ENA <= icrcena;
OCRC_ENA <= ocrcena;
OCRC_IN <= ido(7 downto 0);
end process proc_next;
end syn;
|
-- $Id: rlink_core.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rlink_core - syn
-- Description: rlink core with 9bit interface
--
-- Dependencies: comlib/crc8
--
-- Test bench: tb/tb_rlink_direct
-- tb/tb_rlink_serport
-- tb/tb_rlink_tba_ttcombo
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-12-04 343 12.1 M53d xc3s1000-4 155 322 0 199 s 8.9
-- 2010-06-06 302 11.4 L68 xc3s1000-4 151 323 0 197 s 8.9
-- 2010-04-03 274 11.4 L68 xc3s1000-4 148 313 0 190 s 8.0
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 147 321 0 197 s 8.3
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 3.1.3 now numeric_std clean
-- 2010-12-25 348 3.1.2 drop RL_FLUSH support, add RL_MONI for rlink_core;
-- 2010-12-24 347 3.1.1 rename: CP_*->RL->*
-- 2010-12-22 346 3.1 wblk dcrc error: send nak, transit to s_error now;
-- rename stat flags: [cd]crc->[cd]err, ioto->rbnak,
-- ioerr->rberr; '111' cmd now aborts via s_txnak and
-- sets cerr flag; set [cd]err on eop/nak aborts;
-- 2010-12-04 343 3.0 renamed rri_ -> rlink_; rbus V3 interface: use now
-- aval,re,we; add new states: s_rstart, s_wstart
-- 2010-06-20 308 2.6 use rbinit,rbreq,rbwe state flops to drive rb_mreq;
-- now nak on reserved cmd 111; use do_comma_abort();
-- 2010-06-18 306 2.5.1 rename rbus data fields to _rbf_
-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
-- 2010-06-03 299 2.1.2 drop unneeded unsigned casts; change init encoding
-- 2010-05-02 287 2.1.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- 2010-04-03 274 2.1 add CP_FLUSH output
-- 2009-07-12 233 2.0.1 remove snoopers
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2008-03-02 121 1.1.1 comment out snoopers
-- 2007-11-24 98 1.1 new internal init handling (addr=11111111)
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-09-15 82 1.0 Initial version, fully functional
-- 2007-06-17 58 0.5 First preliminary version
------------------------------------------------------------------------------
--
-- Overall protocol:
-- _idle : expect
-- sop -> _txsop (echo sop, , to _txsop, _rxcmd)
-- eop -> _txeop (send nak,eop , to _txnak, _txeop, _idle)
-- nak -> _txnak (silently ignore nak)
-- attn -> _txito (send ito , to _idle)
-- data -> _idle (silently ignore data)
-- _error: expect
-- sop -> _txnak (send nak , to _txnak, _error)
-- eop -> _txeop (echo eop , to _txeop, _idle)
-- nak -> _txnak (echo nak , to _txnak, _error)
-- attn -> _txito (silently ignore attn)
-- data -> _idle (silently ignore data)
-- _rxcmd: expect
-- sop -> _txnak (send nak , to _txnak, _error)
-- eop -> _txeop (echo eop , to _txeop, _idle)
-- nak -> _txnak (echo nak , to _txnak, _error)
-- attn -> _txito (silently ignore attn)
-- data -> _idle (decode command)
-- _rx...: expect
-- sop -> _txnak (send nak , to _txnak, _error)
-- eop -> _txnak (send nak,eop , to _txnak, _txeop, _idle)
-- nak -> _txnak (echo nak , to _txnak, _error)
-- attn -> _txito (silently ignore attn)
-- data -> _idle (decode data)
--
-- 7 supported commands:
--
-- 000 read reg (rreg):
-- rx: cmd addr ccrc
-- tx: cmd dl dh stat crc
-- seq: _rxcmd _rxaddr _rxccrc (_txcmd|_txnak)
-- _rstart _rreg _txdatl _txdath _txstat _txcrc -> _rxcmd
--
-- 001 read blk (rblk):
-- rx: cmd addr cnt ccrc
-- tx: cmd cnt dl dh ... stat crc
-- seq: _rxcmd _rxaddr _rxcnt _rxccrc (_txcmd|_txnak) _txcnt
-- {_rstart _rreg _txdatl _txdath _blk}*
-- _txstat _txcrc -> _rxcmd
--
-- 010 write reg (wreg):
-- rx: cmd addr dl dh ccrc
-- tx: cmd stat crc
-- seq: _rxcmd _rxaddr _rxdatl _rxdath _rxccrc (_txcmd|_txnak)
-- _wstart _wreg _txstat _txcrc -> _rxcmd
--
-- 011 write blk (wblk):
-- rx: cmd addr cnt ccrc dl dh ... dcrc
-- tx: cmd stat crc
-- seq: _rxcmd _rxaddr _rxcnt _rxccrc (_txcmd|_txnak)
-- {_rxdatl _rxdath _wstart _wreg _blk}*
-- _rxdcrc _txstat _txcrc -> (_rxcmd|_txnak)
--
-- 100 read stat (stat):
-- rx: cmd ccrc
-- tx: cmd ccmd dl dh stat crc
-- seq: _rxcmd _rxccrc (_txcmd|_txnak)
-- _txccmd _txdatl _txdath _txstat _txcrc -> _rxcmd
--
-- 101 read attn (attn):
-- rx: cmd ccrc
-- tx: cmd dl dh stat crc
-- seq: _rxcmd _rxccrc (_txcmd|_txnak)
-- _attn _txdatl _txdath _txstat _txcrc -> _rxcmd
--
-- 110 write init (init):
-- rx: cmd addr dl dh ccrc
-- tx: cmd stat crc
-- seq: _rxcmd _rxaddr _rxdatl _rxdath _rxccrc (_txcmd|_txnak)
-- _txstat _txcrc -> _rxcmd
-- like wreg, but no rp_we - rp_hold, just a 1 cycle rp_init pulse
--
-- 111 is currently not a legal command and causes a nak
-- seq: _txnak
--
-- The state bits nakcerr and nakderr determine whether cerr/derr is set
-- when s_txnak is entered. cerr is '1' during command receive, derr is '1'
-- during data wblk data receive phase:
-- nakcerr set in s_rxcmd (when command received, unless it's stat)
-- clr in s_txcmd (when wblk)
-- clr in s_txnak
-- clr in s_txcrc (for sucessful completion)
-- nakderr set in s_txcmd (when wblk)
-- clr in s_txnak
-- clr in s_txcrc (for sucessful completion)
--
-- The different rbus cycle types are encoded as:
--
-- init aval re we
-- 0 0 0 0 idle
-- 0 0 1 0 not allowed
-- 0 0 0 1 not allowed
-- 0 1 1 0 read
-- 0 1 0 1 write
-- 1 0 0 0 internal init
-- 1 0 0 1 external init
-- 1 0 1 0 not allowed
-- * * 1 1 not allowed
-- 1 1 * * not allowed
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.comlib.all;
use work.rblib.all;
use work.rlinklib.all;
entity rlink_core is -- rlink core with 9bit interface
generic (
ATOWIDTH : positive := 5; -- access timeout counter width
ITOWIDTH : positive := 6); -- idle timeout counter width
port (
CLK : in slbit; -- clock
CE_INT : in slbit := '0'; -- rri ito time unit clock enable
RESET : in slbit; -- reset
RL_DI : in slv9; -- rlink 9b: data in
RL_ENA : in slbit; -- rlink 9b: data enable
RL_BUSY : out slbit; -- rlink 9b: data busy
RL_DO : out slv9; -- rlink 9b: data out
RL_VAL : out slbit; -- rlink 9b: data valid
RL_HOLD : in slbit; -- rlink 9b: data hold
RL_MONI : out rl_moni_type; -- rlink: monitor port
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end entity rlink_core;
architecture syn of rlink_core is
type state_type is (
s_idle, -- s_idle: wait for sop
s_txito, -- s_txito: send timeout symbol
s_txsop, -- s_txsop: send sop
s_txnak, -- s_txnak: send nak
s_txeop, -- s_txeop: send eop
s_error, -- s_error: wait for eop
s_rxcmd, -- s_rxcmd: wait for cmd
s_rxaddr, -- s_rxaddr: wait for addr
s_rxdatl, -- s_rxdatl: wait for data low
s_rxdath, -- s_rxdath: wait for data high
s_rxcnt, -- s_rxcnt: wait for count
s_rxccrc, -- s_rxccrc: wait for command crc
s_txcmd, -- s_txcmd: send cmd
s_txcnt, -- s_txcnt: send cnt
s_rstart, -- s_rstart: start reg or blk read
s_rreg, -- s_rreg: do reg or blk read
s_txdatl, -- s_txdatl: send data low
s_txdath, -- s_txdath: send data high
s_wstart, -- s_wstart: start reg or blk write
s_wreg, -- s_wreg: do reg or blk write
s_blk, -- s_blk: block count handling
s_rxdcrc, -- s_rxdcrc: wait for data crc
s_attn, -- s_attn: handle attention flags
s_txccmd, -- s_txccmd: send last command
s_txstat, -- s_txstat: send status
s_txcrc -- s_txcrc: send crc
);
type regs_type is record
state : state_type; -- state
rcmd : slv8; -- received command
ccmd : slv8; -- current command
addr : slv8; -- register address
dil : slv8; -- input data, lsb
dih : slv8; -- input data, msb
dol : slv8; -- output data, lsb
doh : slv8; -- output data, msb
cnt : slv8; -- block transfer count
attn : slv16; -- attn mask
atocnt : slv(ATOWIDTH-1 downto 0); -- access timeout counter
itocnt : slv(ITOWIDTH-1 downto 0); -- idle timeout counter
itoval : slv(ITOWIDTH-1 downto 0); -- idle timeout value
itoena : slbit; -- idle timeout enable flag
anena : slbit; -- attn notification enable flag
andone : slbit; -- attn notification done
cerr : slbit; -- stat: command error
derr : slbit; -- stat: data error
rbnak: slbit; -- stat: rbus no ack or timeout
rberr : slbit; -- stat: rbus err bit set
nakeop : slbit; -- send eop after nak
nakcerr : slbit; -- set cerr after nak
nakderr : slbit; -- set derr after nak
rbinit : slbit; -- rbus init signal
rbaval : slbit; -- rbus aval signal
rbre : slbit; -- rbus re signal
rbwe : slbit; -- rbus we signal
moneop : slbit; -- rl_moni: eop send pulse
monattn : slbit; -- rl_moni: attn send pulse
monlamp : slbit; -- rl_moni: attn pending state
stat : slv3; -- external status flags
end record regs_type;
constant atocnt_init : slv(ATOWIDTH-1 downto 0) := (others=>'1');
constant itocnt_init : slv(ITOWIDTH-1 downto 0) := (others=>'0');
constant c_idle : slv4 := "0000";
constant c_sop : slv4 := "0001";
constant c_eop : slv4 := "0010";
constant c_nak : slv4 := "0011";
constant c_attn : slv4 := "0100";
constant regs_init : regs_type := (
s_idle, --
(others=>'0'), -- rcmd
(others=>'0'), -- ccmd
(others=>'0'), -- addr
(others=>'0'), -- dil
(others=>'0'), -- dih
(others=>'0'), -- dol
(others=>'0'), -- doh
(others=>'0'), -- cnt
(others=>'0'), -- attn
atocnt_init, -- atocnt
itocnt_init, -- itocnt
itocnt_init, -- itoval
'0', -- itoena
'0','0', -- anena, andone
'0','0','0','0', -- stat flags
'0','0','0', -- nakeop,nakcerr,nakderr
'0','0','0','0', -- rbinit,rbaval,rbre,rbwe
'0','0','0', -- moneop,monattn,monlamp
(others=>'0') -- stat
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal CRC_RESET : slbit := '0';
signal ICRC_ENA : slbit := '0';
signal OCRC_ENA : slbit := '0';
signal ICRC_OUT : slv8 := (others=>'0');
signal OCRC_OUT : slv8 := (others=>'0');
signal OCRC_IN : slv8 := (others=>'0');
begin
assert ITOWIDTH<=8
report "assert(ITOWIDTH<=8): max byte size ITO counter supported"
severity failure;
ICRC : crc8 -- crc generator for input data
port map (
CLK => CLK,
RESET => CRC_RESET,
ENA => ICRC_ENA,
DI => RL_DI(7 downto 0),
CRC => ICRC_OUT
);
OCRC : crc8 -- crc generator for output data
port map (
CLK => CLK,
RESET => CRC_RESET,
ENA => OCRC_ENA,
DI => OCRC_IN,
CRC => OCRC_OUT
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_INT, RL_DI, RL_ENA, RL_HOLD, RB_LAM,
RB_SRES, RB_STAT, ICRC_OUT, OCRC_OUT)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ival : slbit := '0';
variable ibusy : slbit := '0';
variable ido : slv9 := (others=>'0');
variable ato_go : slbit := '0';
variable ato_end : slbit := '0';
variable ito_go : slbit := '0';
variable ito_end : slbit := '0';
variable crcreset : slbit := '0';
variable icrcena : slbit := '0';
variable ocrcena : slbit := '0';
variable has_attn : slbit := '0';
variable snd_attn : slbit := '0';
variable idi8 : slv8 := (others=>'0');
variable is_comma : slbit := '0';
variable comma_typ : slv4 := "0000";
procedure do_comma_abort(nstate : inout state_type;
nnakeop : inout slbit;
comma_typ : in slv4) is
begin
if comma_typ=c_sop or comma_typ=c_eop or comma_typ=c_nak then
if comma_typ = c_eop then
nnakeop := '1';
end if;
nstate := s_txnak; -- next: send nak
end if;
end procedure do_comma_abort;
begin
r := R_REGS;
n := R_REGS;
idi8 := RL_DI(7 downto 0); -- get data part of RL_DI
is_comma := RL_DI(8); -- get comma marker
comma_typ := RL_DI(3 downto 0); -- get comma type
n.rbinit := '0'; -- clear rb(init|aval|re|we) by default
n.rbaval := '0'; -- they must always be set by the
n.rbre := '0'; -- 'previous state'
n.rbwe := '0'; --
n.moneop := '0'; -- default '0', only set by states
n.monattn := '0'; -- "
n.monlamp := '0'; --
ibusy := '1'; -- default is to hold input
ival := '0';
ido := (others=>'0');
crcreset := '0';
icrcena := '0';
ocrcena := '0';
for i in RB_LAM'range loop -- handle attention "LAM's"
if RB_LAM(i) = '1' then -- if LAM bit set
n.attn(i) := '1'; -- set attention bit
end if;
end loop;
has_attn := '0';
snd_attn := '0';
if unsigned(r.attn) /= 0 then -- is any of the attn bits set ?
has_attn := '1';
if r.anena='1' and r.andone='0' then -- is attn notification to be send ?
snd_attn := '1';
n.monlamp := '1'; -- set lamp flag in rl_moni
end if;
end if;
ato_go := '0'; -- default: keep access timeout in reset
ato_end := '0';
if unsigned(r.atocnt) = 0 then -- if access timeout count at zero
ato_end := '1'; -- signal expiration
end if;
ito_go := '0'; -- default: keep idle timeout in reset
ito_end := '0';
if unsigned(r.itocnt) = 0 then -- if idle timeout count at zero
ito_end := '1'; -- signal expiration
end if;
case r.state is
when s_idle => -- s_idle: wait for sop --------------
ito_go := '1'; -- idle timeout active
if snd_attn = '1' then -- if attn notification to be send
n.state := s_txito; -- next: send ito byte
else
ibusy := '0'; -- accept input
if RL_ENA = '1' then -- if input
if is_comma = '1' then -- if comma
case comma_typ is
when c_sop => -- if sop
crcreset := '1'; -- reset crc generators
n.state := s_txsop; -- next: echo it
when c_eop => -- if eop (unexpected)
n.nakeop := '1'; -- send nak,eop
n.state := s_txnak; -- next: send nak
when c_attn => -- if attn
n.state := s_txito; -- next: send ito byte
when others => null; -- other commas: silently ignore
end case;
else -- if normal data
n.state := s_idle; -- silently dropped
end if;
elsif (r.itoena='1' and -- if ito enable, expired and XSEC
ito_end='1' and CE_INT='1') then
n.state := s_txito; -- next: send ito byte
end if;
end if;
when s_txito => -- s_txito: send timeout symbol ------
if has_attn = '1' then
ido := c_rlink_dat_attn; -- if attn pending: send attn symbol
n.andone := '1';
else
ido := c_rlink_dat_idle; -- otherwise: send idle symbol
end if;
ival := '1';
if RL_HOLD = '0' then -- wait for accept
n.monattn := has_attn; -- signal on rl_moni
n.state := s_idle; -- next: wait for sop
end if;
when s_txsop => -- s_txsop: send sop -----------------
ido := c_rlink_dat_sop; -- send sop character
ival := '1';
if RL_HOLD = '0' then -- wait for accept
n.state := s_rxcmd; -- next: read first command
end if;
when s_txnak => -- s_txnak: send nak -----------------
ido := c_rlink_dat_nak; -- send nak character
ival := '1';
if RL_HOLD = '0' then -- wait for accept
n.nakeop := '0'; -- clear all 'do on nak' state flags
n.nakcerr := '0';
n.nakderr := '0';
if r.nakcerr = '1' then -- if setting cerr requested
n.cerr := '1'; -- do it
end if;
if r.nakderr = '1' then -- if settung derr requested
n.derr := '1'; -- do it
end if;
if r.nakeop = '1' then -- if eop after nak requested
n.state := s_txeop; -- next: send eop
else
n.state := s_error; -- next: error state, wait for eop
end if;
end if;
when s_txeop => -- s_txeop: send eop -----------------
ido := c_rlink_dat_eop; -- send eop character
ival := '1';
if RL_HOLD = '0' then -- wait for accept
n.moneop := '1'; -- signal on rl_moni
n.state := s_idle; -- next: idle state, wait for sop
end if;
when s_error => -- s_error: wait for eop -------------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
case comma_typ is
when c_sop => -- if sop (unexpected)
n.state := s_txnak; -- next: send nak
when c_eop => -- if eop
n.state := s_txeop; -- next: echo eop
when c_nak => -- if nak
n.state := s_txnak; -- next: echo nak
when others => null; -- other commas: silently ignore
end case;
else -- if normal data
n.state := s_error; -- silently dropped
end if;
end if;
when s_rxcmd => -- s_rxcmd: wait for cmd -------------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
case comma_typ is
when c_sop => -- if sop (unexpected)
n.state := s_txnak; -- next: send nak
when c_eop => -- if eop
n.state := s_txeop; -- next: echo eop
when c_nak => -- if nak
n.state := s_txnak; -- next: echo nak
when others => null; --other commas: silently ignore
end case;
else -- if not comma
icrcena := '1'; -- update input crc
n.rcmd := idi8; -- latch received command code
-- unless the command is stat
if RL_DI(c_rlink_cmd_rbf_code) /= c_rlink_cmd_stat then
n.nakcerr := '1'; -- set cerr on eop/nak abort
end if;
case RL_DI(c_rlink_cmd_rbf_code) is
when c_rlink_cmd_rreg |
c_rlink_cmd_rblk |
c_rlink_cmd_wreg |
c_rlink_cmd_wblk |
c_rlink_cmd_init => -- for commands needing addr(data)
n.state := s_rxaddr; -- next: read address
when c_rlink_cmd_stat |
c_rlink_cmd_attn => -- stat and attn commands
n.state := s_rxccrc; -- next: read command crc
when others =>
n.state := s_txnak; -- next: send nak
end case; -- rcmd,ccmd always hold good cmd
end if;
end if;
when s_rxaddr => -- s_rxaddr: wait for addr -----------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
do_comma_abort(n.state, n.nakeop, comma_typ);
else
icrcena := '1'; -- update input crc
n.addr := idi8; -- latch read address
case r.rcmd(c_rlink_cmd_rbf_code) is
when c_rlink_cmd_rreg => -- for rreg command
n.state := s_rxccrc; -- next: read command crc
when c_rlink_cmd_wreg |
c_rlink_cmd_init => -- for wreg, init command
n.state := s_rxdatl; -- next: read data lsb
when others => -- for rblk or wblk
n.state := s_rxcnt; -- next: read count
end case;
end if;
end if;
when s_rxdatl => -- s_rxdatl: wait for data low -------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
do_comma_abort(n.state, n.nakeop, comma_typ);
else
icrcena := '1'; -- update input crc
n.dil := idi8; -- latch data lsb part
n.state := s_rxdath; -- next: read data msb
end if;
end if;
when s_rxdath => -- s_rxdath: wait for data high ------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
do_comma_abort(n.state, n.nakeop, comma_typ);
else
icrcena := '1'; -- update input crc
n.dih := idi8; -- latch data msb part
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_wblk then -- if wblk
n.rbaval := '1'; -- prepare rbus cycle
n.state := s_wstart; -- next: start write reg
else -- otherwise
n.state := s_rxccrc; -- next: read command crc
end if;
end if;
end if;
when s_rxcnt => -- s_rxcnt: wait for count -----------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
do_comma_abort(n.state, n.nakeop, comma_typ);
else
icrcena := '1'; -- update input crc
n.cnt := idi8; -- latch count
n.state := s_rxccrc; -- next: read command crc
end if;
end if;
when s_rxccrc => -- s_rxccrc: wait for command crc ----
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
do_comma_abort(n.state, n.nakeop, comma_typ);
else
if idi8 /= ICRC_OUT then -- if crc error
-- unless the command is stat
if r.rcmd(c_rlink_cmd_rbf_code) /= c_rlink_cmd_stat then
n.cerr := '1'; -- set command error flag
end if;
n.state := s_txnak; -- next: send nak
else -- if crc ok
n.state := s_txcmd; -- next: echo command
end if;
end if;
end if;
when s_txcmd => -- s_txcmd: send cmd -----------------
ido := '0' & r.rcmd; -- send read command
ival := '1';
if RL_HOLD = '0' then -- wait for accept
ocrcena := '1'; -- update output crc
if r.rcmd(c_rlink_cmd_rbf_code) /= c_rlink_cmd_stat then --unless stat
n.ccmd := r.rcmd; -- latch current command in ccmd
n.stat := RB_STAT; -- latch external status bits
n.cerr := '0';
n.derr := '0';
n.rbnak := '0';
n.rberr := '0';
end if;
n.nakcerr := '0'; -- all command rx done up to here
case r.rcmd(c_rlink_cmd_rbf_code) is -- main command dispatcher
when c_rlink_cmd_rreg => -- rreg ----------------
n.rbaval := '1'; -- prepare rbus cycle
n.state := s_rstart; -- next: start read reg
when c_rlink_cmd_rblk => -- rblk ----------------
n.state := s_txcnt;
when c_rlink_cmd_wreg => -- wreg ----------------
n.rbaval := '1'; -- prepare rbus cycle
n.state := s_wstart; -- next: start write reg
when c_rlink_cmd_wblk => -- wblk ----------------
n.nakderr := '1'; -- set derr on eop/nak abort
n.state := s_rxdatl;
when c_rlink_cmd_stat => -- stat ----------------
n.state := s_txccmd;
when c_rlink_cmd_attn => -- attn ----------------
n.state := s_attn;
when c_rlink_cmd_init => -- init ----------------
n.rbinit := '1'; -- send init pulse
if r.addr(7 downto 3) = "11111" then -- is internal init
if r.addr(2 downto 0) = "111" then -- is rri init
n.anena := r.dih(c_rlink_iint_rbf_anena - 8);
n.itoena := r.dih(c_rlink_iint_rbf_itoena - 8);
n.itoval := r.dil(ITOWIDTH-1 downto 0);
-- note: itocnt will load in next
-- cycle because ito_go=0, so no
-- action required here
end if;
else -- is external init
n.rbwe := '1'; -- send init with we
end if;
n.state := s_txstat;
when others => -- '111' ---------------
n.state := s_txnak; -- send NAK on reserved command
end case;
end if;
when s_txcnt => -- s_txcnt: send cnt -----------------
ido := '0' & r.cnt; -- send cnt
ival := '1';
if RL_HOLD = '0' then -- wait for accept
ocrcena := '1'; -- update output crc
n.rbaval := '1'; -- prepare rbus cycle
n.state := s_rstart; -- next: start first read reg
end if;
when s_rstart => -- s_rstart: start reg or blk read ---
n.rbaval := '1'; -- start actual read cycle
n.rbre := '1';
n.state := s_rreg; -- next: reg read
when s_rreg => -- s_rreg: do reg or blk read --------
-- this state handles all rbus reads
ato_go := '1'; -- activate timeout counter
if RB_SRES.err = '1' then -- latch rbus error flag
n.rberr := '1';
end if;
n.doh := RB_SRES.dout(15 downto 8); -- latch data
n.dol := RB_SRES.dout( 7 downto 0);
n.stat := RB_STAT; -- latch external status bits
if RB_SRES.busy='0' or ato_end='1' then -- wait for non-busy or timeout
if RB_SRES.busy='1' and ato_end='1' then -- if timeout and still busy
n.rbnak := '1'; -- set rbus nak flag
elsif RB_SRES.ack = '0' then -- if non-busy and no ack
n.rbnak := '1'; -- set rbus nak flag
end if;
n.state := s_txdatl; -- next: send data lsb
else -- otherwise rbus read continues
n.rbaval := '1'; -- extend cycle
n.rbre := '1';
end if;
when s_txdatl => -- s_txdatl: send data low -----------
ido := '0' & r.dol; -- send data
ival := '1';
if RL_HOLD = '0' then -- wait for accept
ocrcena := '1'; -- update output crc
n.state := s_txdath; -- next: send data msb
end if;
when s_txdath => -- s_txdath: send data high
ido := '0' & r.doh; -- send data
ival := '1';
if RL_HOLD = '0' then -- wait for accept
ocrcena := '1'; -- update output crc
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_rblk then -- if rblk
n.state := s_blk; -- next: block count handling
else -- otherwise
n.state := s_txstat; -- next: send stat
end if;
end if;
when s_wstart => -- s_wstart: start reg or blk write --
n.rbaval := '1'; -- start actual write cycle
n.rbwe := '1';
n.state := s_wreg; -- next: reg write
when s_wreg => -- s_wreg: do reg or blk write -------
-- this state handles all rbus writes
ato_go := '1'; -- activate timeout counter
if RB_SRES.err = '1' then -- latch rbus error flag
n.rberr := '1';
end if;
n.stat := RB_STAT; -- latch external status bits
if RB_SRES.busy='0' or ato_end='1' then -- wait for non-busy or timeout
if RB_SRES.busy='1' and ato_end='1' then -- if timeout and still busy
n.rbnak := '1'; -- set rbus nak flag
elsif RB_SRES.ack='0' then -- if non-busy and no ack
n.rbnak := '1'; -- set rbus nak flag
end if;
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_wblk then -- if wblk
n.state := s_blk; -- next: block count handling
else -- otherwise
n.state := s_txstat; -- next: send stat
end if;
else -- otherwise rbus write continues
n.rbaval := '1'; -- extend cycle
n.rbwe := '1';
end if;
when s_blk => -- s_blk: block count handling -------
n.cnt := slv(unsigned(r.cnt) - 1);-- decrement transfer count
if unsigned(r.cnt) = 0 then -- if last transfer
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_rblk then -- if rblk
n.state := s_txstat; -- next: send stat
else -- otherwise
n.state := s_rxdcrc; -- next: read data crc
end if;
else -- otherwise more to transfer
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_rblk then -- if rblk
n.rbaval := '1'; -- prepare rbus cycle
n.state := s_rstart; -- next: start read blk
else -- otherwise
n.state := s_rxdatl; -- next: read data
end if;
end if;
when s_rxdcrc => -- s_rxdcrc: wait for data crc -------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
do_comma_abort(n.state, n.nakeop, comma_typ);
else
if idi8 /= ICRC_OUT then -- if crc error
n.derr := '1'; -- set data error flag
end if;
n.state := s_txstat; -- next: echo command
end if;
end if;
when s_attn => -- s_attn: handle attention flags ----
n.dol := r.attn(7 downto 0); -- move attention flags to do buffer
n.doh := r.attn(15 downto 8);
n.attn := RB_LAM; -- LAM in current cycle send next time
n.andone := '0'; -- reenable attn nofification
n.state := s_txdatl; -- next: send data lsb
when s_txccmd => -- s_txccmd: send last command
ido := '0' & r.ccmd; -- send last accepted command
ival := '1';
if RL_HOLD = '0' then -- wait for accept
ocrcena := '1'; -- update output crc
n.state := s_txdatl; -- next: send last data lsb
end if;
when s_txstat => -- s_txstat: send status -------------
ido := (others=>'0');
ido(c_rlink_stat_rbf_stat) := r.stat;
ido(c_rlink_stat_rbf_attn) := has_attn;
ido(c_rlink_stat_rbf_cerr) := r.cerr;
ido(c_rlink_stat_rbf_derr) := r.derr;
ido(c_rlink_stat_rbf_rbnak) := r.rbnak;
ido(c_rlink_stat_rbf_rberr) := r.rberr;
ival := '1';
if RL_HOLD ='0' then -- wait for accept
ocrcena := '1'; -- update output crc
n.state := s_txcrc; -- next: send crc
end if;
when s_txcrc => -- s_txcrc: send crc -----------------
ido := "0" & OCRC_OUT; -- send crc code
ival := '1';
if RL_HOLD = '0' then -- wait for accept
-- if dcrc seen in wblk
if r.rcmd(c_rlink_cmd_rbf_code)=c_rlink_cmd_wblk and r.derr='1' then
n.state := s_txnak; -- next: send nak
else -- otherwise
n.nakcerr := '0'; -- clear 'set on nak' requests
n.nakderr := '0';
n.state := s_rxcmd; -- next: read command or eop
end if;
end if;
when others => null; -- <> --------------------------------
end case;
if ato_go = '0' then -- handle access timeout counter
n.atocnt := atocnt_init; -- if ato_go=0, keep in reset
else
n.atocnt := slv(unsigned(r.atocnt) - 1);-- otherwise count down
end if;
if ito_go = '0' then -- handle idle timeout counter
n.itocnt := r.itoval; -- if ito_go=0, keep at start value
else
if CE_INT = '1' then
n.itocnt := slv(unsigned(r.itocnt) - 1);-- otherwise cnt dn every CE_INT
end if;
end if;
N_REGS <= n;
RL_BUSY <= ibusy;
RL_DO <= ido;
RL_VAL <= ival;
RL_MONI.eop <= r.moneop;
RL_MONI.attn <= r.monattn;
RL_MONI.lamp <= r.monlamp;
RB_MREQ <= rb_mreq_init;
RB_MREQ.aval <= r.rbaval;
RB_MREQ.re <= r.rbre;
RB_MREQ.we <= r.rbwe;
RB_MREQ.init <= r.rbinit;
RB_MREQ.addr <= r.addr;
RB_MREQ.din <= r.dih & r.dil;
CRC_RESET <= crcreset;
ICRC_ENA <= icrcena;
OCRC_ENA <= ocrcena;
OCRC_IN <= ido(7 downto 0);
end process proc_next;
end syn;
|
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
|
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
|
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
|
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
|
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
|
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
|
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
|
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
|
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
|
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
|
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FPC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** ADSPB instantiated functions. Provides ***
--*** interface between ADSPB tool's types ***
--*** and hcc library elements ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE fpc_library_package_cmd IS
constant m_fpOutputScale : integer := 0; -- -ni: Fully pre-normalize single precision multipliers
constant m_fpRoundConvert : integer := 0; -- -rc: all conversions between signed and unsigned numbers
constant m_fpDoubleSpeed : integer := 1; -- -ds: Pipeline longer additions
constant m_fpOutputPipe : integer := 1; -- -op: Optimize away registers on simple internal output nodes
constant m_fpNormalisationSpeed : integer := 3; -- -ns: Normalization block performance (1,2 or 3)
constant m_SingleMantissaWidth : integer := 32; -- -mm: 0=>32-bit, 1=>36-bit
constant m_fpShiftSpeed : integer := 1; -- -ps: Remove pipelines out of large alignments
function deviceFamilyA5( f : string ) return integer;
function deviceFamily( f : string ) return integer;
function deviceFamilyS3( f : string ) return integer;
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
--***************************************************
--*** Single Precision ***
--***************************************************
COMPONENT fp_mult_sNorm_2_sInternal
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sNorm
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sIEEE
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM_v31
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (45 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternal_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal_v31
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
--***************************************************
--*** Double Precision ***
--***************************************************
COMPONENT fp_mult_dNorm_2_dInternal
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_dNorm_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_dInternal_2_dInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sNorm
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sInternal
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_sIEEE_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_dIEEE_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
END fpc_library_package_cmd;
PACKAGE BODY fpc_library_package_cmd is
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8;
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(31) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (UNSIGNED(arg(22 DOWNTO 0)))) / (2.0 ** 23);
expon := to_integer (UNSIGNED(arg (30 downto 23)));
exp := expon - expon_base;
if exp > expon_base then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac);
end if;
return sign;
end sIEEE_2_real;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sNorm_2_real;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternal_2_real;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (UNSIGNED(arg(42 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternalSM_2_real;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11;
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(63) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (SIGNED('0' & arg(51 DOWNTO 21)))) / (2.0 ** 31); -- ignore low bits to fit within VHDL types
fraclo := REAL(to_integer (SIGNED('0' & arg(20 DOWNTO 0)))) / (2.0 ** 52);
expon := to_integer (SIGNED('0' & arg (62 downto 52)));
exp := expon - expon_base;
-- Fatal error (vsim-3421) if outside range -1e+308 +1e+308 which can still happen if exp = 1023
if exp >= 1023 then
sign := sign * 9.999e+307;
elsif expon = 0 then
sign := 0.0;
-- ignore denormalized mantissa
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end dIEEE_2_real;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(66 DOWNTO 35)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
if exp >= 1024 then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dNorm_2_real;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
variable sign_bit : STD_LOGIC;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(76 DOWNTO 45)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
sign_bit := arg(76);
if exp >= 1024 then
-- perhaps
-- or (arg(74) /= sign_bit and exp >= 1023) or (arg(74) /= sign_bit and arg(75) /= sign_bit and exp >= 1022) then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dInternal_2_real;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable exponBase : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
exponBase := 2**(expWidth-1) -1;
if arg(arg'high) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
if fracWidth > 31 then
frac := REAL(to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))))) / (2.0 ** 31);
fraclo := REAL(to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)))) / (2.0 ** fracWidth);
else
frac := REAL(to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)))) / (2.0 ** fracWidth);
fraclo := 0.0;
end if;
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
exp := expon - exponBase;
if exp > exponBase or exp >= 1023 then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end vIEEE_2_real;
function sIEEEisNan (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(30 downto 23) = "11111111" and a(22 downto 0) /= "00000000000000000000000";
end sIEEEisNan;
function sIEEEisInf (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(30 downto 0) = "1111111100000000000000000000000" then
--if a(30 downto 23) = "11111111" then
return TRUE;
else
return FALSE;
end if;
end sIEEEisInf;
function sIEEEisNegative (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(31) = '1';
end sIEEEisNegative;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if sIEEEisNan(a) and sIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if sIEEEisInf(a) and sIEEEisInf(b) then
return sIEEEisNegative(a) = sIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if sIEEEisInf(a) or sIEEEisInf(b) then
return FALSE;
end if;
a_real := sIEEE_2_real(a);
b_real := sIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end sIEEEisEqual;
function dIEEEisNan (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(62 downto 52) = "11111111111" and a(51 downto 0) /= "0000000000000000000000000000000000000000000000000000";
end dIEEEisNan;
function dIEEEisInf (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(62 downto 0) = "111111111110000000000000000000000000000000000000000000000000000" then
--if a(62 downto 52) = "11111111111" then
return TRUE;
else
return FALSE;
end if;
end dIEEEisInf;
function dIEEEisNegative (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(63) = '1';
end dIEEEisNegative;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if dIEEEisNan(a) and dIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if dIEEEisInf(a) and dIEEEisInf(b) then
return dIEEEisNegative(a) = dIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if dIEEEisInf(a) or dIEEEisInf(b) then
return FALSE;
end if;
a_real := dIEEE_2_real(a);
b_real := dIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end dIEEEisEqual;
function vIEEEisNan (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return TRUE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac /= 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac /= 0);
end vIEEEisNan;
function vIEEEisInf (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
-- ignore sign bit since this returns true for -inf and +inf
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return FALSE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac = 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac = 0);
end vIEEEisInf;
function vIEEEisNegative (arg : STD_LOGIC_VECTOR; we, wf : INTEGER) return BOOLEAN is
begin
return arg(arg'high) = '1';
end vIEEEisNegative;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
a_real := vIEEE_2_real(a, expWidth, fracWidth);
b_real := vIEEE_2_real(b, expWidth, fracWidth);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end vIEEEisEqual;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
if (vIEEEisSubnormal(a, expWidth, fracWidth) or vIEEEisZero(a, expWidth, fracWidth)) and
(vIEEEisSubnormal(b, expWidth, fracWidth) or vIEEEisZero(b, expWidth, fracWidth)) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
if (a = b) then
return TRUE;
end if;
return FALSE;
end vIEEEisExactEqual;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA /= 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisSubnormal;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA = 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisZero;
FUNCTION deviceFamilyA5 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" THEN
RETURN 2;
ELSIF f = "Arria V" THEN
RETURN 3;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamilyA5;
FUNCTION deviceFamily ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" or f = "Arria V" THEN
RETURN 2;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamily;
FUNCTION deviceFamilyS3 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
-- "Stratix V" also though many FPC components have not yet been optimized for this family
END FUNCTION deviceFamilyS3;
END fpc_library_package_cmd;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FPC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** ADSPB instantiated functions. Provides ***
--*** interface between ADSPB tool's types ***
--*** and hcc library elements ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE fpc_library_package_cmd IS
constant m_fpOutputScale : integer := 0; -- -ni: Fully pre-normalize single precision multipliers
constant m_fpRoundConvert : integer := 0; -- -rc: all conversions between signed and unsigned numbers
constant m_fpDoubleSpeed : integer := 1; -- -ds: Pipeline longer additions
constant m_fpOutputPipe : integer := 1; -- -op: Optimize away registers on simple internal output nodes
constant m_fpNormalisationSpeed : integer := 3; -- -ns: Normalization block performance (1,2 or 3)
constant m_SingleMantissaWidth : integer := 32; -- -mm: 0=>32-bit, 1=>36-bit
constant m_fpShiftSpeed : integer := 1; -- -ps: Remove pipelines out of large alignments
function deviceFamilyA5( f : string ) return integer;
function deviceFamily( f : string ) return integer;
function deviceFamilyS3( f : string ) return integer;
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
--***************************************************
--*** Single Precision ***
--***************************************************
COMPONENT fp_mult_sNorm_2_sInternal
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sNorm
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sIEEE
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM_v31
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (45 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternal_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal_v31
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
--***************************************************
--*** Double Precision ***
--***************************************************
COMPONENT fp_mult_dNorm_2_dInternal
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_dNorm_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_dInternal_2_dInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sNorm
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sInternal
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_sIEEE_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_dIEEE_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
END fpc_library_package_cmd;
PACKAGE BODY fpc_library_package_cmd is
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8;
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(31) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (UNSIGNED(arg(22 DOWNTO 0)))) / (2.0 ** 23);
expon := to_integer (UNSIGNED(arg (30 downto 23)));
exp := expon - expon_base;
if exp > expon_base then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac);
end if;
return sign;
end sIEEE_2_real;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sNorm_2_real;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternal_2_real;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (UNSIGNED(arg(42 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternalSM_2_real;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11;
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(63) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (SIGNED('0' & arg(51 DOWNTO 21)))) / (2.0 ** 31); -- ignore low bits to fit within VHDL types
fraclo := REAL(to_integer (SIGNED('0' & arg(20 DOWNTO 0)))) / (2.0 ** 52);
expon := to_integer (SIGNED('0' & arg (62 downto 52)));
exp := expon - expon_base;
-- Fatal error (vsim-3421) if outside range -1e+308 +1e+308 which can still happen if exp = 1023
if exp >= 1023 then
sign := sign * 9.999e+307;
elsif expon = 0 then
sign := 0.0;
-- ignore denormalized mantissa
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end dIEEE_2_real;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(66 DOWNTO 35)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
if exp >= 1024 then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dNorm_2_real;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
variable sign_bit : STD_LOGIC;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(76 DOWNTO 45)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
sign_bit := arg(76);
if exp >= 1024 then
-- perhaps
-- or (arg(74) /= sign_bit and exp >= 1023) or (arg(74) /= sign_bit and arg(75) /= sign_bit and exp >= 1022) then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dInternal_2_real;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable exponBase : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
exponBase := 2**(expWidth-1) -1;
if arg(arg'high) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
if fracWidth > 31 then
frac := REAL(to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))))) / (2.0 ** 31);
fraclo := REAL(to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)))) / (2.0 ** fracWidth);
else
frac := REAL(to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)))) / (2.0 ** fracWidth);
fraclo := 0.0;
end if;
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
exp := expon - exponBase;
if exp > exponBase or exp >= 1023 then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end vIEEE_2_real;
function sIEEEisNan (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(30 downto 23) = "11111111" and a(22 downto 0) /= "00000000000000000000000";
end sIEEEisNan;
function sIEEEisInf (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(30 downto 0) = "1111111100000000000000000000000" then
--if a(30 downto 23) = "11111111" then
return TRUE;
else
return FALSE;
end if;
end sIEEEisInf;
function sIEEEisNegative (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(31) = '1';
end sIEEEisNegative;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if sIEEEisNan(a) and sIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if sIEEEisInf(a) and sIEEEisInf(b) then
return sIEEEisNegative(a) = sIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if sIEEEisInf(a) or sIEEEisInf(b) then
return FALSE;
end if;
a_real := sIEEE_2_real(a);
b_real := sIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end sIEEEisEqual;
function dIEEEisNan (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(62 downto 52) = "11111111111" and a(51 downto 0) /= "0000000000000000000000000000000000000000000000000000";
end dIEEEisNan;
function dIEEEisInf (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(62 downto 0) = "111111111110000000000000000000000000000000000000000000000000000" then
--if a(62 downto 52) = "11111111111" then
return TRUE;
else
return FALSE;
end if;
end dIEEEisInf;
function dIEEEisNegative (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(63) = '1';
end dIEEEisNegative;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if dIEEEisNan(a) and dIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if dIEEEisInf(a) and dIEEEisInf(b) then
return dIEEEisNegative(a) = dIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if dIEEEisInf(a) or dIEEEisInf(b) then
return FALSE;
end if;
a_real := dIEEE_2_real(a);
b_real := dIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end dIEEEisEqual;
function vIEEEisNan (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return TRUE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac /= 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac /= 0);
end vIEEEisNan;
function vIEEEisInf (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
-- ignore sign bit since this returns true for -inf and +inf
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return FALSE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac = 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac = 0);
end vIEEEisInf;
function vIEEEisNegative (arg : STD_LOGIC_VECTOR; we, wf : INTEGER) return BOOLEAN is
begin
return arg(arg'high) = '1';
end vIEEEisNegative;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
a_real := vIEEE_2_real(a, expWidth, fracWidth);
b_real := vIEEE_2_real(b, expWidth, fracWidth);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end vIEEEisEqual;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
if (vIEEEisSubnormal(a, expWidth, fracWidth) or vIEEEisZero(a, expWidth, fracWidth)) and
(vIEEEisSubnormal(b, expWidth, fracWidth) or vIEEEisZero(b, expWidth, fracWidth)) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
if (a = b) then
return TRUE;
end if;
return FALSE;
end vIEEEisExactEqual;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA /= 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisSubnormal;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA = 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisZero;
FUNCTION deviceFamilyA5 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" THEN
RETURN 2;
ELSIF f = "Arria V" THEN
RETURN 3;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamilyA5;
FUNCTION deviceFamily ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" or f = "Arria V" THEN
RETURN 2;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamily;
FUNCTION deviceFamilyS3 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
-- "Stratix V" also though many FPC components have not yet been optimized for this family
END FUNCTION deviceFamilyS3;
END fpc_library_package_cmd;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FPC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** ADSPB instantiated functions. Provides ***
--*** interface between ADSPB tool's types ***
--*** and hcc library elements ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE fpc_library_package_cmd IS
constant m_fpOutputScale : integer := 0; -- -ni: Fully pre-normalize single precision multipliers
constant m_fpRoundConvert : integer := 0; -- -rc: all conversions between signed and unsigned numbers
constant m_fpDoubleSpeed : integer := 1; -- -ds: Pipeline longer additions
constant m_fpOutputPipe : integer := 1; -- -op: Optimize away registers on simple internal output nodes
constant m_fpNormalisationSpeed : integer := 3; -- -ns: Normalization block performance (1,2 or 3)
constant m_SingleMantissaWidth : integer := 32; -- -mm: 0=>32-bit, 1=>36-bit
constant m_fpShiftSpeed : integer := 1; -- -ps: Remove pipelines out of large alignments
function deviceFamilyA5( f : string ) return integer;
function deviceFamily( f : string ) return integer;
function deviceFamilyS3( f : string ) return integer;
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
--***************************************************
--*** Single Precision ***
--***************************************************
COMPONENT fp_mult_sNorm_2_sInternal
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sNorm
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sIEEE
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM_v31
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (45 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternal_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal_v31
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
--***************************************************
--*** Double Precision ***
--***************************************************
COMPONENT fp_mult_dNorm_2_dInternal
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_dNorm_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_dInternal_2_dInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sNorm
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sInternal
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_sIEEE_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_dIEEE_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
END fpc_library_package_cmd;
PACKAGE BODY fpc_library_package_cmd is
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8;
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(31) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (UNSIGNED(arg(22 DOWNTO 0)))) / (2.0 ** 23);
expon := to_integer (UNSIGNED(arg (30 downto 23)));
exp := expon - expon_base;
if exp > expon_base then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac);
end if;
return sign;
end sIEEE_2_real;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sNorm_2_real;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternal_2_real;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (UNSIGNED(arg(42 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternalSM_2_real;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11;
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(63) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (SIGNED('0' & arg(51 DOWNTO 21)))) / (2.0 ** 31); -- ignore low bits to fit within VHDL types
fraclo := REAL(to_integer (SIGNED('0' & arg(20 DOWNTO 0)))) / (2.0 ** 52);
expon := to_integer (SIGNED('0' & arg (62 downto 52)));
exp := expon - expon_base;
-- Fatal error (vsim-3421) if outside range -1e+308 +1e+308 which can still happen if exp = 1023
if exp >= 1023 then
sign := sign * 9.999e+307;
elsif expon = 0 then
sign := 0.0;
-- ignore denormalized mantissa
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end dIEEE_2_real;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(66 DOWNTO 35)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
if exp >= 1024 then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dNorm_2_real;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
variable sign_bit : STD_LOGIC;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(76 DOWNTO 45)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
sign_bit := arg(76);
if exp >= 1024 then
-- perhaps
-- or (arg(74) /= sign_bit and exp >= 1023) or (arg(74) /= sign_bit and arg(75) /= sign_bit and exp >= 1022) then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dInternal_2_real;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable exponBase : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
exponBase := 2**(expWidth-1) -1;
if arg(arg'high) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
if fracWidth > 31 then
frac := REAL(to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))))) / (2.0 ** 31);
fraclo := REAL(to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)))) / (2.0 ** fracWidth);
else
frac := REAL(to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)))) / (2.0 ** fracWidth);
fraclo := 0.0;
end if;
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
exp := expon - exponBase;
if exp > exponBase or exp >= 1023 then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end vIEEE_2_real;
function sIEEEisNan (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(30 downto 23) = "11111111" and a(22 downto 0) /= "00000000000000000000000";
end sIEEEisNan;
function sIEEEisInf (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(30 downto 0) = "1111111100000000000000000000000" then
--if a(30 downto 23) = "11111111" then
return TRUE;
else
return FALSE;
end if;
end sIEEEisInf;
function sIEEEisNegative (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(31) = '1';
end sIEEEisNegative;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if sIEEEisNan(a) and sIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if sIEEEisInf(a) and sIEEEisInf(b) then
return sIEEEisNegative(a) = sIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if sIEEEisInf(a) or sIEEEisInf(b) then
return FALSE;
end if;
a_real := sIEEE_2_real(a);
b_real := sIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end sIEEEisEqual;
function dIEEEisNan (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(62 downto 52) = "11111111111" and a(51 downto 0) /= "0000000000000000000000000000000000000000000000000000";
end dIEEEisNan;
function dIEEEisInf (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(62 downto 0) = "111111111110000000000000000000000000000000000000000000000000000" then
--if a(62 downto 52) = "11111111111" then
return TRUE;
else
return FALSE;
end if;
end dIEEEisInf;
function dIEEEisNegative (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(63) = '1';
end dIEEEisNegative;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if dIEEEisNan(a) and dIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if dIEEEisInf(a) and dIEEEisInf(b) then
return dIEEEisNegative(a) = dIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if dIEEEisInf(a) or dIEEEisInf(b) then
return FALSE;
end if;
a_real := dIEEE_2_real(a);
b_real := dIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end dIEEEisEqual;
function vIEEEisNan (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return TRUE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac /= 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac /= 0);
end vIEEEisNan;
function vIEEEisInf (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
-- ignore sign bit since this returns true for -inf and +inf
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return FALSE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac = 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac = 0);
end vIEEEisInf;
function vIEEEisNegative (arg : STD_LOGIC_VECTOR; we, wf : INTEGER) return BOOLEAN is
begin
return arg(arg'high) = '1';
end vIEEEisNegative;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
a_real := vIEEE_2_real(a, expWidth, fracWidth);
b_real := vIEEE_2_real(b, expWidth, fracWidth);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end vIEEEisEqual;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
if (vIEEEisSubnormal(a, expWidth, fracWidth) or vIEEEisZero(a, expWidth, fracWidth)) and
(vIEEEisSubnormal(b, expWidth, fracWidth) or vIEEEisZero(b, expWidth, fracWidth)) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
if (a = b) then
return TRUE;
end if;
return FALSE;
end vIEEEisExactEqual;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA /= 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisSubnormal;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA = 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisZero;
FUNCTION deviceFamilyA5 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" THEN
RETURN 2;
ELSIF f = "Arria V" THEN
RETURN 3;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamilyA5;
FUNCTION deviceFamily ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" or f = "Arria V" THEN
RETURN 2;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamily;
FUNCTION deviceFamilyS3 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
-- "Stratix V" also though many FPC components have not yet been optimized for this family
END FUNCTION deviceFamilyS3;
END fpc_library_package_cmd;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FPC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** ADSPB instantiated functions. Provides ***
--*** interface between ADSPB tool's types ***
--*** and hcc library elements ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE fpc_library_package_cmd IS
constant m_fpOutputScale : integer := 0; -- -ni: Fully pre-normalize single precision multipliers
constant m_fpRoundConvert : integer := 0; -- -rc: all conversions between signed and unsigned numbers
constant m_fpDoubleSpeed : integer := 1; -- -ds: Pipeline longer additions
constant m_fpOutputPipe : integer := 1; -- -op: Optimize away registers on simple internal output nodes
constant m_fpNormalisationSpeed : integer := 3; -- -ns: Normalization block performance (1,2 or 3)
constant m_SingleMantissaWidth : integer := 32; -- -mm: 0=>32-bit, 1=>36-bit
constant m_fpShiftSpeed : integer := 1; -- -ps: Remove pipelines out of large alignments
function deviceFamilyA5( f : string ) return integer;
function deviceFamily( f : string ) return integer;
function deviceFamilyS3( f : string ) return integer;
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
--***************************************************
--*** Single Precision ***
--***************************************************
COMPONENT fp_mult_sNorm_2_sInternal
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sNorm
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sIEEE
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM_v31
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (45 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternal_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal_v31
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
--***************************************************
--*** Double Precision ***
--***************************************************
COMPONENT fp_mult_dNorm_2_dInternal
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_dNorm_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_dInternal_2_dInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sNorm
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sInternal
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_sIEEE_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_dIEEE_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
END fpc_library_package_cmd;
PACKAGE BODY fpc_library_package_cmd is
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8;
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(31) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (UNSIGNED(arg(22 DOWNTO 0)))) / (2.0 ** 23);
expon := to_integer (UNSIGNED(arg (30 downto 23)));
exp := expon - expon_base;
if exp > expon_base then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac);
end if;
return sign;
end sIEEE_2_real;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sNorm_2_real;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternal_2_real;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (UNSIGNED(arg(42 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternalSM_2_real;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11;
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(63) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (SIGNED('0' & arg(51 DOWNTO 21)))) / (2.0 ** 31); -- ignore low bits to fit within VHDL types
fraclo := REAL(to_integer (SIGNED('0' & arg(20 DOWNTO 0)))) / (2.0 ** 52);
expon := to_integer (SIGNED('0' & arg (62 downto 52)));
exp := expon - expon_base;
-- Fatal error (vsim-3421) if outside range -1e+308 +1e+308 which can still happen if exp = 1023
if exp >= 1023 then
sign := sign * 9.999e+307;
elsif expon = 0 then
sign := 0.0;
-- ignore denormalized mantissa
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end dIEEE_2_real;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(66 DOWNTO 35)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
if exp >= 1024 then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dNorm_2_real;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
variable sign_bit : STD_LOGIC;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(76 DOWNTO 45)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
sign_bit := arg(76);
if exp >= 1024 then
-- perhaps
-- or (arg(74) /= sign_bit and exp >= 1023) or (arg(74) /= sign_bit and arg(75) /= sign_bit and exp >= 1022) then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dInternal_2_real;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable exponBase : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
exponBase := 2**(expWidth-1) -1;
if arg(arg'high) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
if fracWidth > 31 then
frac := REAL(to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))))) / (2.0 ** 31);
fraclo := REAL(to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)))) / (2.0 ** fracWidth);
else
frac := REAL(to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)))) / (2.0 ** fracWidth);
fraclo := 0.0;
end if;
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
exp := expon - exponBase;
if exp > exponBase or exp >= 1023 then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end vIEEE_2_real;
function sIEEEisNan (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(30 downto 23) = "11111111" and a(22 downto 0) /= "00000000000000000000000";
end sIEEEisNan;
function sIEEEisInf (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(30 downto 0) = "1111111100000000000000000000000" then
--if a(30 downto 23) = "11111111" then
return TRUE;
else
return FALSE;
end if;
end sIEEEisInf;
function sIEEEisNegative (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(31) = '1';
end sIEEEisNegative;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if sIEEEisNan(a) and sIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if sIEEEisInf(a) and sIEEEisInf(b) then
return sIEEEisNegative(a) = sIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if sIEEEisInf(a) or sIEEEisInf(b) then
return FALSE;
end if;
a_real := sIEEE_2_real(a);
b_real := sIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end sIEEEisEqual;
function dIEEEisNan (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(62 downto 52) = "11111111111" and a(51 downto 0) /= "0000000000000000000000000000000000000000000000000000";
end dIEEEisNan;
function dIEEEisInf (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(62 downto 0) = "111111111110000000000000000000000000000000000000000000000000000" then
--if a(62 downto 52) = "11111111111" then
return TRUE;
else
return FALSE;
end if;
end dIEEEisInf;
function dIEEEisNegative (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(63) = '1';
end dIEEEisNegative;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if dIEEEisNan(a) and dIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if dIEEEisInf(a) and dIEEEisInf(b) then
return dIEEEisNegative(a) = dIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if dIEEEisInf(a) or dIEEEisInf(b) then
return FALSE;
end if;
a_real := dIEEE_2_real(a);
b_real := dIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end dIEEEisEqual;
function vIEEEisNan (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return TRUE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac /= 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac /= 0);
end vIEEEisNan;
function vIEEEisInf (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
-- ignore sign bit since this returns true for -inf and +inf
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return FALSE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac = 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac = 0);
end vIEEEisInf;
function vIEEEisNegative (arg : STD_LOGIC_VECTOR; we, wf : INTEGER) return BOOLEAN is
begin
return arg(arg'high) = '1';
end vIEEEisNegative;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
a_real := vIEEE_2_real(a, expWidth, fracWidth);
b_real := vIEEE_2_real(b, expWidth, fracWidth);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end vIEEEisEqual;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
if (vIEEEisSubnormal(a, expWidth, fracWidth) or vIEEEisZero(a, expWidth, fracWidth)) and
(vIEEEisSubnormal(b, expWidth, fracWidth) or vIEEEisZero(b, expWidth, fracWidth)) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
if (a = b) then
return TRUE;
end if;
return FALSE;
end vIEEEisExactEqual;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA /= 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisSubnormal;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA = 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisZero;
FUNCTION deviceFamilyA5 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" THEN
RETURN 2;
ELSIF f = "Arria V" THEN
RETURN 3;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamilyA5;
FUNCTION deviceFamily ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" or f = "Arria V" THEN
RETURN 2;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamily;
FUNCTION deviceFamilyS3 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
-- "Stratix V" also though many FPC components have not yet been optimized for this family
END FUNCTION deviceFamilyS3;
END fpc_library_package_cmd;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FPC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** ADSPB instantiated functions. Provides ***
--*** interface between ADSPB tool's types ***
--*** and hcc library elements ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE fpc_library_package_cmd IS
constant m_fpOutputScale : integer := 0; -- -ni: Fully pre-normalize single precision multipliers
constant m_fpRoundConvert : integer := 0; -- -rc: all conversions between signed and unsigned numbers
constant m_fpDoubleSpeed : integer := 1; -- -ds: Pipeline longer additions
constant m_fpOutputPipe : integer := 1; -- -op: Optimize away registers on simple internal output nodes
constant m_fpNormalisationSpeed : integer := 3; -- -ns: Normalization block performance (1,2 or 3)
constant m_SingleMantissaWidth : integer := 32; -- -mm: 0=>32-bit, 1=>36-bit
constant m_fpShiftSpeed : integer := 1; -- -ps: Remove pipelines out of large alignments
function deviceFamilyA5( f : string ) return integer;
function deviceFamily( f : string ) return integer;
function deviceFamilyS3( f : string ) return integer;
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
--***************************************************
--*** Single Precision ***
--***************************************************
COMPONENT fp_mult_sNorm_2_sInternal
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sNorm
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sIEEE
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM_v31
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (45 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternal_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal_v31
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
--***************************************************
--*** Double Precision ***
--***************************************************
COMPONENT fp_mult_dNorm_2_dInternal
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_dNorm_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_dInternal_2_dInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sNorm
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sInternal
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_sIEEE_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_dIEEE_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
END fpc_library_package_cmd;
PACKAGE BODY fpc_library_package_cmd is
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8;
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(31) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (UNSIGNED(arg(22 DOWNTO 0)))) / (2.0 ** 23);
expon := to_integer (UNSIGNED(arg (30 downto 23)));
exp := expon - expon_base;
if exp > expon_base then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac);
end if;
return sign;
end sIEEE_2_real;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sNorm_2_real;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternal_2_real;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (UNSIGNED(arg(42 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternalSM_2_real;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11;
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(63) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (SIGNED('0' & arg(51 DOWNTO 21)))) / (2.0 ** 31); -- ignore low bits to fit within VHDL types
fraclo := REAL(to_integer (SIGNED('0' & arg(20 DOWNTO 0)))) / (2.0 ** 52);
expon := to_integer (SIGNED('0' & arg (62 downto 52)));
exp := expon - expon_base;
-- Fatal error (vsim-3421) if outside range -1e+308 +1e+308 which can still happen if exp = 1023
if exp >= 1023 then
sign := sign * 9.999e+307;
elsif expon = 0 then
sign := 0.0;
-- ignore denormalized mantissa
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end dIEEE_2_real;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(66 DOWNTO 35)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
if exp >= 1024 then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dNorm_2_real;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
variable sign_bit : STD_LOGIC;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(76 DOWNTO 45)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
sign_bit := arg(76);
if exp >= 1024 then
-- perhaps
-- or (arg(74) /= sign_bit and exp >= 1023) or (arg(74) /= sign_bit and arg(75) /= sign_bit and exp >= 1022) then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dInternal_2_real;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable exponBase : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
exponBase := 2**(expWidth-1) -1;
if arg(arg'high) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
if fracWidth > 31 then
frac := REAL(to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))))) / (2.0 ** 31);
fraclo := REAL(to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)))) / (2.0 ** fracWidth);
else
frac := REAL(to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)))) / (2.0 ** fracWidth);
fraclo := 0.0;
end if;
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
exp := expon - exponBase;
if exp > exponBase or exp >= 1023 then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end vIEEE_2_real;
function sIEEEisNan (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(30 downto 23) = "11111111" and a(22 downto 0) /= "00000000000000000000000";
end sIEEEisNan;
function sIEEEisInf (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(30 downto 0) = "1111111100000000000000000000000" then
--if a(30 downto 23) = "11111111" then
return TRUE;
else
return FALSE;
end if;
end sIEEEisInf;
function sIEEEisNegative (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(31) = '1';
end sIEEEisNegative;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if sIEEEisNan(a) and sIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if sIEEEisInf(a) and sIEEEisInf(b) then
return sIEEEisNegative(a) = sIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if sIEEEisInf(a) or sIEEEisInf(b) then
return FALSE;
end if;
a_real := sIEEE_2_real(a);
b_real := sIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end sIEEEisEqual;
function dIEEEisNan (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(62 downto 52) = "11111111111" and a(51 downto 0) /= "0000000000000000000000000000000000000000000000000000";
end dIEEEisNan;
function dIEEEisInf (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(62 downto 0) = "111111111110000000000000000000000000000000000000000000000000000" then
--if a(62 downto 52) = "11111111111" then
return TRUE;
else
return FALSE;
end if;
end dIEEEisInf;
function dIEEEisNegative (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(63) = '1';
end dIEEEisNegative;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if dIEEEisNan(a) and dIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if dIEEEisInf(a) and dIEEEisInf(b) then
return dIEEEisNegative(a) = dIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if dIEEEisInf(a) or dIEEEisInf(b) then
return FALSE;
end if;
a_real := dIEEE_2_real(a);
b_real := dIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end dIEEEisEqual;
function vIEEEisNan (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return TRUE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac /= 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac /= 0);
end vIEEEisNan;
function vIEEEisInf (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
-- ignore sign bit since this returns true for -inf and +inf
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return FALSE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac = 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac = 0);
end vIEEEisInf;
function vIEEEisNegative (arg : STD_LOGIC_VECTOR; we, wf : INTEGER) return BOOLEAN is
begin
return arg(arg'high) = '1';
end vIEEEisNegative;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
a_real := vIEEE_2_real(a, expWidth, fracWidth);
b_real := vIEEE_2_real(b, expWidth, fracWidth);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end vIEEEisEqual;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
if (vIEEEisSubnormal(a, expWidth, fracWidth) or vIEEEisZero(a, expWidth, fracWidth)) and
(vIEEEisSubnormal(b, expWidth, fracWidth) or vIEEEisZero(b, expWidth, fracWidth)) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
if (a = b) then
return TRUE;
end if;
return FALSE;
end vIEEEisExactEqual;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA /= 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisSubnormal;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA = 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisZero;
FUNCTION deviceFamilyA5 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" THEN
RETURN 2;
ELSIF f = "Arria V" THEN
RETURN 3;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamilyA5;
FUNCTION deviceFamily ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" or f = "Arria V" THEN
RETURN 2;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamily;
FUNCTION deviceFamilyS3 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
-- "Stratix V" also though many FPC components have not yet been optimized for this family
END FUNCTION deviceFamilyS3;
END fpc_library_package_cmd;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FPC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** ADSPB instantiated functions. Provides ***
--*** interface between ADSPB tool's types ***
--*** and hcc library elements ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE fpc_library_package_cmd IS
constant m_fpOutputScale : integer := 0; -- -ni: Fully pre-normalize single precision multipliers
constant m_fpRoundConvert : integer := 0; -- -rc: all conversions between signed and unsigned numbers
constant m_fpDoubleSpeed : integer := 1; -- -ds: Pipeline longer additions
constant m_fpOutputPipe : integer := 1; -- -op: Optimize away registers on simple internal output nodes
constant m_fpNormalisationSpeed : integer := 3; -- -ns: Normalization block performance (1,2 or 3)
constant m_SingleMantissaWidth : integer := 32; -- -mm: 0=>32-bit, 1=>36-bit
constant m_fpShiftSpeed : integer := 1; -- -ps: Remove pipelines out of large alignments
function deviceFamilyA5( f : string ) return integer;
function deviceFamily( f : string ) return integer;
function deviceFamilyS3( f : string ) return integer;
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
--***************************************************
--*** Single Precision ***
--***************************************************
COMPONENT fp_mult_sNorm_2_sInternal
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sNorm
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sIEEE
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM_v31
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (45 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternal_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal_v31
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
--***************************************************
--*** Double Precision ***
--***************************************************
COMPONENT fp_mult_dNorm_2_dInternal
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_dNorm_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_dInternal_2_dInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sNorm
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sInternal
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_sIEEE_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_dIEEE_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
END fpc_library_package_cmd;
PACKAGE BODY fpc_library_package_cmd is
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8;
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(31) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (UNSIGNED(arg(22 DOWNTO 0)))) / (2.0 ** 23);
expon := to_integer (UNSIGNED(arg (30 downto 23)));
exp := expon - expon_base;
if exp > expon_base then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac);
end if;
return sign;
end sIEEE_2_real;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sNorm_2_real;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternal_2_real;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (UNSIGNED(arg(42 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternalSM_2_real;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11;
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(63) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (SIGNED('0' & arg(51 DOWNTO 21)))) / (2.0 ** 31); -- ignore low bits to fit within VHDL types
fraclo := REAL(to_integer (SIGNED('0' & arg(20 DOWNTO 0)))) / (2.0 ** 52);
expon := to_integer (SIGNED('0' & arg (62 downto 52)));
exp := expon - expon_base;
-- Fatal error (vsim-3421) if outside range -1e+308 +1e+308 which can still happen if exp = 1023
if exp >= 1023 then
sign := sign * 9.999e+307;
elsif expon = 0 then
sign := 0.0;
-- ignore denormalized mantissa
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end dIEEE_2_real;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(66 DOWNTO 35)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
if exp >= 1024 then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dNorm_2_real;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
variable sign_bit : STD_LOGIC;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(76 DOWNTO 45)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
sign_bit := arg(76);
if exp >= 1024 then
-- perhaps
-- or (arg(74) /= sign_bit and exp >= 1023) or (arg(74) /= sign_bit and arg(75) /= sign_bit and exp >= 1022) then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dInternal_2_real;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable exponBase : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
exponBase := 2**(expWidth-1) -1;
if arg(arg'high) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
if fracWidth > 31 then
frac := REAL(to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))))) / (2.0 ** 31);
fraclo := REAL(to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)))) / (2.0 ** fracWidth);
else
frac := REAL(to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)))) / (2.0 ** fracWidth);
fraclo := 0.0;
end if;
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
exp := expon - exponBase;
if exp > exponBase or exp >= 1023 then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end vIEEE_2_real;
function sIEEEisNan (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(30 downto 23) = "11111111" and a(22 downto 0) /= "00000000000000000000000";
end sIEEEisNan;
function sIEEEisInf (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(30 downto 0) = "1111111100000000000000000000000" then
--if a(30 downto 23) = "11111111" then
return TRUE;
else
return FALSE;
end if;
end sIEEEisInf;
function sIEEEisNegative (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(31) = '1';
end sIEEEisNegative;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if sIEEEisNan(a) and sIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if sIEEEisInf(a) and sIEEEisInf(b) then
return sIEEEisNegative(a) = sIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if sIEEEisInf(a) or sIEEEisInf(b) then
return FALSE;
end if;
a_real := sIEEE_2_real(a);
b_real := sIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end sIEEEisEqual;
function dIEEEisNan (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(62 downto 52) = "11111111111" and a(51 downto 0) /= "0000000000000000000000000000000000000000000000000000";
end dIEEEisNan;
function dIEEEisInf (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(62 downto 0) = "111111111110000000000000000000000000000000000000000000000000000" then
--if a(62 downto 52) = "11111111111" then
return TRUE;
else
return FALSE;
end if;
end dIEEEisInf;
function dIEEEisNegative (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(63) = '1';
end dIEEEisNegative;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if dIEEEisNan(a) and dIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if dIEEEisInf(a) and dIEEEisInf(b) then
return dIEEEisNegative(a) = dIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if dIEEEisInf(a) or dIEEEisInf(b) then
return FALSE;
end if;
a_real := dIEEE_2_real(a);
b_real := dIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end dIEEEisEqual;
function vIEEEisNan (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return TRUE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac /= 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac /= 0);
end vIEEEisNan;
function vIEEEisInf (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
-- ignore sign bit since this returns true for -inf and +inf
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return FALSE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac = 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac = 0);
end vIEEEisInf;
function vIEEEisNegative (arg : STD_LOGIC_VECTOR; we, wf : INTEGER) return BOOLEAN is
begin
return arg(arg'high) = '1';
end vIEEEisNegative;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
a_real := vIEEE_2_real(a, expWidth, fracWidth);
b_real := vIEEE_2_real(b, expWidth, fracWidth);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end vIEEEisEqual;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
if (vIEEEisSubnormal(a, expWidth, fracWidth) or vIEEEisZero(a, expWidth, fracWidth)) and
(vIEEEisSubnormal(b, expWidth, fracWidth) or vIEEEisZero(b, expWidth, fracWidth)) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
if (a = b) then
return TRUE;
end if;
return FALSE;
end vIEEEisExactEqual;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA /= 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisSubnormal;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA = 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisZero;
FUNCTION deviceFamilyA5 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" THEN
RETURN 2;
ELSIF f = "Arria V" THEN
RETURN 3;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamilyA5;
FUNCTION deviceFamily ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" or f = "Arria V" THEN
RETURN 2;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamily;
FUNCTION deviceFamilyS3 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
-- "Stratix V" also though many FPC components have not yet been optimized for this family
END FUNCTION deviceFamilyS3;
END fpc_library_package_cmd;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FPC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** ADSPB instantiated functions. Provides ***
--*** interface between ADSPB tool's types ***
--*** and hcc library elements ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE fpc_library_package_cmd IS
constant m_fpOutputScale : integer := 0; -- -ni: Fully pre-normalize single precision multipliers
constant m_fpRoundConvert : integer := 0; -- -rc: all conversions between signed and unsigned numbers
constant m_fpDoubleSpeed : integer := 1; -- -ds: Pipeline longer additions
constant m_fpOutputPipe : integer := 1; -- -op: Optimize away registers on simple internal output nodes
constant m_fpNormalisationSpeed : integer := 3; -- -ns: Normalization block performance (1,2 or 3)
constant m_SingleMantissaWidth : integer := 32; -- -mm: 0=>32-bit, 1=>36-bit
constant m_fpShiftSpeed : integer := 1; -- -ps: Remove pipelines out of large alignments
function deviceFamilyA5( f : string ) return integer;
function deviceFamily( f : string ) return integer;
function deviceFamilyS3( f : string ) return integer;
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
--***************************************************
--*** Single Precision ***
--***************************************************
COMPONENT fp_mult_sNorm_2_sInternal
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sNorm
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sIEEE
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM_v31
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (45 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternal_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal_v31
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
--***************************************************
--*** Double Precision ***
--***************************************************
COMPONENT fp_mult_dNorm_2_dInternal
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_dNorm_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_dInternal_2_dInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sNorm
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sInternal
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_sIEEE_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_dIEEE_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
END fpc_library_package_cmd;
PACKAGE BODY fpc_library_package_cmd is
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8;
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(31) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (UNSIGNED(arg(22 DOWNTO 0)))) / (2.0 ** 23);
expon := to_integer (UNSIGNED(arg (30 downto 23)));
exp := expon - expon_base;
if exp > expon_base then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac);
end if;
return sign;
end sIEEE_2_real;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sNorm_2_real;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternal_2_real;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (UNSIGNED(arg(42 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternalSM_2_real;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11;
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(63) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (SIGNED('0' & arg(51 DOWNTO 21)))) / (2.0 ** 31); -- ignore low bits to fit within VHDL types
fraclo := REAL(to_integer (SIGNED('0' & arg(20 DOWNTO 0)))) / (2.0 ** 52);
expon := to_integer (SIGNED('0' & arg (62 downto 52)));
exp := expon - expon_base;
-- Fatal error (vsim-3421) if outside range -1e+308 +1e+308 which can still happen if exp = 1023
if exp >= 1023 then
sign := sign * 9.999e+307;
elsif expon = 0 then
sign := 0.0;
-- ignore denormalized mantissa
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end dIEEE_2_real;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(66 DOWNTO 35)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
if exp >= 1024 then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dNorm_2_real;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
variable sign_bit : STD_LOGIC;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(76 DOWNTO 45)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
sign_bit := arg(76);
if exp >= 1024 then
-- perhaps
-- or (arg(74) /= sign_bit and exp >= 1023) or (arg(74) /= sign_bit and arg(75) /= sign_bit and exp >= 1022) then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dInternal_2_real;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable exponBase : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
exponBase := 2**(expWidth-1) -1;
if arg(arg'high) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
if fracWidth > 31 then
frac := REAL(to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))))) / (2.0 ** 31);
fraclo := REAL(to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)))) / (2.0 ** fracWidth);
else
frac := REAL(to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)))) / (2.0 ** fracWidth);
fraclo := 0.0;
end if;
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
exp := expon - exponBase;
if exp > exponBase or exp >= 1023 then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end vIEEE_2_real;
function sIEEEisNan (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(30 downto 23) = "11111111" and a(22 downto 0) /= "00000000000000000000000";
end sIEEEisNan;
function sIEEEisInf (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(30 downto 0) = "1111111100000000000000000000000" then
--if a(30 downto 23) = "11111111" then
return TRUE;
else
return FALSE;
end if;
end sIEEEisInf;
function sIEEEisNegative (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(31) = '1';
end sIEEEisNegative;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if sIEEEisNan(a) and sIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if sIEEEisInf(a) and sIEEEisInf(b) then
return sIEEEisNegative(a) = sIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if sIEEEisInf(a) or sIEEEisInf(b) then
return FALSE;
end if;
a_real := sIEEE_2_real(a);
b_real := sIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end sIEEEisEqual;
function dIEEEisNan (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(62 downto 52) = "11111111111" and a(51 downto 0) /= "0000000000000000000000000000000000000000000000000000";
end dIEEEisNan;
function dIEEEisInf (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(62 downto 0) = "111111111110000000000000000000000000000000000000000000000000000" then
--if a(62 downto 52) = "11111111111" then
return TRUE;
else
return FALSE;
end if;
end dIEEEisInf;
function dIEEEisNegative (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(63) = '1';
end dIEEEisNegative;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if dIEEEisNan(a) and dIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if dIEEEisInf(a) and dIEEEisInf(b) then
return dIEEEisNegative(a) = dIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if dIEEEisInf(a) or dIEEEisInf(b) then
return FALSE;
end if;
a_real := dIEEE_2_real(a);
b_real := dIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end dIEEEisEqual;
function vIEEEisNan (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return TRUE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac /= 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac /= 0);
end vIEEEisNan;
function vIEEEisInf (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
-- ignore sign bit since this returns true for -inf and +inf
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return FALSE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac = 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac = 0);
end vIEEEisInf;
function vIEEEisNegative (arg : STD_LOGIC_VECTOR; we, wf : INTEGER) return BOOLEAN is
begin
return arg(arg'high) = '1';
end vIEEEisNegative;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
a_real := vIEEE_2_real(a, expWidth, fracWidth);
b_real := vIEEE_2_real(b, expWidth, fracWidth);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end vIEEEisEqual;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
if (vIEEEisSubnormal(a, expWidth, fracWidth) or vIEEEisZero(a, expWidth, fracWidth)) and
(vIEEEisSubnormal(b, expWidth, fracWidth) or vIEEEisZero(b, expWidth, fracWidth)) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
if (a = b) then
return TRUE;
end if;
return FALSE;
end vIEEEisExactEqual;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA /= 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisSubnormal;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA = 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisZero;
FUNCTION deviceFamilyA5 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" THEN
RETURN 2;
ELSIF f = "Arria V" THEN
RETURN 3;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamilyA5;
FUNCTION deviceFamily ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" or f = "Arria V" THEN
RETURN 2;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamily;
FUNCTION deviceFamilyS3 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
-- "Stratix V" also though many FPC components have not yet been optimized for this family
END FUNCTION deviceFamilyS3;
END fpc_library_package_cmd;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FPC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** ADSPB instantiated functions. Provides ***
--*** interface between ADSPB tool's types ***
--*** and hcc library elements ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE fpc_library_package_cmd IS
constant m_fpOutputScale : integer := 0; -- -ni: Fully pre-normalize single precision multipliers
constant m_fpRoundConvert : integer := 0; -- -rc: all conversions between signed and unsigned numbers
constant m_fpDoubleSpeed : integer := 1; -- -ds: Pipeline longer additions
constant m_fpOutputPipe : integer := 1; -- -op: Optimize away registers on simple internal output nodes
constant m_fpNormalisationSpeed : integer := 3; -- -ns: Normalization block performance (1,2 or 3)
constant m_SingleMantissaWidth : integer := 32; -- -mm: 0=>32-bit, 1=>36-bit
constant m_fpShiftSpeed : integer := 1; -- -ps: Remove pipelines out of large alignments
function deviceFamilyA5( f : string ) return integer;
function deviceFamily( f : string ) return integer;
function deviceFamilyS3( f : string ) return integer;
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
--***************************************************
--*** Single Precision ***
--***************************************************
COMPONENT fp_mult_sNorm_2_sInternal
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sNorm
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sIEEE
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM_v31
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (45 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternal_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal_v31
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
--***************************************************
--*** Double Precision ***
--***************************************************
COMPONENT fp_mult_dNorm_2_dInternal
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_dNorm_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_dInternal_2_dInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sNorm
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sInternal
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_sIEEE_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_dIEEE_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
END fpc_library_package_cmd;
PACKAGE BODY fpc_library_package_cmd is
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8;
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(31) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (UNSIGNED(arg(22 DOWNTO 0)))) / (2.0 ** 23);
expon := to_integer (UNSIGNED(arg (30 downto 23)));
exp := expon - expon_base;
if exp > expon_base then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac);
end if;
return sign;
end sIEEE_2_real;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sNorm_2_real;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternal_2_real;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (UNSIGNED(arg(42 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternalSM_2_real;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11;
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(63) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (SIGNED('0' & arg(51 DOWNTO 21)))) / (2.0 ** 31); -- ignore low bits to fit within VHDL types
fraclo := REAL(to_integer (SIGNED('0' & arg(20 DOWNTO 0)))) / (2.0 ** 52);
expon := to_integer (SIGNED('0' & arg (62 downto 52)));
exp := expon - expon_base;
-- Fatal error (vsim-3421) if outside range -1e+308 +1e+308 which can still happen if exp = 1023
if exp >= 1023 then
sign := sign * 9.999e+307;
elsif expon = 0 then
sign := 0.0;
-- ignore denormalized mantissa
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end dIEEE_2_real;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(66 DOWNTO 35)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
if exp >= 1024 then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dNorm_2_real;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
variable sign_bit : STD_LOGIC;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(76 DOWNTO 45)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
sign_bit := arg(76);
if exp >= 1024 then
-- perhaps
-- or (arg(74) /= sign_bit and exp >= 1023) or (arg(74) /= sign_bit and arg(75) /= sign_bit and exp >= 1022) then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dInternal_2_real;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable exponBase : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
exponBase := 2**(expWidth-1) -1;
if arg(arg'high) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
if fracWidth > 31 then
frac := REAL(to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))))) / (2.0 ** 31);
fraclo := REAL(to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)))) / (2.0 ** fracWidth);
else
frac := REAL(to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)))) / (2.0 ** fracWidth);
fraclo := 0.0;
end if;
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
exp := expon - exponBase;
if exp > exponBase or exp >= 1023 then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end vIEEE_2_real;
function sIEEEisNan (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(30 downto 23) = "11111111" and a(22 downto 0) /= "00000000000000000000000";
end sIEEEisNan;
function sIEEEisInf (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(30 downto 0) = "1111111100000000000000000000000" then
--if a(30 downto 23) = "11111111" then
return TRUE;
else
return FALSE;
end if;
end sIEEEisInf;
function sIEEEisNegative (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(31) = '1';
end sIEEEisNegative;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if sIEEEisNan(a) and sIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if sIEEEisInf(a) and sIEEEisInf(b) then
return sIEEEisNegative(a) = sIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if sIEEEisInf(a) or sIEEEisInf(b) then
return FALSE;
end if;
a_real := sIEEE_2_real(a);
b_real := sIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end sIEEEisEqual;
function dIEEEisNan (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(62 downto 52) = "11111111111" and a(51 downto 0) /= "0000000000000000000000000000000000000000000000000000";
end dIEEEisNan;
function dIEEEisInf (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(62 downto 0) = "111111111110000000000000000000000000000000000000000000000000000" then
--if a(62 downto 52) = "11111111111" then
return TRUE;
else
return FALSE;
end if;
end dIEEEisInf;
function dIEEEisNegative (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(63) = '1';
end dIEEEisNegative;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if dIEEEisNan(a) and dIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if dIEEEisInf(a) and dIEEEisInf(b) then
return dIEEEisNegative(a) = dIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if dIEEEisInf(a) or dIEEEisInf(b) then
return FALSE;
end if;
a_real := dIEEE_2_real(a);
b_real := dIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end dIEEEisEqual;
function vIEEEisNan (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return TRUE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac /= 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac /= 0);
end vIEEEisNan;
function vIEEEisInf (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
-- ignore sign bit since this returns true for -inf and +inf
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return FALSE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac = 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac = 0);
end vIEEEisInf;
function vIEEEisNegative (arg : STD_LOGIC_VECTOR; we, wf : INTEGER) return BOOLEAN is
begin
return arg(arg'high) = '1';
end vIEEEisNegative;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
a_real := vIEEE_2_real(a, expWidth, fracWidth);
b_real := vIEEE_2_real(b, expWidth, fracWidth);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end vIEEEisEqual;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
if (vIEEEisSubnormal(a, expWidth, fracWidth) or vIEEEisZero(a, expWidth, fracWidth)) and
(vIEEEisSubnormal(b, expWidth, fracWidth) or vIEEEisZero(b, expWidth, fracWidth)) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
if (a = b) then
return TRUE;
end if;
return FALSE;
end vIEEEisExactEqual;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA /= 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisSubnormal;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA = 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisZero;
FUNCTION deviceFamilyA5 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" THEN
RETURN 2;
ELSIF f = "Arria V" THEN
RETURN 3;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamilyA5;
FUNCTION deviceFamily ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" or f = "Arria V" THEN
RETURN 2;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamily;
FUNCTION deviceFamilyS3 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
-- "Stratix V" also though many FPC components have not yet been optimized for this family
END FUNCTION deviceFamilyS3;
END fpc_library_package_cmd;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FPC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** ADSPB instantiated functions. Provides ***
--*** interface between ADSPB tool's types ***
--*** and hcc library elements ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE fpc_library_package_cmd IS
constant m_fpOutputScale : integer := 0; -- -ni: Fully pre-normalize single precision multipliers
constant m_fpRoundConvert : integer := 0; -- -rc: all conversions between signed and unsigned numbers
constant m_fpDoubleSpeed : integer := 1; -- -ds: Pipeline longer additions
constant m_fpOutputPipe : integer := 1; -- -op: Optimize away registers on simple internal output nodes
constant m_fpNormalisationSpeed : integer := 3; -- -ns: Normalization block performance (1,2 or 3)
constant m_SingleMantissaWidth : integer := 32; -- -mm: 0=>32-bit, 1=>36-bit
constant m_fpShiftSpeed : integer := 1; -- -ps: Remove pipelines out of large alignments
function deviceFamilyA5( f : string ) return integer;
function deviceFamily( f : string ) return integer;
function deviceFamilyS3( f : string ) return integer;
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
--***************************************************
--*** Single Precision ***
--***************************************************
COMPONENT fp_mult_sNorm_2_sInternal
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sNorm
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sIEEE
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM_v31
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (45 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternal_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal_v31
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
--***************************************************
--*** Double Precision ***
--***************************************************
COMPONENT fp_mult_dNorm_2_dInternal
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_dNorm_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_dInternal_2_dInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sNorm
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sInternal
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_sIEEE_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_dIEEE_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
END fpc_library_package_cmd;
PACKAGE BODY fpc_library_package_cmd is
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8;
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(31) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (UNSIGNED(arg(22 DOWNTO 0)))) / (2.0 ** 23);
expon := to_integer (UNSIGNED(arg (30 downto 23)));
exp := expon - expon_base;
if exp > expon_base then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac);
end if;
return sign;
end sIEEE_2_real;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sNorm_2_real;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternal_2_real;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (UNSIGNED(arg(42 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternalSM_2_real;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11;
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(63) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (SIGNED('0' & arg(51 DOWNTO 21)))) / (2.0 ** 31); -- ignore low bits to fit within VHDL types
fraclo := REAL(to_integer (SIGNED('0' & arg(20 DOWNTO 0)))) / (2.0 ** 52);
expon := to_integer (SIGNED('0' & arg (62 downto 52)));
exp := expon - expon_base;
-- Fatal error (vsim-3421) if outside range -1e+308 +1e+308 which can still happen if exp = 1023
if exp >= 1023 then
sign := sign * 9.999e+307;
elsif expon = 0 then
sign := 0.0;
-- ignore denormalized mantissa
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end dIEEE_2_real;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(66 DOWNTO 35)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
if exp >= 1024 then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dNorm_2_real;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
variable sign_bit : STD_LOGIC;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(76 DOWNTO 45)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
sign_bit := arg(76);
if exp >= 1024 then
-- perhaps
-- or (arg(74) /= sign_bit and exp >= 1023) or (arg(74) /= sign_bit and arg(75) /= sign_bit and exp >= 1022) then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dInternal_2_real;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable exponBase : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
exponBase := 2**(expWidth-1) -1;
if arg(arg'high) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
if fracWidth > 31 then
frac := REAL(to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))))) / (2.0 ** 31);
fraclo := REAL(to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)))) / (2.0 ** fracWidth);
else
frac := REAL(to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)))) / (2.0 ** fracWidth);
fraclo := 0.0;
end if;
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
exp := expon - exponBase;
if exp > exponBase or exp >= 1023 then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end vIEEE_2_real;
function sIEEEisNan (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(30 downto 23) = "11111111" and a(22 downto 0) /= "00000000000000000000000";
end sIEEEisNan;
function sIEEEisInf (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(30 downto 0) = "1111111100000000000000000000000" then
--if a(30 downto 23) = "11111111" then
return TRUE;
else
return FALSE;
end if;
end sIEEEisInf;
function sIEEEisNegative (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(31) = '1';
end sIEEEisNegative;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if sIEEEisNan(a) and sIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if sIEEEisInf(a) and sIEEEisInf(b) then
return sIEEEisNegative(a) = sIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if sIEEEisInf(a) or sIEEEisInf(b) then
return FALSE;
end if;
a_real := sIEEE_2_real(a);
b_real := sIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end sIEEEisEqual;
function dIEEEisNan (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(62 downto 52) = "11111111111" and a(51 downto 0) /= "0000000000000000000000000000000000000000000000000000";
end dIEEEisNan;
function dIEEEisInf (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(62 downto 0) = "111111111110000000000000000000000000000000000000000000000000000" then
--if a(62 downto 52) = "11111111111" then
return TRUE;
else
return FALSE;
end if;
end dIEEEisInf;
function dIEEEisNegative (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(63) = '1';
end dIEEEisNegative;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if dIEEEisNan(a) and dIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if dIEEEisInf(a) and dIEEEisInf(b) then
return dIEEEisNegative(a) = dIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if dIEEEisInf(a) or dIEEEisInf(b) then
return FALSE;
end if;
a_real := dIEEE_2_real(a);
b_real := dIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end dIEEEisEqual;
function vIEEEisNan (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return TRUE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac /= 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac /= 0);
end vIEEEisNan;
function vIEEEisInf (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
-- ignore sign bit since this returns true for -inf and +inf
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return FALSE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac = 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac = 0);
end vIEEEisInf;
function vIEEEisNegative (arg : STD_LOGIC_VECTOR; we, wf : INTEGER) return BOOLEAN is
begin
return arg(arg'high) = '1';
end vIEEEisNegative;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
a_real := vIEEE_2_real(a, expWidth, fracWidth);
b_real := vIEEE_2_real(b, expWidth, fracWidth);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end vIEEEisEqual;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
if (vIEEEisSubnormal(a, expWidth, fracWidth) or vIEEEisZero(a, expWidth, fracWidth)) and
(vIEEEisSubnormal(b, expWidth, fracWidth) or vIEEEisZero(b, expWidth, fracWidth)) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
if (a = b) then
return TRUE;
end if;
return FALSE;
end vIEEEisExactEqual;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA /= 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisSubnormal;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA = 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisZero;
FUNCTION deviceFamilyA5 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" THEN
RETURN 2;
ELSIF f = "Arria V" THEN
RETURN 3;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamilyA5;
FUNCTION deviceFamily ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" or f = "Arria V" THEN
RETURN 2;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamily;
FUNCTION deviceFamilyS3 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
-- "Stratix V" also though many FPC components have not yet been optimized for this family
END FUNCTION deviceFamilyS3;
END fpc_library_package_cmd;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FPC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** ADSPB instantiated functions. Provides ***
--*** interface between ADSPB tool's types ***
--*** and hcc library elements ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE fpc_library_package_cmd IS
constant m_fpOutputScale : integer := 0; -- -ni: Fully pre-normalize single precision multipliers
constant m_fpRoundConvert : integer := 0; -- -rc: all conversions between signed and unsigned numbers
constant m_fpDoubleSpeed : integer := 1; -- -ds: Pipeline longer additions
constant m_fpOutputPipe : integer := 1; -- -op: Optimize away registers on simple internal output nodes
constant m_fpNormalisationSpeed : integer := 3; -- -ns: Normalization block performance (1,2 or 3)
constant m_SingleMantissaWidth : integer := 32; -- -mm: 0=>32-bit, 1=>36-bit
constant m_fpShiftSpeed : integer := 1; -- -ps: Remove pipelines out of large alignments
function deviceFamilyA5( f : string ) return integer;
function deviceFamily( f : string ) return integer;
function deviceFamilyS3( f : string ) return integer;
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
--***************************************************
--*** Single Precision ***
--***************************************************
COMPONENT fp_mult_sNorm_2_sInternal
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sNorm
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sIEEE
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM_v31
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (45 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternal_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal_v31
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
--***************************************************
--*** Double Precision ***
--***************************************************
COMPONENT fp_mult_dNorm_2_dInternal
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_dNorm_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_dInternal_2_dInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sNorm
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sInternal
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_sIEEE_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_dIEEE_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
END fpc_library_package_cmd;
PACKAGE BODY fpc_library_package_cmd is
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8;
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(31) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (UNSIGNED(arg(22 DOWNTO 0)))) / (2.0 ** 23);
expon := to_integer (UNSIGNED(arg (30 downto 23)));
exp := expon - expon_base;
if exp > expon_base then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac);
end if;
return sign;
end sIEEE_2_real;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sNorm_2_real;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternal_2_real;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (UNSIGNED(arg(42 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternalSM_2_real;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11;
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(63) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (SIGNED('0' & arg(51 DOWNTO 21)))) / (2.0 ** 31); -- ignore low bits to fit within VHDL types
fraclo := REAL(to_integer (SIGNED('0' & arg(20 DOWNTO 0)))) / (2.0 ** 52);
expon := to_integer (SIGNED('0' & arg (62 downto 52)));
exp := expon - expon_base;
-- Fatal error (vsim-3421) if outside range -1e+308 +1e+308 which can still happen if exp = 1023
if exp >= 1023 then
sign := sign * 9.999e+307;
elsif expon = 0 then
sign := 0.0;
-- ignore denormalized mantissa
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end dIEEE_2_real;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(66 DOWNTO 35)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
if exp >= 1024 then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dNorm_2_real;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
variable sign_bit : STD_LOGIC;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(76 DOWNTO 45)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
sign_bit := arg(76);
if exp >= 1024 then
-- perhaps
-- or (arg(74) /= sign_bit and exp >= 1023) or (arg(74) /= sign_bit and arg(75) /= sign_bit and exp >= 1022) then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dInternal_2_real;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable exponBase : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
exponBase := 2**(expWidth-1) -1;
if arg(arg'high) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
if fracWidth > 31 then
frac := REAL(to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))))) / (2.0 ** 31);
fraclo := REAL(to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)))) / (2.0 ** fracWidth);
else
frac := REAL(to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)))) / (2.0 ** fracWidth);
fraclo := 0.0;
end if;
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
exp := expon - exponBase;
if exp > exponBase or exp >= 1023 then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end vIEEE_2_real;
function sIEEEisNan (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(30 downto 23) = "11111111" and a(22 downto 0) /= "00000000000000000000000";
end sIEEEisNan;
function sIEEEisInf (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(30 downto 0) = "1111111100000000000000000000000" then
--if a(30 downto 23) = "11111111" then
return TRUE;
else
return FALSE;
end if;
end sIEEEisInf;
function sIEEEisNegative (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(31) = '1';
end sIEEEisNegative;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if sIEEEisNan(a) and sIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if sIEEEisInf(a) and sIEEEisInf(b) then
return sIEEEisNegative(a) = sIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if sIEEEisInf(a) or sIEEEisInf(b) then
return FALSE;
end if;
a_real := sIEEE_2_real(a);
b_real := sIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end sIEEEisEqual;
function dIEEEisNan (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(62 downto 52) = "11111111111" and a(51 downto 0) /= "0000000000000000000000000000000000000000000000000000";
end dIEEEisNan;
function dIEEEisInf (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(62 downto 0) = "111111111110000000000000000000000000000000000000000000000000000" then
--if a(62 downto 52) = "11111111111" then
return TRUE;
else
return FALSE;
end if;
end dIEEEisInf;
function dIEEEisNegative (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(63) = '1';
end dIEEEisNegative;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if dIEEEisNan(a) and dIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if dIEEEisInf(a) and dIEEEisInf(b) then
return dIEEEisNegative(a) = dIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if dIEEEisInf(a) or dIEEEisInf(b) then
return FALSE;
end if;
a_real := dIEEE_2_real(a);
b_real := dIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end dIEEEisEqual;
function vIEEEisNan (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return TRUE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac /= 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac /= 0);
end vIEEEisNan;
function vIEEEisInf (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
-- ignore sign bit since this returns true for -inf and +inf
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return FALSE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac = 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac = 0);
end vIEEEisInf;
function vIEEEisNegative (arg : STD_LOGIC_VECTOR; we, wf : INTEGER) return BOOLEAN is
begin
return arg(arg'high) = '1';
end vIEEEisNegative;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
a_real := vIEEE_2_real(a, expWidth, fracWidth);
b_real := vIEEE_2_real(b, expWidth, fracWidth);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end vIEEEisEqual;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
if (vIEEEisSubnormal(a, expWidth, fracWidth) or vIEEEisZero(a, expWidth, fracWidth)) and
(vIEEEisSubnormal(b, expWidth, fracWidth) or vIEEEisZero(b, expWidth, fracWidth)) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
if (a = b) then
return TRUE;
end if;
return FALSE;
end vIEEEisExactEqual;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA /= 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisSubnormal;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA = 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisZero;
FUNCTION deviceFamilyA5 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" THEN
RETURN 2;
ELSIF f = "Arria V" THEN
RETURN 3;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamilyA5;
FUNCTION deviceFamily ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" or f = "Arria V" THEN
RETURN 2;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamily;
FUNCTION deviceFamilyS3 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
-- "Stratix V" also though many FPC components have not yet been optimized for this family
END FUNCTION deviceFamilyS3;
END fpc_library_package_cmd;
|
-- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2019 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/vhdl_lib.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- gen_lfsr.vhd
--
-- -----------------------------------------------------------------------
--
-- LFSR - Linear Feedback Shift Register
--
-- -----------------------------------------------------------------------
-- bits - number of bits in shift register (valid range 3 to 168)
-- -----------------------------------------------------------------------
-- clk - clock input
-- reset - reset shift register to zero
-- stop - stop shifting if set
-- load - Load shift register from d input
-- d - input for load
-- q - LFSR output
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_lfsr is
generic (
bits : integer := 8
);
port (
clk : in std_logic;
reset : in std_logic := '0';
stop : in std_logic := '0';
load : in std_logic := '0';
d : in unsigned(bits-1 downto 0) := (others => '0');
q : out unsigned(bits-1 downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gen_lfsr is
signal shift_reg : unsigned(bits-1 downto 0) := (others => '0');
function feedback(sr : in unsigned(bits-1 downto 0)) return std_logic is
variable result : std_logic;
begin
result := '0';
-- Magic tap points following Xilinx application note XAPP052
-- Take note the application note counts bits from 1. Here we count from 0, so all the indexes are 1 lower.
case bits is
when 3 | 4 | 6 | 7 | 15 | 22 | 60 | 63 | 127 =>
result := sr(bits-1) xnor sr(bits-2);
when 5 =>
result := sr(bits-1) xnor sr(2);
when 8 =>
result := sr(bits-1) xnor sr(5) xnor sr(4) xnor sr(3);
when 9 =>
result := sr(bits-1) xnor sr(4);
when 10 =>
result := sr(bits-1) xnor sr(6);
when 11 =>
result := sr(bits-1) xnor sr(8);
when 12 =>
result := sr(bits-1) xnor sr(5) xnor sr(3) xnor sr(0);
when 13 =>
result := sr(bits-1) xnor sr(3) xnor sr(2) xnor sr(0);
when 14 =>
result := sr(bits-1) xnor sr(4) xnor sr(2) xnor sr(0);
when 16 =>
result := sr(bits-1) xnor sr(14) xnor sr(12) xnor sr(3);
when 17 =>
result := sr(bits-1) xnor sr(13);
when 18 =>
result := sr(bits-1) xnor sr(10);
when others =>
assert(false);
end case;
return result;
end function;
begin
q <= shift_reg;
process(clk) is
begin
if rising_edge(clk) then
if stop = '0' then
shift_reg <= shift_reg(bits-2 downto 0) & feedback(shift_reg);
end if;
if load = '1' then
shift_reg <= d;
end if;
if reset = '1' then
shift_reg <= (others => '0');
end if;
end if;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:39:32 01/12/2015
-- Design Name:
-- Module Name: delayDone - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use IEEE.numeric_std.all;
entity delayDone is
generic(
Steps : integer := 10);
port(
clk : In Std_logic;
init_model : in STD_LOGIC; --signal to all components to go into their init state
Start : In Std_logic;
Done : Out Std_logic
);
end delayDone;
architecture Behavioral of delayDone is
signal count : integer ;
signal count_next : integer ;
signal Done_next : std_logic ;
begin
combinationProc : process (count,start,init_model)
begin
count_next <= count;
Done_next <= '0';
if init_model = '1' then
count_next <= Steps;
Done_next <= '1';
else
if start = '1' then
count_next <= 0;
elsif count < Steps then
count_next <= count + 1;
else
Done_next <= '1';
end if;
end if;
end process;
synchronousProc : process (clk)
begin
if clk'event and clk = '1' then
count <= count_next;
Done <= Done_next;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:39:32 01/12/2015
-- Design Name:
-- Module Name: delayDone - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use IEEE.numeric_std.all;
entity delayDone is
generic(
Steps : integer := 10);
port(
clk : In Std_logic;
init_model : in STD_LOGIC; --signal to all components to go into their init state
Start : In Std_logic;
Done : Out Std_logic
);
end delayDone;
architecture Behavioral of delayDone is
signal count : integer ;
signal count_next : integer ;
signal Done_next : std_logic ;
begin
combinationProc : process (count,start,init_model)
begin
count_next <= count;
Done_next <= '0';
if init_model = '1' then
count_next <= Steps;
Done_next <= '1';
else
if start = '1' then
count_next <= 0;
elsif count < Steps then
count_next <= count + 1;
else
Done_next <= '1';
end if;
end if;
end process;
synchronousProc : process (clk)
begin
if clk'event and clk = '1' then
count <= count_next;
Done <= Done_next;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:25:11 05/06/2017
-- Design Name:
-- Module Name: Mux_reg2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux_reg2 is
Port ( alusrcb : in STD_LOGIC_VECTOR (1 downto 0);
muxreg2 : in STD_LOGIC_VECTOR (15 downto 0);
mux_imm : in STD_LOGIC_VECTOR (15 downto 0);
mux_dataB : out STD_LOGIC_VECTOR (15 downto 0));
end mux_reg2;
architecture Behavioral of mux_reg2 is
begin
process(alusrcb)
begin
case alusrcb is
when "00"=>
mux_dataB<=muxreg2;
when "01"=>
mux_dataB<=mux_imm;
when others=>null;
end case;
end process;
end Behavioral;
|
------------------------------------------------------------------------------------------------------------------------
-- OpenMAC - DPR for Xilinx FPGA
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-08-07 V0.01 zelenkaj Converted to official version.
-- 2011-10-12 V0.10 zelenkaj Implementation is based on UG687 (v13.2)
-- 2012-03-01 V0.11 mairt added memory init for pdi dpr
------------------------------------------------------------------------------------------------------------------------
--
-- dual clocked DPRAM for XILINX SPARTAN 6 --
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dc_dpr is
generic (
WIDTH : integer := 16;
SIZE : integer := 128;
ADDRWIDTH : integer := 7
);
port (
clkA : in std_logic;
clkB : in std_logic;
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
addrA : in std_logic_vector(ADDRWIDTH-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTH-1 downto 0);
diA : in std_logic_vector(WIDTH-1 downto 0);
diB : in std_logic_vector(WIDTH-1 downto 0);
doA : out std_logic_vector(WIDTH-1 downto 0);
doB : out std_logic_vector(WIDTH-1 downto 0)
);
end dc_dpr;
architecture xilinx of dc_dpr is
function log2 (val: INTEGER) return natural is
variable res : natural;
begin
for i in 0 to 31 loop
if (val <= (2**i)) then
res := i;
exit;
end if;
end loop;
return res;
end function Log2;
type ramType is array (0 to SIZE-1) of std_logic_vector(WIDTH-1 downto 0);
shared variable ram : ramType := (others => (others => '0'));
signal readA : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
signal readB : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
begin
process (clkA)
begin
if rising_edge(clkA) then
if enA = '1' then
if weA = '1' then
ram(conv_integer(addrA)) := diA;
end if;
readA <= ram(conv_integer(addrA));
end if;
end if;
end process;
doA <= readA;
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
if weB = '1' then
ram(conv_integer(addrB)) := diB;
end if;
readB <= ram(conv_integer(addrB));
end if;
end if;
end process;
doB <= readB;
end xilinx;
-- dual clocked DPRAM with byte enables for XILINX SPARTAN 6 --
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dc_dpr_be is
generic (
gDoInit : boolean := false; -- if dpr is used in pdi init state field with invalid state
WIDTH : integer := 16;
SIZE : integer := 128;
ADDRWIDTH : integer := 7
);
port (
clkA : in std_logic;
clkB : in std_logic;
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
beA : in std_logic_vector(WIDTH/8-1 downto 0);
beB : in std_logic_vector(WIDTH/8-1 downto 0);
addrA : in std_logic_vector(ADDRWIDTH-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTH-1 downto 0);
diA : in std_logic_vector(WIDTH-1 downto 0);
diB : in std_logic_vector(WIDTH-1 downto 0);
doA : out std_logic_vector(WIDTH-1 downto 0);
doB : out std_logic_vector(WIDTH-1 downto 0)
);
end dc_dpr_be;
architecture xilinx of dc_dpr_be is
function log2 (val: INTEGER) return natural is
variable res : natural;
begin
for i in 0 to 31 loop
if (val <= (2**i)) then
res := i;
exit;
end if;
end loop;
return res;
end function Log2;
type ramType is array (0 to SIZE-1) of std_logic_vector(WIDTH-1 downto 0);
function InitRam return ramType is
variable RAM : ramType := (others => (others => '0'));
begin
if gDoInit = true then
for i in ramType'range loop
RAM(i) := X"00000000";
if i = 4 then -- init state field with invalid state
RAM(i) := X"00EEFFFF";
end if;
end loop;
end if;
return RAM;
end function;
shared variable ram : ramType := InitRam;
constant BYTE : integer := 8;
signal readA : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
signal readB : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
begin
process (clkA)
begin
if rising_edge(clkA) then
if enA = '1' then
if weA = '1' then
for i in beA'range loop
if beA(i) = '1' then
ram(conv_integer(addrA))((i+1)*BYTE-1 downto i*BYTE) := diA((i+1)*BYTE-1 downto i*BYTE);
end if;
end loop;
end if;
readA <= ram(conv_integer(addrA));
end if;
end if;
end process;
doA <= readA;
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
if weB = '1' then
for i in beB'range loop
if beB(i) = '1' then
ram(conv_integer(addrB))((i+1)*BYTE-1 downto i*BYTE) := diB((i+1)*BYTE-1 downto i*BYTE);
end if;
end loop;
end if;
readB <= ram(conv_integer(addrB));
end if;
end if;
end process;
doB <= readB;
end xilinx;
-- dual clocked DPRAM with 16x16 --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity Dpr_16_16 is
generic(Simulate : in boolean);
port (
ClkA, ClkB : in std_logic;
WeA, WeB : in std_logic := '0';
EnA, EnB : in std_logic := '1';
BeA : in std_logic_vector ( 1 downto 0) := "11";
AddrA : in std_logic_vector ( 7 downto 0);
DiA : in std_logic_vector (15 downto 0) := (others => '0');
DoA : out std_logic_vector(15 downto 0);
BeB : in std_logic_vector ( 1 downto 0) := "11";
AddrB : in std_logic_vector ( 7 downto 0);
DiB : in std_logic_vector (15 downto 0) := (others => '0');
DoB : out std_logic_vector(15 downto 0)
);
end Dpr_16_16;
architecture struct of Dpr_16_16 is
begin
dpr_packet: entity work.dc_dpr_be
generic map (
gDoInit => false,
WIDTH => 16,
SIZE => 2**AddrA'length,
ADDRWIDTH => AddrA'length
)
port map (
clkA => ClkA, clkB => ClkB,
enA => EnA, enB => EnB,
addrA => AddrA, addrB => AddrB,
diA => DiA, diB => DiB,
doA => DoA, doB => DoB,
weA => WeA, weB => WeB,
beA => BeA, beB => BeB
);
end struct;
-- dual clocked DPRAM with 16x32 --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity Dpr_16_32 is
generic(Simulate : in boolean);
port (
ClkA, ClkB : in std_logic;
WeA : in std_logic := '0';
EnA, EnB : in std_logic := '1';
AddrA : in std_logic_vector ( 7 downto 0);
DiA : in std_logic_vector (15 downto 0) := (others => '0');
BeA : in std_logic_vector ( 1 downto 0) := "11";
AddrB : in std_logic_vector ( 6 downto 0);
DoB : out std_logic_vector(31 downto 0)
);
end Dpr_16_32;
architecture struct of Dpr_16_32 is
signal addra_s : std_logic_vector(AddrB'range);
signal dia_s : std_logic_vector(DoB'range);
signal bea_s : std_logic_vector(DoB'length/8-1 downto 0);
begin
dpr_packet: entity work.dc_dpr_be
generic map (
gDoInit => false,
WIDTH => 32,
SIZE => 2**AddrB'length,
ADDRWIDTH => AddrB'length
)
port map (
clkA => ClkA, clkB => ClkB,
enA => EnA, enB => EnB,
addrA => addra_s, addrB => AddrB,
diA => dia_s, diB => (others => '0'),
doA => open, doB => DoB,
weA => weA, weB => '0',
beA => bea_s, beB => (others => '1')
);
addra_s <= AddrA(AddrA'left downto 1);
dia_s <= DiA & DiA;
bea_s(3) <= BeA(1) and AddrA(0);
bea_s(2) <= BeA(0) and AddrA(0);
bea_s(1) <= BeA(1) and not AddrA(0);
bea_s(0) <= BeA(0) and not AddrA(0);
end struct;
-- dual clocked DPRAM with 32x32 for packets --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY OpenMAC_DPRpackets IS
GENERIC
(
memSizeLOG2_g : integer := 10;
memSize_g : integer := 1024
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (memSizeLOG2_g-2 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (memSizeLOG2_g-3 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
rden_a : IN STD_LOGIC := '1';
rden_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END OpenMAC_DPRpackets;
architecture struct of OpenMAC_DPRpackets is
signal address_a_s : std_logic_vector(address_b'range);
signal bea : std_logic_vector(byteena_b'range);
signal q_a_s, q_b_s, data_a_s : std_logic_vector(q_b'range);
signal q_a_s1 : std_logic_vector(q_a'range);
begin
dpr_packet: entity work.dc_dpr_be
generic map (
gDoInit => false,
WIDTH => 32,
SIZE => memSize_g/4,
ADDRWIDTH => memSizeLOG2_g-2
)
port map (
clkA => clock_a, clkB => clock_b,
enA => '1', enB => '1',
addrA => address_a_s, addrB => address_b,
diA => data_a_s, diB => data_b,
doA => q_a_s, doB => q_b_s,
weA => wren_a, weB => wren_b,
beA => bea, beB => byteena_b
);
address_a_s <= address_a(address_a'left downto 1);
bea(3) <= byteena_a(1) and address_a(0);
bea(2) <= byteena_a(0) and address_a(0);
bea(1) <= byteena_a(1) and not address_a(0);
bea(0) <= byteena_a(0) and not address_a(0);
data_a_s <= data_a & data_a;
q_a_s1 <= q_a_s(q_a'length*2-1 downto q_a'length) when address_a(0) = '1' else
q_a_s(q_a'range);
--sync outputs
process(clock_a)
begin
if rising_edge(clock_a) then
q_a <= q_a_s1;
end if;
end process;
process(clock_b)
begin
if rising_edge(clock_b) then
q_b <= q_b_s;
end if;
end process;
end struct;
|
------------------------------------------------------------------------------------------------------------------------
-- OpenMAC - DPR for Xilinx FPGA
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-08-07 V0.01 zelenkaj Converted to official version.
-- 2011-10-12 V0.10 zelenkaj Implementation is based on UG687 (v13.2)
-- 2012-03-01 V0.11 mairt added memory init for pdi dpr
------------------------------------------------------------------------------------------------------------------------
--
-- dual clocked DPRAM for XILINX SPARTAN 6 --
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dc_dpr is
generic (
WIDTH : integer := 16;
SIZE : integer := 128;
ADDRWIDTH : integer := 7
);
port (
clkA : in std_logic;
clkB : in std_logic;
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
addrA : in std_logic_vector(ADDRWIDTH-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTH-1 downto 0);
diA : in std_logic_vector(WIDTH-1 downto 0);
diB : in std_logic_vector(WIDTH-1 downto 0);
doA : out std_logic_vector(WIDTH-1 downto 0);
doB : out std_logic_vector(WIDTH-1 downto 0)
);
end dc_dpr;
architecture xilinx of dc_dpr is
function log2 (val: INTEGER) return natural is
variable res : natural;
begin
for i in 0 to 31 loop
if (val <= (2**i)) then
res := i;
exit;
end if;
end loop;
return res;
end function Log2;
type ramType is array (0 to SIZE-1) of std_logic_vector(WIDTH-1 downto 0);
shared variable ram : ramType := (others => (others => '0'));
signal readA : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
signal readB : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
begin
process (clkA)
begin
if rising_edge(clkA) then
if enA = '1' then
if weA = '1' then
ram(conv_integer(addrA)) := diA;
end if;
readA <= ram(conv_integer(addrA));
end if;
end if;
end process;
doA <= readA;
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
if weB = '1' then
ram(conv_integer(addrB)) := diB;
end if;
readB <= ram(conv_integer(addrB));
end if;
end if;
end process;
doB <= readB;
end xilinx;
-- dual clocked DPRAM with byte enables for XILINX SPARTAN 6 --
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dc_dpr_be is
generic (
gDoInit : boolean := false; -- if dpr is used in pdi init state field with invalid state
WIDTH : integer := 16;
SIZE : integer := 128;
ADDRWIDTH : integer := 7
);
port (
clkA : in std_logic;
clkB : in std_logic;
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
beA : in std_logic_vector(WIDTH/8-1 downto 0);
beB : in std_logic_vector(WIDTH/8-1 downto 0);
addrA : in std_logic_vector(ADDRWIDTH-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTH-1 downto 0);
diA : in std_logic_vector(WIDTH-1 downto 0);
diB : in std_logic_vector(WIDTH-1 downto 0);
doA : out std_logic_vector(WIDTH-1 downto 0);
doB : out std_logic_vector(WIDTH-1 downto 0)
);
end dc_dpr_be;
architecture xilinx of dc_dpr_be is
function log2 (val: INTEGER) return natural is
variable res : natural;
begin
for i in 0 to 31 loop
if (val <= (2**i)) then
res := i;
exit;
end if;
end loop;
return res;
end function Log2;
type ramType is array (0 to SIZE-1) of std_logic_vector(WIDTH-1 downto 0);
function InitRam return ramType is
variable RAM : ramType := (others => (others => '0'));
begin
if gDoInit = true then
for i in ramType'range loop
RAM(i) := X"00000000";
if i = 4 then -- init state field with invalid state
RAM(i) := X"00EEFFFF";
end if;
end loop;
end if;
return RAM;
end function;
shared variable ram : ramType := InitRam;
constant BYTE : integer := 8;
signal readA : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
signal readB : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
begin
process (clkA)
begin
if rising_edge(clkA) then
if enA = '1' then
if weA = '1' then
for i in beA'range loop
if beA(i) = '1' then
ram(conv_integer(addrA))((i+1)*BYTE-1 downto i*BYTE) := diA((i+1)*BYTE-1 downto i*BYTE);
end if;
end loop;
end if;
readA <= ram(conv_integer(addrA));
end if;
end if;
end process;
doA <= readA;
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
if weB = '1' then
for i in beB'range loop
if beB(i) = '1' then
ram(conv_integer(addrB))((i+1)*BYTE-1 downto i*BYTE) := diB((i+1)*BYTE-1 downto i*BYTE);
end if;
end loop;
end if;
readB <= ram(conv_integer(addrB));
end if;
end if;
end process;
doB <= readB;
end xilinx;
-- dual clocked DPRAM with 16x16 --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity Dpr_16_16 is
generic(Simulate : in boolean);
port (
ClkA, ClkB : in std_logic;
WeA, WeB : in std_logic := '0';
EnA, EnB : in std_logic := '1';
BeA : in std_logic_vector ( 1 downto 0) := "11";
AddrA : in std_logic_vector ( 7 downto 0);
DiA : in std_logic_vector (15 downto 0) := (others => '0');
DoA : out std_logic_vector(15 downto 0);
BeB : in std_logic_vector ( 1 downto 0) := "11";
AddrB : in std_logic_vector ( 7 downto 0);
DiB : in std_logic_vector (15 downto 0) := (others => '0');
DoB : out std_logic_vector(15 downto 0)
);
end Dpr_16_16;
architecture struct of Dpr_16_16 is
begin
dpr_packet: entity work.dc_dpr_be
generic map (
gDoInit => false,
WIDTH => 16,
SIZE => 2**AddrA'length,
ADDRWIDTH => AddrA'length
)
port map (
clkA => ClkA, clkB => ClkB,
enA => EnA, enB => EnB,
addrA => AddrA, addrB => AddrB,
diA => DiA, diB => DiB,
doA => DoA, doB => DoB,
weA => WeA, weB => WeB,
beA => BeA, beB => BeB
);
end struct;
-- dual clocked DPRAM with 16x32 --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity Dpr_16_32 is
generic(Simulate : in boolean);
port (
ClkA, ClkB : in std_logic;
WeA : in std_logic := '0';
EnA, EnB : in std_logic := '1';
AddrA : in std_logic_vector ( 7 downto 0);
DiA : in std_logic_vector (15 downto 0) := (others => '0');
BeA : in std_logic_vector ( 1 downto 0) := "11";
AddrB : in std_logic_vector ( 6 downto 0);
DoB : out std_logic_vector(31 downto 0)
);
end Dpr_16_32;
architecture struct of Dpr_16_32 is
signal addra_s : std_logic_vector(AddrB'range);
signal dia_s : std_logic_vector(DoB'range);
signal bea_s : std_logic_vector(DoB'length/8-1 downto 0);
begin
dpr_packet: entity work.dc_dpr_be
generic map (
gDoInit => false,
WIDTH => 32,
SIZE => 2**AddrB'length,
ADDRWIDTH => AddrB'length
)
port map (
clkA => ClkA, clkB => ClkB,
enA => EnA, enB => EnB,
addrA => addra_s, addrB => AddrB,
diA => dia_s, diB => (others => '0'),
doA => open, doB => DoB,
weA => weA, weB => '0',
beA => bea_s, beB => (others => '1')
);
addra_s <= AddrA(AddrA'left downto 1);
dia_s <= DiA & DiA;
bea_s(3) <= BeA(1) and AddrA(0);
bea_s(2) <= BeA(0) and AddrA(0);
bea_s(1) <= BeA(1) and not AddrA(0);
bea_s(0) <= BeA(0) and not AddrA(0);
end struct;
-- dual clocked DPRAM with 32x32 for packets --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY OpenMAC_DPRpackets IS
GENERIC
(
memSizeLOG2_g : integer := 10;
memSize_g : integer := 1024
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (memSizeLOG2_g-2 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (memSizeLOG2_g-3 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
rden_a : IN STD_LOGIC := '1';
rden_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END OpenMAC_DPRpackets;
architecture struct of OpenMAC_DPRpackets is
signal address_a_s : std_logic_vector(address_b'range);
signal bea : std_logic_vector(byteena_b'range);
signal q_a_s, q_b_s, data_a_s : std_logic_vector(q_b'range);
signal q_a_s1 : std_logic_vector(q_a'range);
begin
dpr_packet: entity work.dc_dpr_be
generic map (
gDoInit => false,
WIDTH => 32,
SIZE => memSize_g/4,
ADDRWIDTH => memSizeLOG2_g-2
)
port map (
clkA => clock_a, clkB => clock_b,
enA => '1', enB => '1',
addrA => address_a_s, addrB => address_b,
diA => data_a_s, diB => data_b,
doA => q_a_s, doB => q_b_s,
weA => wren_a, weB => wren_b,
beA => bea, beB => byteena_b
);
address_a_s <= address_a(address_a'left downto 1);
bea(3) <= byteena_a(1) and address_a(0);
bea(2) <= byteena_a(0) and address_a(0);
bea(1) <= byteena_a(1) and not address_a(0);
bea(0) <= byteena_a(0) and not address_a(0);
data_a_s <= data_a & data_a;
q_a_s1 <= q_a_s(q_a'length*2-1 downto q_a'length) when address_a(0) = '1' else
q_a_s(q_a'range);
--sync outputs
process(clock_a)
begin
if rising_edge(clock_a) then
q_a <= q_a_s1;
end if;
end process;
process(clock_b)
begin
if rising_edge(clock_b) then
q_b <= q_b_s;
end if;
end process;
end struct;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:08:25 11/17/2013
-- Design Name:
-- Module Name: C:/Users/etingi01/Mips32_948282/My_And_tb_948282.vhd
-- Project Name: Mips32_948282
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: My_And_948282
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY My_And_tb_948282 IS
END My_And_tb_948282;
ARCHITECTURE behavior OF My_And_tb_948282 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT My_And_948282
PORT(
A : IN std_logic;
B : IN std_logic;
R : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';
--Outputs
signal R : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: My_And_948282 PORT MAP (
A => A,
B => B,
R => R
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
A<='0';
B<='1';
wait for 20 ns;
A<= '0';
B<='0';
wait for 20 ns;
A<='1';
B<='1';
wait for 20 ns;
-- insert stimulus here
wait;
end process;
END;
|
-------------------------------------------------------------------------------
-- system_axi_dispctrl_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_dispctrl_v1_00_a;
use axi_dispctrl_v1_00_a.all;
entity system_axi_dispctrl_0_wrapper is
port (
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
VDMA_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
FSYNC_O : out std_logic;
HSYNC_O : out std_logic;
VSYNC_O : out std_logic;
DE_O : out std_logic;
RED_O : out std_logic_vector(7 downto 0);
GREEN_O : out std_logic_vector(7 downto 0);
BLUE_O : out std_logic_vector(7 downto 0);
ENABLE_O : out std_logic;
DEBUG_O : out std_logic_vector(31 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TVALID : in std_logic;
S_AXIS_TLAST : in std_logic;
S_AXIS_TSTRB : in std_logic_vector(3 downto 0)
);
end system_axi_dispctrl_0_wrapper;
architecture STRUCTURE of system_axi_dispctrl_0_wrapper is
component axi_dispctrl is
generic (
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_MIN_SIZE : std_logic_vector;
C_USE_WSTRB : INTEGER;
C_DPHASE_TIMEOUT : INTEGER;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_FAMILY : STRING;
C_NUM_REG : INTEGER;
C_NUM_MEM : INTEGER;
C_SLV_AWIDTH : INTEGER;
C_SLV_DWIDTH : INTEGER;
C_USE_BUFR_DIV5 : INTEGER;
C_RED_WIDTH : INTEGER;
C_GREEN_WIDTH : INTEGER;
C_BLUE_WIDTH : INTEGER;
C_S_AXIS_MM2S_TDATA_WIDTH : INTEGER
);
port (
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
VDMA_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
FSYNC_O : out std_logic;
HSYNC_O : out std_logic;
VSYNC_O : out std_logic;
DE_O : out std_logic;
RED_O : out std_logic_vector((C_RED_WIDTH-1) downto 0);
GREEN_O : out std_logic_vector((C_GREEN_WIDTH-1) downto 0);
BLUE_O : out std_logic_vector((C_BLUE_WIDTH-1) downto 0);
ENABLE_O : out std_logic;
DEBUG_O : out std_logic_vector(31 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_WSTRB : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in std_logic_vector((C_S_AXIS_MM2S_TDATA_WIDTH-1) downto 0);
S_AXIS_TVALID : in std_logic;
S_AXIS_TLAST : in std_logic;
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0)
);
end component;
begin
axi_dispctrl_0 : axi_dispctrl
generic map (
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 32,
C_S_AXI_MIN_SIZE => X"000001ff",
C_USE_WSTRB => 0,
C_DPHASE_TIMEOUT => 8,
C_BASEADDR => X"75c00000",
C_HIGHADDR => X"75c0ffff",
C_FAMILY => "zynq",
C_NUM_REG => 1,
C_NUM_MEM => 1,
C_SLV_AWIDTH => 32,
C_SLV_DWIDTH => 32,
C_USE_BUFR_DIV5 => 1,
C_RED_WIDTH => 8,
C_GREEN_WIDTH => 8,
C_BLUE_WIDTH => 8,
C_S_AXIS_MM2S_TDATA_WIDTH => 32
)
port map (
REF_CLK_I => REF_CLK_I,
PXL_CLK_O => PXL_CLK_O,
VDMA_CLK_O => VDMA_CLK_O,
PXL_CLK_5X_O => PXL_CLK_5X_O,
LOCKED_O => LOCKED_O,
FSYNC_O => FSYNC_O,
HSYNC_O => HSYNC_O,
VSYNC_O => VSYNC_O,
DE_O => DE_O,
RED_O => RED_O,
GREEN_O => GREEN_O,
BLUE_O => BLUE_O,
ENABLE_O => ENABLE_O,
DEBUG_O => DEBUG_O,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_ACLK => S_AXIS_ACLK,
S_AXIS_ARESETN => S_AXIS_ARESETN,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TSTRB => S_AXIS_TSTRB
);
end architecture STRUCTURE;
|
-------------------------------------------------------------------------------
-- system_axi_dispctrl_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_dispctrl_v1_00_a;
use axi_dispctrl_v1_00_a.all;
entity system_axi_dispctrl_0_wrapper is
port (
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
VDMA_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
FSYNC_O : out std_logic;
HSYNC_O : out std_logic;
VSYNC_O : out std_logic;
DE_O : out std_logic;
RED_O : out std_logic_vector(7 downto 0);
GREEN_O : out std_logic_vector(7 downto 0);
BLUE_O : out std_logic_vector(7 downto 0);
ENABLE_O : out std_logic;
DEBUG_O : out std_logic_vector(31 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TVALID : in std_logic;
S_AXIS_TLAST : in std_logic;
S_AXIS_TSTRB : in std_logic_vector(3 downto 0)
);
end system_axi_dispctrl_0_wrapper;
architecture STRUCTURE of system_axi_dispctrl_0_wrapper is
component axi_dispctrl is
generic (
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_MIN_SIZE : std_logic_vector;
C_USE_WSTRB : INTEGER;
C_DPHASE_TIMEOUT : INTEGER;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_FAMILY : STRING;
C_NUM_REG : INTEGER;
C_NUM_MEM : INTEGER;
C_SLV_AWIDTH : INTEGER;
C_SLV_DWIDTH : INTEGER;
C_USE_BUFR_DIV5 : INTEGER;
C_RED_WIDTH : INTEGER;
C_GREEN_WIDTH : INTEGER;
C_BLUE_WIDTH : INTEGER;
C_S_AXIS_MM2S_TDATA_WIDTH : INTEGER
);
port (
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
VDMA_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
FSYNC_O : out std_logic;
HSYNC_O : out std_logic;
VSYNC_O : out std_logic;
DE_O : out std_logic;
RED_O : out std_logic_vector((C_RED_WIDTH-1) downto 0);
GREEN_O : out std_logic_vector((C_GREEN_WIDTH-1) downto 0);
BLUE_O : out std_logic_vector((C_BLUE_WIDTH-1) downto 0);
ENABLE_O : out std_logic;
DEBUG_O : out std_logic_vector(31 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_WSTRB : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in std_logic_vector((C_S_AXIS_MM2S_TDATA_WIDTH-1) downto 0);
S_AXIS_TVALID : in std_logic;
S_AXIS_TLAST : in std_logic;
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0)
);
end component;
begin
axi_dispctrl_0 : axi_dispctrl
generic map (
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 32,
C_S_AXI_MIN_SIZE => X"000001ff",
C_USE_WSTRB => 0,
C_DPHASE_TIMEOUT => 8,
C_BASEADDR => X"75c00000",
C_HIGHADDR => X"75c0ffff",
C_FAMILY => "zynq",
C_NUM_REG => 1,
C_NUM_MEM => 1,
C_SLV_AWIDTH => 32,
C_SLV_DWIDTH => 32,
C_USE_BUFR_DIV5 => 1,
C_RED_WIDTH => 8,
C_GREEN_WIDTH => 8,
C_BLUE_WIDTH => 8,
C_S_AXIS_MM2S_TDATA_WIDTH => 32
)
port map (
REF_CLK_I => REF_CLK_I,
PXL_CLK_O => PXL_CLK_O,
VDMA_CLK_O => VDMA_CLK_O,
PXL_CLK_5X_O => PXL_CLK_5X_O,
LOCKED_O => LOCKED_O,
FSYNC_O => FSYNC_O,
HSYNC_O => HSYNC_O,
VSYNC_O => VSYNC_O,
DE_O => DE_O,
RED_O => RED_O,
GREEN_O => GREEN_O,
BLUE_O => BLUE_O,
ENABLE_O => ENABLE_O,
DEBUG_O => DEBUG_O,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_ACLK => S_AXIS_ACLK,
S_AXIS_ARESETN => S_AXIS_ARESETN,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TSTRB => S_AXIS_TSTRB
);
end architecture STRUCTURE;
|
-------------------------------------------------------------------------------
-- system_axi_dispctrl_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_dispctrl_v1_00_a;
use axi_dispctrl_v1_00_a.all;
entity system_axi_dispctrl_0_wrapper is
port (
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
VDMA_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
FSYNC_O : out std_logic;
HSYNC_O : out std_logic;
VSYNC_O : out std_logic;
DE_O : out std_logic;
RED_O : out std_logic_vector(7 downto 0);
GREEN_O : out std_logic_vector(7 downto 0);
BLUE_O : out std_logic_vector(7 downto 0);
ENABLE_O : out std_logic;
DEBUG_O : out std_logic_vector(31 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TVALID : in std_logic;
S_AXIS_TLAST : in std_logic;
S_AXIS_TSTRB : in std_logic_vector(3 downto 0)
);
end system_axi_dispctrl_0_wrapper;
architecture STRUCTURE of system_axi_dispctrl_0_wrapper is
component axi_dispctrl is
generic (
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_MIN_SIZE : std_logic_vector;
C_USE_WSTRB : INTEGER;
C_DPHASE_TIMEOUT : INTEGER;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_FAMILY : STRING;
C_NUM_REG : INTEGER;
C_NUM_MEM : INTEGER;
C_SLV_AWIDTH : INTEGER;
C_SLV_DWIDTH : INTEGER;
C_USE_BUFR_DIV5 : INTEGER;
C_RED_WIDTH : INTEGER;
C_GREEN_WIDTH : INTEGER;
C_BLUE_WIDTH : INTEGER;
C_S_AXIS_MM2S_TDATA_WIDTH : INTEGER
);
port (
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
VDMA_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
FSYNC_O : out std_logic;
HSYNC_O : out std_logic;
VSYNC_O : out std_logic;
DE_O : out std_logic;
RED_O : out std_logic_vector((C_RED_WIDTH-1) downto 0);
GREEN_O : out std_logic_vector((C_GREEN_WIDTH-1) downto 0);
BLUE_O : out std_logic_vector((C_BLUE_WIDTH-1) downto 0);
ENABLE_O : out std_logic;
DEBUG_O : out std_logic_vector(31 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_WSTRB : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in std_logic_vector((C_S_AXIS_MM2S_TDATA_WIDTH-1) downto 0);
S_AXIS_TVALID : in std_logic;
S_AXIS_TLAST : in std_logic;
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0)
);
end component;
begin
axi_dispctrl_0 : axi_dispctrl
generic map (
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 32,
C_S_AXI_MIN_SIZE => X"000001ff",
C_USE_WSTRB => 0,
C_DPHASE_TIMEOUT => 8,
C_BASEADDR => X"75c00000",
C_HIGHADDR => X"75c0ffff",
C_FAMILY => "zynq",
C_NUM_REG => 1,
C_NUM_MEM => 1,
C_SLV_AWIDTH => 32,
C_SLV_DWIDTH => 32,
C_USE_BUFR_DIV5 => 1,
C_RED_WIDTH => 8,
C_GREEN_WIDTH => 8,
C_BLUE_WIDTH => 8,
C_S_AXIS_MM2S_TDATA_WIDTH => 32
)
port map (
REF_CLK_I => REF_CLK_I,
PXL_CLK_O => PXL_CLK_O,
VDMA_CLK_O => VDMA_CLK_O,
PXL_CLK_5X_O => PXL_CLK_5X_O,
LOCKED_O => LOCKED_O,
FSYNC_O => FSYNC_O,
HSYNC_O => HSYNC_O,
VSYNC_O => VSYNC_O,
DE_O => DE_O,
RED_O => RED_O,
GREEN_O => GREEN_O,
BLUE_O => BLUE_O,
ENABLE_O => ENABLE_O,
DEBUG_O => DEBUG_O,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_ACLK => S_AXIS_ACLK,
S_AXIS_ARESETN => S_AXIS_ARESETN,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TSTRB => S_AXIS_TSTRB
);
end architecture STRUCTURE;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity tb_bit_to_analog is
end tb_bit_to_analog;
architecture TB_bit2analog of tb_bit_to_analog is
-- Component declarations
-- Signal declarations
terminal ana_out : electrical;
signal ina : bit;
signal ina_tmp : std_logic;
begin
-- Signal assignments
ina <= To_bit(ina_tmp); -- convert std_logic to bit
-- Component instances
d2a1 : entity work.bit_to_analog(ideal)
port map(
d => ina, -- bit type pin
a => ana_out
);
clk1 : entity work.clock_duty(ideal)
generic map(
off_time => 2 ms,
on_time => 1 ms
)
port map(
CLOCK_OUT => ina_tmp -- std_logic type pin
);
R1 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => ana_out,
p2 => electrical_ref
);
end TB_bit2analog;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity tb_bit_to_analog is
end tb_bit_to_analog;
architecture TB_bit2analog of tb_bit_to_analog is
-- Component declarations
-- Signal declarations
terminal ana_out : electrical;
signal ina : bit;
signal ina_tmp : std_logic;
begin
-- Signal assignments
ina <= To_bit(ina_tmp); -- convert std_logic to bit
-- Component instances
d2a1 : entity work.bit_to_analog(ideal)
port map(
d => ina, -- bit type pin
a => ana_out
);
clk1 : entity work.clock_duty(ideal)
generic map(
off_time => 2 ms,
on_time => 1 ms
)
port map(
CLOCK_OUT => ina_tmp -- std_logic type pin
);
R1 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => ana_out,
p2 => electrical_ref
);
end TB_bit2analog;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity tb_bit_to_analog is
end tb_bit_to_analog;
architecture TB_bit2analog of tb_bit_to_analog is
-- Component declarations
-- Signal declarations
terminal ana_out : electrical;
signal ina : bit;
signal ina_tmp : std_logic;
begin
-- Signal assignments
ina <= To_bit(ina_tmp); -- convert std_logic to bit
-- Component instances
d2a1 : entity work.bit_to_analog(ideal)
port map(
d => ina, -- bit type pin
a => ana_out
);
clk1 : entity work.clock_duty(ideal)
generic map(
off_time => 2 ms,
on_time => 1 ms
)
port map(
CLOCK_OUT => ina_tmp -- std_logic type pin
);
R1 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => ana_out,
p2 => electrical_ref
);
end TB_bit2analog;
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.