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package body RTL is
attribute mark_debug of wr_en : signal is "true";
attribute mark_debug of almost_empty : signal is "true";
attribute mark_debug of full : signal is "true";
procedure rst_procedure is
attribute mark_debug of wr_en : signal is "true";
attribute mark_debug of almost_empty : signal is "true";
attribute mark_debug of full : signal is "true";
begin
end procedure;
end package body RTL;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity RAMF is
generic (
RAMD_W : INTEGER := 12;
RAMA_W : INTEGER := 6
);
port (
d : in STD_LOGIC_VECTOR(RAMD_W-1 downto 0);
waddr : in STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
raddr : in STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
we : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(RAMD_W-1 downto 0)
);
end RAMF;
architecture RTL of RAMF is
type mem_type is array ((2**RAMA_W)-1 downto 0) of
STD_LOGIC_VECTOR(RAMD_W-1 downto 0);
signal mem : mem_type;
signal read_addr : STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
begin
-------------------------------------------------------------------------------
q_sg:
-------------------------------------------------------------------------------
q <= mem(TO_INTEGER(UNSIGNED(read_addr)));
-------------------------------------------------------------------------------
read_proc: -- register read address
-------------------------------------------------------------------------------
process (clk)
begin
if clk = '1' and clk'event then
read_addr <= raddr;
end if;
end process;
-------------------------------------------------------------------------------
write_proc: --write access
-------------------------------------------------------------------------------
process (clk) begin
if clk = '1' and clk'event then
if we = '1' then
mem(TO_INTEGER(UNSIGNED(waddr))) <= d;
end if;
end if;
end process;
end RTL;
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library WORK;
entity FIFO is
generic (
DATA_WIDTH : INTEGER := 12;
ADDR_WIDTH : INTEGER := 2
);
port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
rinc : in STD_LOGIC;
winc : in STD_LOGIC;
datai : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
datao : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
fullo : out STD_LOGIC;
emptyo : out STD_LOGIC;
count : out STD_LOGIC_VECTOR (ADDR_WIDTH downto 0)
);
end FIFO;
architecture RTL of FIFO is
signal raddr_reg : STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
signal waddr_reg : STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
signal count_reg : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0);
signal rd_en_reg : STD_LOGIC;
signal wr_en_reg : STD_LOGIC;
signal empty_reg : STD_LOGIC;
signal full_reg : STD_LOGIC;
signal ramq : STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
signal ramd : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
signal ramwaddr : STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
signal ramenw : STD_LOGIC;
signal ramraddr : STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
signal ramenr : STD_LOGIC;
constant ZEROS_C : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '0');
constant ONES_C : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
component RAMF
generic (
RAMD_W : INTEGER := 12;
RAMA_W : INTEGER := 6
);
port (
d : in STD_LOGIC_VECTOR(RAMD_W-1 downto 0);
waddr : in STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
raddr : in STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
we : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(RAMD_W-1 downto 0)
);
end component;
begin
U_RAMF : RAMF
generic map (
RAMD_W => DATA_WIDTH,
RAMA_W => ADDR_WIDTH
)
port map (
d => ramd,
waddr => ramwaddr,
raddr => ramraddr,
we => ramenw,
clk => clk,
q => ramq
);
ramd <= datai;
ramwaddr <= waddr_reg;
ramenw <= wr_en_reg;
ramraddr <= raddr_reg;
ramenr <= '1';
datao <= ramq;
emptyo <= empty_reg;
fullo <= full_reg;
rd_en_reg <= (rinc and not empty_reg);
wr_en_reg <= (winc and not full_reg);
count <= count_reg;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
empty_reg <= '1';
else
if count_reg = ZEROS_C or
(count_reg = 1 and rd_en_reg = '1' and wr_en_reg = '0') then
empty_reg <= '1';
else
empty_reg <= '0';
end if;
end if;
end if;
end process;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
full_reg <= '0';
else
if count_reg = 2**ADDR_WIDTH or
(count_reg = 2**ADDR_WIDTH-1 and wr_en_reg = '1' and rd_en_reg = '0') then
full_reg <= '1';
else
full_reg <= '0';
end if;
end if;
end if;
end process;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
raddr_reg <= (others => '0');
else
if rd_en_reg = '1' then
raddr_reg <= raddr_reg + '1';
end if;
end if;
end if;
end process;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
waddr_reg <= (others => '0');
else
if wr_en_reg = '1' then
waddr_reg <= waddr_reg + '1';
end if;
end if;
end if;
end process;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
count_reg <= (others => '0');
else
if (rd_en_reg = '1' and wr_en_reg = '0') or (rd_en_reg = '0' and wr_en_reg = '1') then
if rd_en_reg = '1' then
count_reg <= count_reg - '1';
else
count_reg <= count_reg + '1';
end if;
end if;
end if;
end if;
end process;
end RTL;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity RAMF is
generic (
RAMD_W : INTEGER := 12;
RAMA_W : INTEGER := 6
);
port (
d : in STD_LOGIC_VECTOR(RAMD_W-1 downto 0);
waddr : in STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
raddr : in STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
we : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(RAMD_W-1 downto 0)
);
end RAMF;
architecture RTL of RAMF is
type mem_type is array ((2**RAMA_W)-1 downto 0) of
STD_LOGIC_VECTOR(RAMD_W-1 downto 0);
signal mem : mem_type;
signal read_addr : STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
begin
-------------------------------------------------------------------------------
q_sg:
-------------------------------------------------------------------------------
q <= mem(TO_INTEGER(UNSIGNED(read_addr)));
-------------------------------------------------------------------------------
read_proc: -- register read address
-------------------------------------------------------------------------------
process (clk)
begin
if clk = '1' and clk'event then
read_addr <= raddr;
end if;
end process;
-------------------------------------------------------------------------------
write_proc: --write access
-------------------------------------------------------------------------------
process (clk) begin
if clk = '1' and clk'event then
if we = '1' then
mem(TO_INTEGER(UNSIGNED(waddr))) <= d;
end if;
end if;
end process;
end RTL;
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library WORK;
entity FIFO is
generic (
DATA_WIDTH : INTEGER := 12;
ADDR_WIDTH : INTEGER := 2
);
port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
rinc : in STD_LOGIC;
winc : in STD_LOGIC;
datai : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
datao : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
fullo : out STD_LOGIC;
emptyo : out STD_LOGIC;
count : out STD_LOGIC_VECTOR (ADDR_WIDTH downto 0)
);
end FIFO;
architecture RTL of FIFO is
signal raddr_reg : STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
signal waddr_reg : STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
signal count_reg : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0);
signal rd_en_reg : STD_LOGIC;
signal wr_en_reg : STD_LOGIC;
signal empty_reg : STD_LOGIC;
signal full_reg : STD_LOGIC;
signal ramq : STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
signal ramd : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
signal ramwaddr : STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
signal ramenw : STD_LOGIC;
signal ramraddr : STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
signal ramenr : STD_LOGIC;
constant ZEROS_C : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '0');
constant ONES_C : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
component RAMF
generic (
RAMD_W : INTEGER := 12;
RAMA_W : INTEGER := 6
);
port (
d : in STD_LOGIC_VECTOR(RAMD_W-1 downto 0);
waddr : in STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
raddr : in STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
we : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(RAMD_W-1 downto 0)
);
end component;
begin
U_RAMF : RAMF
generic map (
RAMD_W => DATA_WIDTH,
RAMA_W => ADDR_WIDTH
)
port map (
d => ramd,
waddr => ramwaddr,
raddr => ramraddr,
we => ramenw,
clk => clk,
q => ramq
);
ramd <= datai;
ramwaddr <= waddr_reg;
ramenw <= wr_en_reg;
ramraddr <= raddr_reg;
ramenr <= '1';
datao <= ramq;
emptyo <= empty_reg;
fullo <= full_reg;
rd_en_reg <= (rinc and not empty_reg);
wr_en_reg <= (winc and not full_reg);
count <= count_reg;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
empty_reg <= '1';
else
if count_reg = ZEROS_C or
(count_reg = 1 and rd_en_reg = '1' and wr_en_reg = '0') then
empty_reg <= '1';
else
empty_reg <= '0';
end if;
end if;
end if;
end process;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
full_reg <= '0';
else
if count_reg = 2**ADDR_WIDTH or
(count_reg = 2**ADDR_WIDTH-1 and wr_en_reg = '1' and rd_en_reg = '0') then
full_reg <= '1';
else
full_reg <= '0';
end if;
end if;
end if;
end process;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
raddr_reg <= (others => '0');
else
if rd_en_reg = '1' then
raddr_reg <= raddr_reg + '1';
end if;
end if;
end if;
end process;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
waddr_reg <= (others => '0');
else
if wr_en_reg = '1' then
waddr_reg <= waddr_reg + '1';
end if;
end if;
end if;
end process;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
count_reg <= (others => '0');
else
if (rd_en_reg = '1' and wr_en_reg = '0') or (rd_en_reg = '0' and wr_en_reg = '1') then
if rd_en_reg = '1' then
count_reg <= count_reg - '1';
else
count_reg <= count_reg + '1';
end if;
end if;
end if;
end if;
end process;
end RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1886.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01886ent IS
END c07s01b00x00p08n01i01886ent;
ARCHITECTURE c07s01b00x00p08n01i01886arch OF c07s01b00x00p08n01i01886ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal obus : cmd_bus(small_int);
BEGIN
TESTING : PROCESS
BEGIN
lop : for i in small_int loop
obus <= (0 => lop, others => 5) after 5 ns; -- loop label illegal here
end loop;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01886 - Loop labels are not permitted as primaries in a element association expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01886arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1886.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01886ent IS
END c07s01b00x00p08n01i01886ent;
ARCHITECTURE c07s01b00x00p08n01i01886arch OF c07s01b00x00p08n01i01886ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal obus : cmd_bus(small_int);
BEGIN
TESTING : PROCESS
BEGIN
lop : for i in small_int loop
obus <= (0 => lop, others => 5) after 5 ns; -- loop label illegal here
end loop;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01886 - Loop labels are not permitted as primaries in a element association expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01886arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1886.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01886ent IS
END c07s01b00x00p08n01i01886ent;
ARCHITECTURE c07s01b00x00p08n01i01886arch OF c07s01b00x00p08n01i01886ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal obus : cmd_bus(small_int);
BEGIN
TESTING : PROCESS
BEGIN
lop : for i in small_int loop
obus <= (0 => lop, others => 5) after 5 ns; -- loop label illegal here
end loop;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01886 - Loop labels are not permitted as primaries in a element association expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01886arch;
|
-- lab5_new Testbench. A test bench is a file that describes the commands that should
-- be used when simulating the design. The test bench does not describe any hardware,
-- but is only used during simulation. In Lab 2, you can use this test bench directly,
-- and do *not need to modify it* (in later labs, you will have to write test benches).
-- Therefore, you do not need to worry about the details in this file (but you might find
-- it interesting to look through anyway).
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
-- Testbenches don't have input and output ports. We'll talk about that in class
-- later in the course.
entity lab5_new_tb is
end lab5_new_tb;
architecture stimulus of lab5_new_tb is
--Declare the device under test (DUT)
component lab5_new is
port(CLOCK_50 : in std_logic;
KEY : in std_logic_vector(3 downto 0);
SW : in std_logic_vector(17 downto 0);
--LEDG : out std_logic_vector(7 downto 0);
colour_out : out std_logic_vector(2 downto 0);
x_out : out std_logic_vector(7 downto 0);
y_out : out std_logic_vector(6 downto 0);
plot_out : out std_logic);
end component;
--Signals that connect to the ports of the DUT. The inputs would be
--driven inside the testbench according to different test cases, and
--the output would be monitored in the waveform viewer.
--Input/Output mapping signals
signal clk: std_logic := '0';
signal key : std_logic_vector(3 downto 0);
signal sw : std_logic_vector(17 downto 0);
-- signal led_out : std_logic_vector(7 downto 0);
signal colour_out : std_logic_vector(2 downto 0);
signal x_out : std_logic_vector(7 downto 0);
signal y_out : std_logic_vector(6 downto 0);
signal plot_out : std_logic;
--Component Signals
--KEY Signals
signal resetb : std_logic := '1';
--SW Signals
signal p1_goalie : std_logic := '0';
signal p1_fwd : std_logic := '0';
signal p2_goalie : std_logic := '0';
signal p2_fwd : std_logic := '0';
--Records/Arrays for testing
--type record_name is
-- output_record
-- colour : std_logic_vector(2 downto 0);
-- x_out : std_logic_vector(7 downto 0);
-- y_out : std_logic_vector(6 downto 0);
-- plot : std_logic;
-- end record;
--type record_name is
-- input_record
-- key : in std_logic_vector(3 downto 0);
-- sw : in std_logic_vector(17 downto 0);
-- end record;
--type input_record_array is array (0 to 10) of input_record;
--type output_record_array is array (0 to 10) of output_record;
--signal s_input_sequence : input_record_array;
--signal s_output_sequence : output_record_array;
--Declare a constant of type 'time'. This would be used to cause delay
-- between clock edges
--Period of 50MHz Clock
--constant HALF_PERIOD : Time := 10ns;
constant HALF_PERIOD : Time := 1ps;
--Colour constants
constant WALL_COLOUR : std_logic_vector(2 downto 0) := "111";
constant BACKGROUND_COLOUR : std_logic_vector(2 downto 0) := "000";
constant P1_COLOUR : std_logic_vector(2 downto 0) := "001";
constant P2_COLOUR : std_logic_vector(2 downto 0) := "100";
--Position constants
constant INIT_X_PUCK : unsigned(7 downto 0) := "01010000"; --80
constant INIT_Y_PUCK : unsigned(6 downto 0) := "0111100"; --60
--constant INIT_X_DRAW : std_logic_vector(7 downto 0) := "00000101"; --5
--constant INIT_Y_DRAW : std_logic_vector(7 downto 0) := "0000101"; --5
begin
key <= resetb & "000";
sw <= p2_fwd & p2_goalie & "00000000000000" & p2_fwd & p2_goalie;
DUT: lab5_new
port map (
CLOCK_50 => clk,
key => key,
sw => sw,
-- ledg => out_led,
colour_out => colour_out,
x_out => x_out,
y_out => y_out,
plot_out => plot_out
);
-- CLOCK STIMULI
clock_process: process is
begin
CLK <= not clk after HALF_PERIOD;
wait for 2*HALF_PERIOD;
end process;
test: process is
variable t1g, t1f, t2g, t2f: unsigned(6 downto 0);
variable puckx : unsigned(7 downto 0) := INIT_X_PUCK; -- 80
variable pucky : unsigned(6 downto 0) := INIT_Y_PUCK; -- 60
variable velx : std_logic := '0';
variable vely : std_logic := '0';
variable tmp_i_y : integer := 0;
variable tmp_i_x : integer := 0;
-- procedure test_sequence(
-- input_sequence: input_record_array;
-- expected_output_sequence: output_record_array
-- ) is begin
-- for i in input_sequence'range loop
-- x_out <= input_sequence(i);
-- wait until rising_edge(clk);
-- assert colour_out = expected_output_sequence(i).colour;
-- --assert x_out = expected_output_sequence(i).x_out;
-- --assert y_out = expected_output_sequence(i).y_out;
-- assert plot_out = expected_output_sequence(i).plot;
-- end loop;
-- end;
procedure clear_screen is
begin
wait until rising_edge(clk);
assert x_out = "00000000" report "x not initialized to 0" severity failure;
assert y_out = "0000000" report "y not initialized to 0run" severity failure;
assert plot_out = '0' report "plot != 0 " severity failure;
assert colour_out = BACKGROUND_COLOUR report "color not 000 " severity failure;
wait until rising_edge(clk);
wait until rising_edge(clk);
for i_y in 0 to 119 loop
for i_x in 1 to 160 loop
tmp_i_x := i_x;
tmp_i_y := i_y;
--report "plot_out is "& std_logic'image( plot_out );
assert plot_out = '1' report "plot not 1 CLRSCRN. plot_out:"& std_logic'image( plot_out) &" i_x:"&integer'image( i_x)& " i_y:"& integer'image( i_y) severity failure;
-- assert x_out = std_logic_vector(i_x);
-- assert y_out = std_logic_vector(i_y);
assert colour_out = BACKGROUND_COLOUR report "color not 000 CLRSCRN" severity failure;
wait until rising_edge(clk);
end loop;
end loop;
--report "END CLR SCRN\n";
--report "plot_out:"& std_logic'image( plot_out) &" i_x:"&integer'image( tmp_i_x)& " i_y:"& integer'image( tmp_i_y);
--report "colour_out:"& integer'image( conv_integer(colour_out) ) &" x_out:"&integer'image( conv_integer(x_out) )& " y_out:"& integer'image( conv_integer(y_out) );
end clear_screen;
procedure draw_walls is
begin
--wait until rising_edge(clk);
--Check we are starting in correct state
--assert plot_out = '1' ;
assert colour_out = WALL_COLOUR report "colour_out not WALL_COLOUR (111)" severity failure; -- make sure colour of walls is white
-- make sure we start at (5,5)
--report "x_out is "& integer'image( conv_integer(x_out) );
assert x_out = "00000101" report "x_out not 5" severity failure;
assert y_out = "0000101" report "y_out not 5" severity failure;
wait until rising_edge(clk);
--Draw top wall
for i in 6 to 154 loop
--report "plot_out is "& std_logic'image( plot_out );
assert plot_out = '1' report "plot not 1 CLRSCRN" severity failure;
-- assert x_out = std_logic_vector(i);
-- assert y_out = "0000101";
assert colour_out = WALL_COLOUR report "colour_out not WALL_COLOUR (111)" severity failure;
wait until rising_edge(clk);
end loop;
--report "colour_out:"& integer'image( conv_integer(colour_out) ) &" x_out:"&integer'image( conv_integer(x_out) )& " y_out:"& integer'image( conv_integer(y_out) );
-- make sure we start at (5,155)
assert x_out = "00000101" report "x_out not 5" severity failure;
assert y_out = "1110011" report "x_out not 115" severity failure;
wait until rising_edge(clk);
--report "colour_out:"& integer'image( conv_integer(colour_out) ) &" x_out:"&integer'image( conv_integer(x_out) )& " y_out:"& integer'image( conv_integer(y_out) );
--Draw bottom wall
for i in 6 to 154 loop
assert plot_out = '1' report "plot not 1 CLRSCRN" severity failure;
assert x_out = conv_std_logic_vector(i,x_out'length) report "x_out not i. x_out:"&integer'image(conv_integer(x_out))&" i:"&integer'image(i) severity failure;
assert y_out = "1110011" report "x_out not 115" severity failure;
assert colour_out = WALL_COLOUR report "colour_out not WALL_COLOUR (111)" severity failure;
wait until rising_edge(clk);
end loop;
end draw_walls;
procedure draw_paddles is
begin
--STEP #1
--test s1g state (DRAW PLYR1 GOALIE)
--Start drawing from (5,6)
assert x_out = "00000101" report "x_out not 5" severity failure; -- 5
assert y_out = "0000110" report "x_out not 5" severity failure; -- 6
assert colour_out = BACKGROUND_COLOUR report "colour_out not BACKGROUND_COLOUR (000)" severity failure;
assert plot_out = '1' report "plot not 1 CLRSCRN" severity failure;
wait until rising_edge(clk);
--run s1g state (DRAW PLYR2 GOALIE)
for i in 7 to 115 loop
assert plot_out = '1' report "plot not 1 CLRSCRN" severity failure;
if((i >= 54) and (i <= 66)) then
assert colour_out = P1_COLOUR report "colour_out not P1_COLOUR" severity failure;
elsif(i = 115) then
assert colour_out = WALL_COLOUR report "colour_out not WALL_COLOUR (111)" severity failure;
else
assert colour_out = BACKGROUND_COLOUR report "colour_out not BACKGROUND_COLOUR (000)" severity failure;
end if;
wait until rising_edge(clk);
end loop;
t1g := t1g + 1;
--STEP #2
--test s1f state (DRAW PLYR1 FWD)
assert x_out = "01000011"; -- 67
assert y_out = "0000110" report "x_out not 5" severity failure; -- 6
assert colour_out = BACKGROUND_COLOUR report "BACKGROUND_COLOUR" severity failure;
assert plot_out = '1' report "plot not 1 CLRSCRN" severity failure;
wait until rising_edge(clk);
--run s1f state (DRAW PLYR1 FWD)
for i in 7 to 115 loop
assert plot_out = '1' report "plot not 1 CLRSCRN" severity failure;
if(i >= 54 and i <= 66) then
assert colour_out = P1_COLOUR report "colour_out not P2_COLOUR" severity failure;
elsif(i = 115) then
assert colour_out = WALL_COLOUR report "colour_out not WALL_COLOUR (111)" severity failure;
else
assert colour_out = BACKGROUND_COLOUR report "colour_out not BACKGROUND_COLOUR (000)" severity failure;
end if;
wait until rising_edge(clk);
end loop;
t1f := t1f + 1;
--STEP #3
--test s2g state (DRAW PLYR2 GOALIE)
assert x_out = "10011010"; -- 154
assert y_out = "0000110" report "x_out not 5" severity failure; -- 6
assert colour_out = BACKGROUND_COLOUR report "colour_out not BACKGROUND_COLOUR (000)" severity failure;
assert plot_out = '1' report "plot not 1 CLRSCRN" severity failure;
wait until rising_edge(clk);
--run s2g state (DRAW PLYR2 GOALIE)
for i in 7 to 115 loop
assert plot_out = '1' report "plot not 1 CLRSCRN" severity failure;
if(i >= 54 and i <= 66) then
assert colour_out = P2_COLOUR report "colour_out not P2_COLOUR" severity failure;
elsif(i = 115) then
assert colour_out = WALL_COLOUR report "colour_out not WALL_COLOUR (111)" severity failure;
else
assert colour_out = BACKGROUND_COLOUR report "colour_out not BACKGROUND_COLOUR (000)" severity failure;
end if;
wait until rising_edge(clk);
end loop;
t2g := t2g + 1;
--STEP #4
--test s2f state (DRAW PLYR2 FWD)
assert x_out = "01011101"; -- 93
assert y_out = "0000110" report "x_out not 5" severity failure; -- 6
assert colour_out = BACKGROUND_COLOUR report "colour_out not BACKGROUND_COLOUR (000)" severity failure;
assert plot_out = '1' report "plot not 1 CLRSCRN" severity failure;
wait until rising_edge(clk);
--run s2g state (DRAW PLYR2 GOALIE)
for i in 7 to 115 loop
assert plot_out = '1' report "plot not 1 CLRSCRN" severity failure;
if(i >= 54 and i <= 66) then
assert colour_out = P2_COLOUR report "colour_out not P2_COLOUR" severity failure;
elsif(i = 115) then
assert colour_out = WALL_COLOUR report "colour_out not WALL_COLOUR (111)" severity failure;
else
assert colour_out = BACKGROUND_COLOUR report "colour_out not BACKGROUND_COLOUR (000)" severity failure;
end if;
wait until rising_edge(clk);
end loop;
t2f := t2f + 1;
--STEP #5
--test sgp1 state (INIT PUCK)
assert plot_out = '1' report "plot not 1 CLRSCRN" severity failure;
assert colour_out = BACKGROUND_COLOUR report "colour not BACKGROUND_COLOUR" severity failure;
assert x_out = std_logic_vector(INIT_X_PUCK) report "x_out not INIT_X_PUCK (80)" severity failure; -- 80
assert y_out = std_logic_vector(INIT_Y_PUCK) report"y_out not INIT_Y_PUCK (60)" severity failure; -- 60
wait until rising_edge(clk);
end draw_paddles;
begin
--Test #1: Move All Paddles DOWN
--Initialize inputs
p2_fwd <= '0';
p2_goalie <= '0';
p1_fwd <= '0';
p2_goalie <= '0';
--Initialization Procedure
t1g := "0110110";
t1f := "0110110";
t2g := "0110110";
t2f := "0110110";
velx := p2_fwd xor p1_fwd;
velx := p2_goalie xor p1_goalie;
--Press Reset
resetb <= '0';
wait until rising_edge(clk);
--Clear Screen Initial State
resetb <= '1';
clear_screen;
draw_walls;
draw_paddles;
--wait until rising_edge(clk);
--Test 1 | STEP #1
--test sgp2 state (PUCK COLLISION and PUCK DRAW)
-- PUCK will move on UPWARD-LEFT trajectory till (26, 6)
for i in 0 to 53 loop
--Draw ball
assert plot_out = '1' report "plot not 1 CLRSCRN" severity failure;
--report "colour_out:"& integer'image( conv_integer(colour_out) ) &" x_out:"&integer'image( conv_integer(x_out) )& " y_out:"& integer'image( conv_integer(y_out) );
--report " i:"&integer'image( i );
assert colour_out = WALL_COLOUR report "colour_out not WALL_COLOUR (111)" severity failure;
puckx := puckx - 1;
pucky := pucky - 1;
assert x_out = std_logic_vector(puckx);
assert y_out = std_logic_vector(pucky);
wait until rising_edge(clk);
--Wait until paddle have been updated
assert plot_out = '0' report "plot!=1 " severity failure;
wait until plot_out = '1';
--Wait until paddles have been fully drawn
for b in 0 to 441 loop
assert plot_out = '1' report "plot != 1 " severity failure;
wait until rising_edge(clk);
end loop;
end loop;
-- PUCK hits TOP wall and bounces off DOWNWARD-LEFT after (26, 6)
assert y_out = "0000101" report "ynot != 5" severity failure; -- 5
assert x_out = "00011011" report "xnot != 25" severity failure; -- 25
puckx := puckx - 1;
pucky := pucky + 1;
vely := '1';
wait until rising_edge(clk);
-- PUCK will move on a DOWNWARD-LEFT trajectory till (4, 28)
for i in 0 to 21 loop
assert colour_out = WALL_COLOUR report "colour_out not WALL_COLOUR (111)" severity failure;
puckx := puckx - 1;
pucky := pucky + 1;
wait until rising_edge(clk);
--Wait until paddle have been updated
assert plot_out = '0' report "plot != 0" severity failure;
wait until plot_out = '1';
--Wait until paddles have been fully drawn
for b in 0 to 440 loop
assert plot_out = '1' report "plot != 1" severity failure;
wait until rising_edge(clk);
end loop;
end loop;
-- PUCK hit RIGHT WALL and bounces off DOWNWARD-RIGHT after (4, 28)
-- Player2 scores a point and game resets
assert y_out = "0000101" report "y_out != 5" severity failure; -- 5
assert x_out = "00011011" report "x_out != 25" severity failure; -- 25
puckx := puckx + 1;
pucky := pucky + 1;
vely := '1';
wait until rising_edge(clk);
-- PUCK will be reset to (80,60)
clear_screen;
draw_walls;
draw_paddles;
assert x_out = std_logic_vector(INIT_X_PUCK) report "x_out != 80" severity failure; -- 80
assert y_out = std_logic_vector(INIT_Y_PUCK) report "y_out != 60" severity failure; -- 60
wait until rising_edge(clk);
report "FINISHED TEST#1";
std.env.finish;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1703.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p05n01i01703ent IS
END c09s02b00x00p05n01i01703ent;
ARCHITECTURE c09s02b00x00p05n01i01703arch OF c09s02b00x00p05n01i01703ent IS
signal s : boolean := false;
BEGIN
TESTING: PROCESS
type result_type is (fail, pass);
variable result : result_type := fail;
variable i, j : integer;
variable k : integer := 0;
BEGIN
--
-- Test all sequential statements in this process
--
s <= true; -- signal assignment
j := 1; -- variable assignment
i := 0;
L1: while ( i < 10 ) loop -- conditional loop
if i > 2 then
exit;
end if;
case i is
when 0 =>
L2: for j in 1 to 3 loop
case j is
when 3 => -- should never execute because of
i := i + 1; -- alternative 2
k := 1;
exit;
assert false
report "exit in loop 2 case failed."
severity note;
when 2 =>
i := i + 1;
next L1;
k := 1;
assert false -- should never execute
report "next in loop 2 case failed."
severity note;
when 1 =>
assert false
report "first iteration of loop 2."
severity note ;
next; -- applies to loop L2
when others =>
--
-- This should never be executed but is
-- required by the 1076-1987 spec. which
-- says the subtype of 'j' is the same as
-- the base type (integer) and not constrained
-- to the range "1 to 3".
--
k := 1;
assert false
report "Should never get here."
severity note ;
end case;
k := 1;
assert false -- should never execute
report "next in loop 2 failed."
severity note;
end loop L2;
when 2 =>
s <= false after 5 ns;
wait for 6 ns;
assert not s
report "wait statement in loop L1 failed."
severity note ;
i := i +1;
when 1 =>
null;
assert false
report "null statement and next statement worked."
severity note ;
i := i +1;
when others =>
k := 1;
assert false
report "exit in if statement in loop L1 failed."
severity note ;
exit;
end case;
end loop L1;
wait for 50 ns;
assert NOT(s=false and k = 0 and j=1)
report "***PASSED TEST: c09s02b00x00p05n01i01703"
severity NOTE;
assert (s=false and k = 0 and j=1)
report "***FAILED TEST: c09s02b00x00p05n01i01703 - Process statement execution failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s02b00x00p05n01i01703arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1703.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p05n01i01703ent IS
END c09s02b00x00p05n01i01703ent;
ARCHITECTURE c09s02b00x00p05n01i01703arch OF c09s02b00x00p05n01i01703ent IS
signal s : boolean := false;
BEGIN
TESTING: PROCESS
type result_type is (fail, pass);
variable result : result_type := fail;
variable i, j : integer;
variable k : integer := 0;
BEGIN
--
-- Test all sequential statements in this process
--
s <= true; -- signal assignment
j := 1; -- variable assignment
i := 0;
L1: while ( i < 10 ) loop -- conditional loop
if i > 2 then
exit;
end if;
case i is
when 0 =>
L2: for j in 1 to 3 loop
case j is
when 3 => -- should never execute because of
i := i + 1; -- alternative 2
k := 1;
exit;
assert false
report "exit in loop 2 case failed."
severity note;
when 2 =>
i := i + 1;
next L1;
k := 1;
assert false -- should never execute
report "next in loop 2 case failed."
severity note;
when 1 =>
assert false
report "first iteration of loop 2."
severity note ;
next; -- applies to loop L2
when others =>
--
-- This should never be executed but is
-- required by the 1076-1987 spec. which
-- says the subtype of 'j' is the same as
-- the base type (integer) and not constrained
-- to the range "1 to 3".
--
k := 1;
assert false
report "Should never get here."
severity note ;
end case;
k := 1;
assert false -- should never execute
report "next in loop 2 failed."
severity note;
end loop L2;
when 2 =>
s <= false after 5 ns;
wait for 6 ns;
assert not s
report "wait statement in loop L1 failed."
severity note ;
i := i +1;
when 1 =>
null;
assert false
report "null statement and next statement worked."
severity note ;
i := i +1;
when others =>
k := 1;
assert false
report "exit in if statement in loop L1 failed."
severity note ;
exit;
end case;
end loop L1;
wait for 50 ns;
assert NOT(s=false and k = 0 and j=1)
report "***PASSED TEST: c09s02b00x00p05n01i01703"
severity NOTE;
assert (s=false and k = 0 and j=1)
report "***FAILED TEST: c09s02b00x00p05n01i01703 - Process statement execution failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s02b00x00p05n01i01703arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1703.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p05n01i01703ent IS
END c09s02b00x00p05n01i01703ent;
ARCHITECTURE c09s02b00x00p05n01i01703arch OF c09s02b00x00p05n01i01703ent IS
signal s : boolean := false;
BEGIN
TESTING: PROCESS
type result_type is (fail, pass);
variable result : result_type := fail;
variable i, j : integer;
variable k : integer := 0;
BEGIN
--
-- Test all sequential statements in this process
--
s <= true; -- signal assignment
j := 1; -- variable assignment
i := 0;
L1: while ( i < 10 ) loop -- conditional loop
if i > 2 then
exit;
end if;
case i is
when 0 =>
L2: for j in 1 to 3 loop
case j is
when 3 => -- should never execute because of
i := i + 1; -- alternative 2
k := 1;
exit;
assert false
report "exit in loop 2 case failed."
severity note;
when 2 =>
i := i + 1;
next L1;
k := 1;
assert false -- should never execute
report "next in loop 2 case failed."
severity note;
when 1 =>
assert false
report "first iteration of loop 2."
severity note ;
next; -- applies to loop L2
when others =>
--
-- This should never be executed but is
-- required by the 1076-1987 spec. which
-- says the subtype of 'j' is the same as
-- the base type (integer) and not constrained
-- to the range "1 to 3".
--
k := 1;
assert false
report "Should never get here."
severity note ;
end case;
k := 1;
assert false -- should never execute
report "next in loop 2 failed."
severity note;
end loop L2;
when 2 =>
s <= false after 5 ns;
wait for 6 ns;
assert not s
report "wait statement in loop L1 failed."
severity note ;
i := i +1;
when 1 =>
null;
assert false
report "null statement and next statement worked."
severity note ;
i := i +1;
when others =>
k := 1;
assert false
report "exit in if statement in loop L1 failed."
severity note ;
exit;
end case;
end loop L1;
wait for 50 ns;
assert NOT(s=false and k = 0 and j=1)
report "***PASSED TEST: c09s02b00x00p05n01i01703"
severity NOTE;
assert (s=false and k = 0 and j=1)
report "***FAILED TEST: c09s02b00x00p05n01i01703 - Process statement execution failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s02b00x00p05n01i01703arch;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := artix7;
constant CFG_MEMTECH : integer := artix7;
constant CFG_PADTECH : integer := artix7;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex;
constant CFG_CLKMUL : integer := (1);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 0 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 0;
constant CFG_ITBSZ : integer := 0;
constant CFG_ATBSZ : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 0;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- SDRAM controller
constant CFG_SDCTRL : integer := 0;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 0;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- PCI interface
constant CFG_PCI : integer := 0;
constant CFG_PCIVID : integer := 16#0#;
constant CFG_PCIDID : integer := 16#0#;
constant CFG_PCIDEPTH : integer := 8;
constant CFG_PCI_MTF : integer := 1;
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 1;
constant CFG_GPT_WDOG : integer := 16#FFFF#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := artix7;
constant CFG_MEMTECH : integer := artix7;
constant CFG_PADTECH : integer := artix7;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex;
constant CFG_CLKMUL : integer := (1);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 0 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 0;
constant CFG_ITBSZ : integer := 0;
constant CFG_ATBSZ : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 0;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- SDRAM controller
constant CFG_SDCTRL : integer := 0;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 0;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- PCI interface
constant CFG_PCI : integer := 0;
constant CFG_PCIVID : integer := 16#0#;
constant CFG_PCIDID : integer := 16#0#;
constant CFG_PCIDEPTH : integer := 8;
constant CFG_PCI_MTF : integer := 1;
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 1;
constant CFG_GPT_WDOG : integer := 16#FFFF#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := artix7;
constant CFG_MEMTECH : integer := artix7;
constant CFG_PADTECH : integer := artix7;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex;
constant CFG_CLKMUL : integer := (1);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 0 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 0;
constant CFG_ITBSZ : integer := 0;
constant CFG_ATBSZ : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 0;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- SDRAM controller
constant CFG_SDCTRL : integer := 0;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 0;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- PCI interface
constant CFG_PCI : integer := 0;
constant CFG_PCIVID : integer := 16#0#;
constant CFG_PCIDID : integer := 16#0#;
constant CFG_PCIDEPTH : integer := 8;
constant CFG_PCI_MTF : integer := 1;
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 1;
constant CFG_GPT_WDOG : integer := 16#FFFF#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-- DDS Frequency Synthesizer
--
-- Output frequency is f=ftw_i/2^ftw_width*fclk
-- Output initial phase is phi=phase_i/2^phase_width*2*pi
--
-- Copyright (C) 2009 Martin Kumm
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
-- Package Definition
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
use work.sine_lut_pkg.all;
package dds_synthesizer_pkg is
component dds_synthesizer
generic(
ftw_width : integer
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
ftw_i : in std_logic_vector(ftw_width-1 downto 0);
phase_i : in std_logic_vector(PHASE_WIDTH-1 downto 0);
phase_o : out std_logic_vector(PHASE_WIDTH-1 downto 0);
ampl_o : out std_logic_vector(AMPL_WIDTH-1 downto 0)
);
end component;
end dds_synthesizer_pkg;
package body dds_synthesizer_pkg is
end dds_synthesizer_pkg;
-- Entity Definition
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
use work.sine_lut_pkg.all;
entity dds_synthesizer is
generic(
ftw_width : integer := 32
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
ftw_i : in std_logic_vector(ftw_width-1 downto 0);
phase_i : in std_logic_vector(PHASE_WIDTH-1 downto 0);
phase_o : out std_logic_vector(PHASE_WIDTH-1 downto 0);
ampl_o : out std_logic_vector(AMPL_WIDTH-1 downto 0)
);
end dds_synthesizer;
architecture dds_synthesizer_arch of dds_synthesizer is
signal ftw_accu : std_logic_vector(ftw_width-1 downto 0);
signal phase : std_logic_vector(PHASE_WIDTH-1 downto 0);
signal lut_in : std_logic_vector(PHASE_WIDTH-3 downto 0);
signal lut_out : std_logic_vector(AMPL_WIDTH-1 downto 0);
signal lut_out_delay : std_logic_vector(AMPL_WIDTH-1 downto 0);
signal lut_out_inv_delay : std_logic_vector(AMPL_WIDTH-1 downto 0);
signal quadrant_2_or_4 : std_logic;
signal quadrant_3_or_4 : std_logic;
signal quadrant_3_or_4_delay : std_logic;
signal quadrant_3_or_4_2delay : std_logic;
begin
phase_o <= phase;
quadrant_2_or_4 <= phase(PHASE_WIDTH-2);
quadrant_3_or_4 <= phase(PHASE_WIDTH-1);
lut_in <= phase(PHASE_WIDTH-3 downto 0) when quadrant_2_or_4 = '0' else conv_std_logic_vector(2**(PHASE_WIDTH-2)-conv_integer(phase(PHASE_WIDTH-3 downto 0)), PHASE_WIDTH-2);
ampl_o <= lut_out_delay when quadrant_3_or_4_2delay = '0' else lut_out_inv_delay;
process (clk_i, rst_i)
begin
if rst_i = '1' then
ftw_accu <= (others => '0');
phase <= (others => '0');
lut_out <= (others => '0');
lut_out_delay <= (others => '0');
lut_out_inv_delay <= (others => '0');
quadrant_3_or_4_delay <= '0';
quadrant_3_or_4_2delay <= '0';
elsif clk_i'event and clk_i = '1' then
ftw_accu <= ftw_accu + ftw_i;
phase <= ftw_accu(ftw_width-1 downto ftw_width-PHASE_WIDTH) + phase_i;
if quadrant_2_or_4 = '1' and phase(PHASE_WIDTH - 3 downto 0) = conv_std_logic_vector (0, PHASE_WIDTH - 2) then
lut_out <= conv_std_logic_vector(2**(AMPL_WIDTH - 1) - 1, AMPL_WIDTH);
else
lut_out <= sine_lut(conv_integer(lut_in));
end if;
quadrant_3_or_4_delay <= quadrant_3_or_4;
quadrant_3_or_4_2delay <= quadrant_3_or_4_delay;
lut_out_inv_delay <= conv_std_logic_vector(-1*conv_integer(lut_out), AMPL_WIDTH);
lut_out_delay <= lut_out;
end if;
end process;
end dds_synthesizer_arch;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_t
--
-- Generated
-- by: wig
-- on: Thu Oct 13 08:24:14 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../intra.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-e.vhd,v 1.2 2006/01/19 09:18:58 wig Exp $
-- $Date: 2006/01/19 09:18:58 $
-- $Log: ent_t-e.vhd,v $
-- Revision 1.2 2006/01/19 09:18:58 wig
-- Updated testcases, left 6 failing now (constant, bitsplice/X, ...)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.59 2005/10/06 11:21:44 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.37 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_t
--
entity ent_t is
-- Generics:
generic(
-- Generated Generics for Entity ent_t
generic_20 : integer := 32 -- Parameter for generic on topGeneric on top
-- End of Generated Generics for Entity ent_t
);
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_t
const_p_18 : in std_ulogic_vector(11 downto 0); -- Constant on top
sig_i_a : in std_ulogic;
sig_i_a2 : in std_ulogic;
sig_i_ae : in std_ulogic_vector(6 downto 0);
sig_o_a : out std_ulogic;
sig_o_a2 : out std_ulogic;
sig_o_ae : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ent_t
);
end ent_t;
--
-- End of Generated Entity ent_t
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:22:23 01/22/2014
-- Design Name:
-- Module Name: Multiply16Booth4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Multiply16Booth4 is
PORT (
a: IN STD_LOGIC_VECTOR(15 downto 0);
b: IN STD_LOGIC_VECTOR(15 downto 0);
o: OUT STD_LOGIC_VECTOR(15 downto 0));
end Multiply16Booth4;
architecture Behavioral of Multiply16Booth4 is
COMPONENT BoothPartProdGen is
PORT (
bin3: in STD_LOGIC_VECTOR(2 downto 0);
a: in STD_LOGIC_VECTOR(15 downto 0);
product: out STD_LOGIC_VECTOR(16 downto 0)
);
end COMPONENT;
COMPONENT BoothPartProdRed is
PORT(
prod0: in STD_LOGIC_VECTOR(19 downto 0);
prod1: in STD_LOGIC_VECTOR(20 downto 2);
prod2: in STD_LOGIC_VECTOR(22 downto 4);
prod3: in STD_LOGIC_VECTOR(24 downto 6);
prod4: in STD_LOGIC_VECTOR(26 downto 8);
prod5: in STD_LOGIC_VECTOR(28 downto 10);
prod6: in STD_LOGIC_VECTOR(30 downto 12);
prod7: in STD_LOGIC_VECTOR(31 downto 14);
result: out STD_LOGIC_VECTOR(31 downto 0));
end COMPONENT;
SIGNAL aTmp: STD_LOGIC_VECTOR(16 downto 0);
SIGNAL oTmp: STD_LOGIC_VECTOR(31 downto 0);
SIGNAL prod0: STD_LOGIC_VECTOR(19 downto 0);
SIGNAL prod1: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod2: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod3: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod4: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod5: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod6: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod7: STD_LOGIC_VECTOR(17 downto 0);
begin
aTmp <= a & '0';
prod0(19 downto 17) <= (not prod0(16)) & prod0(16) & prod0(16);
prod1(18 downto 17) <= '1' & (not prod1(16));
prod2(18 downto 17) <= '1' & (not prod2(16));
prod3(18 downto 17) <= '1' & (not prod3(16));
prod4(18 downto 17) <= '1' & (not prod4(16));
prod5(18 downto 17) <= '1' & (not prod5(16));
prod6(18 downto 17) <= '1' & (not prod6(16));
prod7(17) <= not prod7(16);
prodgen0: BoothPartProdGen PORT MAP (
bin3 => aTmp(2 downto 0),
a => b,
product => prod0(16 downto 0)
);
prodgen1: BoothPartProdGen PORT MAP (
bin3 => aTmp(4 downto 2),
a => b,
product => prod1(16 downto 0)
);
prodgen2: BoothPartProdGen PORT MAP (
bin3 => aTmp(6 downto 4),
a => b,
product => prod2(16 downto 0)
);
prodgen3: BoothPartProdGen PORT MAP (
bin3 => aTmp(8 downto 6),
a => b,
product => prod3(16 downto 0)
);
prodgen4: BoothPartProdGen PORT MAP (
bin3 => aTmp(10 downto 8),
a => b,
product => prod4(16 downto 0)
);
prodgen5: BoothPartProdGen PORT MAP (
bin3 => aTmp(12 downto 10),
a => b,
product => prod5(16 downto 0)
);
prodgen6: BoothPartProdGen PORT MAP (
bin3 => aTmp(14 downto 12),
a => b,
product => prod6(16 downto 0)
);
prodgen7: BoothPartProdGen PORT MAP (
bin3 => aTmp(16 downto 14),
a => b,
product => prod7(16 downto 0)
);
output: BoothPartProdRed PORT MAP (
prod0 => prod0,
prod1 => prod1,
prod2 => prod2,
prod3 => prod3,
prod4 => prod4,
prod5 => prod5,
prod6 => prod6,
prod7 => prod7,
result => oTmp
);
o <= oTmp(29 downto 14);
end Behavioral; |
-- Based on wb_fabric_pkg.vhd from Tomasz Wlostowski
-- Modified by Lucas Russo <[email protected]>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
package wb_stream_pkg is
-- Must be at least 2 bits wide
constant c_wbs_address_width : integer := 4;
-- Must be at least 16 bits wide. Not a good solution, as streaming interfaces
-- might different widths. FIX ME!
constant c_wbs_data_width : integer := 64;
subtype t_wbs_address is
std_logic_vector(c_wbs_address_width-1 downto 0);
subtype t_wbs_data is
std_logic_vector(c_wbs_data_width-1 downto 0);
subtype t_wbs_byte_select is
std_logic_vector((c_wbs_data_width/8)-1 downto 0);
constant c_WBS_DATA : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(0, c_wbs_address_width);
constant c_WBS_OOB : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(1, c_wbs_address_width);
constant c_WBS_STATUS : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(2, c_wbs_address_width);
constant c_WBS_USER : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(3, c_wbs_address_width);
--constant c_WRF_OOB_TYPE_RX : std_logic_vector(3 downto 0) := "0000";
--constant c_WRF_OOB_TYPE_TX : std_logic_vector(3 downto 0) := "0001";
type t_wbs_status_reg is record
is_hp : std_logic;
has_smac : std_logic;
has_crc : std_logic;
error : std_logic;
tag_me : std_logic;
match_class : std_logic_vector(7 downto 0);
end record;
type t_wbs_source_out is record
adr : t_wbs_address;
dat : t_wbs_data;
cyc : std_logic;
stb : std_logic;
we : std_logic;
sel : t_wbs_byte_select;
end record;
subtype t_wbs_sink_in is t_wbs_source_out;
type t_wbs_source_in is record
ack : std_logic;
stall : std_logic;
err : std_logic;
rty : std_logic;
end record;
subtype t_wbs_sink_out is t_wbs_source_in;
--type t_wrf_oob is record
-- valid: std_logic;
-- oob_type : std_logic_vector(3 downto 0);
-- ts_r : std_logic_vector(27 downto 0);
-- ts_f : std_logic_vector(3 downto 0);
-- frame_id : std_logic_vector(15 downto 0);
-- port_id : std_logic_vector(5 downto 0);
--end record;
type t_wbs_source_in_array is array (natural range <>) of t_wbs_source_in;
type t_wbs_source_out_array is array (natural range <>) of t_wbs_source_out;
subtype t_wbs_sink_in_array is t_wbs_source_out_array;
subtype t_wbs_sink_out_array is t_wbs_source_in_array;
function f_marshall_wbs_status (stat : t_wbs_status_reg) return std_logic_vector;
function f_unmarshall_wbs_status(stat : std_logic_vector) return t_wbs_status_reg;
function f_packet_num_bits(packet_size : natural) return natural;
constant cc_dummy_wbs_addr : std_logic_vector(c_wbs_address_width-1 downto 0):=
(others => 'X');
constant cc_dummy_wbs_dat : std_logic_vector(c_wbs_data_width-1 downto 0) :=
(others => 'X');
constant cc_dummy_wbs_sel : std_logic_vector(c_wbs_data_width/8-1 downto 0) :=
(others => 'X');
constant cc_dummy_src_in : t_wbs_source_in :=
('0', '0', '0', '0');
constant cc_dummy_snk_in : t_wbs_sink_in :=
(cc_dummy_wbs_addr, cc_dummy_wbs_dat, '0', '0', '0', cc_dummy_wbs_sel);
-- Components
component xwb_stream_source
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
src_i : in t_wbs_source_in;
src_o : out t_wbs_source_out;
-- Decoded & buffered logic
addr_i : in std_logic_vector(c_wbs_address_width-1 downto 0);
data_i : in std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_i : in std_logic;
sof_i : in std_logic;
eof_i : in std_logic;
error_i : in std_logic;
bytesel_i : in std_logic_vector((c_wbs_data_width/8)-1 downto 0);
dreq_o : out std_logic
);
end component;
component xwb_stream_sink
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
snk_i : in t_wbs_sink_in;
snk_o : out t_wbs_sink_out;
-- Decoded & buffered fabric
addr_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
data_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic_vector((c_wbs_data_width/8)-1 downto 0);
dreq_i : in std_logic
);
end component;
end wb_stream_pkg;
package body wb_stream_pkg is
function f_marshall_wbs_status(stat : t_wbs_status_reg)
return std_logic_vector
is
-- Wishbone bus data_width is at least 16 bits
variable tmp : std_logic_vector(c_wbs_data_width-1 downto 0);
begin
tmp(0) := stat.is_hp;
tmp(1) := stat.error;
tmp(2) := stat.has_smac;
tmp(3) := stat.has_crc;
tmp(15 downto 8) := stat.match_class;
return tmp;
end;
function f_unmarshall_wbs_status(stat : std_logic_vector)
return t_wbs_status_reg
is
variable tmp : t_wbs_status_reg;
begin
tmp.is_hp := stat(0);
tmp.error := stat(1);
tmp.has_smac := stat(2);
tmp.has_crc := stat(3);
tmp.match_class := stat(15 downto 8);
return tmp;
end f_unmarshall_wbs_status;
function f_packet_num_bits(packet_size : natural)
return natural
is
-- Slightly different behaviour than the one located at wishbone_pkg.vhd
function f_ceil_log2(x : natural) return natural is
begin
if x <= 2
then return 1;
else return f_ceil_log2((x+1)/2) +1;
end if;
end f_ceil_log2;
begin
return f_ceil_log2(packet_size);
end f_packet_num_bits;
end wb_stream_pkg;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/21/2015 12:33:51 PM
-- Design Name:
-- Module Name: Decoder2to4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Decoder2to4 is
Port
(
A : in BIT_VECTOR(1 downto 0); -- 2-Bit Memory Address (Input)
X : out BIT_VECTOR(3 downto 0) -- 4-Bit Address Lines (Output)
);
end Decoder2to4;
architecture Behavioral of Decoder2to4 is
begin
-- 00
X(0) <= not(A(0)) and not(A(1));
-- 01
X(1) <= A(0) and not (A(1));
-- 10
X(2) <= not(A(0)) and A(1);
-- 11
X(3) <= A(0) and A(1);
end Behavioral;
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple memory tester that can be
-- traced with chipscope.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_test_v5 is
port (
clock : in std_logic := '0';
reset : in std_logic := '0';
inhibit : out std_logic := '0';
req : out t_mem_req_32;
resp : in t_mem_resp_32;
run : out std_logic;
okay : out std_logic );
end entity;
architecture gideon of ext_mem_test_v5 is
signal req_i : t_mem_req_32;
signal expected_data : std_logic_vector(31 downto 0);
signal okay_i : std_logic;
signal run_i : std_logic;
function xor_reduce(s : std_logic_vector) return std_logic is
variable o : std_logic := '1';
begin
for i in s'range loop
o := o xor s(i);
end loop;
return o;
end function;
begin
req <= req_i;
okay <= okay_i;
run <= run_i;
p_test: process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
req_i <= c_mem_req_32_init;
req_i.read_writen <= '0'; -- write
req_i.request <= '1';
req_i.size <= '1';
req_i.data <= X"12345678";
req_i.byte_en <= "1000";
req_i.tag <= X"34";
okay_i <= '1';
run_i <= '0';
else
if resp.rack='1' then
if req_i.read_writen = '1' then
if signed(req_i.address) = -4 then
req_i.data <= not req_i.data;
run_i <= not run_i;
end if;
req_i.address <= req_i.address + 4;
else
expected_data <= req_i.data;
end if;
req_i.read_writen <= not req_i.read_writen;
end if;
if resp.dack_tag = X"34" then
if resp.data /= expected_data then
okay_i <= not okay_i;
end if;
end if;
end if;
end if;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple memory tester that can be
-- traced with chipscope.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_test_v5 is
port (
clock : in std_logic := '0';
reset : in std_logic := '0';
inhibit : out std_logic := '0';
req : out t_mem_req_32;
resp : in t_mem_resp_32;
run : out std_logic;
okay : out std_logic );
end entity;
architecture gideon of ext_mem_test_v5 is
signal req_i : t_mem_req_32;
signal expected_data : std_logic_vector(31 downto 0);
signal okay_i : std_logic;
signal run_i : std_logic;
function xor_reduce(s : std_logic_vector) return std_logic is
variable o : std_logic := '1';
begin
for i in s'range loop
o := o xor s(i);
end loop;
return o;
end function;
begin
req <= req_i;
okay <= okay_i;
run <= run_i;
p_test: process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
req_i <= c_mem_req_32_init;
req_i.read_writen <= '0'; -- write
req_i.request <= '1';
req_i.size <= '1';
req_i.data <= X"12345678";
req_i.byte_en <= "1000";
req_i.tag <= X"34";
okay_i <= '1';
run_i <= '0';
else
if resp.rack='1' then
if req_i.read_writen = '1' then
if signed(req_i.address) = -4 then
req_i.data <= not req_i.data;
run_i <= not run_i;
end if;
req_i.address <= req_i.address + 4;
else
expected_data <= req_i.data;
end if;
req_i.read_writen <= not req_i.read_writen;
end if;
if resp.dack_tag = X"34" then
if resp.data /= expected_data then
okay_i <= not okay_i;
end if;
end if;
end if;
end if;
end process;
end architecture;
|
-- The NEO430 Processor Project, by Stephan Nolting
-- Auto-generated memory init file (for APPLICATION)
library ieee;
use ieee.std_logic_1164.all;
package neo430_application_image is
type application_init_image_t is array (0 to 65535) of std_ulogic_vector(15 downto 0);
constant application_init_image : application_init_image_t := (
000000 => x"4038",
000001 => x"c000",
000002 => x"4211",
000003 => x"fffa",
000004 => x"4302",
000005 => x"5801",
000006 => x"8321",
000007 => x"40b2",
000008 => x"4700",
000009 => x"ffb8",
000010 => x"4039",
000011 => x"ff80",
000012 => x"9309",
000013 => x"2404",
000014 => x"4389",
000015 => x"0000",
000016 => x"5329",
000017 => x"3ffa",
000018 => x"9801",
000019 => x"2404",
000020 => x"4388",
000021 => x"0000",
000022 => x"5328",
000023 => x"3ffa",
000024 => x"4035",
000025 => x"0228",
000026 => x"4036",
000027 => x"0228",
000028 => x"4037",
000029 => x"c008",
000030 => x"9506",
000031 => x"2404",
000032 => x"45b7",
000033 => x"0000",
000034 => x"5327",
000035 => x"3ffa",
000036 => x"4032",
000037 => x"4000",
000038 => x"4304",
000039 => x"430a",
000040 => x"430b",
000041 => x"430c",
000042 => x"430d",
000043 => x"430e",
000044 => x"430f",
000045 => x"12b0",
000046 => x"006c",
000047 => x"4302",
000048 => x"40b2",
000049 => x"4700",
000050 => x"ffb8",
000051 => x"4032",
000052 => x"0010",
000053 => x"4303",
000054 => x"120a",
000055 => x"1209",
000056 => x"1208",
000057 => x"1207",
000058 => x"403c",
000059 => x"4b00",
000060 => x"434d",
000061 => x"12b0",
000062 => x"00a8",
000063 => x"403c",
000064 => x"020c",
000065 => x"12b0",
000066 => x"013c",
000067 => x"434c",
000068 => x"4037",
000069 => x"016c",
000070 => x"4039",
000071 => x"0172",
000072 => x"4078",
000073 => x"00c8",
000074 => x"4c0a",
000075 => x"531a",
000076 => x"f03c",
000077 => x"00ff",
000078 => x"1287",
000079 => x"480c",
000080 => x"1289",
000081 => x"4a0c",
000082 => x"4030",
000083 => x"0094",
000084 => x"120a",
000085 => x"1209",
000086 => x"421a",
000087 => x"fffc",
000088 => x"421b",
000089 => x"fffe",
000090 => x"4c0e",
000091 => x"5c0e",
000092 => x"4d0f",
000093 => x"6d0f",
000094 => x"434c",
000095 => x"4f09",
000096 => x"9f0b",
000097 => x"2804",
000098 => x"9b09",
000099 => x"201b",
000100 => x"9e0a",
000101 => x"2c19",
000102 => x"434a",
000103 => x"4079",
000104 => x"0003",
000105 => x"407d",
000106 => x"00ff",
000107 => x"9c0d",
000108 => x"2817",
000109 => x"4382",
000110 => x"ffa0",
000111 => x"4a0d",
000112 => x"5a0d",
000113 => x"5d0d",
000114 => x"5d0d",
000115 => x"5d0d",
000116 => x"5d0d",
000117 => x"5d0d",
000118 => x"5d0d",
000119 => x"5d0d",
000120 => x"dc0d",
000121 => x"d03d",
000122 => x"1000",
000123 => x"4d82",
000124 => x"ffa0",
000125 => x"4030",
000126 => x"01a8",
000127 => x"8e0a",
000128 => x"7f0b",
000129 => x"531c",
000130 => x"4030",
000131 => x"00c0",
000132 => x"936a",
000133 => x"2402",
000134 => x"926a",
000135 => x"2008",
000136 => x"490d",
000137 => x"12b0",
000138 => x"01b4",
000139 => x"535a",
000140 => x"f03a",
000141 => x"00ff",
000142 => x"4030",
000143 => x"00d2",
000144 => x"c312",
000145 => x"100c",
000146 => x"4030",
000147 => x"0116",
000148 => x"f03c",
000149 => x"00ff",
000150 => x"403e",
000151 => x"ffa0",
000152 => x"4e2d",
000153 => x"930d",
000154 => x"3bfd",
000155 => x"4c82",
000156 => x"ffa2",
000157 => x"4130",
000158 => x"120a",
000159 => x"1209",
000160 => x"1208",
000161 => x"1207",
000162 => x"4c09",
000163 => x"4038",
000164 => x"0128",
000165 => x"4077",
000166 => x"000d",
000167 => x"496a",
000168 => x"930a",
000169 => x"2002",
000170 => x"4030",
000171 => x"01a4",
000172 => x"903a",
000173 => x"000a",
000174 => x"2002",
000175 => x"474c",
000176 => x"1288",
000177 => x"4a4c",
000178 => x"1288",
000179 => x"5319",
000180 => x"4030",
000181 => x"014e",
000182 => x"4c82",
000183 => x"ffac",
000184 => x"4130",
000185 => x"421e",
000186 => x"fffe",
000187 => x"430f",
000188 => x"4e0b",
000189 => x"5e0b",
000190 => x"4f0d",
000191 => x"6f0d",
000192 => x"4c0e",
000193 => x"430f",
000194 => x"4b0c",
000195 => x"12b0",
000196 => x"01ba",
000197 => x"533c",
000198 => x"633d",
000199 => x"933c",
000200 => x"2003",
000201 => x"933d",
000202 => x"2001",
000203 => x"4130",
000204 => x"4303",
000205 => x"4030",
000206 => x"018a",
000207 => x"4134",
000208 => x"4135",
000209 => x"4136",
000210 => x"4137",
000211 => x"4138",
000212 => x"4139",
000213 => x"413a",
000214 => x"4130",
000215 => x"533d",
000216 => x"c312",
000217 => x"100c",
000218 => x"930d",
000219 => x"23fb",
000220 => x"4130",
000221 => x"120a",
000222 => x"1209",
000223 => x"1208",
000224 => x"1207",
000225 => x"1206",
000226 => x"4c0a",
000227 => x"4d0b",
000228 => x"407d",
000229 => x"0021",
000230 => x"4348",
000231 => x"4349",
000232 => x"4e0c",
000233 => x"df0c",
000234 => x"930c",
000235 => x"2405",
000236 => x"537d",
000237 => x"f03d",
000238 => x"00ff",
000239 => x"930d",
000240 => x"2004",
000241 => x"480c",
000242 => x"490d",
000243 => x"4030",
000244 => x"01a2",
000245 => x"4e0c",
000246 => x"f35c",
000247 => x"930c",
000248 => x"2402",
000249 => x"5a08",
000250 => x"6b09",
000251 => x"4a06",
000252 => x"4b07",
000253 => x"5a06",
000254 => x"6b07",
000255 => x"460a",
000256 => x"470b",
000257 => x"c312",
000258 => x"100f",
000259 => x"100e",
000260 => x"4030",
000261 => x"01d0",
000262 => x"420a",
000263 => x"696c",
000264 => x"6b6e",
000265 => x"6e69",
000266 => x"2067",
000267 => x"454c",
000268 => x"2044",
000269 => x"6564",
000270 => x"6f6d",
000271 => x"7020",
000272 => x"6f72",
000273 => x"7267",
000274 => x"6d61",
000275 => x"000a",
others => x"0000"
);
end neo430_application_image;
|
library verilog;
use verilog.vl_types.all;
entity ama_scanchain is
generic(
width_scanin : integer := 1;
width_scanchain : integer := 1;
input_register_clock_0: string := "UNREGISTERED";
input_register_aclr_0: string := "NONE";
input_register_clock_1: string := "UNREGISTERED";
input_register_aclr_1: string := "NONE";
input_register_clock_2: string := "UNREGISTERED";
input_register_aclr_2: string := "NONE";
input_register_clock_3: string := "UNREGISTERED";
input_register_aclr_3: string := "NONE";
scanchain_register_clock: string := "UNREGISTERED";
scanchain_register_aclr: string := "NONE";
port_sign : string := "PORT_UNUSED";
number_of_multipliers: integer := 1;
width_scanin_msb: vl_notype;
width_scanchain_msb: vl_notype
);
port(
clock : in vl_logic_vector(3 downto 0);
aclr : in vl_logic_vector(3 downto 0);
ena : in vl_logic_vector(3 downto 0);
sign : in vl_logic;
scanin : in vl_logic_vector;
data_out_0 : out vl_logic_vector;
data_out_1 : out vl_logic_vector;
data_out_2 : out vl_logic_vector;
data_out_3 : out vl_logic_vector;
scanout : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_scanin : constant is 1;
attribute mti_svvh_generic_type of width_scanchain : constant is 1;
attribute mti_svvh_generic_type of input_register_clock_0 : constant is 1;
attribute mti_svvh_generic_type of input_register_aclr_0 : constant is 1;
attribute mti_svvh_generic_type of input_register_clock_1 : constant is 1;
attribute mti_svvh_generic_type of input_register_aclr_1 : constant is 1;
attribute mti_svvh_generic_type of input_register_clock_2 : constant is 1;
attribute mti_svvh_generic_type of input_register_aclr_2 : constant is 1;
attribute mti_svvh_generic_type of input_register_clock_3 : constant is 1;
attribute mti_svvh_generic_type of input_register_aclr_3 : constant is 1;
attribute mti_svvh_generic_type of scanchain_register_clock : constant is 1;
attribute mti_svvh_generic_type of scanchain_register_aclr : constant is 1;
attribute mti_svvh_generic_type of port_sign : constant is 1;
attribute mti_svvh_generic_type of number_of_multipliers : constant is 1;
attribute mti_svvh_generic_type of width_scanin_msb : constant is 3;
attribute mti_svvh_generic_type of width_scanchain_msb : constant is 3;
end ama_scanchain;
|
library verilog;
use verilog.vl_types.all;
entity ama_scanchain is
generic(
width_scanin : integer := 1;
width_scanchain : integer := 1;
input_register_clock_0: string := "UNREGISTERED";
input_register_aclr_0: string := "NONE";
input_register_clock_1: string := "UNREGISTERED";
input_register_aclr_1: string := "NONE";
input_register_clock_2: string := "UNREGISTERED";
input_register_aclr_2: string := "NONE";
input_register_clock_3: string := "UNREGISTERED";
input_register_aclr_3: string := "NONE";
scanchain_register_clock: string := "UNREGISTERED";
scanchain_register_aclr: string := "NONE";
port_sign : string := "PORT_UNUSED";
number_of_multipliers: integer := 1;
width_scanin_msb: vl_notype;
width_scanchain_msb: vl_notype
);
port(
clock : in vl_logic_vector(3 downto 0);
aclr : in vl_logic_vector(3 downto 0);
ena : in vl_logic_vector(3 downto 0);
sign : in vl_logic;
scanin : in vl_logic_vector;
data_out_0 : out vl_logic_vector;
data_out_1 : out vl_logic_vector;
data_out_2 : out vl_logic_vector;
data_out_3 : out vl_logic_vector;
scanout : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_scanin : constant is 1;
attribute mti_svvh_generic_type of width_scanchain : constant is 1;
attribute mti_svvh_generic_type of input_register_clock_0 : constant is 1;
attribute mti_svvh_generic_type of input_register_aclr_0 : constant is 1;
attribute mti_svvh_generic_type of input_register_clock_1 : constant is 1;
attribute mti_svvh_generic_type of input_register_aclr_1 : constant is 1;
attribute mti_svvh_generic_type of input_register_clock_2 : constant is 1;
attribute mti_svvh_generic_type of input_register_aclr_2 : constant is 1;
attribute mti_svvh_generic_type of input_register_clock_3 : constant is 1;
attribute mti_svvh_generic_type of input_register_aclr_3 : constant is 1;
attribute mti_svvh_generic_type of scanchain_register_clock : constant is 1;
attribute mti_svvh_generic_type of scanchain_register_aclr : constant is 1;
attribute mti_svvh_generic_type of port_sign : constant is 1;
attribute mti_svvh_generic_type of number_of_multipliers : constant is 1;
attribute mti_svvh_generic_type of width_scanin_msb : constant is 3;
attribute mti_svvh_generic_type of width_scanchain_msb : constant is 3;
end ama_scanchain;
|
library verilog;
use verilog.vl_types.all;
entity ama_scanchain is
generic(
width_scanin : integer := 1;
width_scanchain : integer := 1;
input_register_clock_0: string := "UNREGISTERED";
input_register_aclr_0: string := "NONE";
input_register_clock_1: string := "UNREGISTERED";
input_register_aclr_1: string := "NONE";
input_register_clock_2: string := "UNREGISTERED";
input_register_aclr_2: string := "NONE";
input_register_clock_3: string := "UNREGISTERED";
input_register_aclr_3: string := "NONE";
scanchain_register_clock: string := "UNREGISTERED";
scanchain_register_aclr: string := "NONE";
port_sign : string := "PORT_UNUSED";
number_of_multipliers: integer := 1;
width_scanin_msb: vl_notype;
width_scanchain_msb: vl_notype
);
port(
clock : in vl_logic_vector(3 downto 0);
aclr : in vl_logic_vector(3 downto 0);
ena : in vl_logic_vector(3 downto 0);
sign : in vl_logic;
scanin : in vl_logic_vector;
data_out_0 : out vl_logic_vector;
data_out_1 : out vl_logic_vector;
data_out_2 : out vl_logic_vector;
data_out_3 : out vl_logic_vector;
scanout : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_scanin : constant is 1;
attribute mti_svvh_generic_type of width_scanchain : constant is 1;
attribute mti_svvh_generic_type of input_register_clock_0 : constant is 1;
attribute mti_svvh_generic_type of input_register_aclr_0 : constant is 1;
attribute mti_svvh_generic_type of input_register_clock_1 : constant is 1;
attribute mti_svvh_generic_type of input_register_aclr_1 : constant is 1;
attribute mti_svvh_generic_type of input_register_clock_2 : constant is 1;
attribute mti_svvh_generic_type of input_register_aclr_2 : constant is 1;
attribute mti_svvh_generic_type of input_register_clock_3 : constant is 1;
attribute mti_svvh_generic_type of input_register_aclr_3 : constant is 1;
attribute mti_svvh_generic_type of scanchain_register_clock : constant is 1;
attribute mti_svvh_generic_type of scanchain_register_aclr : constant is 1;
attribute mti_svvh_generic_type of port_sign : constant is 1;
attribute mti_svvh_generic_type of number_of_multipliers : constant is 1;
attribute mti_svvh_generic_type of width_scanin_msb : constant is 3;
attribute mti_svvh_generic_type of width_scanchain_msb : constant is 3;
end ama_scanchain;
|
library verilog;
use verilog.vl_types.all;
entity ama_scanchain is
generic(
width_scanin : integer := 1;
width_scanchain : integer := 1;
input_register_clock_0: string := "UNREGISTERED";
input_register_aclr_0: string := "NONE";
input_register_clock_1: string := "UNREGISTERED";
input_register_aclr_1: string := "NONE";
input_register_clock_2: string := "UNREGISTERED";
input_register_aclr_2: string := "NONE";
input_register_clock_3: string := "UNREGISTERED";
input_register_aclr_3: string := "NONE";
scanchain_register_clock: string := "UNREGISTERED";
scanchain_register_aclr: string := "NONE";
port_sign : string := "PORT_UNUSED";
number_of_multipliers: integer := 1;
width_scanin_msb: vl_notype;
width_scanchain_msb: vl_notype
);
port(
clock : in vl_logic_vector(3 downto 0);
aclr : in vl_logic_vector(3 downto 0);
ena : in vl_logic_vector(3 downto 0);
sign : in vl_logic;
scanin : in vl_logic_vector;
data_out_0 : out vl_logic_vector;
data_out_1 : out vl_logic_vector;
data_out_2 : out vl_logic_vector;
data_out_3 : out vl_logic_vector;
scanout : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_scanin : constant is 1;
attribute mti_svvh_generic_type of width_scanchain : constant is 1;
attribute mti_svvh_generic_type of input_register_clock_0 : constant is 1;
attribute mti_svvh_generic_type of input_register_aclr_0 : constant is 1;
attribute mti_svvh_generic_type of input_register_clock_1 : constant is 1;
attribute mti_svvh_generic_type of input_register_aclr_1 : constant is 1;
attribute mti_svvh_generic_type of input_register_clock_2 : constant is 1;
attribute mti_svvh_generic_type of input_register_aclr_2 : constant is 1;
attribute mti_svvh_generic_type of input_register_clock_3 : constant is 1;
attribute mti_svvh_generic_type of input_register_aclr_3 : constant is 1;
attribute mti_svvh_generic_type of scanchain_register_clock : constant is 1;
attribute mti_svvh_generic_type of scanchain_register_aclr : constant is 1;
attribute mti_svvh_generic_type of port_sign : constant is 1;
attribute mti_svvh_generic_type of number_of_multipliers : constant is 1;
attribute mti_svvh_generic_type of width_scanin_msb : constant is 3;
attribute mti_svvh_generic_type of width_scanchain_msb : constant is 3;
end ama_scanchain;
|
library verilog;
use verilog.vl_types.all;
entity ama_scanchain is
generic(
width_scanin : integer := 1;
width_scanchain : integer := 1;
input_register_clock_0: string := "UNREGISTERED";
input_register_aclr_0: string := "NONE";
input_register_clock_1: string := "UNREGISTERED";
input_register_aclr_1: string := "NONE";
input_register_clock_2: string := "UNREGISTERED";
input_register_aclr_2: string := "NONE";
input_register_clock_3: string := "UNREGISTERED";
input_register_aclr_3: string := "NONE";
scanchain_register_clock: string := "UNREGISTERED";
scanchain_register_aclr: string := "NONE";
port_sign : string := "PORT_UNUSED";
number_of_multipliers: integer := 1;
width_scanin_msb: vl_notype;
width_scanchain_msb: vl_notype
);
port(
clock : in vl_logic_vector(3 downto 0);
aclr : in vl_logic_vector(3 downto 0);
ena : in vl_logic_vector(3 downto 0);
sign : in vl_logic;
scanin : in vl_logic_vector;
data_out_0 : out vl_logic_vector;
data_out_1 : out vl_logic_vector;
data_out_2 : out vl_logic_vector;
data_out_3 : out vl_logic_vector;
scanout : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_scanin : constant is 1;
attribute mti_svvh_generic_type of width_scanchain : constant is 1;
attribute mti_svvh_generic_type of input_register_clock_0 : constant is 1;
attribute mti_svvh_generic_type of input_register_aclr_0 : constant is 1;
attribute mti_svvh_generic_type of input_register_clock_1 : constant is 1;
attribute mti_svvh_generic_type of input_register_aclr_1 : constant is 1;
attribute mti_svvh_generic_type of input_register_clock_2 : constant is 1;
attribute mti_svvh_generic_type of input_register_aclr_2 : constant is 1;
attribute mti_svvh_generic_type of input_register_clock_3 : constant is 1;
attribute mti_svvh_generic_type of input_register_aclr_3 : constant is 1;
attribute mti_svvh_generic_type of scanchain_register_clock : constant is 1;
attribute mti_svvh_generic_type of scanchain_register_aclr : constant is 1;
attribute mti_svvh_generic_type of port_sign : constant is 1;
attribute mti_svvh_generic_type of number_of_multipliers : constant is 1;
attribute mti_svvh_generic_type of width_scanin_msb : constant is 3;
attribute mti_svvh_generic_type of width_scanchain_msb : constant is 3;
end ama_scanchain;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package tcp_bridge_pkg is
function byte_swap(word_in : std_logic_vector) return std_logic_vector;
component axis_srl_fifo
generic (
DATA_WIDTH : natural := 8;
DEPTH : natural := 16
);
port (
clk : in std_logic;
rst : in std_logic;
input_axis_tdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
input_axis_tvalid : in std_logic;
input_axis_tready : out std_logic;
input_axis_tlast : in std_logic;
input_axis_tuser : in std_logic;
output_axis_tdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
output_axis_tvalid : out std_logic;
output_axis_tready : in std_logic;
output_axis_tlast : out std_logic;
output_axis_tuser : out std_logic;
count : out std_logic_vector(integer(ceil(log2(real(DEPTH+1))))-1 downto 0)
);
end component;
component axis_demux_2
generic (
DATA_WIDTH : natural := 8
);
port (
clk : in std_logic;
rst : in std_logic;
input_axis_tdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
input_axis_tvalid : in std_logic;
input_axis_tready : out std_logic;
input_axis_tlast : in std_logic;
input_axis_tuser : in std_logic;
output_0_axis_tdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
output_0_axis_tvalid : out std_logic;
output_0_axis_tready : in std_logic;
output_0_axis_tlast : out std_logic;
output_0_axis_tuser : out std_logic;
output_1_axis_tdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
output_1_axis_tvalid : out std_logic;
output_1_axis_tready : in std_logic;
output_1_axis_tlast : out std_logic;
output_1_axis_tuser : out std_logic;
enable : in std_logic;
control : in std_logic_vector(0 downto 0)
);
end component;
component axis_adapter
generic (
INPUT_DATA_WIDTH : natural := 8;
INPUT_KEEP_WIDTH : natural := 1;
OUTPUT_DATA_WIDTH : natural := 8;
OUTPUT_KEEP_WIDTH : natural := 1
);
port (
clk : in std_logic;
rst : in std_logic;
--AXIS input
input_axis_tdata : in std_logic_vector(INPUT_DATA_WIDTH-1 downto 0);
input_axis_tkeep : in std_logic_vector(INPUT_KEEP_WIDTH-1 downto 0);
input_axis_tvalid : in std_logic;
input_axis_tready : out std_logic;
input_axis_tlast : in std_logic;
input_axis_tuser : in std_logic;
--AXIS input
output_axis_tdata : out std_logic_vector(OUTPUT_DATA_WIDTH-1 downto 0);
output_axis_tkeep : out std_logic_vector(OUTPUT_KEEP_WIDTH-1 downto 0);
output_axis_tvalid : out std_logic;
output_axis_tready : in std_logic;
output_axis_tlast : out std_logic;
output_axis_tuser : out std_logic
);
end component;
component axis_arb_mux_3
generic (
DATA_WIDTH : natural := 8;
ARB_TYPE : string := "PRIORITY"; --"PRIORITY" or "ROUND_ROBIN"
LSB_PRIORITY : string := "HIGH" --"LOW" or "HIGH"
);
port (
clk : in std_logic;
rst : in std_logic;
input_0_axis_tdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
input_0_axis_tvalid : in std_logic;
input_0_axis_tready : out std_logic;
input_0_axis_tlast : in std_logic;
input_0_axis_tuser : in std_logic;
input_1_axis_tdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
input_1_axis_tvalid : in std_logic;
input_1_axis_tready : out std_logic;
input_1_axis_tlast : in std_logic;
input_1_axis_tuser : in std_logic;
input_2_axis_tdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
input_2_axis_tvalid : in std_logic;
input_2_axis_tready : out std_logic;
input_2_axis_tlast : in std_logic;
input_2_axis_tuser : in std_logic;
output_axis_tdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
output_axis_tvalid : out std_logic;
output_axis_tready : in std_logic;
output_axis_tlast : out std_logic;
output_axis_tuser : out std_logic
);
end component;
component axis_async_fifo
generic (
ADDR_WIDTH : natural := 12;
DATA_WIDTH : natural := 8
);
port (
async_rst : in std_logic;
input_clk : in std_logic;
input_axis_tdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
input_axis_tvalid : in std_logic;
input_axis_tready : out std_logic;
input_axis_tlast : in std_logic;
input_axis_tuser : in std_logic;
output_clk : in std_logic;
output_axis_tdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
output_axis_tvalid : out std_logic;
output_axis_tready : in std_logic;
output_axis_tlast : out std_logic;
output_axis_tuser : out std_logic
);
end component;
end tcp_bridge_pkg;
package body tcp_bridge_pkg is
function byte_swap(word_in : std_logic_vector) return std_logic_vector is
variable word_out : std_logic_vector(word_in'range);
variable num_bytes : natural := word_in'length/8;
begin
for ct in 0 to num_bytes-1 loop
word_out(8*(ct+1)-1 downto 8*ct) := word_in(8*(num_bytes-ct)-1 downto 8*(num_bytes-ct-1));
end loop;
return word_out;
end function byte_swap;
end package body;
|
package test is
constant C_ZERO : bit_vector(4 downto 0) := 5d"0";
constant C_ONE : bit_vector(4 downto 0) := 5d"1";
constant C_TWO : bit_vector(4 downto 0) := 5d"2";
constant C_THREE : bit_vector(4 downto 0) := 5d"3";
constant C_TWENTY : bit_vector(4 downto 0) := 5d"20";
end package test;
|
package pack is
constant iname : string := pack'instance_name;
procedure proc;
end package;
package body pack is
procedure proc is
begin
report pack'instance_name & " <--";
report iname & " <--";
end procedure;
end package body;
-------------------------------------------------------------------------------
entity attr12 is
end entity;
use work.pack.all;
architecture test of attr12 is
begin
process is
begin
proc;
wait;
end process;
end architecture;
|
-- Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3
-- Component : Murax
-- Git hash : 68e704f3092be640aa92c876cf78702a83167f94
package pkg_enum is
type BranchCtrlEnum is (INC,B,JAL,JALR);
type ShiftCtrlEnum is (DISABLE_1,SLL_1,SRL_1,SRA_1);
type AluBitwiseCtrlEnum is (XOR_1,OR_1,AND_1);
type AluCtrlEnum is (ADD_SUB,SLT_SLTU,BITWISE);
type EnvCtrlEnum is (NONE,XRET);
type Src2CtrlEnum is (RS,IMI,IMS,PC);
type Src1CtrlEnum is (RS,IMU,PC_INCREMENT,URS1);
type JtagState is (RESET,IDLE,IR_SELECT,IR_CAPTURE,IR_SHIFT,IR_EXIT1,IR_PAUSE,IR_EXIT2,IR_UPDATE,DR_SELECT,DR_CAPTURE,DR_SHIFT,DR_EXIT1,DR_PAUSE,DR_EXIT2,DR_UPDATE);
type UartStopType is (ONE,TWO);
type UartParityType is (NONE,EVEN,ODD);
type UartCtrlTxState is (IDLE,START,DATA,PARITY,STOP);
type UartCtrlRxState is (IDLE,START,DATA,PARITY,STOP);
function pkg_mux (sel : bit; one : BranchCtrlEnum; zero : BranchCtrlEnum) return BranchCtrlEnum;
subtype BranchCtrlEnum_binary_sequential_type is bit_vector(1 downto 0);
constant BranchCtrlEnum_binary_sequential_INC : BranchCtrlEnum_binary_sequential_type := "00";
constant BranchCtrlEnum_binary_sequential_B : BranchCtrlEnum_binary_sequential_type := "01";
constant BranchCtrlEnum_binary_sequential_JAL : BranchCtrlEnum_binary_sequential_type := "10";
constant BranchCtrlEnum_binary_sequential_JALR : BranchCtrlEnum_binary_sequential_type := "11";
function pkg_mux (sel : bit; one : ShiftCtrlEnum; zero : ShiftCtrlEnum) return ShiftCtrlEnum;
subtype ShiftCtrlEnum_binary_sequential_type is bit_vector(1 downto 0);
constant ShiftCtrlEnum_binary_sequential_DISABLE_1 : ShiftCtrlEnum_binary_sequential_type := "00";
constant ShiftCtrlEnum_binary_sequential_SLL_1 : ShiftCtrlEnum_binary_sequential_type := "01";
constant ShiftCtrlEnum_binary_sequential_SRL_1 : ShiftCtrlEnum_binary_sequential_type := "10";
constant ShiftCtrlEnum_binary_sequential_SRA_1 : ShiftCtrlEnum_binary_sequential_type := "11";
function pkg_mux (sel : bit; one : AluBitwiseCtrlEnum; zero : AluBitwiseCtrlEnum) return AluBitwiseCtrlEnum;
subtype AluBitwiseCtrlEnum_binary_sequential_type is bit_vector(1 downto 0);
constant AluBitwiseCtrlEnum_binary_sequential_XOR_1 : AluBitwiseCtrlEnum_binary_sequential_type := "00";
constant AluBitwiseCtrlEnum_binary_sequential_OR_1 : AluBitwiseCtrlEnum_binary_sequential_type := "01";
constant AluBitwiseCtrlEnum_binary_sequential_AND_1 : AluBitwiseCtrlEnum_binary_sequential_type := "10";
function pkg_mux (sel : bit; one : AluCtrlEnum; zero : AluCtrlEnum) return AluCtrlEnum;
subtype AluCtrlEnum_binary_sequential_type is bit_vector(1 downto 0);
constant AluCtrlEnum_binary_sequential_ADD_SUB : AluCtrlEnum_binary_sequential_type := "00";
constant AluCtrlEnum_binary_sequential_SLT_SLTU : AluCtrlEnum_binary_sequential_type := "01";
constant AluCtrlEnum_binary_sequential_BITWISE : AluCtrlEnum_binary_sequential_type := "10";
function pkg_mux (sel : bit; one : EnvCtrlEnum; zero : EnvCtrlEnum) return EnvCtrlEnum;
subtype EnvCtrlEnum_binary_sequential_type is bit_vector(0 downto 0);
constant EnvCtrlEnum_binary_sequential_NONE : EnvCtrlEnum_binary_sequential_type := "0";
constant EnvCtrlEnum_binary_sequential_XRET : EnvCtrlEnum_binary_sequential_type := "1";
function pkg_mux (sel : bit; one : Src2CtrlEnum; zero : Src2CtrlEnum) return Src2CtrlEnum;
subtype Src2CtrlEnum_binary_sequential_type is bit_vector(1 downto 0);
constant Src2CtrlEnum_binary_sequential_RS : Src2CtrlEnum_binary_sequential_type := "00";
constant Src2CtrlEnum_binary_sequential_IMI : Src2CtrlEnum_binary_sequential_type := "01";
constant Src2CtrlEnum_binary_sequential_IMS : Src2CtrlEnum_binary_sequential_type := "10";
constant Src2CtrlEnum_binary_sequential_PC : Src2CtrlEnum_binary_sequential_type := "11";
function pkg_mux (sel : bit; one : Src1CtrlEnum; zero : Src1CtrlEnum) return Src1CtrlEnum;
subtype Src1CtrlEnum_binary_sequential_type is bit_vector(1 downto 0);
constant Src1CtrlEnum_binary_sequential_RS : Src1CtrlEnum_binary_sequential_type := "00";
constant Src1CtrlEnum_binary_sequential_IMU : Src1CtrlEnum_binary_sequential_type := "01";
constant Src1CtrlEnum_binary_sequential_PC_INCREMENT : Src1CtrlEnum_binary_sequential_type := "10";
constant Src1CtrlEnum_binary_sequential_URS1 : Src1CtrlEnum_binary_sequential_type := "11";
function pkg_mux (sel : bit; one : JtagState; zero : JtagState) return JtagState;
function pkg_toStdLogicVector_native (value : JtagState) return bit_vector;
function pkg_toJtagState_native (value : bit_vector(3 downto 0)) return JtagState;
function pkg_mux (sel : bit; one : UartStopType; zero : UartStopType) return UartStopType;
subtype UartStopType_binary_sequential_type is bit_vector(0 downto 0);
constant UartStopType_binary_sequential_ONE : UartStopType_binary_sequential_type := "0";
constant UartStopType_binary_sequential_TWO : UartStopType_binary_sequential_type := "1";
function pkg_mux (sel : bit; one : UartParityType; zero : UartParityType) return UartParityType;
subtype UartParityType_binary_sequential_type is bit_vector(1 downto 0);
constant UartParityType_binary_sequential_NONE : UartParityType_binary_sequential_type := "00";
constant UartParityType_binary_sequential_EVEN : UartParityType_binary_sequential_type := "01";
constant UartParityType_binary_sequential_ODD : UartParityType_binary_sequential_type := "10";
function pkg_mux (sel : bit; one : UartCtrlTxState; zero : UartCtrlTxState) return UartCtrlTxState;
function pkg_toStdLogicVector_native (value : UartCtrlTxState) return bit_vector;
function pkg_toUartCtrlTxState_native (value : bit_vector(2 downto 0)) return UartCtrlTxState;
function pkg_mux (sel : bit; one : UartCtrlRxState; zero : UartCtrlRxState) return UartCtrlRxState;
function pkg_toStdLogicVector_native (value : UartCtrlRxState) return bit_vector;
function pkg_toUartCtrlRxState_native (value : bit_vector(2 downto 0)) return UartCtrlRxState;
end pkg_enum;
package pkg_scala2hdl is
function pkg_extract (that : bit_vector; bitId : integer) return bit;
type unsigned is array (natural range <>) of bit;
type signed is array (natural range <>) of bit;
function pkg_cat (a : signed; b : signed) return signed;
function pkg_not (value : signed) return signed;
function pkg_mux (sel : bit; one : bit; zero : bit) return bit;
function pkg_mux (sel : bit; one : bit_vector; zero : bit_vector) return bit_vector;
function pkg_mux (sel : bit; one : unsigned; zero : unsigned) return unsigned;
function pkg_mux (sel : bit; one : signed; zero : signed) return signed;
function pkg_toStdLogic (value : boolean) return bit;
function pkg_toStdLogicVector (value : bit) return bit_vector;
end pkg_scala2hdl;
library work;
use work.pkg_scala2hdl.all;
use work.all;
use work.pkg_enum.all;
entity UartCtrlTx is
port(
io_configFrame_dataLength : in unsigned(2 downto 0);
io_configFrame_stop : in UartStopType_binary_sequential_type;
io_configFrame_parity : in UartParityType_binary_sequential_type;
io_samplingTick : in bit;
io_write_valid : in bit;
io_write_ready : out bit;
io_write_payload : in bit_vector(7 downto 0);
io_cts : in bit;
io_txd : out bit;
io_break : in bit;
io_mainClk : in bit;
resetCtrl_systemReset : in bit
);
end UartCtrlTx;
architecture arch of UartCtrlTx is
signal clockDivider_counter_willIncrement : bit;
signal clockDivider_counter_willClear : bit;
signal clockDivider_counter_valueNext : unsigned(2 downto 0);
signal clockDivider_counter_value : unsigned(2 downto 0);
signal clockDivider_counter_willOverflowIfInc : bit;
signal clockDivider_counter_willOverflow : bit;
signal tickCounter_value : unsigned(2 downto 0);
signal stateMachine_state : UartCtrlTxState;
signal stateMachine_parity : bit;
signal stateMachine_txd : bit;
signal when_UartCtrlTx_l58 : bit;
signal when_UartCtrlTx_l73 : bit;
signal when_UartCtrlTx_l76 : bit;
signal when_UartCtrlTx_l93 : bit;
signal zz_io_txd : bit;
begin
process(io_samplingTick)
begin
clockDivider_counter_willIncrement <= pkg_toStdLogic(false);
if io_samplingTick = '1' then
clockDivider_counter_willIncrement <= pkg_toStdLogic(true);
end if;
end process;
clockDivider_counter_willClear <= pkg_toStdLogic(false);
process(stateMachine_state,io_write_payload,tickCounter_value,stateMachine_parity)
begin
stateMachine_txd <= pkg_toStdLogic(true);
case stateMachine_state is
when pkg_enum.IDLE =>
when pkg_enum.START =>
stateMachine_txd <= pkg_toStdLogic(false);
when pkg_enum.DATA =>
when pkg_enum.PARITY =>
stateMachine_txd <= stateMachine_parity;
when others =>
end case;
end process;
process(io_break,stateMachine_state,clockDivider_counter_willOverflow,when_UartCtrlTx_l73)
begin
io_write_ready <= io_break;
case stateMachine_state is
when pkg_enum.IDLE =>
when pkg_enum.START =>
when pkg_enum.DATA =>
if clockDivider_counter_willOverflow = '1' then
if when_UartCtrlTx_l73 = '1' then
io_write_ready <= pkg_toStdLogic(true);
end if;
end if;
when pkg_enum.PARITY =>
when others =>
end case;
end process;
io_txd <= zz_io_txd;
process(io_mainClk, resetCtrl_systemReset)
begin
if resetCtrl_systemReset = '1' then
stateMachine_state <= pkg_enum.IDLE;
zz_io_txd <= pkg_toStdLogic(true);
elsif io_mainClk'active and io_mainClk = '1' then
clockDivider_counter_value <= clockDivider_counter_valueNext;
case stateMachine_state is
when pkg_enum.IDLE =>
if when_UartCtrlTx_l58 = '1' then
stateMachine_state <= pkg_enum.START;
end if;
when pkg_enum.START =>
if clockDivider_counter_willOverflow = '1' then
stateMachine_state <= pkg_enum.DATA;
end if;
when pkg_enum.DATA =>
if clockDivider_counter_willOverflow = '1' then
if when_UartCtrlTx_l73 = '1' then
if when_UartCtrlTx_l76 = '1' then
stateMachine_state <= pkg_enum.STOP;
else
stateMachine_state <= pkg_enum.PARITY;
end if;
end if;
end if;
when pkg_enum.PARITY =>
if clockDivider_counter_willOverflow = '1' then
stateMachine_state <= pkg_enum.STOP;
end if;
when others =>
if clockDivider_counter_willOverflow = '1' then
if when_UartCtrlTx_l93 = '1' then
stateMachine_state <= pkg_mux(io_write_valid,pkg_enum.START,pkg_enum.IDLE);
end if;
end if;
end case;
zz_io_txd <= (stateMachine_txd and (not io_break));
end if;
end process;
end arch;
|
entity tb_arr02 is
end tb_arr02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_arr02 is
signal a : std_logic_vector (31 downto 0);
signal sel : natural range 0 to 3;
signal clk : std_logic;
signal res : std_logic_vector (3 downto 0);
begin
dut: entity work.arr02
port map (a, sel, clk, res);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
a <= x"a1b2c3d4";
sel <= 0;
pulse;
pulse;
assert res = x"1" severity failure;
sel <= 1;
pulse;
assert res = x"1" severity failure;
sel <= 2;
pulse;
assert res = x"2" severity failure;
sel <= 3;
pulse;
assert res = x"3" severity failure;
sel <= 0;
pulse;
assert res = x"4" severity failure;
wait;
end process;
end behav;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity clkgen_c5ekit is
port (
clkin: in std_ulogic;
clkm: out std_ulogic;
ssclk: out std_ulogic;
locked: out std_ulogic
);
end;
architecture rtl of clkgen_c5ekit is
component syspll1 is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
locked : out std_logic -- export
);
end component syspll1;
signal cgi: clkgen_in_type;
signal cgo: clkgen_out_type;
signal gnd: std_ulogic;
begin
pll0: syspll1
port map (clkin, '0', clkm, locked);
ssclk <= '0';
end;
|
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`protect end_protected
|
Library IEEE;
use IEEE.Std_Logic_1164.all;
use ieee.numeric_std.all;
library UNISIM; -- include this library and use statement to ensure that the PLL component can be found by the Xilinx compiler.
use UNISIM.Vcomponents.ALL;
entity PllClip is
port(
-- Asynchronous reset signal from the LabVIEW FPGA environment.
aReset : in std_logic; -- this signal will be used to reset the PLL
-- LabVIEW FPGA I/O
-- PLL I/O
CLKIN1_IN : in std_logic; -- reference clock input from the LVFPGA diagram
LOCKED_OUT : out std_logic; -- indicate to the LVFPGA diagram that the PLL has locked to the reference clock
CLKOUT0_OUT : out std_logic --PLL clock output to the LVFPGA diagram
);
end PllClip;
architecture behavioral of PllClip is
-- Internal clock signals
signal UserGClk0 : std_logic; -- this internal signal will be used to route the PLL output clock back to LVFPGA and out a GPIO line
signal ClkOut0Ddr: std_logic; -- output of DDR routed to GPIO line
-- PLL Internal Signals
signal CLKFBOUT_CLKFBIN : std_logic; -- internal feedback signal for PLL
signal CLKOUT0_BUF : std_logic; -- signal routed to global clock buffer from PLL
-- Internal signals created by core generator and are used to configure the PLL
signal GND_BIT : std_logic;
signal GND_BUS_5 : std_logic_vector (4 downto 0);
signal GND_BUS_16 : std_logic_vector (15 downto 0);
signal VCC_BIT : std_logic;
-- Reset signals
signal rDelayRstReg : std_logic_vector(15 downto 0) := x"ffff";
signal rDelayGo, rDelayGo_ms : boolean := false;
begin
---------------------------
-- Reset logic
---------------------------
--Double sync to come out of reset safely. This relies on the
--default condition of the registers
PllGoSync: process (CLKIN1_IN)
begin
if(rising_edge(CLKIN1_IN)) then
rDelayGo_ms <= true;
rDelayGo <= rDelayGo_ms;
end if;
end process;
-- IODELAYCTRL must be held in reset for several clock cycles (50 ns)
IoDelayReset: process (aReset, CLKIN1_IN)
begin
if(rising_edge(CLKIN1_IN)) then
if(rDelayGo) then
rDelayRstReg <= '0' & rDelayRstReg(rDelayRstReg'left downto 1);
end if;
end if;
end process;
-- Assign bit values to the internal signals
GND_BIT <= '0';
GND_BUS_5(4 downto 0) <= "00000";
GND_BUS_16(15 downto 0) <= "0000000000000000";
VCC_BIT <= '1';
-- Instantiate the PLL for LabVIEW FPGA
-- The formatting has been modified but the instantiation is identical to the code component created by core generator.
PLL_ADV_INST : PLL_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKIN1_PERIOD => 25.000, -- input clock period of 40 MHz
CLKIN2_PERIOD => 10.000,
CLKOUT0_DIVIDE => 7, -- output clock divide value O
CLKOUT1_DIVIDE => 8,
CLKOUT2_DIVIDE => 8,
CLKOUT3_DIVIDE => 8,
CLKOUT4_DIVIDE => 8,
CLKOUT5_DIVIDE => 8,
CLKOUT0_PHASE => 0.000,
CLKOUT1_PHASE => 0.000,
CLKOUT2_PHASE => 0.000,
CLKOUT3_PHASE => 0.000,
CLKOUT4_PHASE => 0.000,
CLKOUT5_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500, -- output clock duty cycle
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DUTY_CYCLE => 0.500,
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1, -- output clock D value
CLKFBOUT_MULT => 13, -- output clock M value
CLKFBOUT_PHASE => 0.0,
REF_JITTER => 0.000000)
port map (
CLKFBIN => CLKFBOUT_CLKFBIN, -- route the feedback signal in
CLKINSEL => VCC_BIT,
CLKIN1 => CLKIN1_IN,
CLKIN2 => GND_BIT,
DADDR(4 downto 0) => GND_BUS_5(4 downto 0),
DCLK => GND_BIT,
DEN => GND_BIT,
DI(15 downto 0) => GND_BUS_16(15 downto 0),
DWE => GND_BIT,
REL => GND_BIT,
RST => rDelayRstReg(0), -- attach LVFPGA diagram reset to PLL; a more robust reset design will be required for shipping designs
CLKFBDCM => open,
CLKFBOUT => CLKFBOUT_CLKFBIN,
CLKOUTDCM0 => open,
CLKOUTDCM1 => open,
CLKOUTDCM2 => open,
CLKOUTDCM3 => open,
CLKOUTDCM4 => open,
CLKOUTDCM5 => open,
CLKOUT0 => CLKOUT0_BUF,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
DO => open,
DRDY => open,
LOCKED => LOCKED_OUT);
CLKOUT0_BUFG_INST : BUFG -- route the output clock from the PLL to a global clock buffer
port map (
I=> CLKOUT0_BUF,
O=> CLKOUT0_OUT);
end behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D4_C2 is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D4_C2;
architecture D4_C2 of D4_C2 is
begin
process(rst,clk)
variable dem:integer range 0 to 8;
begin
if (rst='1') then dem:=0;
elsif (rising_edge(clk)) then
if (dem=8) then dem:=0;
else dem:=dem+1;
end if;
end if;
case dem is
when 0=> seg <="00000000";
when 1=> seg <="00000001";
when 2=> seg <="00000011";
when 3=> seg <="00000111";
when 4=> seg <="00001111";
when 5=> seg <="00011111";
when 6=> seg <="00111111";
when 7=> seg <="01111111";
when others=> seg <="11111111";
end case;
end process;
end D4_C2;
--rst=0.5Mhz; clk=20Mhz; |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_868 is
port (
eq : out std_logic;
in1 : in std_logic_vector(23 downto 0);
in0 : in std_logic_vector(23 downto 0)
);
end cmp_868;
architecture augh of cmp_868 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_868 is
port (
eq : out std_logic;
in1 : in std_logic_vector(23 downto 0);
in0 : in std_logic_vector(23 downto 0)
);
end cmp_868;
architecture augh of cmp_868 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
entity issue45 is
begin
end entity issue45;
architecture a of issue45 is
begin
b: block is
begin
p : process
begin
report p'instance_name;
report b'instance_name;
wait;
end process p;
end block;
end architecture a;
|
entity issue45 is
begin
end entity issue45;
architecture a of issue45 is
begin
b: block is
begin
p : process
begin
report p'instance_name;
report b'instance_name;
wait;
end process p;
end block;
end architecture a;
|
entity issue45 is
begin
end entity issue45;
architecture a of issue45 is
begin
b: block is
begin
p : process
begin
report p'instance_name;
report b'instance_name;
wait;
end process p;
end block;
end architecture a;
|
entity issue45 is
begin
end entity issue45;
architecture a of issue45 is
begin
b: block is
begin
p : process
begin
report p'instance_name;
report b'instance_name;
wait;
end process p;
end block;
end architecture a;
|
entity issue45 is
begin
end entity issue45;
architecture a of issue45 is
begin
b: block is
begin
p : process
begin
report p'instance_name;
report b'instance_name;
wait;
end process p;
end block;
end architecture a;
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity coproc_1 is
port(
clock : in std_logic;
reset : in std_logic;
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_1_valid : in std_logic;
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of coproc_1 is
SIGNAL mem : UNSIGNED(31 downto 0);
signal val0, val1, val2, val3, min, max , max_tmp, min_tmp: std_logic_vector(7 downto 0);
signal max01, max23, max0123, min01, min23, min0123: std_logic_vector(7 downto 0);
begin
-- Registres contenant les valeurs du min et du max courant
-- Quand reset actif, alors on initialise min et max
-- A chaque écriture dans le coproc, on met à jour le min et le max avec les 4 nouvelles valeurs
-------------------------------------------------------------------------
process (clock, reset)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
min <= (others => '1');
max <= (others => '0');
ELSE
IF INPUT_1_valid = '1' THEN
min <= min_tmp;
max <= max_tmp;
ELSE
min <= min;
max <= max;
END IF;
END IF;
END IF;
end process;
-------------------------------------------------------------------------
val0 <= INPUT_1(31 downto 24 );
val1 <= INPUT_1(23 downto 16 );
val2 <= INPUT_1(15 downto 8 );
val3 <= INPUT_1(7 downto 0 );
compute_max : process(max, val0, val1, val2, val3, max01, max23, max0123)
begin
if(val0 > val1) then
max01 <= val0;
else
max01 <= val1;
end if;
if(val2 > val3) then
max23 <= val2;
else
max23 <= val3;
end if;
if(max01 > max23) then
max0123 <= max01;
else
max0123 <= max23;
end if;
if(max0123 > max) then
max_tmp <= max0123;
else
max_tmp <= max;
end if;
end process;
compute_min : process(min, val0, val1, val2, val3, min01, min23, min0123)
begin
if(val0 < val1) then
min01 <= val0;
else
min01 <= val1;
end if;
if(val2 < val3) then
min23 <= val2;
else
min23 <= val3;
end if;
if(min01 < min23) then
min0123 <= min01;
else
min0123 <= min23;
end if;
if(min0123 < min) then
min_tmp <= min0123;
else
min_tmp <= min;
end if;
end process;
--OUTPUT_1 <= "0000000000000000"&min&max;
OUTPUT_1 <= "00000000000000000000000000000000";
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity coproc_1 is
port(
clock : in std_logic;
reset : in std_logic;
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_1_valid : in std_logic;
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of coproc_1 is
SIGNAL mem : UNSIGNED(31 downto 0);
signal val0, val1, val2, val3, min, max , max_tmp, min_tmp: std_logic_vector(7 downto 0);
signal max01, max23, max0123, min01, min23, min0123: std_logic_vector(7 downto 0);
begin
-- Registres contenant les valeurs du min et du max courant
-- Quand reset actif, alors on initialise min et max
-- A chaque écriture dans le coproc, on met à jour le min et le max avec les 4 nouvelles valeurs
-------------------------------------------------------------------------
process (clock, reset)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
min <= (others => '1');
max <= (others => '0');
ELSE
IF INPUT_1_valid = '1' THEN
min <= min_tmp;
max <= max_tmp;
ELSE
min <= min;
max <= max;
END IF;
END IF;
END IF;
end process;
-------------------------------------------------------------------------
val0 <= INPUT_1(31 downto 24 );
val1 <= INPUT_1(23 downto 16 );
val2 <= INPUT_1(15 downto 8 );
val3 <= INPUT_1(7 downto 0 );
compute_max : process(max, val0, val1, val2, val3, max01, max23, max0123)
begin
if(val0 > val1) then
max01 <= val0;
else
max01 <= val1;
end if;
if(val2 > val3) then
max23 <= val2;
else
max23 <= val3;
end if;
if(max01 > max23) then
max0123 <= max01;
else
max0123 <= max23;
end if;
if(max0123 > max) then
max_tmp <= max0123;
else
max_tmp <= max;
end if;
end process;
compute_min : process(min, val0, val1, val2, val3, min01, min23, min0123)
begin
if(val0 < val1) then
min01 <= val0;
else
min01 <= val1;
end if;
if(val2 < val3) then
min23 <= val2;
else
min23 <= val3;
end if;
if(min01 < min23) then
min0123 <= min01;
else
min0123 <= min23;
end if;
if(min0123 < min) then
min_tmp <= min0123;
else
min_tmp <= min;
end if;
end process;
--OUTPUT_1 <= "0000000000000000"&min&max;
OUTPUT_1 <= "00000000000000000000000000000000";
end; --architecture logic
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: target
-- File: target.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: LEON target configuration package
------------------------------------------------------------------------------
-- 29.01.02 Configuration of DDM. LA
-- 13.03.02 MDCT added. APB masters incremented by 1 in AHB configuration, and
-- mdct address added in APB configuration.
library IEEE;
use IEEE.std_logic_1164.all;
package target is
type targettechs is (gen, virtex, atc35, atc25, fs90, umc18);
-- synthesis configuration
type syn_config_type is record
targettech : targettechs;
infer_ram : boolean; -- infer cache ram automatically
infer_regf : boolean; -- infer regfile automatically
infer_rom : boolean; -- infer boot prom automatically
infer_pads : boolean; -- infer pads automatically
infer_mult : boolean; -- infer multiplier automatically
gatedclk : boolean; -- select clocking strategy
rftype : integer; -- regfile implementation option
end record;
-- processor configuration
type multypes is (none, iterative, m32x8, m16x16, m32x16, m32x32);
type divtypes is (none, radix2);
type iu_config_type is record
nwindows : integer; -- # register windows (2 - 32)
multiplier : multypes; -- multiplier type
divider : divtypes; -- divider type
mac : boolean; -- multiply/accumulate
fpuen : integer range 0 to 1; -- FPU enable (integer due to synopsys limitations....sigh!)
cpen : boolean; -- co-processor enable
fastjump : boolean; -- enable fast jump address generation
icchold : boolean; -- enable fast branch logic
lddelay : integer range 1 to 2; -- # load delay cycles (1-2)
fastdecode : boolean; -- optimise instruction decoding (FPGA only)
watchpoints : integer range 0 to 4; -- # hardware watchpoints (0-4)
impl : integer range 0 to 15; -- IU implementation ID
version : integer range 0 to 15; -- IU version ID
end record;
-- FPU configuration
type fputype is (none, meiko, fpc); -- FPU type
type fpu_config_type is record
fpu : fputype; -- FPU type
fregs : integer; -- 32 for internal meiko, 0 for external FPC
version : integer range 0 to 7; -- FPU version ID
end record;
-- co-processor configuration
type cptype is (none, cpc); -- CP type
type cp_config_type is record
cp : cptype; -- Co-processor type
version : integer range 0 to 7; -- CP version ID
-- add your CP-specific configuration options here!!
end record;
-- cache configuration
type cache_config_type is record
icachesize : integer; -- size of I-cache in Kbytes
ilinesize : integer; -- # words per I-cache line
dcachesize : integer; -- size of D-cache in Kbytes
dlinesize : integer; -- # words per D-cache line
end record;
-- memory controller configuration
type mctrl_config_type is record
bus8en : boolean; -- enable 8-bit bus operation
bus16en : boolean; -- enable 16-bit bus operation
rawaddr : boolean; -- enable unlatched address option
end record;
type boottype is (memory, prom, dual);
type boot_config_type is record
boot : boottype; -- select boot source
ramrws : integer range 0 to 3; -- ram read waitstates
ramwws : integer range 0 to 3; -- ram write waitstates
sysclk : integer; -- cpu clock
baud : positive; -- UART baud rate
extbaud : boolean; -- use external baud rate setting
pabits : positive; -- internal boot-prom address bits
end record;
-- PCI configuration
type pcitype is (none, insilicon, esa, ahbtst); -- PCI core type
type pci_config_type is record
pcicore : pcitype; -- PCI core type
ahbmasters : integer; -- number of ahb master interfaces
ahbslaves : integer; -- number of ahb slave interfaces
arbiter : boolean; -- enable PCI arbiter
fixpri : boolean; -- use fixed arbitration priority
prilevels : integer; -- number of priority levels in arbiter
pcimasters : integer; -- number of PCI masters to be handled by arbiter
vendorid : integer; -- PCI vendor ID
deviceid : integer; -- PCI device ID
subsysid : integer; -- PCI subsystem ID
revisionid : integer; -- PCI revision ID
classcode : integer; -- PCI class code
pmepads : boolean; -- enable power down pads
p66pad : boolean; -- enable PCI66 pad
end record;
-- debug configuration
type debug_config_type is record
enable : boolean; -- enable debug port
uart : boolean; -- enable fast uart data to console
iureg : boolean; -- enable tracing of iu register writes
fpureg : boolean; -- enable tracing of fpu register writes
nohalt : boolean; -- dont halt on error
pclow : integer; -- set to 2 for synthesis, 0 for debug
end record;
-- AMBA configuration types
constant AHB_MST_MAX : integer := 4; -- maximum AHB masters
constant AHB_SLV_MAX : integer := 7; -- maximum AHB slaves
constant AHB_SLV_ADDR_MSB : integer := 4; -- MSB address bits to decode slaves
constant AHB_CACHE_MAX : integer := 4; -- maximum cacheability ranges
constant AHB_CACHE_ADDR_MSB : integer := 3; -- MSB address bits to decode cacheability
subtype ahb_range_addr_type is std_logic_vector(AHB_SLV_ADDR_MSB-1 downto 0);
subtype ahb_cache_addr_type is std_logic_vector(AHB_CACHE_ADDR_MSB-1 downto 0);
type ahb_slv_config_type is record
firstaddr : ahb_range_addr_type;
lastaddr : ahb_range_addr_type;
index : integer range 0 to AHB_SLV_MAX-1;
split : boolean;
enable : boolean;
end record;
type ahb_slv_config_vector is array (Natural Range <> ) of ahb_slv_config_type;
constant ahb_slv_config_void : ahb_slv_config_type :=
((others => '0'), (others => '0'), 0, false, false);
type ahb_cache_config_type is record
firstaddr : ahb_cache_addr_type;
lastaddr : ahb_cache_addr_type;
end record;
type ahb_cache_config_vector is array (Natural Range <> ) of ahb_cache_config_type;
constant ahb_cache_config_void : ahb_cache_config_type :=
((others => '0'), (others => '0'));
type ahb_config_type is record
masters : integer range 1 to AHB_MST_MAX;
defmst : integer range 0 to AHB_MST_MAX-1;
split : boolean; -- add support for SPLIT reponse
slvtable : ahb_slv_config_vector(0 to AHB_SLV_MAX-1);
cachetable : ahb_cache_config_vector(0 to AHB_CACHE_MAX-1);
end record;
constant APB_SLV_MAX : integer := 16; -- maximum APB slaves
constant APB_SLV_ADDR_BITS : integer := 10; -- address bits to decode APB slaves
subtype apb_range_addr_type is std_logic_vector(APB_SLV_ADDR_BITS-1 downto 0);
type apb_slv_config_type is record
firstaddr : apb_range_addr_type;
lastaddr : apb_range_addr_type;
index : integer;
enable : boolean;
end record;
type apb_slv_config_vector is array (Natural Range <> ) of apb_slv_config_type;
constant apb_slv_config_void : apb_slv_config_type :=
((others => '0'), (others => '0'), 0, false);
type apb_config_type is record
table : apb_slv_config_vector(0 to APB_SLV_MAX-1);
end record;
type irq_filter_type is (lvl0, lvl1, edge0, edge1);
type irq_filter_vec is array (0 to 31) of irq_filter_type;
type irq2type is record
enable : boolean; -- enable chained interrupt controller
channels : integer; -- number of additional interrupts (1 - 32)
filter : irq_filter_vec; -- irq filter definitions
end record;
type peri_config_type is record
cfgreg : boolean; -- enable LEON configuration register
ahbstat : boolean; -- enable AHB status register
wprot : boolean; -- enable RAM write-protection unit
wdog : boolean; -- enable watchdog
irq2cfg : irq2type; -- chained interrupt controller config
end record;
-- complete configuration record type
type config_type is record
synthesis : syn_config_type;
iu : iu_config_type;
fpu : fpu_config_type;
cp : cp_config_type;
cache : cache_config_type;
ahb : ahb_config_type;
apb : apb_config_type;
mctrl : mctrl_config_type;
boot : boot_config_type;
debug : debug_config_type;
pci : pci_config_type;
peri : peri_config_type;
end record;
----------------------------------------------------------------------------
-- Synthesis configurations
----------------------------------------------------------------------------
constant syn_atc25 : syn_config_type := (
targettech => atc25, infer_pads => false,
infer_ram => false, infer_regf => false, infer_rom => true,
infer_mult => false, gatedclk => false, rftype => 1);
constant syn_atc35 : syn_config_type := (
targettech => atc35, infer_pads => false,
infer_ram => false, infer_regf => false, infer_rom => true,
infer_mult => false, gatedclk => false, rftype => 1);
constant syn_gen : syn_config_type := (
targettech => gen, infer_pads => true,
infer_ram => true, infer_regf => true, infer_rom => true,
infer_mult => true, gatedclk => false, rftype => 1);
constant syn_virtex : syn_config_type := (
targettech => virtex, infer_pads => true,
infer_ram => false, infer_regf => false, infer_rom => true,
infer_mult => true, gatedclk => false, rftype => 1);
constant syn_virtex_blockprom : syn_config_type := (
targettech => virtex, infer_pads => true,
infer_ram => false, infer_regf => false, infer_rom => false,
infer_mult => true, gatedclk => false, rftype => 1);
constant syn_systel_asic : syn_config_type := (
targettech => atc25, infer_pads => false,
infer_ram => false, infer_regf => false, infer_rom => true,
infer_mult => false, gatedclk => false, rftype => 1);
constant syn_fs90 : syn_config_type := (
targettech => fs90, infer_pads => false,
infer_ram => false, infer_regf => false, infer_rom => true,
infer_mult => false, gatedclk => false, rftype => 1);
constant syn_umc18 : syn_config_type := (
targettech => umc18, infer_pads => false,
infer_ram => false, infer_regf => false, infer_rom => true,
-- infer_multgates => false,
infer_mult => false, gatedclk => false, rftype => 1);
----------------------------------------------------------------------------
-- IU configurations
----------------------------------------------------------------------------
constant iu_std : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => false,
fpuen => 0, cpen => false, fastjump => true, icchold => false, lddelay => 1,
fastdecode => false, watchpoints => 0, impl => 0, version => 0);
constant iu_std_mac : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => true,
fpuen => 0, cpen => false, fastjump => true, icchold => false, lddelay => 1,
fastdecode => false, watchpoints => 0, impl => 0, version => 0);
constant iu_fpu : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => false,
fpuen => 1, cpen => false, fastjump => false, icchold => false, lddelay => 1,
fastdecode => false, watchpoints => 0, impl => 0, version => 0);
constant iu_fpga : iu_config_type := (
nwindows => 8, multiplier => none, divider => none, mac => false,
fpuen => 0, cpen => false, fastjump => true, icchold => true, lddelay => 1,
fastdecode => true, watchpoints => 0, impl => 0, version => 0);
constant iu_fpga_v8 : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => false,
fpuen => 0, cpen => false, fastjump => true, icchold => true, lddelay => 1,
fastdecode => true, watchpoints => 0, impl => 0, version => 0);
constant iu_fpga_v8_fpu : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => false,
fpuen => 1, cpen => false, fastjump => true, icchold => true, lddelay => 1,
fastdecode => true, watchpoints => 0, impl => 0, version => 0);
constant iu_fpga_v8_mac : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => true,
fpuen => 0, cpen => false, fastjump => true, icchold => true, lddelay => 1,
fastdecode => true, watchpoints => 0, impl => 0, version => 0);
constant iu_fpga_v8_small : iu_config_type := (
nwindows => 8, multiplier => iterative, divider => radix2, mac => false,
fpuen => 0, cpen => false, fastjump => true, icchold => true, lddelay => 1,
fastdecode => true, watchpoints => 0, impl => 0, version => 0);
constant iu_atc25 : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => true,
fpuen => 0, cpen => false, fastjump => true, icchold => false, lddelay => 1,
fastdecode => false, watchpoints => 2, impl => 0, version => 0);
constant iu_atc25_fpu : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => true,
fpuen => 1, cpen => false, fastjump => true, icchold => false, lddelay => 1,
fastdecode => false, watchpoints => 2, impl => 0, version => 0);
----------------------------------------------------------------------------
-- FPU configurations
----------------------------------------------------------------------------
constant fpu_none : fpu_config_type := (fpu => none, fregs => 0, version => 0);
constant fpu_meiko: fpu_config_type := (fpu => meiko, fregs => 32, version => 0);
constant fpu_fpc : fpu_config_type := (fpu => fpc, fregs => 0, version => 0);
----------------------------------------------------------------------------
-- CP configurations
----------------------------------------------------------------------------
constant cp_none : cp_config_type := (cp => none, version => 0);
constant cp_cpc : cp_config_type := (cp => cpc, version => 0);
----------------------------------------------------------------------------
-- cache configurations
----------------------------------------------------------------------------
constant cache_1k1k : cache_config_type := (
icachesize => 1, ilinesize => 4, dcachesize => 1, dlinesize => 4);
constant cache_2k1k : cache_config_type := (
icachesize => 2, ilinesize => 4, dcachesize => 1, dlinesize => 4);
constant cache_2k2k : cache_config_type := (
icachesize => 2, ilinesize => 4, dcachesize => 2, dlinesize => 4);
constant cache_2kl8_2kl4 : cache_config_type := (
icachesize => 2, ilinesize => 8, dcachesize => 2, dlinesize => 4);
constant cache_4k2k : cache_config_type := (
icachesize => 4, ilinesize => 8, dcachesize => 2, dlinesize => 4);
constant cache_1k4k : cache_config_type := (
icachesize => 1, ilinesize => 4, dcachesize => 4, dlinesize => 4);
constant cache_4k4k : cache_config_type := (
icachesize => 4, ilinesize => 4, dcachesize => 4, dlinesize => 4);
constant cache_8k8k : cache_config_type := (
icachesize => 8, ilinesize => 8, dcachesize => 8, dlinesize => 4);
----------------------------------------------------------------------------
-- Memory controller configurations
----------------------------------------------------------------------------
constant mctrl_std : mctrl_config_type := (
bus8en => true, bus16en => true, rawaddr => false);
constant mctrl_mem32 : mctrl_config_type := (
bus8en => false, bus16en => false, rawaddr => false);
constant mctrl_mem16 : mctrl_config_type := (
bus8en => false, bus16en => true, rawaddr => false);
----------------------------------------------------------------------------
-- boot configurations
----------------------------------------------------------------------------
constant boot_mem_25M : boot_config_type := (boot => memory, ramrws => 0,
ramwws => 0, sysclk => 24576000, baud => 38400, extbaud => false,
pabits => 8); -- 21.02.02 Booting system with 25 MHZ LA
constant boot_mem_33M : boot_config_type := (boot => memory, ramrws => 0,
ramwws => 0, sysclk => 33333333, baud => 38400, extbaud => false,
pabits => 8); -- 15.02.02 Booting system with 33.3 MHZ LA
constant boot_mem : boot_config_type := (boot => memory, ramrws => 0,
ramwws => 0, sysclk => 1000000, baud => 19200, extbaud => false,
pabits => 8);
constant boot_pmon : boot_config_type := (boot => prom, ramrws => 0,
ramwws => 0, sysclk => 24576000, baud => 38400, extbaud=> false,
pabits => 8);
constant boot_rdbmon : boot_config_type := (boot => prom, ramrws => 0,
ramwws => 0, sysclk => 24576000, baud => 38400, extbaud=> false,
pabits => 11);
constant boot_prom_xess16 : boot_config_type := (boot => prom, ramrws => 0,
ramwws => 0, sysclk => 25000000, baud => 38400, extbaud=> false,
pabits => 8);
----------------------------------------------------------------------------
-- PCI configurations
----------------------------------------------------------------------------
-- NOTE: 0x16E3 is ESA vendor ID - do NOT use without authorisation!!
-- NOTE: 0x1438 is ATMEL vendor ID - do NOT use without authorisation!!
constant pci_none : pci_config_type := (
pcicore => none, ahbmasters => 0, ahbslaves => 0,
arbiter => false, fixpri => false, prilevels => 4, pcimasters => 4,
vendorid => 16#16E3#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
constant pci_test : pci_config_type := (
pcicore => ahbtst, ahbmasters => 2, ahbslaves => 1,
arbiter => false, fixpri => true, prilevels => 4, pcimasters => 4,
vendorid => 16#16E3#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
constant pci_insilicon : pci_config_type := (
pcicore => insilicon, ahbmasters => 2, ahbslaves => 1,
arbiter => true, fixpri => false, prilevels => 4, pcimasters => 4,
vendorid => 16#16E3#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
constant pci_esaif : pci_config_type := (
pcicore => esa, ahbmasters => 1, ahbslaves => 1,
arbiter => true, fixpri => false, prilevels => 4, pcimasters => 4,
vendorid => 16#16E3#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
constant pci_ahb_test : pci_config_type := (
pcicore => ahbtst, ahbmasters => 0, ahbslaves => 1,
arbiter => false, fixpri => true, prilevels => 4, pcimasters => 4,
vendorid => 16#16E3#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
constant pci_atc25 : pci_config_type := (
pcicore => ahbtst, ahbmasters => 2, ahbslaves => 1,
arbiter => true, fixpri => false, prilevels => 4, pcimasters => 4,
vendorid => 16#16E3#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
-- In-Silicon PCI core in ATMEL configuration
constant pci_atmel : pci_config_type := (
pcicore => insilicon, ahbmasters => 2, ahbslaves => 1,
arbiter => true, fixpri => false, prilevels => 4, pcimasters => 4,
vendorid => 16#1438#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
----------------------------------------------------------------------------
-- Peripherals configurations
----------------------------------------------------------------------------
constant irq2none : irq2type := ( enable => false, channels => 32,
filter => (others => lvl0));
constant irq2chan4 : irq2type := ( enable => true, channels => 4,
filter => (lvl0, lvl1, edge0, edge1, others => lvl0));
constant peri_std : peri_config_type := (
cfgreg => true, ahbstat => true, wprot => true, wdog => true,
irq2cfg => irq2none);
constant peri_fpga : peri_config_type := (
cfgreg => true, ahbstat => false, wprot => false, wdog => false,
irq2cfg => irq2none);
constant peri_irq2 : peri_config_type := (
cfgreg => true, ahbstat => false, wprot => false, wdog => false,
irq2cfg => irq2chan4);
----------------------------------------------------------------------------
-- Debug configurations
----------------------------------------------------------------------------
constant debug_none : debug_config_type := ( enable => false, uart => false,
iureg => false, fpureg => false, nohalt => false, pclow => 2);
constant debug_disas : debug_config_type := ( enable => true, uart => false,
iureg => false, fpureg => false, nohalt => false, pclow => 2);
constant debug_msp : debug_config_type := ( enable => true, uart => false,
iureg => false, fpureg => false, nohalt => true, pclow => 2);
constant debug_uart : debug_config_type := ( enable => true, uart => true,
iureg => false, fpureg => false, nohalt => false, pclow => 0);
constant debug_fpu : debug_config_type := ( enable => true, uart => true,
iureg => false, fpureg => true, nohalt => false, pclow => 2);
constant debug_all : debug_config_type := ( enable => true, uart => true,
iureg => true, fpureg => true, nohalt => false, pclow => 0);
----------------------------------------------------------------------------
-- Amba AHB configurations
----------------------------------------------------------------------------
-- standard slave config
constant ahbslvcfg_std : ahb_slv_config_vector(0 to AHB_SLV_MAX-1) := (
-- first last index split enable function HADDR[31:28]
("0000", "0111", 0, false, true), -- memory controller, 0x0- 0x7
("1000", "1000", 1, false, true), -- APB bridge, 256 MB 0x8- 0x8
others => ahb_slv_config_void);
-- AHB test slave config
constant ahbslvcfg_test : ahb_slv_config_vector(0 to AHB_SLV_MAX-1) := (
-- first last index split enable function HADDR[31:28]
("0000", "0111", 0, false, true), -- memory controller, 0x0- 0x7
("1000", "1000", 1, false, true), -- APB bridge, 128 MB 0x8- 0x8
("1010", "1010", 2, true, true), -- AHB test module 0xA- 0xA
("1100", "1111", 3, false, true), -- PCI initiator 0xC- 0xF
others => ahb_slv_config_void);
-- PCI slave config
constant ahbslvcfg_pci : ahb_slv_config_vector(0 to AHB_SLV_MAX-1) := (
-- first last index split enable function HADDR[31:28]
("0000", "0111", 0, false, true), -- memory controller, 0x0- 0x7
("1000", "1000", 1, false, true), -- APB bridge, 128 MB 0x8- 0x8
("1010", "1111", 2, false, true), -- PCI initiator 0xA- 0xF
others => ahb_slv_config_void);
-- standard cacheability config
constant ahbcachecfg_std : ahb_cache_config_vector(0 to AHB_CACHE_MAX-1) := (
-- first last function HADDR[31:29]
("000", "000"), -- PROM area 0x0- 0x0
("010", "011"), -- RAM area 0x2- 0x3
others => ahb_cache_config_void);
-- standard config record
constant ahb_std : ahb_config_type := (
masters => 3, defmst => 0, split => false, -- masters increased by 2 for DDM & mdct. LA
slvtable => ahbslvcfg_std, cachetable => ahbcachecfg_std);
-- FPGA config record
constant ahb_fpga : ahb_config_type := (
masters => 3, defmst => 0, split => false, -- masters increased by 2 for DDM & mdct. LA
slvtable => ahbslvcfg_std, cachetable => ahbcachecfg_std);
-- Phoenix PCI core config record (uses two AHB master instefaces)
constant ahb_insilicon_pci : ahb_config_type := (
masters => 5, defmst => 0, split => false, -- masters increased by 2 for DDM & mdct. LA
slvtable => ahbslvcfg_pci, cachetable => ahbcachecfg_std);
-- ESTEC PCI core config record (uses one AHB master insteface)
constant ahb_esa_pci : ahb_config_type := (
masters => 4, defmst => 0, split => false, -- masters increased by 2 for DDM & mdct. LA
slvtable => ahbslvcfg_pci, cachetable => ahbcachecfg_std);
-- AHB test config
constant ahb_test : ahb_config_type := (
masters => 5, defmst => 0, split => true, -- masters increased by 2 for DDM & mdct. LA
slvtable => ahbslvcfg_test, cachetable => ahbcachecfg_std);
----------------------------------------------------------------------------
-- Amba APB configurations
----------------------------------------------------------------------------
-- standard config
constant apbslvcfg_std : apb_slv_config_vector(0 to APB_SLV_MAX-1) := (
-- first last index enable function PADDR[9:0]
( "0000000000", "0000001000", 0, true), -- memory controller, 0x00 - 0x08
( "0000001100", "0000010000", 1, true), -- AHB status reg., 0x0C - 0x10
( "0000010100", "0000011000", 2, true), -- cache controller, 0x14 - 0x18
( "0000011100", "0000100000", 3, true), -- write protection, 0x1C - 0x20
( "0000100100", "0000100100", 4, true), -- config register, 0x24 - 0x24
( "0001000000", "0001101100", 5, true), -- timers, 0x40 - 0x6C
( "0001110000", "0001111100", 6, true), -- uart1, 0x70 - 0x7C
( "0010000000", "0010001100", 7, true), -- uart2, 0x80 - 0x8C
( "0010010000", "0010011100", 8, true), -- interrupt ctrl 0x90 - 0x9C
( "0010100000", "0010101100", 9, true), -- I/O port 0xA0 - 0xAC
( "0100000000", "0111111100", 10, false), -- PCI configuration 0x100 - 0x1FC
( "1000000000", "1000011000", 11, true), -- ddm 0x200 - 0x218
( "1100000000", "1100011000", 12, true), -- mdct 0x300 - 0x318
others => apb_slv_config_void);
-- standard config with secondary interrupt controller
constant apbslvcfg_irq2 : apb_slv_config_vector(0 to APB_SLV_MAX-1) := (
-- first last index enable function PADDR[9:0]
( "0000000000", "0000001000", 0, true), -- memory controller, 0x00 - 0x08
( "0000001100", "0000010000", 1, true), -- AHB status reg., 0x0C - 0x10
( "0000010100", "0000011000", 2, true), -- cache controller, 0x14 - 0x18
( "0000011100", "0000100000", 3, true), -- write protection, 0x1C - 0x20
( "0000100100", "0000100100", 4, true), -- config register, 0x24 - 0x24
( "0001000000", "0001101100", 5, true), -- timers, 0x40 - 0x6C
( "0001110000", "0001111100", 6, true), -- uart1, 0x70 - 0x7C
( "0010000000", "0010001100", 7, true), -- uart2, 0x80 - 0x8C
( "0010010000", "0010011100", 8, true), -- interrupt ctrl 0x90 - 0x9C
( "0010100000", "0010101100", 9, true), -- I/O port 0xA0 - 0xAC
( "0010110000", "0010111100", 10, true), -- 2nd interrupt ctrl 0xB0 - 0xBC
( "1000000000", "1000011000", 11, true), -- ddm 0x200 - 0x218
( "1100000000", "1100011000", 12, true), -- mdct 0x300 - 0x318
others => apb_slv_config_void);
-- PCI config
constant apbslvcfg_pci : apb_slv_config_vector(0 to APB_SLV_MAX-1) := (
-- first last index enable function PADDR[9:0]
( "0000000000", "0000001000", 0, true), -- memory controller, 0x00 - 0x08
( "0000001100", "0000010000", 1, true), -- AHB status reg., 0x0C - 0x10
( "0000010100", "0000011000", 2, true), -- cache controller, 0x14 - 0x18
( "0000011100", "0000100000", 3, true), -- write protection, 0x1C - 0x20
( "0000100100", "0000100100", 4, true), -- config register, 0x24 - 0x24
( "0001000000", "0001101100", 5, true), -- timers, 0x40 - 0x6C
( "0001110000", "0001111100", 6, true), -- uart1, 0x70 - 0x7C
( "0010000000", "0010001100", 7, true), -- uart2, 0x80 - 0x8C
( "0010010000", "0010011100", 8, true), -- interrupt ctrl 0x90 - 0x9C
( "0010100000", "0010101100", 9, true), -- I/O port 0xA0 - 0xAC
( "0100000000", "0111111100", 10, true), -- PCI configuration 0x100- 0x1FC
( "1000000000", "1011111100", 11, true), -- PCI arbiter 0x200- 0x2FC
others => apb_slv_config_void);
constant apb_std : apb_config_type := (table => apbslvcfg_std);
constant apb_irq2 : apb_config_type := (table => apbslvcfg_irq2);
constant apb_pci : apb_config_type := (table => apbslvcfg_pci);
----------------------------------------------------------------------------
-- Pre-defined LEON configurations
----------------------------------------------------------------------------
-- VIRTEX, 2 + 2 Kbyte cache, fpu
constant virtex_2k2k_25M_fpu : config_type := (
synthesis => syn_virtex, iu => iu_fpga_v8_fpu, fpu => fpu_meiko, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem_25M, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 4 + 4 Kbyte cache, mul/div, fpu, 25M
constant fpga_4k4k_v8_fpu_33M : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8_fpu, fpu => fpu_meiko, cp => cp_none,
cache => cache_4k4k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem_33M, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache 25 MHz
constant fpga_2k2k_25M : config_type := (
synthesis => syn_gen, iu => iu_fpga, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem_25M, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache 33.3 MHz
constant fpga_2k2k_33M : config_type := (
synthesis => syn_gen, iu => iu_fpga, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem_33M, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache
constant fpga_2k2k : config_type := (
synthesis => syn_gen, iu => iu_fpga, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache, mul/div
constant fpga_2k2k_v8 : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache, secondary irq controller (test only)
constant fpga_2k2k_irq2 : config_type := (
synthesis => syn_gen, iu => iu_fpga, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_irq2, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_irq2);
-- Any FPGA, 2 + 2 Kbyte cache, inferred boot-prom
constant fpga_2k2k_softprom : config_type := (
synthesis => syn_gen, iu => iu_fpga, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_pmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache, inferred boot-prom, mul/div
constant fpga_2k2k_v8_softprom : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_pmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 4 + 4 Kbyte cache, mul/div, fpu
constant fpga_4k4k_v8_fpu : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8_fpu, fpu => fpu_meiko, cp => cp_none,
cache => cache_4k4k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem_25M, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 4 + 4 Kbyte cache, inferred boot-prom, mul/div, fpu
constant fpga_4k4k_v8_fpu_softprom : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8_fpu, fpu => fpu_meiko, cp => cp_none,
cache => cache_4k4k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_pmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache, inferred boot-prom, mul/div, MAC
constant fpga_2k2k_v8_mac_softprom : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8_mac, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_pmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- VIRTEX, 2 + 2 Kbyte cache, hard boot-prom
constant virtex_2k2k_blockprom : config_type := (
synthesis => syn_virtex_blockprom, iu => iu_fpga_v8_fpu, fpu => fpu_meiko, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_pmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- VIRTEX, 2 + 1 Kbyte cache, hard boot-prom with rdbmon
constant virtex_2k1k_rdbmon : config_type := (
synthesis => syn_virtex_blockprom, iu => iu_fpga, fpu => fpu_none, cp => cp_none,
cache => cache_2k1k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_rdbmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- VIRTEX, 2 + 2 Kbyte cache, hard boot-prom, mul/div
constant virtex_2k2k_v8_blockprom : config_type := (
synthesis => syn_virtex_blockprom, iu => iu_fpga_v8, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_pmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- synthesis targetting ATC25 asic lib
constant gen_atc25 : config_type := (
synthesis => syn_atc25, iu => iu_atc25, fpu => fpu_none, cp => cp_none,
cache => cache_8k8k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- synthesis targetting ATC25 asic lib, serial Meiko FPU
constant gen_atc25_meiko : config_type := (
synthesis => syn_atc25, iu => iu_atc25_fpu, fpu => fpu_meiko, cp => cp_none,
cache => cache_8k8k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- synthesis targetting ATC25 asic lib, parallel FPU
constant gen_atc25_fpc : config_type := (
synthesis => syn_atc25, iu => iu_atc25_fpu, fpu => fpu_fpc, cp => cp_none,
cache => cache_8k8k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- synthesis targetting ATC25 asic lib + Insilicon PCI core
constant gen_atc25_insilicon_pci : config_type := (
synthesis => syn_atc25, iu => iu_std, fpu => fpu_none, cp => cp_none,
cache => cache_4k4k, ahb => ahb_insilicon_pci, apb => apb_pci,
mctrl => mctrl_std, boot => boot_mem, debug => debug_disas, pci => pci_atmel,
peri => peri_std);
-- simulatiom with Insilicon PCI core
constant gen_insilicon_pci : config_type := (
synthesis => syn_gen, iu => iu_std, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_insilicon_pci, apb => apb_pci,
mctrl => mctrl_std, boot => boot_mem, debug => debug_disas, pci => pci_atmel,
peri => peri_std);
-- synthesis targetting ATC35 asic lib, synopsys
constant gen_atc35 : config_type := (
synthesis => syn_atc35, iu => iu_std, fpu => fpu_none, cp => cp_none,
cache => cache_4k4k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- Systel FPGA configuration
constant systel_fpga : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8, fpu => fpu_none, cp => cp_none,
cache => cache_1k1k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- Systel ASIC configuration
constant systel_asic : config_type := (
synthesis => syn_systel_asic, iu => iu_std, fpu => fpu_none, cp => cp_none,
cache => cache_1k1k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- synthesis targetting UMC FS90A/B asic lib
constant gen_fs90 : config_type := (
synthesis => syn_fs90, iu => iu_std, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- synthesis targetting UMC18 asic lib, synopsys + AMBIT
constant gen_umc18 : config_type := (
synthesis => syn_umc18, iu => iu_std, fpu => fpu_none, cp => cp_none,
cache => cache_4k4k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
end;
|
process(S,R)
begin
if(R = '1') then
Q <= '0';
elsif(S = '1') then
Q <= '1';
end if;
end process;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08/14/2014 12:18:30 PM
-- Design Name:
-- Module Name: tb_vhdl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlconstant;
ENTITY Program_Counter_Constant_0_0 IS
PORT (
dout : OUT STD_LOGIC_VECTOR(10-1 DOWNTO 0)
);
END Program_Counter_Constant_0_0;
ARCHITECTURE Program_Counter_Constant_0_0_arch OF Program_Counter_Constant_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Program_Counter_Constant_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlconstant IS
GENERIC (
CONST_VAL : STD_LOGIC_VECTOR(10-1 DOWNTO 0);
CONST_WIDTH : INTEGER
);
PORT (
dout : OUT STD_LOGIC_VECTOR(10-1 DOWNTO 0)
);
END COMPONENT xlconstant;
BEGIN
U0 : xlconstant
GENERIC MAP (
CONST_VAL => "1111111111",
CONST_WIDTH => 10
)
PORT MAP (
dout => dout
);
END Program_Counter_Constant_0_0_arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08/14/2014 12:18:30 PM
-- Design Name:
-- Module Name: tb_vhdl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlconstant;
ENTITY Program_Counter_Constant_0_0 IS
PORT (
dout : OUT STD_LOGIC_VECTOR(10-1 DOWNTO 0)
);
END Program_Counter_Constant_0_0;
ARCHITECTURE Program_Counter_Constant_0_0_arch OF Program_Counter_Constant_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Program_Counter_Constant_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlconstant IS
GENERIC (
CONST_VAL : STD_LOGIC_VECTOR(10-1 DOWNTO 0);
CONST_WIDTH : INTEGER
);
PORT (
dout : OUT STD_LOGIC_VECTOR(10-1 DOWNTO 0)
);
END COMPONENT xlconstant;
BEGIN
U0 : xlconstant
GENERIC MAP (
CONST_VAL => "1111111111",
CONST_WIDTH => 10
)
PORT MAP (
dout => dout
);
END Program_Counter_Constant_0_0_arch;
|
-------------------------------------------------------------------------------
-- $Id: or_gate128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate128.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate128.vhd
-- Version: v1.00a
-- Description: OR gate implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate128.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
-- GAB 07/11/05
-- ^^^^^^
-- Adjusted range on C_BUS_WIDTH to support 128 bit dwidths
-- Renamed to or_gate128.vhd
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate128 is
generic (
C_OR_WIDTH : natural range 1 to 32 := 17;
C_BUS_WIDTH : natural range 1 to 128 := 1;
C_USE_LUT_OR : boolean := TRUE
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate128;
architecture imp of or_gate128 is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component or_muxcy
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end component or_muxcy;
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
USE_LUT_OR_GEN: if C_USE_LUT_OR generate
OR_PROCESS: process( A ) is
variable yi : std_logic_vector(0 to (C_OR_WIDTH));
begin
for j in 0 to C_BUS_WIDTH-1 loop
yi(0) := '0';
for i in 0 to C_OR_WIDTH-1 loop
yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j);
end loop;
Y(j) <= yi(C_OR_WIDTH);
end loop;
end process OR_PROCESS;
end generate USE_LUT_OR_GEN;
USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: or_muxcy
generic map (
C_NUM_BITS => C_OR_WIDTH
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end generate USE_MUXCY_OR_GEN;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: or_gate128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate128.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate128.vhd
-- Version: v1.00a
-- Description: OR gate implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate128.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
-- GAB 07/11/05
-- ^^^^^^
-- Adjusted range on C_BUS_WIDTH to support 128 bit dwidths
-- Renamed to or_gate128.vhd
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate128 is
generic (
C_OR_WIDTH : natural range 1 to 32 := 17;
C_BUS_WIDTH : natural range 1 to 128 := 1;
C_USE_LUT_OR : boolean := TRUE
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate128;
architecture imp of or_gate128 is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component or_muxcy
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end component or_muxcy;
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
USE_LUT_OR_GEN: if C_USE_LUT_OR generate
OR_PROCESS: process( A ) is
variable yi : std_logic_vector(0 to (C_OR_WIDTH));
begin
for j in 0 to C_BUS_WIDTH-1 loop
yi(0) := '0';
for i in 0 to C_OR_WIDTH-1 loop
yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j);
end loop;
Y(j) <= yi(C_OR_WIDTH);
end loop;
end process OR_PROCESS;
end generate USE_LUT_OR_GEN;
USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: or_muxcy
generic map (
C_NUM_BITS => C_OR_WIDTH
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end generate USE_MUXCY_OR_GEN;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: or_gate128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate128.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate128.vhd
-- Version: v1.00a
-- Description: OR gate implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate128.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
-- GAB 07/11/05
-- ^^^^^^
-- Adjusted range on C_BUS_WIDTH to support 128 bit dwidths
-- Renamed to or_gate128.vhd
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate128 is
generic (
C_OR_WIDTH : natural range 1 to 32 := 17;
C_BUS_WIDTH : natural range 1 to 128 := 1;
C_USE_LUT_OR : boolean := TRUE
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate128;
architecture imp of or_gate128 is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component or_muxcy
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end component or_muxcy;
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
USE_LUT_OR_GEN: if C_USE_LUT_OR generate
OR_PROCESS: process( A ) is
variable yi : std_logic_vector(0 to (C_OR_WIDTH));
begin
for j in 0 to C_BUS_WIDTH-1 loop
yi(0) := '0';
for i in 0 to C_OR_WIDTH-1 loop
yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j);
end loop;
Y(j) <= yi(C_OR_WIDTH);
end loop;
end process OR_PROCESS;
end generate USE_LUT_OR_GEN;
USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: or_muxcy
generic map (
C_NUM_BITS => C_OR_WIDTH
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end generate USE_MUXCY_OR_GEN;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: or_gate128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate128.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate128.vhd
-- Version: v1.00a
-- Description: OR gate implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate128.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
-- GAB 07/11/05
-- ^^^^^^
-- Adjusted range on C_BUS_WIDTH to support 128 bit dwidths
-- Renamed to or_gate128.vhd
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate128 is
generic (
C_OR_WIDTH : natural range 1 to 32 := 17;
C_BUS_WIDTH : natural range 1 to 128 := 1;
C_USE_LUT_OR : boolean := TRUE
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate128;
architecture imp of or_gate128 is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component or_muxcy
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end component or_muxcy;
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
USE_LUT_OR_GEN: if C_USE_LUT_OR generate
OR_PROCESS: process( A ) is
variable yi : std_logic_vector(0 to (C_OR_WIDTH));
begin
for j in 0 to C_BUS_WIDTH-1 loop
yi(0) := '0';
for i in 0 to C_OR_WIDTH-1 loop
yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j);
end loop;
Y(j) <= yi(C_OR_WIDTH);
end loop;
end process OR_PROCESS;
end generate USE_LUT_OR_GEN;
USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: or_muxcy
generic map (
C_NUM_BITS => C_OR_WIDTH
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end generate USE_MUXCY_OR_GEN;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: or_gate128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate128.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate128.vhd
-- Version: v1.00a
-- Description: OR gate implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate128.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
-- GAB 07/11/05
-- ^^^^^^
-- Adjusted range on C_BUS_WIDTH to support 128 bit dwidths
-- Renamed to or_gate128.vhd
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate128 is
generic (
C_OR_WIDTH : natural range 1 to 32 := 17;
C_BUS_WIDTH : natural range 1 to 128 := 1;
C_USE_LUT_OR : boolean := TRUE
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate128;
architecture imp of or_gate128 is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component or_muxcy
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end component or_muxcy;
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
USE_LUT_OR_GEN: if C_USE_LUT_OR generate
OR_PROCESS: process( A ) is
variable yi : std_logic_vector(0 to (C_OR_WIDTH));
begin
for j in 0 to C_BUS_WIDTH-1 loop
yi(0) := '0';
for i in 0 to C_OR_WIDTH-1 loop
yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j);
end loop;
Y(j) <= yi(C_OR_WIDTH);
end loop;
end process OR_PROCESS;
end generate USE_LUT_OR_GEN;
USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: or_muxcy
generic map (
C_NUM_BITS => C_OR_WIDTH
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end generate USE_MUXCY_OR_GEN;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: or_gate128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate128.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate128.vhd
-- Version: v1.00a
-- Description: OR gate implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate128.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
-- GAB 07/11/05
-- ^^^^^^
-- Adjusted range on C_BUS_WIDTH to support 128 bit dwidths
-- Renamed to or_gate128.vhd
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate128 is
generic (
C_OR_WIDTH : natural range 1 to 32 := 17;
C_BUS_WIDTH : natural range 1 to 128 := 1;
C_USE_LUT_OR : boolean := TRUE
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate128;
architecture imp of or_gate128 is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component or_muxcy
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end component or_muxcy;
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
USE_LUT_OR_GEN: if C_USE_LUT_OR generate
OR_PROCESS: process( A ) is
variable yi : std_logic_vector(0 to (C_OR_WIDTH));
begin
for j in 0 to C_BUS_WIDTH-1 loop
yi(0) := '0';
for i in 0 to C_OR_WIDTH-1 loop
yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j);
end loop;
Y(j) <= yi(C_OR_WIDTH);
end loop;
end process OR_PROCESS;
end generate USE_LUT_OR_GEN;
USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: or_muxcy
generic map (
C_NUM_BITS => C_OR_WIDTH
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end generate USE_MUXCY_OR_GEN;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: or_gate128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate128.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate128.vhd
-- Version: v1.00a
-- Description: OR gate implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate128.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
-- GAB 07/11/05
-- ^^^^^^
-- Adjusted range on C_BUS_WIDTH to support 128 bit dwidths
-- Renamed to or_gate128.vhd
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate128 is
generic (
C_OR_WIDTH : natural range 1 to 32 := 17;
C_BUS_WIDTH : natural range 1 to 128 := 1;
C_USE_LUT_OR : boolean := TRUE
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate128;
architecture imp of or_gate128 is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component or_muxcy
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end component or_muxcy;
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
USE_LUT_OR_GEN: if C_USE_LUT_OR generate
OR_PROCESS: process( A ) is
variable yi : std_logic_vector(0 to (C_OR_WIDTH));
begin
for j in 0 to C_BUS_WIDTH-1 loop
yi(0) := '0';
for i in 0 to C_OR_WIDTH-1 loop
yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j);
end loop;
Y(j) <= yi(C_OR_WIDTH);
end loop;
end process OR_PROCESS;
end generate USE_LUT_OR_GEN;
USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: or_muxcy
generic map (
C_NUM_BITS => C_OR_WIDTH
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end generate USE_MUXCY_OR_GEN;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: or_gate128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate128.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate128.vhd
-- Version: v1.00a
-- Description: OR gate implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate128.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
-- GAB 07/11/05
-- ^^^^^^
-- Adjusted range on C_BUS_WIDTH to support 128 bit dwidths
-- Renamed to or_gate128.vhd
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate128 is
generic (
C_OR_WIDTH : natural range 1 to 32 := 17;
C_BUS_WIDTH : natural range 1 to 128 := 1;
C_USE_LUT_OR : boolean := TRUE
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate128;
architecture imp of or_gate128 is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component or_muxcy
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end component or_muxcy;
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
USE_LUT_OR_GEN: if C_USE_LUT_OR generate
OR_PROCESS: process( A ) is
variable yi : std_logic_vector(0 to (C_OR_WIDTH));
begin
for j in 0 to C_BUS_WIDTH-1 loop
yi(0) := '0';
for i in 0 to C_OR_WIDTH-1 loop
yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j);
end loop;
Y(j) <= yi(C_OR_WIDTH);
end loop;
end process OR_PROCESS;
end generate USE_LUT_OR_GEN;
USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: or_muxcy
generic map (
C_NUM_BITS => C_OR_WIDTH
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end generate USE_MUXCY_OR_GEN;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: or_gate128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate128.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate128.vhd
-- Version: v1.00a
-- Description: OR gate implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate128.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
-- GAB 07/11/05
-- ^^^^^^
-- Adjusted range on C_BUS_WIDTH to support 128 bit dwidths
-- Renamed to or_gate128.vhd
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate128 is
generic (
C_OR_WIDTH : natural range 1 to 32 := 17;
C_BUS_WIDTH : natural range 1 to 128 := 1;
C_USE_LUT_OR : boolean := TRUE
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate128;
architecture imp of or_gate128 is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component or_muxcy
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end component or_muxcy;
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
USE_LUT_OR_GEN: if C_USE_LUT_OR generate
OR_PROCESS: process( A ) is
variable yi : std_logic_vector(0 to (C_OR_WIDTH));
begin
for j in 0 to C_BUS_WIDTH-1 loop
yi(0) := '0';
for i in 0 to C_OR_WIDTH-1 loop
yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j);
end loop;
Y(j) <= yi(C_OR_WIDTH);
end loop;
end process OR_PROCESS;
end generate USE_LUT_OR_GEN;
USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: or_muxcy
generic map (
C_NUM_BITS => C_OR_WIDTH
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end generate USE_MUXCY_OR_GEN;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: or_gate128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate128.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate128.vhd
-- Version: v1.00a
-- Description: OR gate implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate128.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
-- GAB 07/11/05
-- ^^^^^^
-- Adjusted range on C_BUS_WIDTH to support 128 bit dwidths
-- Renamed to or_gate128.vhd
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate128 is
generic (
C_OR_WIDTH : natural range 1 to 32 := 17;
C_BUS_WIDTH : natural range 1 to 128 := 1;
C_USE_LUT_OR : boolean := TRUE
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate128;
architecture imp of or_gate128 is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component or_muxcy
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end component or_muxcy;
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
USE_LUT_OR_GEN: if C_USE_LUT_OR generate
OR_PROCESS: process( A ) is
variable yi : std_logic_vector(0 to (C_OR_WIDTH));
begin
for j in 0 to C_BUS_WIDTH-1 loop
yi(0) := '0';
for i in 0 to C_OR_WIDTH-1 loop
yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j);
end loop;
Y(j) <= yi(C_OR_WIDTH);
end loop;
end process OR_PROCESS;
end generate USE_LUT_OR_GEN;
USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: or_muxcy
generic map (
C_NUM_BITS => C_OR_WIDTH
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end generate USE_MUXCY_OR_GEN;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: or_gate128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate128.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate128.vhd
-- Version: v1.00a
-- Description: OR gate implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate128.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
-- GAB 07/11/05
-- ^^^^^^
-- Adjusted range on C_BUS_WIDTH to support 128 bit dwidths
-- Renamed to or_gate128.vhd
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate128 is
generic (
C_OR_WIDTH : natural range 1 to 32 := 17;
C_BUS_WIDTH : natural range 1 to 128 := 1;
C_USE_LUT_OR : boolean := TRUE
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate128;
architecture imp of or_gate128 is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component or_muxcy
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end component or_muxcy;
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
USE_LUT_OR_GEN: if C_USE_LUT_OR generate
OR_PROCESS: process( A ) is
variable yi : std_logic_vector(0 to (C_OR_WIDTH));
begin
for j in 0 to C_BUS_WIDTH-1 loop
yi(0) := '0';
for i in 0 to C_OR_WIDTH-1 loop
yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j);
end loop;
Y(j) <= yi(C_OR_WIDTH);
end loop;
end process OR_PROCESS;
end generate USE_LUT_OR_GEN;
USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: or_muxcy
generic map (
C_NUM_BITS => C_OR_WIDTH
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end generate USE_MUXCY_OR_GEN;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: or_gate128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate128.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate128.vhd
-- Version: v1.00a
-- Description: OR gate implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate128.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
-- GAB 07/11/05
-- ^^^^^^
-- Adjusted range on C_BUS_WIDTH to support 128 bit dwidths
-- Renamed to or_gate128.vhd
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate128 is
generic (
C_OR_WIDTH : natural range 1 to 32 := 17;
C_BUS_WIDTH : natural range 1 to 128 := 1;
C_USE_LUT_OR : boolean := TRUE
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate128;
architecture imp of or_gate128 is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component or_muxcy
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end component or_muxcy;
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
USE_LUT_OR_GEN: if C_USE_LUT_OR generate
OR_PROCESS: process( A ) is
variable yi : std_logic_vector(0 to (C_OR_WIDTH));
begin
for j in 0 to C_BUS_WIDTH-1 loop
yi(0) := '0';
for i in 0 to C_OR_WIDTH-1 loop
yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j);
end loop;
Y(j) <= yi(C_OR_WIDTH);
end loop;
end process OR_PROCESS;
end generate USE_LUT_OR_GEN;
USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: or_muxcy
generic map (
C_NUM_BITS => C_OR_WIDTH
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end generate USE_MUXCY_OR_GEN;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: or_gate128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate128.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate128.vhd
-- Version: v1.00a
-- Description: OR gate implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate128.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
-- GAB 07/11/05
-- ^^^^^^
-- Adjusted range on C_BUS_WIDTH to support 128 bit dwidths
-- Renamed to or_gate128.vhd
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate128 is
generic (
C_OR_WIDTH : natural range 1 to 32 := 17;
C_BUS_WIDTH : natural range 1 to 128 := 1;
C_USE_LUT_OR : boolean := TRUE
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate128;
architecture imp of or_gate128 is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component or_muxcy
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end component or_muxcy;
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
USE_LUT_OR_GEN: if C_USE_LUT_OR generate
OR_PROCESS: process( A ) is
variable yi : std_logic_vector(0 to (C_OR_WIDTH));
begin
for j in 0 to C_BUS_WIDTH-1 loop
yi(0) := '0';
for i in 0 to C_OR_WIDTH-1 loop
yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j);
end loop;
Y(j) <= yi(C_OR_WIDTH);
end loop;
end process OR_PROCESS;
end generate USE_LUT_OR_GEN;
USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: or_muxcy
generic map (
C_NUM_BITS => C_OR_WIDTH
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end generate USE_MUXCY_OR_GEN;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: or_gate128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate128.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate128.vhd
-- Version: v1.00a
-- Description: OR gate implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate128.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
-- GAB 07/11/05
-- ^^^^^^
-- Adjusted range on C_BUS_WIDTH to support 128 bit dwidths
-- Renamed to or_gate128.vhd
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate128 is
generic (
C_OR_WIDTH : natural range 1 to 32 := 17;
C_BUS_WIDTH : natural range 1 to 128 := 1;
C_USE_LUT_OR : boolean := TRUE
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate128;
architecture imp of or_gate128 is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component or_muxcy
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end component or_muxcy;
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
USE_LUT_OR_GEN: if C_USE_LUT_OR generate
OR_PROCESS: process( A ) is
variable yi : std_logic_vector(0 to (C_OR_WIDTH));
begin
for j in 0 to C_BUS_WIDTH-1 loop
yi(0) := '0';
for i in 0 to C_OR_WIDTH-1 loop
yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j);
end loop;
Y(j) <= yi(C_OR_WIDTH);
end loop;
end process OR_PROCESS;
end generate USE_LUT_OR_GEN;
USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: or_muxcy
generic map (
C_NUM_BITS => C_OR_WIDTH
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end generate USE_MUXCY_OR_GEN;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: or_gate128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate128.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate128.vhd
-- Version: v1.00a
-- Description: OR gate implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate128.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
-- GAB 07/11/05
-- ^^^^^^
-- Adjusted range on C_BUS_WIDTH to support 128 bit dwidths
-- Renamed to or_gate128.vhd
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate128 is
generic (
C_OR_WIDTH : natural range 1 to 32 := 17;
C_BUS_WIDTH : natural range 1 to 128 := 1;
C_USE_LUT_OR : boolean := TRUE
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate128;
architecture imp of or_gate128 is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component or_muxcy
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end component or_muxcy;
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
USE_LUT_OR_GEN: if C_USE_LUT_OR generate
OR_PROCESS: process( A ) is
variable yi : std_logic_vector(0 to (C_OR_WIDTH));
begin
for j in 0 to C_BUS_WIDTH-1 loop
yi(0) := '0';
for i in 0 to C_OR_WIDTH-1 loop
yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j);
end loop;
Y(j) <= yi(C_OR_WIDTH);
end loop;
end process OR_PROCESS;
end generate USE_LUT_OR_GEN;
USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: or_muxcy
generic map (
C_NUM_BITS => C_OR_WIDTH
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end generate USE_MUXCY_OR_GEN;
end architecture imp;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_atanpi_s5
-- VHDL created on Tue Mar 12 11:23:23 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_atanpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_atanpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBiasM2_uid6_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal ooPi_uid9_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal piO2_uid46_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0);
signal piO4_uid47_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid64_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal zS_uid67_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q : std_logic_vector (12 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a : std_logic_vector (23 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 : std_logic_vector (50 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr : UNSIGNED (50 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q : std_logic_vector (50 downto 0);
signal fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (9 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (10 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector (23 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 : std_logic_vector (47 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr : UNSIGNED (47 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (47 downto 0);
signal roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_q : std_logic_vector (40 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_b : std_logic_vector (21 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_s1 : std_logic_vector (36 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_pr : SIGNED (37 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_q : std_logic_vector (36 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid299_atanXOXTabGen_lutmem_ia : std_logic_vector (30 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_iq : std_logic_vector (30 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_q : std_logic_vector (30 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid300_atanXOXTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid301_atanXOXTabGen_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid344_invTabGen_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid345_invTabGen_lutmem_ia : std_logic_vector (19 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_iq : std_logic_vector (19 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_q : std_logic_vector (19 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid346_invTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q : std_logic_vector (19 downto 0);
signal reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q : std_logic_vector (21 downto 0);
signal reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q : std_logic_vector (28 downto 0);
signal reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q : std_logic_vector (30 downto 0);
signal reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (26 downto 0);
signal reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (8 downto 0);
signal reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (31 downto 0);
signal reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (32 downto 0);
signal reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (22 downto 0);
signal reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (22 downto 0);
signal reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (22 downto 0);
signal reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (7 downto 0);
signal reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (7 downto 0);
signal reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (22 downto 0);
signal reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (23 downto 0);
signal reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (34 downto 0);
signal reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (11 downto 0);
signal reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q : std_logic_vector (7 downto 0);
signal ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (7 downto 0);
signal ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (8 downto 0);
signal ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (22 downto 0);
signal ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (7 downto 0);
signal ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (20 downto 0);
signal ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (18 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q : std_logic_vector (12 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 : std_logic;
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : signal is true;
signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : signal is true;
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : signal is true;
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_c : std_logic_vector (0 downto 0);
signal excSelBits_uid114_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a : std_logic_vector(33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b : std_logic_vector(33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o : std_logic_vector (33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q : std_logic_vector (33 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o : std_logic_vector (32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0);
signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid15_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid15_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid16_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid16_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal singX_uid17_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal singX_uid17_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q : std_logic_vector (9 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_a : std_logic_vector(26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_b : std_logic_vector(26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_o : std_logic_vector (26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (26 downto 0);
signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (35 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal fracOOPi_uid10_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracOOPi_uid10_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid80_atanX_uid8_fpArctanPiTest_in : std_logic_vector (49 downto 0);
signal normBit_uid80_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in : std_logic_vector (48 downto 0);
signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in : std_logic_vector (47 downto 0);
signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (47 downto 0);
signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (46 downto 0);
signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (45 downto 0);
signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (21 downto 0);
signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (21 downto 0);
signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in : std_logic_vector (36 downto 0);
signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b : std_logic_vector (22 downto 0);
signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal R_uid221_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (14 downto 0);
signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (14 downto 0);
signal R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal constOut_uid54_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal constOut_uid54_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal u_uid58_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal u_uid58_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal R_uid120_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (16 downto 0);
signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (8 downto 0);
signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in : std_logic_vector (8 downto 0);
signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in : std_logic_vector (25 downto 0);
signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (11 downto 0);
signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (9 downto 0);
signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (33 downto 0);
signal fpOOPi_uid11_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (32 downto 0);
signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0);
signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (28 downto 0);
signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (24 downto 0);
signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (0 downto 0);
signal stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal lowRangeB_uid304_atanXOXPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid304_atanXOXPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid305_atanXOXPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid305_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid310_atanXOXPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid310_atanXOXPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid311_atanXOXPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid311_atanXOXPolyEval_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid349_invPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid349_invPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid350_invPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid350_invPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid355_invPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid355_invPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid356_invPolyEval_in : std_logic_vector (22 downto 0);
signal highBBits_uid356_invPolyEval_b : std_logic_vector (20 downto 0);
signal y_uid73_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal y_uid73_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0);
signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal yT1_uid347_invPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid347_invPolyEval_b : std_logic_vector (11 downto 0);
signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal expU_uid59_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expU_uid59_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracU_uid60_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracU_uid60_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0);
signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b : std_logic_vector (3 downto 0);
signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (1 downto 0);
signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (34 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_a : std_logic_vector(31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_b : std_logic_vector(31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_o : std_logic_vector (31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_q : std_logic_vector (31 downto 0);
signal sumAHighB_uid351_invPolyEval_a : std_logic_vector(20 downto 0);
signal sumAHighB_uid351_invPolyEval_b : std_logic_vector(20 downto 0);
signal sumAHighB_uid351_invPolyEval_o : std_logic_vector (20 downto 0);
signal sumAHighB_uid351_invPolyEval_q : std_logic_vector (20 downto 0);
signal sumAHighB_uid357_invPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid357_invPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid357_invPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid357_invPolyEval_q : std_logic_vector (29 downto 0);
signal yAddr_uid75_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0);
signal yAddr_uid75_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in : std_logic_vector (26 downto 0);
signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b : std_logic_vector (17 downto 0);
signal rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0);
signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b : std_logic_vector (4 downto 0);
signal expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0);
signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal s1_uid304_uid307_atanXOXPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid310_uid313_atanXOXPolyEval_q : std_logic_vector (33 downto 0);
signal s1_uid349_uid352_invPolyEval_q : std_logic_vector (21 downto 0);
signal s2_uid355_uid358_invPolyEval_q : std_logic_vector (31 downto 0);
signal yT1_uid302_atanXOXPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid302_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (20 downto 0);
signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (18 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0);
signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0);
signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (25 downto 0);
begin
--xIn(GPIN,3)@0
--cstAllZWF_uid19_atanX_uid8_fpArctanPiTest(CONSTANT,18)
cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000000";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable(LOGICAL,878)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q <= not ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,1008)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a or ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,1004)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100001";
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,1005)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,1006)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,1009)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,1010)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--fracX_uid16_atanX_uid8_fpArctanPiTest(BITSELECT,15)@0
fracX_uid16_atanX_uid8_fpArctanPiTest_in <= a(22 downto 0);
fracX_uid16_atanX_uid8_fpArctanPiTest_b <= fracX_uid16_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--fracXIsZero_uid35_atanX_uid8_fpArctanPiTest(LOGICAL,34)@0
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b else "0";
--InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest(LOGICAL,36)@0
InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q <= not InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a;
--cstAllOWE_uid18_atanX_uid8_fpArctanPiTest(CONSTANT,17)
cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q <= "11111111";
--expX_uid15_atanX_uid8_fpArctanPiTest(BITSELECT,14)@0
expX_uid15_atanX_uid8_fpArctanPiTest_in <= a(30 downto 0);
expX_uid15_atanX_uid8_fpArctanPiTest_b <= expX_uid15_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--expXIsMax_uid33_atanX_uid8_fpArctanPiTest(LOGICAL,32)@0
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a = expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b else "0";
--exc_N_uid38_atanX_uid8_fpArctanPiTest(LOGICAL,37)@0
exc_N_uid38_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q;
exc_N_uid38_atanX_uid8_fpArctanPiTest_b <= InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q;
exc_N_uid38_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_a and exc_N_uid38_atanX_uid8_fpArctanPiTest_b;
--InvExc_N_uid118_atanX_uid8_fpArctanPiTest(LOGICAL,117)@0
InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q;
InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q <= not InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a;
--singX_uid17_atanX_uid8_fpArctanPiTest(BITSELECT,16)@0
singX_uid17_atanX_uid8_fpArctanPiTest_in <= a;
singX_uid17_atanX_uid8_fpArctanPiTest_b <= singX_uid17_atanX_uid8_fpArctanPiTest_in(31 downto 31);
--signR_uid119_atanX_uid8_fpArctanPiTest(LOGICAL,118)@0
signR_uid119_atanX_uid8_fpArctanPiTest_a <= singX_uid17_atanX_uid8_fpArctanPiTest_b;
signR_uid119_atanX_uid8_fpArctanPiTest_b <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q;
signR_uid119_atanX_uid8_fpArctanPiTest_q <= signR_uid119_atanX_uid8_fpArctanPiTest_a and signR_uid119_atanX_uid8_fpArctanPiTest_b;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,998)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid119_atanX_uid8_fpArctanPiTest_q, xout => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,1000)
-- every=1, low=0, high=33, step=1, init=1
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 32 THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 33;
ELSE
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6));
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,1001)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,1002)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,999)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 34,
width_b => 1,
widthad_b => 6,
numwords_b => 34,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,879)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a or ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,875)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100000";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,876)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,877)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,880)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,881)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,869)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => singX_uid17_atanX_uid8_fpArctanPiTest_b, xout => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,871)
-- every=1, low=0, high=32, step=1, init=1
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 31 THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 32;
ELSE
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6));
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,872)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,873)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,870)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--cstBias_uid22_atanX_uid8_fpArctanPiTest(CONSTANT,21)
cstBias_uid22_atanX_uid8_fpArctanPiTest_q <= "01111111";
--piO2_uid46_atanX_uid8_fpArctanPiTest(CONSTANT,45)
piO2_uid46_atanX_uid8_fpArctanPiTest_q <= "11001001000011111101101011";
--cstPiO2_uid48_atanX_uid8_fpArctanPiTest(BITSELECT,47)@35
cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in <= piO2_uid46_atanX_uid8_fpArctanPiTest_q(24 downto 0);
cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b <= cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in(24 downto 2);
--fpPiO2C_uid49_atanX_uid8_fpArctanPiTest(BITJOIN,48)@35
fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBias_uid22_atanX_uid8_fpArctanPiTest_q & cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b;
--cstBiasM1_uid23_atanX_uid8_fpArctanPiTest(CONSTANT,22)
cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q <= "01111110";
--piO4_uid47_atanX_uid8_fpArctanPiTest(CONSTANT,46)
piO4_uid47_atanX_uid8_fpArctanPiTest_q <= "110010010000111111011011";
--cstPiO4_uid51_atanX_uid8_fpArctanPiTest(BITSELECT,50)@35
cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in <= piO4_uid47_atanX_uid8_fpArctanPiTest_q(22 downto 0);
cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b <= cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--fpPiO4C_uid52_atanX_uid8_fpArctanPiTest(BITJOIN,51)@35
fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q & cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,892)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a or ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b);
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,893)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,894)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b;
--exc_I_uid36_atanX_uid8_fpArctanPiTest(LOGICAL,35)@0
exc_I_uid36_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q;
exc_I_uid36_atanX_uid8_fpArctanPiTest_b <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
exc_I_uid36_atanX_uid8_fpArctanPiTest_q <= exc_I_uid36_atanX_uid8_fpArctanPiTest_a and exc_I_uid36_atanX_uid8_fpArctanPiTest_b;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,882)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid36_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,883)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq,
address_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa,
data_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia
);
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(0 downto 0);
--constOut_uid54_atanX_uid8_fpArctanPiTest(MUX,53)@35
constOut_uid54_atanX_uid8_fpArctanPiTest_s <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q;
constOut_uid54_atanX_uid8_fpArctanPiTest: PROCESS (constOut_uid54_atanX_uid8_fpArctanPiTest_s, en, fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q, fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE constOut_uid54_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expOutCst_uid112_atanX_uid8_fpArctanPiTest(BITSELECT,111)@35
expOutCst_uid112_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expOutCst_uid112_atanX_uid8_fpArctanPiTest_b <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5(REG,428)@35
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--cst01pWShift_uid69_atanX_uid8_fpArctanPiTest(CONSTANT,68)
cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q <= "0000000000000";
--reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2(REG,389)@0
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= signR_uid119_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c(DELAY,707)@1
ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,1022)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a or ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b);
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top(CONSTANT,1018)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q <= "0111";
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp(LOGICAL,1019)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q);
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q <= "1" when ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a = ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b else "0";
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg(REG,1020)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,1023)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,1024)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b;
--cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,230)
cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111110";
--expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest(SUB,259)@0
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q);
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b);
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b));
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,260)@0
expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0);
expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,229)
cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111101";
--expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest(SUB,256)@0
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q);
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b);
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b));
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,257)@0
expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0);
expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,249)@0
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b else "0";
--expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest(MUX,263)@0
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s <= fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q;
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--expXIsZero_uid31_atanX_uid8_fpArctanPiTest(LOGICAL,30)@0
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a = expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b else "0";
--udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,258)@0
udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in <= STD_LOGIC_VECTOR((9 downto 9 => expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(8)) & expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q);
udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in(9 downto 9);
--InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,245)@0
InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a;
--InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,246)@0
InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a <= expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q;
InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a;
--exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,247)@0
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a <= InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b <= InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c;
--xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,264)@0
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q;
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b;
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a and xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b;
--xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,265)@0
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q;
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q <= xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a or xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b;
--excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,266)@0
excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q & expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q & xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q;
--reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0(REG,378)@0
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest(LOOKUP,267)@1
outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest(MUX,269)@1
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q;
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,1012)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt(COUNTER,1014)
-- every=1, low=0, high=7, step=1, init=1
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg(REG,1015)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux(MUX,1016)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,1013)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia
);
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid20_atanX_uid8_fpArctanPiTest(CONSTANT,19)
cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000001";
--oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,248)@0
oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q <= VCC_q & fracX_uid16_atanX_uid8_fpArctanPiTest_b;
--y_uid251_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,250)@0
y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in <= oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q(22 downto 0);
y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,252)@0
yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b;
yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 15);
--reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0(REG,379)@0
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid346_invTabGen_lutmem(DUALMEM,376)@1
memoryC2_uid346_invTabGen_lutmem_ia <= (others => '0');
memoryC2_uid346_invTabGen_lutmem_aa <= (others => '0');
memoryC2_uid346_invTabGen_lutmem_ab <= reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q;
memoryC2_uid346_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC2_uid346_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid346_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid346_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid346_invTabGen_lutmem_iq,
address_a => memoryC2_uid346_invTabGen_lutmem_aa,
data_a => memoryC2_uid346_invTabGen_lutmem_ia
);
memoryC2_uid346_invTabGen_lutmem_reset0 <= areset;
memoryC2_uid346_invTabGen_lutmem_q <= memoryC2_uid346_invTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1(REG,381)@3
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= memoryC2_uid346_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,1011)
ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a(DELAY,680)@0
ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,253)@3
yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in <= ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q(14 downto 0);
yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in(14 downto 0);
--yT1_uid347_invPolyEval(BITSELECT,346)@3
yT1_uid347_invPolyEval_in <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b;
yT1_uid347_invPolyEval_b <= yT1_uid347_invPolyEval_in(14 downto 3);
--reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0(REG,380)@3
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= yT1_uid347_invPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid366_pT1_uid348_invPolyEval(MULT,365)@4
prodXY_uid366_pT1_uid348_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid366_pT1_uid348_invPolyEval_a),13)) * SIGNED(prodXY_uid366_pT1_uid348_invPolyEval_b);
prodXY_uid366_pT1_uid348_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid366_pT1_uid348_invPolyEval_a <= (others => '0');
prodXY_uid366_pT1_uid348_invPolyEval_b <= (others => '0');
prodXY_uid366_pT1_uid348_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid366_pT1_uid348_invPolyEval_a <= reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q;
prodXY_uid366_pT1_uid348_invPolyEval_b <= reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q;
prodXY_uid366_pT1_uid348_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid366_pT1_uid348_invPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid366_pT1_uid348_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid366_pT1_uid348_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid366_pT1_uid348_invPolyEval_q <= prodXY_uid366_pT1_uid348_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid367_pT1_uid348_invPolyEval(BITSELECT,366)@7
prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in <= prodXY_uid366_pT1_uid348_invPolyEval_q;
prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in(23 downto 11);
--highBBits_uid350_invPolyEval(BITSELECT,349)@7
highBBits_uid350_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b;
highBBits_uid350_invPolyEval_b <= highBBits_uid350_invPolyEval_in(12 downto 1);
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a(DELAY,804)@1
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid345_invTabGen_lutmem(DUALMEM,375)@4
memoryC1_uid345_invTabGen_lutmem_ia <= (others => '0');
memoryC1_uid345_invTabGen_lutmem_aa <= (others => '0');
memoryC1_uid345_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q;
memoryC1_uid345_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 20,
widthad_a => 8,
numwords_a => 256,
width_b => 20,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC1_uid345_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid345_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid345_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid345_invTabGen_lutmem_iq,
address_a => memoryC1_uid345_invTabGen_lutmem_aa,
data_a => memoryC1_uid345_invTabGen_lutmem_ia
);
memoryC1_uid345_invTabGen_lutmem_reset0 <= areset;
memoryC1_uid345_invTabGen_lutmem_q <= memoryC1_uid345_invTabGen_lutmem_iq(19 downto 0);
--reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0(REG,383)@6
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= "00000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= memoryC1_uid345_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid351_invPolyEval(ADD,350)@7
sumAHighB_uid351_invPolyEval_a <= STD_LOGIC_VECTOR((20 downto 20 => reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q(19)) & reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q);
sumAHighB_uid351_invPolyEval_b <= STD_LOGIC_VECTOR((20 downto 12 => highBBits_uid350_invPolyEval_b(11)) & highBBits_uid350_invPolyEval_b);
sumAHighB_uid351_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid351_invPolyEval_a) + SIGNED(sumAHighB_uid351_invPolyEval_b));
sumAHighB_uid351_invPolyEval_q <= sumAHighB_uid351_invPolyEval_o(20 downto 0);
--lowRangeB_uid349_invPolyEval(BITSELECT,348)@7
lowRangeB_uid349_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b(0 downto 0);
lowRangeB_uid349_invPolyEval_b <= lowRangeB_uid349_invPolyEval_in(0 downto 0);
--s1_uid349_uid352_invPolyEval(BITJOIN,351)@7
s1_uid349_uid352_invPolyEval_q <= sumAHighB_uid351_invPolyEval_q & lowRangeB_uid349_invPolyEval_b;
--reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1(REG,385)@7
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= "0000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= s1_uid349_uid352_invPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor(LOGICAL,1059)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a or ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b);
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg(REG,966)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena(REG,1060)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q = "1") THEN
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd(LOGICAL,1061)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b <= en;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg(DELAY,1051)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt(COUNTER,962)
-- every=1, low=0, high=1, step=1, init=1
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i,1));
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg(REG,963)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux(MUX,964)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s <= en;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux: PROCESS (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q)
BEGIN
CASE ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s IS
WHEN "0" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
WHEN "1" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q;
WHEN OTHERS => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem(DUALMEM,1052)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia
);
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0(REG,384)@7
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid369_pT2_uid354_invPolyEval(MULT,368)@8
prodXY_uid369_pT2_uid354_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid369_pT2_uid354_invPolyEval_a),16)) * SIGNED(prodXY_uid369_pT2_uid354_invPolyEval_b);
prodXY_uid369_pT2_uid354_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid369_pT2_uid354_invPolyEval_a <= (others => '0');
prodXY_uid369_pT2_uid354_invPolyEval_b <= (others => '0');
prodXY_uid369_pT2_uid354_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid369_pT2_uid354_invPolyEval_a <= reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q;
prodXY_uid369_pT2_uid354_invPolyEval_b <= reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q;
prodXY_uid369_pT2_uid354_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid369_pT2_uid354_invPolyEval_pr,37));
END IF;
END IF;
END PROCESS;
prodXY_uid369_pT2_uid354_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid369_pT2_uid354_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid369_pT2_uid354_invPolyEval_q <= prodXY_uid369_pT2_uid354_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid370_pT2_uid354_invPolyEval(BITSELECT,369)@11
prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in <= prodXY_uid369_pT2_uid354_invPolyEval_q;
prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in(36 downto 14);
--highBBits_uid356_invPolyEval(BITSELECT,355)@11
highBBits_uid356_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b;
highBBits_uid356_invPolyEval_b <= highBBits_uid356_invPolyEval_in(22 downto 2);
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor(LOGICAL,1048)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q <= not (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a or ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b);
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top(CONSTANT,1031)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q <= "0100";
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp(LOGICAL,1032)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q <= "1" when ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a = ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b else "0";
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg(REG,1033)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena(REG,1049)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd(LOGICAL,1050)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a and ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg(DELAY,1038)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt(COUNTER,1027)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i,3));
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg(REG,1028)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux(MUX,1029)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s <= en;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux: PROCESS (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem(DUALMEM,1039)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq(7 downto 0);
--memoryC0_uid344_invTabGen_lutmem(DUALMEM,374)@8
memoryC0_uid344_invTabGen_lutmem_ia <= (others => '0');
memoryC0_uid344_invTabGen_lutmem_aa <= (others => '0');
memoryC0_uid344_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q;
memoryC0_uid344_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC0_uid344_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid344_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid344_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid344_invTabGen_lutmem_iq,
address_a => memoryC0_uid344_invTabGen_lutmem_aa,
data_a => memoryC0_uid344_invTabGen_lutmem_ia
);
memoryC0_uid344_invTabGen_lutmem_reset0 <= areset;
memoryC0_uid344_invTabGen_lutmem_q <= memoryC0_uid344_invTabGen_lutmem_iq(28 downto 0);
--reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0(REG,387)@10
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= "00000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= memoryC0_uid344_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid357_invPolyEval(ADD,356)@11
sumAHighB_uid357_invPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q(28)) & reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q);
sumAHighB_uid357_invPolyEval_b <= STD_LOGIC_VECTOR((29 downto 21 => highBBits_uid356_invPolyEval_b(20)) & highBBits_uid356_invPolyEval_b);
sumAHighB_uid357_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid357_invPolyEval_a) + SIGNED(sumAHighB_uid357_invPolyEval_b));
sumAHighB_uid357_invPolyEval_q <= sumAHighB_uid357_invPolyEval_o(29 downto 0);
--lowRangeB_uid355_invPolyEval(BITSELECT,354)@11
lowRangeB_uid355_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b(1 downto 0);
lowRangeB_uid355_invPolyEval_b <= lowRangeB_uid355_invPolyEval_in(1 downto 0);
--s2_uid355_uid358_invPolyEval(BITJOIN,357)@11
s2_uid355_uid358_invPolyEval_q <= sumAHighB_uid357_invPolyEval_q & lowRangeB_uid355_invPolyEval_b;
--fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,255)@11
fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in <= s2_uid355_uid358_invPolyEval_q(28 downto 0);
fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in(28 downto 5);
--fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,261)@11
fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b(22 downto 0);
fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,688)@0
ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest(MUX,262)@11
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q;
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1(REG,388)@1
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,701)@2
ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 10 )
PORT MAP ( xin => reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest(MUX,268)@12
fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q;
fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid273_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,272)@12
R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q <= ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q & fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,905)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a or ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,901)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "01001";
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,902)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,903)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,906)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,907)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,895)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,897)
-- every=1, low=0, high=9, step=1, init=1
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 8 THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 9;
ELSE
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,4));
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,898)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,899)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,896)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 4,
numwords_a => 10,
width_b => 32,
widthad_b => 4,
numwords_b => 10,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(31 downto 0);
--path2_uid56_atanX_uid8_fpArctanPiTest(COMPARE,55)@0
path2_uid56_atanX_uid8_fpArctanPiTest_cin <= GND_q;
path2_uid56_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid15_atanX_uid8_fpArctanPiTest_b) & '0';
path2_uid56_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q) & path2_uid56_atanX_uid8_fpArctanPiTest_cin(0);
path2_uid56_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_b));
path2_uid56_atanX_uid8_fpArctanPiTest_n(0) <= not path2_uid56_atanX_uid8_fpArctanPiTest_o(10);
--reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1(REG,390)@0
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= path2_uid56_atanX_uid8_fpArctanPiTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b(DELAY,466)@1
ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--u_uid58_atanX_uid8_fpArctanPiTest(MUX,57)@12
u_uid58_atanX_uid8_fpArctanPiTest_s <= ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q;
u_uid58_atanX_uid8_fpArctanPiTest: PROCESS (u_uid58_atanX_uid8_fpArctanPiTest_s, en, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q, R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE u_uid58_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => u_uid58_atanX_uid8_fpArctanPiTest_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q;
WHEN "1" => u_uid58_atanX_uid8_fpArctanPiTest_q <= R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => u_uid58_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracU_uid60_atanX_uid8_fpArctanPiTest(BITSELECT,59)@12
fracU_uid60_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracU_uid60_atanX_uid8_fpArctanPiTest_b <= fracU_uid60_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a(DELAY,471)@12
ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracU_uid60_atanX_uid8_fpArctanPiTest_b, xout => ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest(BITJOIN,60)@13
oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q;
--oFracUExt_uid70_atanX_uid8_fpArctanPiTest(BITJOIN,69)@13
oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q <= cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q & oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q;
--X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,282)@13
X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(24 downto 0);
X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(24 downto 0);
--leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,281)
leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000000000000";
--leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,283)@13
leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5(REG,399)@13
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,279)@13
X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(28 downto 0);
X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(28 downto 0);
--leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,280)@13
leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4(REG,398)@13
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,276)@13
X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(32 downto 0);
X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(32 downto 0);
--leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,275)
leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "0000";
--leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,277)@13
leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3(REG,397)@13
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,396)@13
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--zS_uid67_atanX_uid8_fpArctanPiTest(CONSTANT,66)
zS_uid67_atanX_uid8_fpArctanPiTest_q <= "000000000";
--shiftBias_uid64_atanX_uid8_fpArctanPiTest(CONSTANT,63)
shiftBias_uid64_atanX_uid8_fpArctanPiTest_q <= "01110010";
--expU_uid59_atanX_uid8_fpArctanPiTest(BITSELECT,58)@12
expU_uid59_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expU_uid59_atanX_uid8_fpArctanPiTest_b <= expU_uid59_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1(REG,391)@12
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= expU_uid59_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--shiftValue_uid65_atanX_uid8_fpArctanPiTest(SUB,64)@13
shiftValue_uid65_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q);
shiftValue_uid65_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid64_atanX_uid8_fpArctanPiTest_q);
shiftValue_uid65_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_b));
shiftValue_uid65_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--ShiftValue8_uid66_atanX_uid8_fpArctanPiTest(BITSELECT,65)@13
ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q;
ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in(8 downto 8);
--shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest(MUX,67)@13
shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b;
shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest: PROCESS (shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s, en, shiftValue_uid65_atanX_uid8_fpArctanPiTest_q, zS_uid67_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= zS_uid67_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest(BITSELECT,70)@13
fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in <= shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q(3 downto 0);
fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,284)@13
leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b;
leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,395)@13
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,285)@14
leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q;
leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q, reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q, reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q;
WHEN "11" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,293)@14
LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(33 downto 0);
LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(33 downto 0);
--ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,725)@14
ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,292)
leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000";
--leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,294)@15
leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,290)@14
LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(34 downto 0);
LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(34 downto 0);
--ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,723)@14
ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,289)
leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "00";
--leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,291)@15
leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,287)@14
LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0);
LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(35 downto 0);
--ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,721)@14
ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,288)@15
leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & GND_q;
--reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,401)@14
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,295)@13
leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a(DELAY,829)@13
ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,400)@14
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,296)@15
leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q;
leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid73_atanX_uid8_fpArctanPiTest(BITSELECT,72)@15
y_uid73_atanX_uid8_fpArctanPiTest_in <= leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0);
y_uid73_atanX_uid8_fpArctanPiTest_b <= y_uid73_atanX_uid8_fpArctanPiTest_in(35 downto 1);
--yAddr_uid75_atanX_uid8_fpArctanPiTest(BITSELECT,74)@15
yAddr_uid75_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b;
yAddr_uid75_atanX_uid8_fpArctanPiTest_b <= yAddr_uid75_atanX_uid8_fpArctanPiTest_in(34 downto 27);
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0(REG,402)@15
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= yAddr_uid75_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid301_atanXOXTabGen_lutmem(DUALMEM,373)@16
memoryC2_uid301_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC2_uid301_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC2_uid301_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q;
memoryC2_uid301_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC2_uid301_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid301_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid301_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid301_atanXOXTabGen_lutmem_iq,
address_a => memoryC2_uid301_atanXOXTabGen_lutmem_aa,
data_a => memoryC2_uid301_atanXOXTabGen_lutmem_ia
);
memoryC2_uid301_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC2_uid301_atanXOXTabGen_lutmem_q <= memoryC2_uid301_atanXOXTabGen_lutmem_iq(12 downto 0);
--reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1(REG,404)@18
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= memoryC2_uid301_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--yPPolyEval_uid76_atanX_uid8_fpArctanPiTest(BITSELECT,75)@15
yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b(26 downto 0);
yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in(26 downto 9);
--yT1_uid302_atanXOXPolyEval(BITSELECT,301)@15
yT1_uid302_atanXOXPolyEval_in <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b;
yT1_uid302_atanXOXPolyEval_b <= yT1_uid302_atanXOXPolyEval_in(17 downto 5);
--ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg(DELAY,1062)
ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid302_atanXOXPolyEval_b, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a(DELAY,832)@15
ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0(REG,403)@18
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid360_pT1_uid303_atanXOXPolyEval(MULT,359)@19
prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_a),14)) * SIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_b);
prodXY_uid360_pT1_uid303_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= (others => '0');
prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= (others => '0');
prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q;
prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q;
prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid360_pT1_uid303_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval(BITSELECT,360)@22
prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_q;
prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in(25 downto 12);
--highBBits_uid305_atanXOXPolyEval(BITSELECT,304)@22
highBBits_uid305_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b;
highBBits_uid305_atanXOXPolyEval_b <= highBBits_uid305_atanXOXPolyEval_in(13 downto 1);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a(DELAY,834)@15
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0(REG,405)@18
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid300_atanXOXTabGen_lutmem(DUALMEM,372)@19
memoryC1_uid300_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC1_uid300_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC1_uid300_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q;
memoryC1_uid300_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC1_uid300_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid300_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid300_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid300_atanXOXTabGen_lutmem_iq,
address_a => memoryC1_uid300_atanXOXTabGen_lutmem_aa,
data_a => memoryC1_uid300_atanXOXTabGen_lutmem_ia
);
memoryC1_uid300_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC1_uid300_atanXOXTabGen_lutmem_q <= memoryC1_uid300_atanXOXTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0(REG,406)@21
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= memoryC1_uid300_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid306_atanXOXPolyEval(ADD,305)@22
sumAHighB_uid306_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q(20)) & reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q);
sumAHighB_uid306_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid305_atanXOXPolyEval_b(12)) & highBBits_uid305_atanXOXPolyEval_b);
sumAHighB_uid306_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid306_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid306_atanXOXPolyEval_b));
sumAHighB_uid306_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_o(21 downto 0);
--lowRangeB_uid304_atanXOXPolyEval(BITSELECT,303)@22
lowRangeB_uid304_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b(0 downto 0);
lowRangeB_uid304_atanXOXPolyEval_b <= lowRangeB_uid304_atanXOXPolyEval_in(0 downto 0);
--s1_uid304_uid307_atanXOXPolyEval(BITJOIN,306)@22
s1_uid304_uid307_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_q & lowRangeB_uid304_atanXOXPolyEval_b;
--reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1(REG,408)@22
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= s1_uid304_uid307_atanXOXPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor(LOGICAL,1035)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q <= not (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a or ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b);
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena(REG,1036)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd(LOGICAL,1037)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b <= en;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a and ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b;
--reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0(REG,407)@15
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg(DELAY,1025)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q, xout => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem(DUALMEM,1026)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq,
address_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa,
data_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia
);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid363_pT2_uid309_atanXOXPolyEval(MULT,362)@23
prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_a),19)) * SIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_b);
prodXY_uid363_pT2_uid309_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= (others => '0');
prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= (others => '0');
prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q;
prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q;
prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid363_pT2_uid309_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval(BITSELECT,363)@26
prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_q;
prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in(40 downto 17);
--highBBits_uid311_atanXOXPolyEval(BITSELECT,310)@26
highBBits_uid311_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b;
highBBits_uid311_atanXOXPolyEval_b <= highBBits_uid311_atanXOXPolyEval_in(23 downto 2);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor(LOGICAL,1073)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q <= not (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a or ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena(REG,1074)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q = "1") THEN
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd(LOGICAL,1075)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b <= en;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a and ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b;
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg(DELAY,1063)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem(DUALMEM,1064)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia
);
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0(REG,409)@22
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid299_atanXOXTabGen_lutmem(DUALMEM,371)@23
memoryC0_uid299_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC0_uid299_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC0_uid299_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q;
memoryC0_uid299_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 31,
widthad_a => 8,
numwords_a => 256,
width_b => 31,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC0_uid299_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid299_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid299_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid299_atanXOXTabGen_lutmem_iq,
address_a => memoryC0_uid299_atanXOXTabGen_lutmem_aa,
data_a => memoryC0_uid299_atanXOXTabGen_lutmem_ia
);
memoryC0_uid299_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC0_uid299_atanXOXTabGen_lutmem_q <= memoryC0_uid299_atanXOXTabGen_lutmem_iq(30 downto 0);
--reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0(REG,410)@25
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= memoryC0_uid299_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid312_atanXOXPolyEval(ADD,311)@26
sumAHighB_uid312_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((31 downto 31 => reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q(30)) & reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q);
sumAHighB_uid312_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((31 downto 22 => highBBits_uid311_atanXOXPolyEval_b(21)) & highBBits_uid311_atanXOXPolyEval_b);
sumAHighB_uid312_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid312_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid312_atanXOXPolyEval_b));
sumAHighB_uid312_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_o(31 downto 0);
--lowRangeB_uid310_atanXOXPolyEval(BITSELECT,309)@26
lowRangeB_uid310_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b(1 downto 0);
lowRangeB_uid310_atanXOXPolyEval_b <= lowRangeB_uid310_atanXOXPolyEval_in(1 downto 0);
--s2_uid310_uid313_atanXOXPolyEval(BITJOIN,312)@26
s2_uid310_uid313_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_q & lowRangeB_uid310_atanXOXPolyEval_b;
--fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest(BITSELECT,77)@26
fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in <= s2_uid310_uid313_atanXOXPolyEval_q(31 downto 0);
fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in(31 downto 5);
--reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1(REG,412)@26
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,918)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,914)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01010";
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,915)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,916)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,919)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,920)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0(REG,411)@13
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,908)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,910)
-- every=1, low=0, high=10, step=1, init=1
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 9 THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 10;
ELSE
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4));
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,911)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,912)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,909)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 11,
width_b => 24,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(23 downto 0);
--mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest(MULT,78)@27
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr <= UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a) * UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b);
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= (others => '0');
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= (others => '0');
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr);
END IF;
END IF;
END PROCESS;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid80_atanX_uid8_fpArctanPiTest(BITSELECT,79)@30
normBit_uid80_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(49 downto 0);
normBit_uid80_atanX_uid8_fpArctanPiTest_b <= normBit_uid80_atanX_uid8_fpArctanPiTest_in(49 downto 49);
--InvNormBit_uid84_atanX_uid8_fpArctanPiTest(LOGICAL,83)@30
InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a <= normBit_uid80_atanX_uid8_fpArctanPiTest_b;
InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q <= not InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,931)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,927)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01111";
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,928)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,929)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,932)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,933)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,921)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expU_uid59_atanX_uid8_fpArctanPiTest_b, xout => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,923)
-- every=1, low=0, high=15, step=1, init=1
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4));
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,924)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,925)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,922)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 16,
width_b => 8,
widthad_b => 4,
numwords_b => 16,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(7 downto 0);
--expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest(SUB,84)@30
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q);
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000" & InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q);
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b));
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--fracRPath3High_uid81_atanX_uid8_fpArctanPiTest(BITSELECT,80)@30
fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(48 downto 0);
fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in(48 downto 25);
--fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest(BITSELECT,81)@30
fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(47 downto 0);
fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in(47 downto 24);
--fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest(MUX,82)@30
fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s <= normBit_uid80_atanX_uid8_fpArctanPiTest_b;
fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s, en, fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b, fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b)
BEGIN
CASE fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest(BITJOIN,85)@30
expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q & fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q;
--reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0(REG,420)@30
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest(ADD,86)@31
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q);
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000" & VCC_q);
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b));
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o(33 downto 0);
--expRPath3_uid89_atanX_uid8_fpArctanPiTest(BITSELECT,88)@31
expRPath3_uid89_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(31 downto 0);
expRPath3_uid89_atanX_uid8_fpArctanPiTest_b <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_in(31 downto 24);
--reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4(REG,427)@31
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,971)
ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e(DELAY,534)@32
ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,337)@33
RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 1);
--rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,339)@33
rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= GND_q & RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,333)
rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000";
--rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,322)
rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000000000000000000000";
--X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,321)@32
X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 24);
--rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,323)@32
rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,319)
rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "0000000000000000";
--X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,318)@32
X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 16);
--rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,320)@32
rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,315)@32
X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 8);
--rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,317)@32
rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q & X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a(DELAY,504)@30
ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q, xout => ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest(BITJOIN,93)@32
oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q;
--cstWFP2_uid25_atanX_uid8_fpArctanPiTest(CONSTANT,24)
cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q <= "00011001";
--reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1(REG,413)@30
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest(SUB,89)@31
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q);
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR((10 downto 9 => reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q(8)) & reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q);
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a) - SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b));
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o(9 downto 0);
--shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest(BITSELECT,91)@31
shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q(7 downto 0);
shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest(CONSTANT,23)
cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q <= "01101000";
--shiftOut_uid91_atanX_uid8_fpArctanPiTest(COMPARE,90)@13
shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin <= GND_q;
shiftOut_uid91_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & '0';
shiftOut_uid91_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q) & shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin(0);
shiftOut_uid91_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_b));
shiftOut_uid91_atanX_uid8_fpArctanPiTest_c(0) <= shiftOut_uid91_atanX_uid8_fpArctanPiTest_o(10);
--ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b(DELAY,502)@13
ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => shiftOut_uid91_atanX_uid8_fpArctanPiTest_c, xout => ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--sValPostSOut_uid93_atanX_uid8_fpArctanPiTest(MUX,92)@31
sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s <= ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q;
sValPostSOut_uid93_atanX_uid8_fpArctanPiTest: PROCESS (sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s, en, shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b, cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest(BITSELECT,94)@31
sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in <= sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q(4 downto 0);
sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,324)@31
rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b;
rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,414)@31
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,325)@32
rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q;
rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,332)@32
RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 6);
--ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,762)@32
ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,334)@33
rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,329)@32
RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 4);
--ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,760)@32
ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 21, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,331)@33
rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,326)@32
RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 2);
--ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,758)@32
ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,328)@33
rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2(REG,416)@32
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,335)@31
rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(2 downto 1);
--ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a(DELAY,844)@31
ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,415)@32
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,336)@33
rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q;
rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q, rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,340)@31
rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,417)@31
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b(DELAY,772)@32
ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,341)@33
rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q;
rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest(BITJOIN,96)@33
pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & GND_q;
--reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1(REG,418)@33
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--path2Diff_uid97_atanX_uid8_fpArctanPiTest(SUB,97)@34
path2Diff_uid97_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & piO2_uid46_atanX_uid8_fpArctanPiTest_q);
path2Diff_uid97_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q);
path2Diff_uid97_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_b));
path2Diff_uid97_atanX_uid8_fpArctanPiTest_q <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_o(26 downto 0);
--normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest(BITSELECT,98)@34
normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(25 downto 0);
normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in(25 downto 25);
--expRPath2_uid103_atanX_uid8_fpArctanPiTest(MUX,102)@34
expRPath2_uid103_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b;
expRPath2_uid103_atanX_uid8_fpArctanPiTest: PROCESS (expRPath2_uid103_atanX_uid8_fpArctanPiTest_s, en, cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q, cstBias_uid22_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPath2_uid103_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest(BITSELECT,99)@34
path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(24 downto 0);
path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in(24 downto 1);
--path2DiffLow_uid101_atanX_uid8_fpArctanPiTest(BITSELECT,100)@34
path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(23 downto 0);
path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in(23 downto 0);
--fracRPath2_uid102_atanX_uid8_fpArctanPiTest(MUX,101)@34
fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b;
fracRPath2_uid102_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s, en, path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b, path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b)
BEGIN
CASE fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest(BITJOIN,103)@34
expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q <= expRPath2_uid103_atanX_uid8_fpArctanPiTest_q & fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q;
--reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0(REG,419)@34
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest(ADD,104)@35
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q);
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000" & VCC_q);
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b));
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o(32 downto 0);
--expRPath2_uid107_atanX_uid8_fpArctanPiTest(BITSELECT,106)@35
expRPath2_uid107_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(31 downto 0);
expRPath2_uid107_atanX_uid8_fpArctanPiTest_b <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_in(31 downto 24);
--reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3(REG,426)@35
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor(LOGICAL,1086)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q <= not (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a or ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b);
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena(REG,1087)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q = "1") THEN
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd(LOGICAL,1088)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b <= en;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a and ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg(DELAY,1076)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid15_atanX_uid8_fpArctanPiTest_b, xout => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem(DUALMEM,1077)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 33,
width_b => 8,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq,
address_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa,
data_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia
);
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 <= areset;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq(7 downto 0);
--reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2(REG,425)@35
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,944)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,940)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "010010";
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,941)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,942)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,945)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,946)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--expXIsBias_uid44_atanX_uid8_fpArctanPiTest(LOGICAL,43)@0
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q;
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a = expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b else "0";
--inIsOne_uid45_atanX_uid8_fpArctanPiTest(LOGICAL,44)@0
inIsOne_uid45_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
inIsOne_uid45_atanX_uid8_fpArctanPiTest_b <= expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q;
inIsOne_uid45_atanX_uid8_fpArctanPiTest_q <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_a and inIsOne_uid45_atanX_uid8_fpArctanPiTest_b;
--arctanIsConst_uid55_atanX_uid8_fpArctanPiTest(LOGICAL,54)@0
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_q;
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a or arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c(DELAY,522)@1
ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q, xout => ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasMwShift_uid62_atanX_uid8_fpArctanPiTest(CONSTANT,61)
biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q <= "01110011";
--atanUIsU_uid63_atanX_uid8_fpArctanPiTest(COMPARE,62)@13
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin <= GND_q;
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q) & '0';
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin(0);
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b));
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n(0) <= not atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o(10);
--ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a(DELAY,520)@0
ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => path2_uid56_atanX_uid8_fpArctanPiTest_n, xout => ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--pathSelBits_uid108_atanX_uid8_fpArctanPiTest(BITJOIN,107)@13
pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q <= ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n & ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q;
--reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0(REG,392)@13
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,934)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,936)
-- every=1, low=0, high=18, step=1, init=1
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 17 THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 18;
ELSE
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,5));
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,937)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,938)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,935)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 19,
width_b => 3,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(2 downto 0);
--fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest(LOOKUP,108)@35
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q) IS
WHEN "000" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "001" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "010" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "011" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "110" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "111" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN OTHERS =>
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRCalc_uid113_atanX_uid8_fpArctanPiTest(MUX,112)@36
expRCalc_uid113_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q;
expRCalc_uid113_atanX_uid8_fpArctanPiTest: PROCESS (expRCalc_uid113_atanX_uid8_fpArctanPiTest_s, en, reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q, reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q, ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE expRCalc_uid113_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q;
WHEN "11" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstAllZWE_uid21_atanX_uid8_fpArctanPiTest(CONSTANT,20)
cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q <= "00000000";
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,995)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a or ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,996)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,997)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,985)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid38_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,986)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,982)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,983)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,984)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,972)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q, xout => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,973)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(0 downto 0);
--excSelBits_uid114_atanX_uid8_fpArctanPiTest(BITJOIN,113)@35
excSelBits_uid114_atanX_uid8_fpArctanPiTest_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q & GND_q & ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q;
--reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0(REG,377)@35
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid114_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest(LOOKUP,114)@36
outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid117_atanX_uid8_fpArctanPiTest(MUX,116)@36
expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q;
expRPostExc_uid117_atanX_uid8_fpArctanPiTest: PROCESS (expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, expRCalc_uid113_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid113_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracOutCst_uid110_atanX_uid8_fpArctanPiTest(BITSELECT,109)@35
fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5(REG,424)@35
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor(LOGICAL,968)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q <= not (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a or ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b);
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena(REG,969)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd(LOGICAL,970)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b <= en;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a and ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b;
--fracRPath3_uid88_atanX_uid8_fpArctanPiTest(BITSELECT,87)@31
fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(23 downto 0);
fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in(23 downto 1);
--reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4(REG,423)@31
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,960)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem(DUALMEM,961)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 1,
numwords_a => 2,
width_b => 23,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq,
address_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa,
data_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia
);
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 <= areset;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq(22 downto 0);
--fracRPath2_uid106_atanX_uid8_fpArctanPiTest(BITSELECT,105)@35
fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(23 downto 0);
fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in(23 downto 1);
--reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3(REG,422)@35
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,957)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a or ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,958)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,959)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2(REG,421)@0
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,947)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,948)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 33,
width_b => 23,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(22 downto 0);
--fracRCalc_uid111_atanX_uid8_fpArctanPiTest(MUX,110)@36
fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q;
fracRCalc_uid111_atanX_uid8_fpArctanPiTest: PROCESS (fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s, en, ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q, reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q, reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q;
WHEN "01" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q;
WHEN "11" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid116_atanX_uid8_fpArctanPiTest(MUX,115)@36
fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q;
fracRPostExc_uid116_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid120_atanX_uid8_fpArctanPiTest(BITJOIN,119)@36
R_uid120_atanX_uid8_fpArctanPiTest_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q & expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q & fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q;
--fracX_uid126_rAtanPi_uid13_fpArctanPiTest(BITSELECT,125)@36
fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0);
--reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1(REG,431)@36
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest(LOGICAL,137)@37
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a <= reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q;
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b else "0";
--expX_uid122_rAtanPi_uid13_fpArctanPiTest(BITSELECT,121)@36
expX_uid122_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expX_uid122_rAtanPi_uid13_fpArctanPiTest_b <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23);
--reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1(REG,429)@36
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest(LOGICAL,135)@37
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q;
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b else "0";
--exc_I_uid139_rAtanPi_uid13_fpArctanPiTest(LOGICAL,138)@37
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q;
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q;
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b;
--cstBiasM2_uid6_fpArctanPiTest(CONSTANT,5)
cstBiasM2_uid6_fpArctanPiTest_q <= "01111101";
--ooPi_uid9_fpArctanPiTest(CONSTANT,8)
ooPi_uid9_fpArctanPiTest_q <= "101000101111100110000011";
--fracOOPi_uid10_fpArctanPiTest(BITSELECT,9)@36
fracOOPi_uid10_fpArctanPiTest_in <= ooPi_uid9_fpArctanPiTest_q(22 downto 0);
fracOOPi_uid10_fpArctanPiTest_b <= fracOOPi_uid10_fpArctanPiTest_in(22 downto 0);
--fpOOPi_uid11_fpArctanPiTest(BITJOIN,10)@36
fpOOPi_uid11_fpArctanPiTest_q <= GND_q & cstBiasM2_uid6_fpArctanPiTest_q & fracOOPi_uid10_fpArctanPiTest_b;
--expY_uid123_rAtanPi_uid13_fpArctanPiTest(BITSELECT,122)@36
expY_uid123_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(30 downto 0);
expY_uid123_rAtanPi_uid13_fpArctanPiTest_b <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23);
--expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest(LOGICAL,149)@36
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b;
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a(DELAY,581)@36
ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest(LOGICAL,203)@37
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b;
--fracY_uid128_rAtanPi_uid13_fpArctanPiTest(BITSELECT,127)@36
fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(22 downto 0);
fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0);
--fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest(LOGICAL,153)@36
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b;
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b(DELAY,575)@36
ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest(LOGICAL,151)@36
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b;
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a(DELAY,574)@36
ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid155_rAtanPi_uid13_fpArctanPiTest(LOGICAL,154)@37
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q;
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b <= ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q;
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b;
--expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest(LOGICAL,133)@37
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q;
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b else "0";
--excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest(LOGICAL,204)@37
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b;
--ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest(LOGICAL,205)@37
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q;
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q;
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a or ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b;
--InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest(LOGICAL,155)@36
InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q;
InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a;
--exc_N_uid157_rAtanPi_uid13_fpArctanPiTest(LOGICAL,156)@36
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b;
--ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a(DELAY,579)@36
ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest(LOGICAL,139)@37
InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q;
InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a;
--exc_N_uid141_rAtanPi_uid13_fpArctanPiTest(LOGICAL,140)@37
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b;
--excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest(LOGICAL,206)@37
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c;
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest(LOGICAL,218)@37
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q;
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= not InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a;
END IF;
END PROCESS;
--signY_uid125_rAtanPi_uid13_fpArctanPiTest(BITSELECT,124)@36
signY_uid125_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q;
signY_uid125_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31);
--signX_uid124_rAtanPi_uid13_fpArctanPiTest(BITSELECT,123)@36
signX_uid124_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q;
signX_uid124_rAtanPi_uid13_fpArctanPiTest_b <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31);
--signR_uid190_rAtanPi_uid13_fpArctanPiTest(LOGICAL,189)@36
signR_uid190_rAtanPi_uid13_fpArctanPiTest_a <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_b;
signR_uid190_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_b;
signR_uid190_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= signR_uid190_rAtanPi_uid13_fpArctanPiTest_a xor signR_uid190_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a(DELAY,666)@37
ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid190_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest(LOGICAL,219)@38
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a <= ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q;
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b <= InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q;
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q <= signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a and signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b;
--ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c(DELAY,670)@38
ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest(BITJOIN,128)@36
add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b;
--reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1(REG,433)@36
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest(BITJOIN,126)@36
add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b;
--reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0(REG,432)@36
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--prod_uid165_rAtanPi_uid13_fpArctanPiTest(MULT,164)@37
prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr <= UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_a) * UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_b);
prod_uid165_rAtanPi_uid13_fpArctanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= (others => '0');
prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= (others => '0');
prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q;
prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q;
prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr);
END IF;
END IF;
END PROCESS;
prod_uid165_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1;
END IF;
END IF;
END PROCESS;
--normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest(BITSELECT,165)@40
normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q;
normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in(47 downto 47);
--roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest(CONSTANT,179)
roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q <= "010";
--fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest(BITSELECT,167)@40
fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(46 downto 0);
fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in(46 downto 23);
--fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest(BITSELECT,168)@40
fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(45 downto 0);
fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in(45 downto 22);
--fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest(MUX,169)@40
fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b;
fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s, en, fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b, fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b)
BEGIN
CASE fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "0" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b;
WHEN "1" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b;
WHEN OTHERS => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest(BITSELECT,177)@40
FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in <= fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q(1 downto 0);
FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in(1 downto 0);
--Prod22_uid172_rAtanPi_uid13_fpArctanPiTest(BITSELECT,171)@40
Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(22 downto 0);
Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in(22 downto 22);
--extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest(MUX,172)@40
extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b;
extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest: PROCESS (extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s, en, GND_q, Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b)
BEGIN
CASE extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "0" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b;
WHEN OTHERS => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest(BITSELECT,170)@40
stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(21 downto 0);
stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b <= stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in(21 downto 0);
--stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest(BITJOIN,173)@40
stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q <= extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q & stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b;
--stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest(LOGICAL,175)@40
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a <= stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q;
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q <= "1" when stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a = stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b else "0";
--sticky_uid177_rAtanPi_uid13_fpArctanPiTest(LOGICAL,176)@40
sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a <= stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q;
sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q <= not sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a;
--lrs_uid179_rAtanPi_uid13_fpArctanPiTest(BITJOIN,178)@40
lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b & sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q;
--roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest(LOGICAL,180)@40
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a <= lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q;
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b <= roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q;
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q <= "1" when roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a = roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b else "0";
--roundBit_uid182_rAtanPi_uid13_fpArctanPiTest(LOGICAL,181)@40
roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a <= roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q;
roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q <= not roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a;
--roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest(BITJOIN,184)@40
roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q <= GND_q & normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b & cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q & roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q;
--reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1(REG,436)@40
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--biasInc_uid163_rAtanPi_uid13_fpArctanPiTest(CONSTANT,162)
biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q <= "0001111111";
--ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b(DELAY,586)@36
ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expY_uid123_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expSum_uid162_rAtanPi_uid13_fpArctanPiTest(ADD,161)@37
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q);
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q);
expSum_uid162_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a) + UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q <= expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o(8 downto 0);
--ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a(DELAY,587)@38
ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest(SUB,163)@39
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q);
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q(9)) & biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q);
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b));
END IF;
END IF;
END PROCESS;
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o(10 downto 0);
--expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest(BITJOIN,182)@40
expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q & fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q;
--reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0(REG,435)@40
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest(ADD,185)@41
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q(34)) & reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q);
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q);
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a) + SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b));
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o(35 downto 0);
--expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest(BITSELECT,187)@41
expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q;
expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in(35 downto 24);
--expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest(BITSELECT,188)@41
expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b(7 downto 0);
expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in(7 downto 0);
--ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d(DELAY,664)@41
ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 2 )
PORT MAP ( xin => expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c(DELAY,659)@37
ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1(REG,437)@41
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid193_rAtanPi_uid13_fpArctanPiTest(COMPARE,192)@42
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q;
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & '0';
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q) & expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin(0);
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b));
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o(14);
--InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest(LOGICAL,157)@37
InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q;
InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a;
--InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest(LOGICAL,158)@37
InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a;
--InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest(LOGICAL,159)@37
InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a;
--exc_R_uid161_rAtanPi_uid13_fpArctanPiTest(LOGICAL,160)@37
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c;
--ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b(DELAY,629)@37
ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest(LOGICAL,141)@37
InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a;
--InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest(LOGICAL,142)@37
InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a;
--InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest(LOGICAL,143)@37
InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a;
--exc_R_uid145_rAtanPi_uid13_fpArctanPiTest(LOGICAL,144)@37
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c;
--ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a(DELAY,628)@37
ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest(LOGICAL,201)@42
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c <= expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c;
--excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest(LOGICAL,200)@37
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q;
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q <= excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a and excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c(DELAY,646)@37
ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest(LOGICAL,199)@37
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q;
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q <= excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a and excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b(DELAY,645)@37
ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest(LOGICAL,198)@37
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q <= excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a and excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a(DELAY,644)@37
ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid203_rAtanPi_uid13_fpArctanPiTest(LOGICAL,202)@42
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q <= excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d;
--expUdf_uid191_rAtanPi_uid13_fpArctanPiTest(COMPARE,190)@42
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q;
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0';
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin(0);
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b));
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o(14);
--excZC3_uid197_rAtanPi_uid13_fpArctanPiTest(LOGICAL,196)@42
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c <= expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c;
--excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest(LOGICAL,195)@37
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q;
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c(DELAY,633)@37
ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest(LOGICAL,194)@37
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b(DELAY,632)@37
ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest(LOGICAL,193)@37
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a(DELAY,631)@37
ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid198_rAtanPi_uid13_fpArctanPiTest(LOGICAL,197)@42
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q <= excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d;
--concExc_uid208_rAtanPi_uid13_fpArctanPiTest(BITJOIN,207)@42
concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q <= ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q & excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q & excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q;
--reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0(REG,439)@42
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid209_rAtanPi_uid13_fpArctanPiTest(LOOKUP,208)@43
excREnc_uid209_rAtanPi_uid13_fpArctanPiTest: PROCESS (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q) IS
WHEN "000" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "01";
WHEN "001" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "010" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "10";
WHEN "011" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "100" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "11";
WHEN "101" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "110" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "111" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN OTHERS =>
excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest(MUX,217)@43
expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q;
expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest: PROCESS (expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q;
WHEN "10" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest(BITSELECT,186)@41
fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q(23 downto 0);
fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b <= fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in(23 downto 1);
--ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d(DELAY,662)@41
ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest(MUX,212)@43
fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q;
fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q;
WHEN "10" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid221_rAtanPi_uid13_fpArctanPiTest(BITJOIN,220)@43
R_uid221_rAtanPi_uid13_fpArctanPiTest_q <= ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q & expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q & fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q;
--xOut(GPOUT,4)@43
q <= R_uid221_rAtanPi_uid13_fpArctanPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_atanpi_s5
-- VHDL created on Tue Mar 12 11:23:23 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_atanpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_atanpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBiasM2_uid6_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal ooPi_uid9_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal piO2_uid46_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0);
signal piO4_uid47_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid64_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal zS_uid67_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q : std_logic_vector (12 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a : std_logic_vector (23 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 : std_logic_vector (50 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr : UNSIGNED (50 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q : std_logic_vector (50 downto 0);
signal fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (9 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (10 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector (23 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 : std_logic_vector (47 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr : UNSIGNED (47 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (47 downto 0);
signal roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_q : std_logic_vector (40 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_b : std_logic_vector (21 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_s1 : std_logic_vector (36 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_pr : SIGNED (37 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_q : std_logic_vector (36 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid299_atanXOXTabGen_lutmem_ia : std_logic_vector (30 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_iq : std_logic_vector (30 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_q : std_logic_vector (30 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid300_atanXOXTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid301_atanXOXTabGen_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid344_invTabGen_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid345_invTabGen_lutmem_ia : std_logic_vector (19 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_iq : std_logic_vector (19 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_q : std_logic_vector (19 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid346_invTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q : std_logic_vector (19 downto 0);
signal reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q : std_logic_vector (21 downto 0);
signal reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q : std_logic_vector (28 downto 0);
signal reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q : std_logic_vector (30 downto 0);
signal reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (26 downto 0);
signal reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (8 downto 0);
signal reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (31 downto 0);
signal reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (32 downto 0);
signal reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (22 downto 0);
signal reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (22 downto 0);
signal reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (22 downto 0);
signal reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (7 downto 0);
signal reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (7 downto 0);
signal reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (22 downto 0);
signal reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (23 downto 0);
signal reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (34 downto 0);
signal reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (11 downto 0);
signal reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q : std_logic_vector (7 downto 0);
signal ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (7 downto 0);
signal ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (8 downto 0);
signal ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (22 downto 0);
signal ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (7 downto 0);
signal ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (20 downto 0);
signal ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (18 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q : std_logic_vector (12 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 : std_logic;
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : signal is true;
signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : signal is true;
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : signal is true;
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_c : std_logic_vector (0 downto 0);
signal excSelBits_uid114_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a : std_logic_vector(33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b : std_logic_vector(33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o : std_logic_vector (33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q : std_logic_vector (33 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o : std_logic_vector (32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0);
signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid15_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid15_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid16_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid16_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal singX_uid17_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal singX_uid17_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q : std_logic_vector (9 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_a : std_logic_vector(26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_b : std_logic_vector(26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_o : std_logic_vector (26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (26 downto 0);
signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (35 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal fracOOPi_uid10_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracOOPi_uid10_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid80_atanX_uid8_fpArctanPiTest_in : std_logic_vector (49 downto 0);
signal normBit_uid80_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in : std_logic_vector (48 downto 0);
signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in : std_logic_vector (47 downto 0);
signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (47 downto 0);
signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (46 downto 0);
signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (45 downto 0);
signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (21 downto 0);
signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (21 downto 0);
signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in : std_logic_vector (36 downto 0);
signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b : std_logic_vector (22 downto 0);
signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal R_uid221_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (14 downto 0);
signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (14 downto 0);
signal R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal constOut_uid54_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal constOut_uid54_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal u_uid58_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal u_uid58_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal R_uid120_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (16 downto 0);
signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (8 downto 0);
signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in : std_logic_vector (8 downto 0);
signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in : std_logic_vector (25 downto 0);
signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (11 downto 0);
signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (9 downto 0);
signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (33 downto 0);
signal fpOOPi_uid11_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (32 downto 0);
signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0);
signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (28 downto 0);
signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (24 downto 0);
signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (0 downto 0);
signal stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal lowRangeB_uid304_atanXOXPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid304_atanXOXPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid305_atanXOXPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid305_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid310_atanXOXPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid310_atanXOXPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid311_atanXOXPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid311_atanXOXPolyEval_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid349_invPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid349_invPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid350_invPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid350_invPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid355_invPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid355_invPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid356_invPolyEval_in : std_logic_vector (22 downto 0);
signal highBBits_uid356_invPolyEval_b : std_logic_vector (20 downto 0);
signal y_uid73_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal y_uid73_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0);
signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal yT1_uid347_invPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid347_invPolyEval_b : std_logic_vector (11 downto 0);
signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal expU_uid59_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expU_uid59_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracU_uid60_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracU_uid60_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0);
signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b : std_logic_vector (3 downto 0);
signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (1 downto 0);
signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (34 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_a : std_logic_vector(31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_b : std_logic_vector(31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_o : std_logic_vector (31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_q : std_logic_vector (31 downto 0);
signal sumAHighB_uid351_invPolyEval_a : std_logic_vector(20 downto 0);
signal sumAHighB_uid351_invPolyEval_b : std_logic_vector(20 downto 0);
signal sumAHighB_uid351_invPolyEval_o : std_logic_vector (20 downto 0);
signal sumAHighB_uid351_invPolyEval_q : std_logic_vector (20 downto 0);
signal sumAHighB_uid357_invPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid357_invPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid357_invPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid357_invPolyEval_q : std_logic_vector (29 downto 0);
signal yAddr_uid75_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0);
signal yAddr_uid75_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in : std_logic_vector (26 downto 0);
signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b : std_logic_vector (17 downto 0);
signal rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0);
signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b : std_logic_vector (4 downto 0);
signal expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0);
signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal s1_uid304_uid307_atanXOXPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid310_uid313_atanXOXPolyEval_q : std_logic_vector (33 downto 0);
signal s1_uid349_uid352_invPolyEval_q : std_logic_vector (21 downto 0);
signal s2_uid355_uid358_invPolyEval_q : std_logic_vector (31 downto 0);
signal yT1_uid302_atanXOXPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid302_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (20 downto 0);
signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (18 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0);
signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0);
signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (25 downto 0);
begin
--xIn(GPIN,3)@0
--cstAllZWF_uid19_atanX_uid8_fpArctanPiTest(CONSTANT,18)
cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000000";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable(LOGICAL,878)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q <= not ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,1008)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a or ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,1004)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100001";
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,1005)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,1006)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,1009)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,1010)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--fracX_uid16_atanX_uid8_fpArctanPiTest(BITSELECT,15)@0
fracX_uid16_atanX_uid8_fpArctanPiTest_in <= a(22 downto 0);
fracX_uid16_atanX_uid8_fpArctanPiTest_b <= fracX_uid16_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--fracXIsZero_uid35_atanX_uid8_fpArctanPiTest(LOGICAL,34)@0
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b else "0";
--InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest(LOGICAL,36)@0
InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q <= not InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a;
--cstAllOWE_uid18_atanX_uid8_fpArctanPiTest(CONSTANT,17)
cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q <= "11111111";
--expX_uid15_atanX_uid8_fpArctanPiTest(BITSELECT,14)@0
expX_uid15_atanX_uid8_fpArctanPiTest_in <= a(30 downto 0);
expX_uid15_atanX_uid8_fpArctanPiTest_b <= expX_uid15_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--expXIsMax_uid33_atanX_uid8_fpArctanPiTest(LOGICAL,32)@0
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a = expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b else "0";
--exc_N_uid38_atanX_uid8_fpArctanPiTest(LOGICAL,37)@0
exc_N_uid38_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q;
exc_N_uid38_atanX_uid8_fpArctanPiTest_b <= InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q;
exc_N_uid38_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_a and exc_N_uid38_atanX_uid8_fpArctanPiTest_b;
--InvExc_N_uid118_atanX_uid8_fpArctanPiTest(LOGICAL,117)@0
InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q;
InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q <= not InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a;
--singX_uid17_atanX_uid8_fpArctanPiTest(BITSELECT,16)@0
singX_uid17_atanX_uid8_fpArctanPiTest_in <= a;
singX_uid17_atanX_uid8_fpArctanPiTest_b <= singX_uid17_atanX_uid8_fpArctanPiTest_in(31 downto 31);
--signR_uid119_atanX_uid8_fpArctanPiTest(LOGICAL,118)@0
signR_uid119_atanX_uid8_fpArctanPiTest_a <= singX_uid17_atanX_uid8_fpArctanPiTest_b;
signR_uid119_atanX_uid8_fpArctanPiTest_b <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q;
signR_uid119_atanX_uid8_fpArctanPiTest_q <= signR_uid119_atanX_uid8_fpArctanPiTest_a and signR_uid119_atanX_uid8_fpArctanPiTest_b;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,998)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid119_atanX_uid8_fpArctanPiTest_q, xout => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,1000)
-- every=1, low=0, high=33, step=1, init=1
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 32 THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 33;
ELSE
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6));
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,1001)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,1002)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,999)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 34,
width_b => 1,
widthad_b => 6,
numwords_b => 34,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,879)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a or ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,875)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100000";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,876)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,877)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,880)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,881)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,869)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => singX_uid17_atanX_uid8_fpArctanPiTest_b, xout => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,871)
-- every=1, low=0, high=32, step=1, init=1
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 31 THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 32;
ELSE
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6));
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,872)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,873)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,870)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--cstBias_uid22_atanX_uid8_fpArctanPiTest(CONSTANT,21)
cstBias_uid22_atanX_uid8_fpArctanPiTest_q <= "01111111";
--piO2_uid46_atanX_uid8_fpArctanPiTest(CONSTANT,45)
piO2_uid46_atanX_uid8_fpArctanPiTest_q <= "11001001000011111101101011";
--cstPiO2_uid48_atanX_uid8_fpArctanPiTest(BITSELECT,47)@35
cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in <= piO2_uid46_atanX_uid8_fpArctanPiTest_q(24 downto 0);
cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b <= cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in(24 downto 2);
--fpPiO2C_uid49_atanX_uid8_fpArctanPiTest(BITJOIN,48)@35
fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBias_uid22_atanX_uid8_fpArctanPiTest_q & cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b;
--cstBiasM1_uid23_atanX_uid8_fpArctanPiTest(CONSTANT,22)
cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q <= "01111110";
--piO4_uid47_atanX_uid8_fpArctanPiTest(CONSTANT,46)
piO4_uid47_atanX_uid8_fpArctanPiTest_q <= "110010010000111111011011";
--cstPiO4_uid51_atanX_uid8_fpArctanPiTest(BITSELECT,50)@35
cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in <= piO4_uid47_atanX_uid8_fpArctanPiTest_q(22 downto 0);
cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b <= cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--fpPiO4C_uid52_atanX_uid8_fpArctanPiTest(BITJOIN,51)@35
fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q & cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,892)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a or ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b);
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,893)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,894)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b;
--exc_I_uid36_atanX_uid8_fpArctanPiTest(LOGICAL,35)@0
exc_I_uid36_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q;
exc_I_uid36_atanX_uid8_fpArctanPiTest_b <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
exc_I_uid36_atanX_uid8_fpArctanPiTest_q <= exc_I_uid36_atanX_uid8_fpArctanPiTest_a and exc_I_uid36_atanX_uid8_fpArctanPiTest_b;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,882)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid36_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,883)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq,
address_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa,
data_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia
);
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(0 downto 0);
--constOut_uid54_atanX_uid8_fpArctanPiTest(MUX,53)@35
constOut_uid54_atanX_uid8_fpArctanPiTest_s <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q;
constOut_uid54_atanX_uid8_fpArctanPiTest: PROCESS (constOut_uid54_atanX_uid8_fpArctanPiTest_s, en, fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q, fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE constOut_uid54_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expOutCst_uid112_atanX_uid8_fpArctanPiTest(BITSELECT,111)@35
expOutCst_uid112_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expOutCst_uid112_atanX_uid8_fpArctanPiTest_b <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5(REG,428)@35
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--cst01pWShift_uid69_atanX_uid8_fpArctanPiTest(CONSTANT,68)
cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q <= "0000000000000";
--reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2(REG,389)@0
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= signR_uid119_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c(DELAY,707)@1
ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,1022)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a or ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b);
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top(CONSTANT,1018)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q <= "0111";
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp(LOGICAL,1019)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q);
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q <= "1" when ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a = ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b else "0";
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg(REG,1020)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,1023)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,1024)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b;
--cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,230)
cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111110";
--expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest(SUB,259)@0
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q);
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b);
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b));
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,260)@0
expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0);
expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,229)
cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111101";
--expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest(SUB,256)@0
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q);
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b);
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b));
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,257)@0
expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0);
expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,249)@0
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b else "0";
--expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest(MUX,263)@0
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s <= fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q;
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--expXIsZero_uid31_atanX_uid8_fpArctanPiTest(LOGICAL,30)@0
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a = expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b else "0";
--udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,258)@0
udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in <= STD_LOGIC_VECTOR((9 downto 9 => expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(8)) & expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q);
udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in(9 downto 9);
--InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,245)@0
InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a;
--InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,246)@0
InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a <= expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q;
InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a;
--exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,247)@0
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a <= InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b <= InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c;
--xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,264)@0
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q;
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b;
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a and xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b;
--xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,265)@0
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q;
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q <= xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a or xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b;
--excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,266)@0
excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q & expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q & xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q;
--reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0(REG,378)@0
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest(LOOKUP,267)@1
outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest(MUX,269)@1
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q;
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,1012)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt(COUNTER,1014)
-- every=1, low=0, high=7, step=1, init=1
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg(REG,1015)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux(MUX,1016)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,1013)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia
);
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid20_atanX_uid8_fpArctanPiTest(CONSTANT,19)
cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000001";
--oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,248)@0
oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q <= VCC_q & fracX_uid16_atanX_uid8_fpArctanPiTest_b;
--y_uid251_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,250)@0
y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in <= oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q(22 downto 0);
y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,252)@0
yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b;
yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 15);
--reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0(REG,379)@0
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid346_invTabGen_lutmem(DUALMEM,376)@1
memoryC2_uid346_invTabGen_lutmem_ia <= (others => '0');
memoryC2_uid346_invTabGen_lutmem_aa <= (others => '0');
memoryC2_uid346_invTabGen_lutmem_ab <= reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q;
memoryC2_uid346_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC2_uid346_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid346_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid346_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid346_invTabGen_lutmem_iq,
address_a => memoryC2_uid346_invTabGen_lutmem_aa,
data_a => memoryC2_uid346_invTabGen_lutmem_ia
);
memoryC2_uid346_invTabGen_lutmem_reset0 <= areset;
memoryC2_uid346_invTabGen_lutmem_q <= memoryC2_uid346_invTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1(REG,381)@3
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= memoryC2_uid346_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,1011)
ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a(DELAY,680)@0
ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,253)@3
yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in <= ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q(14 downto 0);
yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in(14 downto 0);
--yT1_uid347_invPolyEval(BITSELECT,346)@3
yT1_uid347_invPolyEval_in <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b;
yT1_uid347_invPolyEval_b <= yT1_uid347_invPolyEval_in(14 downto 3);
--reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0(REG,380)@3
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= yT1_uid347_invPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid366_pT1_uid348_invPolyEval(MULT,365)@4
prodXY_uid366_pT1_uid348_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid366_pT1_uid348_invPolyEval_a),13)) * SIGNED(prodXY_uid366_pT1_uid348_invPolyEval_b);
prodXY_uid366_pT1_uid348_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid366_pT1_uid348_invPolyEval_a <= (others => '0');
prodXY_uid366_pT1_uid348_invPolyEval_b <= (others => '0');
prodXY_uid366_pT1_uid348_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid366_pT1_uid348_invPolyEval_a <= reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q;
prodXY_uid366_pT1_uid348_invPolyEval_b <= reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q;
prodXY_uid366_pT1_uid348_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid366_pT1_uid348_invPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid366_pT1_uid348_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid366_pT1_uid348_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid366_pT1_uid348_invPolyEval_q <= prodXY_uid366_pT1_uid348_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid367_pT1_uid348_invPolyEval(BITSELECT,366)@7
prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in <= prodXY_uid366_pT1_uid348_invPolyEval_q;
prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in(23 downto 11);
--highBBits_uid350_invPolyEval(BITSELECT,349)@7
highBBits_uid350_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b;
highBBits_uid350_invPolyEval_b <= highBBits_uid350_invPolyEval_in(12 downto 1);
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a(DELAY,804)@1
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid345_invTabGen_lutmem(DUALMEM,375)@4
memoryC1_uid345_invTabGen_lutmem_ia <= (others => '0');
memoryC1_uid345_invTabGen_lutmem_aa <= (others => '0');
memoryC1_uid345_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q;
memoryC1_uid345_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 20,
widthad_a => 8,
numwords_a => 256,
width_b => 20,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC1_uid345_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid345_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid345_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid345_invTabGen_lutmem_iq,
address_a => memoryC1_uid345_invTabGen_lutmem_aa,
data_a => memoryC1_uid345_invTabGen_lutmem_ia
);
memoryC1_uid345_invTabGen_lutmem_reset0 <= areset;
memoryC1_uid345_invTabGen_lutmem_q <= memoryC1_uid345_invTabGen_lutmem_iq(19 downto 0);
--reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0(REG,383)@6
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= "00000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= memoryC1_uid345_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid351_invPolyEval(ADD,350)@7
sumAHighB_uid351_invPolyEval_a <= STD_LOGIC_VECTOR((20 downto 20 => reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q(19)) & reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q);
sumAHighB_uid351_invPolyEval_b <= STD_LOGIC_VECTOR((20 downto 12 => highBBits_uid350_invPolyEval_b(11)) & highBBits_uid350_invPolyEval_b);
sumAHighB_uid351_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid351_invPolyEval_a) + SIGNED(sumAHighB_uid351_invPolyEval_b));
sumAHighB_uid351_invPolyEval_q <= sumAHighB_uid351_invPolyEval_o(20 downto 0);
--lowRangeB_uid349_invPolyEval(BITSELECT,348)@7
lowRangeB_uid349_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b(0 downto 0);
lowRangeB_uid349_invPolyEval_b <= lowRangeB_uid349_invPolyEval_in(0 downto 0);
--s1_uid349_uid352_invPolyEval(BITJOIN,351)@7
s1_uid349_uid352_invPolyEval_q <= sumAHighB_uid351_invPolyEval_q & lowRangeB_uid349_invPolyEval_b;
--reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1(REG,385)@7
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= "0000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= s1_uid349_uid352_invPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor(LOGICAL,1059)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a or ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b);
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg(REG,966)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena(REG,1060)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q = "1") THEN
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd(LOGICAL,1061)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b <= en;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg(DELAY,1051)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt(COUNTER,962)
-- every=1, low=0, high=1, step=1, init=1
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i,1));
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg(REG,963)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux(MUX,964)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s <= en;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux: PROCESS (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q)
BEGIN
CASE ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s IS
WHEN "0" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
WHEN "1" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q;
WHEN OTHERS => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem(DUALMEM,1052)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia
);
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0(REG,384)@7
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid369_pT2_uid354_invPolyEval(MULT,368)@8
prodXY_uid369_pT2_uid354_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid369_pT2_uid354_invPolyEval_a),16)) * SIGNED(prodXY_uid369_pT2_uid354_invPolyEval_b);
prodXY_uid369_pT2_uid354_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid369_pT2_uid354_invPolyEval_a <= (others => '0');
prodXY_uid369_pT2_uid354_invPolyEval_b <= (others => '0');
prodXY_uid369_pT2_uid354_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid369_pT2_uid354_invPolyEval_a <= reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q;
prodXY_uid369_pT2_uid354_invPolyEval_b <= reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q;
prodXY_uid369_pT2_uid354_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid369_pT2_uid354_invPolyEval_pr,37));
END IF;
END IF;
END PROCESS;
prodXY_uid369_pT2_uid354_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid369_pT2_uid354_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid369_pT2_uid354_invPolyEval_q <= prodXY_uid369_pT2_uid354_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid370_pT2_uid354_invPolyEval(BITSELECT,369)@11
prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in <= prodXY_uid369_pT2_uid354_invPolyEval_q;
prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in(36 downto 14);
--highBBits_uid356_invPolyEval(BITSELECT,355)@11
highBBits_uid356_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b;
highBBits_uid356_invPolyEval_b <= highBBits_uid356_invPolyEval_in(22 downto 2);
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor(LOGICAL,1048)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q <= not (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a or ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b);
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top(CONSTANT,1031)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q <= "0100";
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp(LOGICAL,1032)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q <= "1" when ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a = ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b else "0";
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg(REG,1033)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena(REG,1049)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd(LOGICAL,1050)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a and ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg(DELAY,1038)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt(COUNTER,1027)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i,3));
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg(REG,1028)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux(MUX,1029)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s <= en;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux: PROCESS (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem(DUALMEM,1039)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq(7 downto 0);
--memoryC0_uid344_invTabGen_lutmem(DUALMEM,374)@8
memoryC0_uid344_invTabGen_lutmem_ia <= (others => '0');
memoryC0_uid344_invTabGen_lutmem_aa <= (others => '0');
memoryC0_uid344_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q;
memoryC0_uid344_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC0_uid344_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid344_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid344_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid344_invTabGen_lutmem_iq,
address_a => memoryC0_uid344_invTabGen_lutmem_aa,
data_a => memoryC0_uid344_invTabGen_lutmem_ia
);
memoryC0_uid344_invTabGen_lutmem_reset0 <= areset;
memoryC0_uid344_invTabGen_lutmem_q <= memoryC0_uid344_invTabGen_lutmem_iq(28 downto 0);
--reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0(REG,387)@10
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= "00000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= memoryC0_uid344_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid357_invPolyEval(ADD,356)@11
sumAHighB_uid357_invPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q(28)) & reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q);
sumAHighB_uid357_invPolyEval_b <= STD_LOGIC_VECTOR((29 downto 21 => highBBits_uid356_invPolyEval_b(20)) & highBBits_uid356_invPolyEval_b);
sumAHighB_uid357_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid357_invPolyEval_a) + SIGNED(sumAHighB_uid357_invPolyEval_b));
sumAHighB_uid357_invPolyEval_q <= sumAHighB_uid357_invPolyEval_o(29 downto 0);
--lowRangeB_uid355_invPolyEval(BITSELECT,354)@11
lowRangeB_uid355_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b(1 downto 0);
lowRangeB_uid355_invPolyEval_b <= lowRangeB_uid355_invPolyEval_in(1 downto 0);
--s2_uid355_uid358_invPolyEval(BITJOIN,357)@11
s2_uid355_uid358_invPolyEval_q <= sumAHighB_uid357_invPolyEval_q & lowRangeB_uid355_invPolyEval_b;
--fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,255)@11
fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in <= s2_uid355_uid358_invPolyEval_q(28 downto 0);
fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in(28 downto 5);
--fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,261)@11
fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b(22 downto 0);
fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,688)@0
ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest(MUX,262)@11
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q;
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1(REG,388)@1
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,701)@2
ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 10 )
PORT MAP ( xin => reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest(MUX,268)@12
fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q;
fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid273_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,272)@12
R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q <= ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q & fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,905)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a or ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,901)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "01001";
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,902)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,903)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,906)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,907)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,895)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,897)
-- every=1, low=0, high=9, step=1, init=1
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 8 THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 9;
ELSE
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,4));
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,898)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,899)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,896)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 4,
numwords_a => 10,
width_b => 32,
widthad_b => 4,
numwords_b => 10,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(31 downto 0);
--path2_uid56_atanX_uid8_fpArctanPiTest(COMPARE,55)@0
path2_uid56_atanX_uid8_fpArctanPiTest_cin <= GND_q;
path2_uid56_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid15_atanX_uid8_fpArctanPiTest_b) & '0';
path2_uid56_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q) & path2_uid56_atanX_uid8_fpArctanPiTest_cin(0);
path2_uid56_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_b));
path2_uid56_atanX_uid8_fpArctanPiTest_n(0) <= not path2_uid56_atanX_uid8_fpArctanPiTest_o(10);
--reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1(REG,390)@0
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= path2_uid56_atanX_uid8_fpArctanPiTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b(DELAY,466)@1
ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--u_uid58_atanX_uid8_fpArctanPiTest(MUX,57)@12
u_uid58_atanX_uid8_fpArctanPiTest_s <= ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q;
u_uid58_atanX_uid8_fpArctanPiTest: PROCESS (u_uid58_atanX_uid8_fpArctanPiTest_s, en, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q, R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE u_uid58_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => u_uid58_atanX_uid8_fpArctanPiTest_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q;
WHEN "1" => u_uid58_atanX_uid8_fpArctanPiTest_q <= R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => u_uid58_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracU_uid60_atanX_uid8_fpArctanPiTest(BITSELECT,59)@12
fracU_uid60_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracU_uid60_atanX_uid8_fpArctanPiTest_b <= fracU_uid60_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a(DELAY,471)@12
ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracU_uid60_atanX_uid8_fpArctanPiTest_b, xout => ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest(BITJOIN,60)@13
oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q;
--oFracUExt_uid70_atanX_uid8_fpArctanPiTest(BITJOIN,69)@13
oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q <= cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q & oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q;
--X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,282)@13
X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(24 downto 0);
X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(24 downto 0);
--leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,281)
leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000000000000";
--leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,283)@13
leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5(REG,399)@13
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,279)@13
X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(28 downto 0);
X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(28 downto 0);
--leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,280)@13
leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4(REG,398)@13
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,276)@13
X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(32 downto 0);
X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(32 downto 0);
--leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,275)
leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "0000";
--leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,277)@13
leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3(REG,397)@13
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,396)@13
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--zS_uid67_atanX_uid8_fpArctanPiTest(CONSTANT,66)
zS_uid67_atanX_uid8_fpArctanPiTest_q <= "000000000";
--shiftBias_uid64_atanX_uid8_fpArctanPiTest(CONSTANT,63)
shiftBias_uid64_atanX_uid8_fpArctanPiTest_q <= "01110010";
--expU_uid59_atanX_uid8_fpArctanPiTest(BITSELECT,58)@12
expU_uid59_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expU_uid59_atanX_uid8_fpArctanPiTest_b <= expU_uid59_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1(REG,391)@12
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= expU_uid59_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--shiftValue_uid65_atanX_uid8_fpArctanPiTest(SUB,64)@13
shiftValue_uid65_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q);
shiftValue_uid65_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid64_atanX_uid8_fpArctanPiTest_q);
shiftValue_uid65_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_b));
shiftValue_uid65_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--ShiftValue8_uid66_atanX_uid8_fpArctanPiTest(BITSELECT,65)@13
ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q;
ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in(8 downto 8);
--shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest(MUX,67)@13
shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b;
shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest: PROCESS (shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s, en, shiftValue_uid65_atanX_uid8_fpArctanPiTest_q, zS_uid67_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= zS_uid67_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest(BITSELECT,70)@13
fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in <= shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q(3 downto 0);
fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,284)@13
leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b;
leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,395)@13
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,285)@14
leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q;
leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q, reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q, reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q;
WHEN "11" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,293)@14
LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(33 downto 0);
LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(33 downto 0);
--ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,725)@14
ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,292)
leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000";
--leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,294)@15
leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,290)@14
LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(34 downto 0);
LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(34 downto 0);
--ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,723)@14
ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,289)
leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "00";
--leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,291)@15
leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,287)@14
LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0);
LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(35 downto 0);
--ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,721)@14
ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,288)@15
leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & GND_q;
--reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,401)@14
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,295)@13
leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a(DELAY,829)@13
ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,400)@14
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,296)@15
leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q;
leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid73_atanX_uid8_fpArctanPiTest(BITSELECT,72)@15
y_uid73_atanX_uid8_fpArctanPiTest_in <= leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0);
y_uid73_atanX_uid8_fpArctanPiTest_b <= y_uid73_atanX_uid8_fpArctanPiTest_in(35 downto 1);
--yAddr_uid75_atanX_uid8_fpArctanPiTest(BITSELECT,74)@15
yAddr_uid75_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b;
yAddr_uid75_atanX_uid8_fpArctanPiTest_b <= yAddr_uid75_atanX_uid8_fpArctanPiTest_in(34 downto 27);
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0(REG,402)@15
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= yAddr_uid75_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid301_atanXOXTabGen_lutmem(DUALMEM,373)@16
memoryC2_uid301_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC2_uid301_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC2_uid301_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q;
memoryC2_uid301_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC2_uid301_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid301_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid301_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid301_atanXOXTabGen_lutmem_iq,
address_a => memoryC2_uid301_atanXOXTabGen_lutmem_aa,
data_a => memoryC2_uid301_atanXOXTabGen_lutmem_ia
);
memoryC2_uid301_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC2_uid301_atanXOXTabGen_lutmem_q <= memoryC2_uid301_atanXOXTabGen_lutmem_iq(12 downto 0);
--reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1(REG,404)@18
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= memoryC2_uid301_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--yPPolyEval_uid76_atanX_uid8_fpArctanPiTest(BITSELECT,75)@15
yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b(26 downto 0);
yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in(26 downto 9);
--yT1_uid302_atanXOXPolyEval(BITSELECT,301)@15
yT1_uid302_atanXOXPolyEval_in <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b;
yT1_uid302_atanXOXPolyEval_b <= yT1_uid302_atanXOXPolyEval_in(17 downto 5);
--ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg(DELAY,1062)
ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid302_atanXOXPolyEval_b, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a(DELAY,832)@15
ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0(REG,403)@18
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid360_pT1_uid303_atanXOXPolyEval(MULT,359)@19
prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_a),14)) * SIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_b);
prodXY_uid360_pT1_uid303_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= (others => '0');
prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= (others => '0');
prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q;
prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q;
prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid360_pT1_uid303_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval(BITSELECT,360)@22
prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_q;
prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in(25 downto 12);
--highBBits_uid305_atanXOXPolyEval(BITSELECT,304)@22
highBBits_uid305_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b;
highBBits_uid305_atanXOXPolyEval_b <= highBBits_uid305_atanXOXPolyEval_in(13 downto 1);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a(DELAY,834)@15
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0(REG,405)@18
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid300_atanXOXTabGen_lutmem(DUALMEM,372)@19
memoryC1_uid300_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC1_uid300_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC1_uid300_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q;
memoryC1_uid300_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC1_uid300_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid300_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid300_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid300_atanXOXTabGen_lutmem_iq,
address_a => memoryC1_uid300_atanXOXTabGen_lutmem_aa,
data_a => memoryC1_uid300_atanXOXTabGen_lutmem_ia
);
memoryC1_uid300_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC1_uid300_atanXOXTabGen_lutmem_q <= memoryC1_uid300_atanXOXTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0(REG,406)@21
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= memoryC1_uid300_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid306_atanXOXPolyEval(ADD,305)@22
sumAHighB_uid306_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q(20)) & reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q);
sumAHighB_uid306_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid305_atanXOXPolyEval_b(12)) & highBBits_uid305_atanXOXPolyEval_b);
sumAHighB_uid306_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid306_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid306_atanXOXPolyEval_b));
sumAHighB_uid306_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_o(21 downto 0);
--lowRangeB_uid304_atanXOXPolyEval(BITSELECT,303)@22
lowRangeB_uid304_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b(0 downto 0);
lowRangeB_uid304_atanXOXPolyEval_b <= lowRangeB_uid304_atanXOXPolyEval_in(0 downto 0);
--s1_uid304_uid307_atanXOXPolyEval(BITJOIN,306)@22
s1_uid304_uid307_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_q & lowRangeB_uid304_atanXOXPolyEval_b;
--reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1(REG,408)@22
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= s1_uid304_uid307_atanXOXPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor(LOGICAL,1035)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q <= not (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a or ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b);
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena(REG,1036)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd(LOGICAL,1037)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b <= en;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a and ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b;
--reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0(REG,407)@15
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg(DELAY,1025)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q, xout => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem(DUALMEM,1026)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq,
address_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa,
data_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia
);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid363_pT2_uid309_atanXOXPolyEval(MULT,362)@23
prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_a),19)) * SIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_b);
prodXY_uid363_pT2_uid309_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= (others => '0');
prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= (others => '0');
prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q;
prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q;
prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid363_pT2_uid309_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval(BITSELECT,363)@26
prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_q;
prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in(40 downto 17);
--highBBits_uid311_atanXOXPolyEval(BITSELECT,310)@26
highBBits_uid311_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b;
highBBits_uid311_atanXOXPolyEval_b <= highBBits_uid311_atanXOXPolyEval_in(23 downto 2);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor(LOGICAL,1073)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q <= not (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a or ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena(REG,1074)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q = "1") THEN
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd(LOGICAL,1075)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b <= en;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a and ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b;
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg(DELAY,1063)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem(DUALMEM,1064)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia
);
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0(REG,409)@22
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid299_atanXOXTabGen_lutmem(DUALMEM,371)@23
memoryC0_uid299_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC0_uid299_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC0_uid299_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q;
memoryC0_uid299_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 31,
widthad_a => 8,
numwords_a => 256,
width_b => 31,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC0_uid299_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid299_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid299_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid299_atanXOXTabGen_lutmem_iq,
address_a => memoryC0_uid299_atanXOXTabGen_lutmem_aa,
data_a => memoryC0_uid299_atanXOXTabGen_lutmem_ia
);
memoryC0_uid299_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC0_uid299_atanXOXTabGen_lutmem_q <= memoryC0_uid299_atanXOXTabGen_lutmem_iq(30 downto 0);
--reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0(REG,410)@25
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= memoryC0_uid299_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid312_atanXOXPolyEval(ADD,311)@26
sumAHighB_uid312_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((31 downto 31 => reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q(30)) & reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q);
sumAHighB_uid312_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((31 downto 22 => highBBits_uid311_atanXOXPolyEval_b(21)) & highBBits_uid311_atanXOXPolyEval_b);
sumAHighB_uid312_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid312_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid312_atanXOXPolyEval_b));
sumAHighB_uid312_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_o(31 downto 0);
--lowRangeB_uid310_atanXOXPolyEval(BITSELECT,309)@26
lowRangeB_uid310_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b(1 downto 0);
lowRangeB_uid310_atanXOXPolyEval_b <= lowRangeB_uid310_atanXOXPolyEval_in(1 downto 0);
--s2_uid310_uid313_atanXOXPolyEval(BITJOIN,312)@26
s2_uid310_uid313_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_q & lowRangeB_uid310_atanXOXPolyEval_b;
--fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest(BITSELECT,77)@26
fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in <= s2_uid310_uid313_atanXOXPolyEval_q(31 downto 0);
fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in(31 downto 5);
--reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1(REG,412)@26
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,918)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,914)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01010";
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,915)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,916)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,919)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,920)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0(REG,411)@13
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,908)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,910)
-- every=1, low=0, high=10, step=1, init=1
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 9 THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 10;
ELSE
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4));
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,911)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,912)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,909)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 11,
width_b => 24,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(23 downto 0);
--mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest(MULT,78)@27
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr <= UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a) * UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b);
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= (others => '0');
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= (others => '0');
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr);
END IF;
END IF;
END PROCESS;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid80_atanX_uid8_fpArctanPiTest(BITSELECT,79)@30
normBit_uid80_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(49 downto 0);
normBit_uid80_atanX_uid8_fpArctanPiTest_b <= normBit_uid80_atanX_uid8_fpArctanPiTest_in(49 downto 49);
--InvNormBit_uid84_atanX_uid8_fpArctanPiTest(LOGICAL,83)@30
InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a <= normBit_uid80_atanX_uid8_fpArctanPiTest_b;
InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q <= not InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,931)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,927)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01111";
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,928)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,929)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,932)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,933)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,921)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expU_uid59_atanX_uid8_fpArctanPiTest_b, xout => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,923)
-- every=1, low=0, high=15, step=1, init=1
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4));
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,924)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,925)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,922)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 16,
width_b => 8,
widthad_b => 4,
numwords_b => 16,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(7 downto 0);
--expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest(SUB,84)@30
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q);
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000" & InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q);
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b));
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--fracRPath3High_uid81_atanX_uid8_fpArctanPiTest(BITSELECT,80)@30
fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(48 downto 0);
fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in(48 downto 25);
--fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest(BITSELECT,81)@30
fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(47 downto 0);
fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in(47 downto 24);
--fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest(MUX,82)@30
fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s <= normBit_uid80_atanX_uid8_fpArctanPiTest_b;
fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s, en, fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b, fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b)
BEGIN
CASE fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest(BITJOIN,85)@30
expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q & fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q;
--reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0(REG,420)@30
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest(ADD,86)@31
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q);
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000" & VCC_q);
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b));
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o(33 downto 0);
--expRPath3_uid89_atanX_uid8_fpArctanPiTest(BITSELECT,88)@31
expRPath3_uid89_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(31 downto 0);
expRPath3_uid89_atanX_uid8_fpArctanPiTest_b <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_in(31 downto 24);
--reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4(REG,427)@31
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,971)
ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e(DELAY,534)@32
ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,337)@33
RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 1);
--rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,339)@33
rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= GND_q & RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,333)
rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000";
--rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,322)
rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000000000000000000000";
--X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,321)@32
X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 24);
--rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,323)@32
rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,319)
rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "0000000000000000";
--X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,318)@32
X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 16);
--rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,320)@32
rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,315)@32
X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 8);
--rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,317)@32
rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q & X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a(DELAY,504)@30
ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q, xout => ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest(BITJOIN,93)@32
oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q;
--cstWFP2_uid25_atanX_uid8_fpArctanPiTest(CONSTANT,24)
cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q <= "00011001";
--reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1(REG,413)@30
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest(SUB,89)@31
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q);
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR((10 downto 9 => reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q(8)) & reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q);
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a) - SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b));
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o(9 downto 0);
--shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest(BITSELECT,91)@31
shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q(7 downto 0);
shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest(CONSTANT,23)
cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q <= "01101000";
--shiftOut_uid91_atanX_uid8_fpArctanPiTest(COMPARE,90)@13
shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin <= GND_q;
shiftOut_uid91_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & '0';
shiftOut_uid91_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q) & shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin(0);
shiftOut_uid91_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_b));
shiftOut_uid91_atanX_uid8_fpArctanPiTest_c(0) <= shiftOut_uid91_atanX_uid8_fpArctanPiTest_o(10);
--ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b(DELAY,502)@13
ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => shiftOut_uid91_atanX_uid8_fpArctanPiTest_c, xout => ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--sValPostSOut_uid93_atanX_uid8_fpArctanPiTest(MUX,92)@31
sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s <= ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q;
sValPostSOut_uid93_atanX_uid8_fpArctanPiTest: PROCESS (sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s, en, shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b, cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest(BITSELECT,94)@31
sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in <= sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q(4 downto 0);
sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,324)@31
rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b;
rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,414)@31
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,325)@32
rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q;
rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,332)@32
RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 6);
--ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,762)@32
ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,334)@33
rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,329)@32
RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 4);
--ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,760)@32
ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 21, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,331)@33
rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,326)@32
RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 2);
--ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,758)@32
ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,328)@33
rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2(REG,416)@32
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,335)@31
rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(2 downto 1);
--ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a(DELAY,844)@31
ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,415)@32
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,336)@33
rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q;
rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q, rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,340)@31
rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,417)@31
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b(DELAY,772)@32
ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,341)@33
rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q;
rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest(BITJOIN,96)@33
pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & GND_q;
--reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1(REG,418)@33
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--path2Diff_uid97_atanX_uid8_fpArctanPiTest(SUB,97)@34
path2Diff_uid97_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & piO2_uid46_atanX_uid8_fpArctanPiTest_q);
path2Diff_uid97_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q);
path2Diff_uid97_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_b));
path2Diff_uid97_atanX_uid8_fpArctanPiTest_q <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_o(26 downto 0);
--normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest(BITSELECT,98)@34
normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(25 downto 0);
normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in(25 downto 25);
--expRPath2_uid103_atanX_uid8_fpArctanPiTest(MUX,102)@34
expRPath2_uid103_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b;
expRPath2_uid103_atanX_uid8_fpArctanPiTest: PROCESS (expRPath2_uid103_atanX_uid8_fpArctanPiTest_s, en, cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q, cstBias_uid22_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPath2_uid103_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest(BITSELECT,99)@34
path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(24 downto 0);
path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in(24 downto 1);
--path2DiffLow_uid101_atanX_uid8_fpArctanPiTest(BITSELECT,100)@34
path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(23 downto 0);
path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in(23 downto 0);
--fracRPath2_uid102_atanX_uid8_fpArctanPiTest(MUX,101)@34
fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b;
fracRPath2_uid102_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s, en, path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b, path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b)
BEGIN
CASE fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest(BITJOIN,103)@34
expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q <= expRPath2_uid103_atanX_uid8_fpArctanPiTest_q & fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q;
--reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0(REG,419)@34
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest(ADD,104)@35
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q);
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000" & VCC_q);
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b));
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o(32 downto 0);
--expRPath2_uid107_atanX_uid8_fpArctanPiTest(BITSELECT,106)@35
expRPath2_uid107_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(31 downto 0);
expRPath2_uid107_atanX_uid8_fpArctanPiTest_b <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_in(31 downto 24);
--reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3(REG,426)@35
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor(LOGICAL,1086)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q <= not (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a or ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b);
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena(REG,1087)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q = "1") THEN
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd(LOGICAL,1088)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b <= en;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a and ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg(DELAY,1076)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid15_atanX_uid8_fpArctanPiTest_b, xout => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem(DUALMEM,1077)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 33,
width_b => 8,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq,
address_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa,
data_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia
);
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 <= areset;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq(7 downto 0);
--reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2(REG,425)@35
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,944)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,940)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "010010";
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,941)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,942)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,945)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,946)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--expXIsBias_uid44_atanX_uid8_fpArctanPiTest(LOGICAL,43)@0
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q;
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a = expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b else "0";
--inIsOne_uid45_atanX_uid8_fpArctanPiTest(LOGICAL,44)@0
inIsOne_uid45_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
inIsOne_uid45_atanX_uid8_fpArctanPiTest_b <= expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q;
inIsOne_uid45_atanX_uid8_fpArctanPiTest_q <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_a and inIsOne_uid45_atanX_uid8_fpArctanPiTest_b;
--arctanIsConst_uid55_atanX_uid8_fpArctanPiTest(LOGICAL,54)@0
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_q;
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a or arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c(DELAY,522)@1
ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q, xout => ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasMwShift_uid62_atanX_uid8_fpArctanPiTest(CONSTANT,61)
biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q <= "01110011";
--atanUIsU_uid63_atanX_uid8_fpArctanPiTest(COMPARE,62)@13
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin <= GND_q;
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q) & '0';
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin(0);
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b));
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n(0) <= not atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o(10);
--ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a(DELAY,520)@0
ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => path2_uid56_atanX_uid8_fpArctanPiTest_n, xout => ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--pathSelBits_uid108_atanX_uid8_fpArctanPiTest(BITJOIN,107)@13
pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q <= ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n & ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q;
--reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0(REG,392)@13
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,934)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,936)
-- every=1, low=0, high=18, step=1, init=1
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 17 THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 18;
ELSE
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,5));
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,937)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,938)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,935)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 19,
width_b => 3,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(2 downto 0);
--fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest(LOOKUP,108)@35
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q) IS
WHEN "000" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "001" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "010" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "011" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "110" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "111" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN OTHERS =>
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRCalc_uid113_atanX_uid8_fpArctanPiTest(MUX,112)@36
expRCalc_uid113_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q;
expRCalc_uid113_atanX_uid8_fpArctanPiTest: PROCESS (expRCalc_uid113_atanX_uid8_fpArctanPiTest_s, en, reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q, reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q, ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE expRCalc_uid113_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q;
WHEN "11" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstAllZWE_uid21_atanX_uid8_fpArctanPiTest(CONSTANT,20)
cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q <= "00000000";
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,995)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a or ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,996)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,997)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,985)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid38_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,986)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,982)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,983)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,984)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,972)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q, xout => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,973)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(0 downto 0);
--excSelBits_uid114_atanX_uid8_fpArctanPiTest(BITJOIN,113)@35
excSelBits_uid114_atanX_uid8_fpArctanPiTest_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q & GND_q & ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q;
--reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0(REG,377)@35
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid114_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest(LOOKUP,114)@36
outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid117_atanX_uid8_fpArctanPiTest(MUX,116)@36
expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q;
expRPostExc_uid117_atanX_uid8_fpArctanPiTest: PROCESS (expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, expRCalc_uid113_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid113_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracOutCst_uid110_atanX_uid8_fpArctanPiTest(BITSELECT,109)@35
fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5(REG,424)@35
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor(LOGICAL,968)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q <= not (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a or ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b);
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena(REG,969)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd(LOGICAL,970)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b <= en;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a and ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b;
--fracRPath3_uid88_atanX_uid8_fpArctanPiTest(BITSELECT,87)@31
fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(23 downto 0);
fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in(23 downto 1);
--reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4(REG,423)@31
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,960)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem(DUALMEM,961)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 1,
numwords_a => 2,
width_b => 23,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq,
address_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa,
data_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia
);
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 <= areset;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq(22 downto 0);
--fracRPath2_uid106_atanX_uid8_fpArctanPiTest(BITSELECT,105)@35
fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(23 downto 0);
fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in(23 downto 1);
--reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3(REG,422)@35
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,957)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a or ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,958)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,959)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2(REG,421)@0
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,947)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,948)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 33,
width_b => 23,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(22 downto 0);
--fracRCalc_uid111_atanX_uid8_fpArctanPiTest(MUX,110)@36
fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q;
fracRCalc_uid111_atanX_uid8_fpArctanPiTest: PROCESS (fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s, en, ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q, reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q, reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q;
WHEN "01" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q;
WHEN "11" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid116_atanX_uid8_fpArctanPiTest(MUX,115)@36
fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q;
fracRPostExc_uid116_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid120_atanX_uid8_fpArctanPiTest(BITJOIN,119)@36
R_uid120_atanX_uid8_fpArctanPiTest_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q & expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q & fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q;
--fracX_uid126_rAtanPi_uid13_fpArctanPiTest(BITSELECT,125)@36
fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0);
--reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1(REG,431)@36
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest(LOGICAL,137)@37
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a <= reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q;
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b else "0";
--expX_uid122_rAtanPi_uid13_fpArctanPiTest(BITSELECT,121)@36
expX_uid122_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expX_uid122_rAtanPi_uid13_fpArctanPiTest_b <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23);
--reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1(REG,429)@36
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest(LOGICAL,135)@37
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q;
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b else "0";
--exc_I_uid139_rAtanPi_uid13_fpArctanPiTest(LOGICAL,138)@37
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q;
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q;
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b;
--cstBiasM2_uid6_fpArctanPiTest(CONSTANT,5)
cstBiasM2_uid6_fpArctanPiTest_q <= "01111101";
--ooPi_uid9_fpArctanPiTest(CONSTANT,8)
ooPi_uid9_fpArctanPiTest_q <= "101000101111100110000011";
--fracOOPi_uid10_fpArctanPiTest(BITSELECT,9)@36
fracOOPi_uid10_fpArctanPiTest_in <= ooPi_uid9_fpArctanPiTest_q(22 downto 0);
fracOOPi_uid10_fpArctanPiTest_b <= fracOOPi_uid10_fpArctanPiTest_in(22 downto 0);
--fpOOPi_uid11_fpArctanPiTest(BITJOIN,10)@36
fpOOPi_uid11_fpArctanPiTest_q <= GND_q & cstBiasM2_uid6_fpArctanPiTest_q & fracOOPi_uid10_fpArctanPiTest_b;
--expY_uid123_rAtanPi_uid13_fpArctanPiTest(BITSELECT,122)@36
expY_uid123_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(30 downto 0);
expY_uid123_rAtanPi_uid13_fpArctanPiTest_b <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23);
--expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest(LOGICAL,149)@36
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b;
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a(DELAY,581)@36
ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest(LOGICAL,203)@37
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b;
--fracY_uid128_rAtanPi_uid13_fpArctanPiTest(BITSELECT,127)@36
fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(22 downto 0);
fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0);
--fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest(LOGICAL,153)@36
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b;
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b(DELAY,575)@36
ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest(LOGICAL,151)@36
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b;
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a(DELAY,574)@36
ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid155_rAtanPi_uid13_fpArctanPiTest(LOGICAL,154)@37
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q;
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b <= ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q;
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b;
--expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest(LOGICAL,133)@37
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q;
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b else "0";
--excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest(LOGICAL,204)@37
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b;
--ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest(LOGICAL,205)@37
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q;
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q;
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a or ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b;
--InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest(LOGICAL,155)@36
InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q;
InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a;
--exc_N_uid157_rAtanPi_uid13_fpArctanPiTest(LOGICAL,156)@36
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b;
--ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a(DELAY,579)@36
ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest(LOGICAL,139)@37
InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q;
InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a;
--exc_N_uid141_rAtanPi_uid13_fpArctanPiTest(LOGICAL,140)@37
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b;
--excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest(LOGICAL,206)@37
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c;
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest(LOGICAL,218)@37
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q;
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= not InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a;
END IF;
END PROCESS;
--signY_uid125_rAtanPi_uid13_fpArctanPiTest(BITSELECT,124)@36
signY_uid125_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q;
signY_uid125_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31);
--signX_uid124_rAtanPi_uid13_fpArctanPiTest(BITSELECT,123)@36
signX_uid124_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q;
signX_uid124_rAtanPi_uid13_fpArctanPiTest_b <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31);
--signR_uid190_rAtanPi_uid13_fpArctanPiTest(LOGICAL,189)@36
signR_uid190_rAtanPi_uid13_fpArctanPiTest_a <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_b;
signR_uid190_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_b;
signR_uid190_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= signR_uid190_rAtanPi_uid13_fpArctanPiTest_a xor signR_uid190_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a(DELAY,666)@37
ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid190_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest(LOGICAL,219)@38
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a <= ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q;
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b <= InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q;
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q <= signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a and signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b;
--ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c(DELAY,670)@38
ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest(BITJOIN,128)@36
add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b;
--reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1(REG,433)@36
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest(BITJOIN,126)@36
add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b;
--reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0(REG,432)@36
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--prod_uid165_rAtanPi_uid13_fpArctanPiTest(MULT,164)@37
prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr <= UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_a) * UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_b);
prod_uid165_rAtanPi_uid13_fpArctanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= (others => '0');
prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= (others => '0');
prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q;
prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q;
prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr);
END IF;
END IF;
END PROCESS;
prod_uid165_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1;
END IF;
END IF;
END PROCESS;
--normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest(BITSELECT,165)@40
normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q;
normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in(47 downto 47);
--roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest(CONSTANT,179)
roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q <= "010";
--fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest(BITSELECT,167)@40
fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(46 downto 0);
fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in(46 downto 23);
--fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest(BITSELECT,168)@40
fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(45 downto 0);
fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in(45 downto 22);
--fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest(MUX,169)@40
fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b;
fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s, en, fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b, fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b)
BEGIN
CASE fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "0" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b;
WHEN "1" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b;
WHEN OTHERS => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest(BITSELECT,177)@40
FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in <= fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q(1 downto 0);
FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in(1 downto 0);
--Prod22_uid172_rAtanPi_uid13_fpArctanPiTest(BITSELECT,171)@40
Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(22 downto 0);
Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in(22 downto 22);
--extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest(MUX,172)@40
extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b;
extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest: PROCESS (extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s, en, GND_q, Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b)
BEGIN
CASE extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "0" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b;
WHEN OTHERS => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest(BITSELECT,170)@40
stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(21 downto 0);
stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b <= stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in(21 downto 0);
--stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest(BITJOIN,173)@40
stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q <= extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q & stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b;
--stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest(LOGICAL,175)@40
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a <= stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q;
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q <= "1" when stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a = stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b else "0";
--sticky_uid177_rAtanPi_uid13_fpArctanPiTest(LOGICAL,176)@40
sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a <= stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q;
sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q <= not sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a;
--lrs_uid179_rAtanPi_uid13_fpArctanPiTest(BITJOIN,178)@40
lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b & sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q;
--roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest(LOGICAL,180)@40
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a <= lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q;
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b <= roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q;
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q <= "1" when roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a = roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b else "0";
--roundBit_uid182_rAtanPi_uid13_fpArctanPiTest(LOGICAL,181)@40
roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a <= roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q;
roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q <= not roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a;
--roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest(BITJOIN,184)@40
roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q <= GND_q & normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b & cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q & roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q;
--reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1(REG,436)@40
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--biasInc_uid163_rAtanPi_uid13_fpArctanPiTest(CONSTANT,162)
biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q <= "0001111111";
--ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b(DELAY,586)@36
ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expY_uid123_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expSum_uid162_rAtanPi_uid13_fpArctanPiTest(ADD,161)@37
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q);
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q);
expSum_uid162_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a) + UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q <= expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o(8 downto 0);
--ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a(DELAY,587)@38
ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest(SUB,163)@39
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q);
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q(9)) & biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q);
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b));
END IF;
END IF;
END PROCESS;
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o(10 downto 0);
--expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest(BITJOIN,182)@40
expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q & fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q;
--reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0(REG,435)@40
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest(ADD,185)@41
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q(34)) & reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q);
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q);
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a) + SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b));
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o(35 downto 0);
--expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest(BITSELECT,187)@41
expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q;
expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in(35 downto 24);
--expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest(BITSELECT,188)@41
expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b(7 downto 0);
expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in(7 downto 0);
--ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d(DELAY,664)@41
ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 2 )
PORT MAP ( xin => expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c(DELAY,659)@37
ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1(REG,437)@41
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid193_rAtanPi_uid13_fpArctanPiTest(COMPARE,192)@42
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q;
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & '0';
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q) & expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin(0);
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b));
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o(14);
--InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest(LOGICAL,157)@37
InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q;
InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a;
--InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest(LOGICAL,158)@37
InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a;
--InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest(LOGICAL,159)@37
InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a;
--exc_R_uid161_rAtanPi_uid13_fpArctanPiTest(LOGICAL,160)@37
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c;
--ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b(DELAY,629)@37
ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest(LOGICAL,141)@37
InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a;
--InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest(LOGICAL,142)@37
InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a;
--InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest(LOGICAL,143)@37
InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a;
--exc_R_uid145_rAtanPi_uid13_fpArctanPiTest(LOGICAL,144)@37
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c;
--ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a(DELAY,628)@37
ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest(LOGICAL,201)@42
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c <= expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c;
--excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest(LOGICAL,200)@37
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q;
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q <= excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a and excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c(DELAY,646)@37
ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest(LOGICAL,199)@37
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q;
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q <= excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a and excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b(DELAY,645)@37
ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest(LOGICAL,198)@37
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q <= excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a and excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a(DELAY,644)@37
ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid203_rAtanPi_uid13_fpArctanPiTest(LOGICAL,202)@42
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q <= excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d;
--expUdf_uid191_rAtanPi_uid13_fpArctanPiTest(COMPARE,190)@42
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q;
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0';
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin(0);
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b));
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o(14);
--excZC3_uid197_rAtanPi_uid13_fpArctanPiTest(LOGICAL,196)@42
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c <= expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c;
--excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest(LOGICAL,195)@37
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q;
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c(DELAY,633)@37
ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest(LOGICAL,194)@37
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b(DELAY,632)@37
ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest(LOGICAL,193)@37
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a(DELAY,631)@37
ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid198_rAtanPi_uid13_fpArctanPiTest(LOGICAL,197)@42
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q <= excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d;
--concExc_uid208_rAtanPi_uid13_fpArctanPiTest(BITJOIN,207)@42
concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q <= ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q & excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q & excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q;
--reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0(REG,439)@42
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid209_rAtanPi_uid13_fpArctanPiTest(LOOKUP,208)@43
excREnc_uid209_rAtanPi_uid13_fpArctanPiTest: PROCESS (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q) IS
WHEN "000" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "01";
WHEN "001" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "010" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "10";
WHEN "011" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "100" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "11";
WHEN "101" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "110" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "111" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN OTHERS =>
excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest(MUX,217)@43
expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q;
expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest: PROCESS (expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q;
WHEN "10" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest(BITSELECT,186)@41
fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q(23 downto 0);
fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b <= fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in(23 downto 1);
--ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d(DELAY,662)@41
ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest(MUX,212)@43
fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q;
fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q;
WHEN "10" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid221_rAtanPi_uid13_fpArctanPiTest(BITJOIN,220)@43
R_uid221_rAtanPi_uid13_fpArctanPiTest_q <= ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q & expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q & fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q;
--xOut(GPOUT,4)@43
q <= R_uid221_rAtanPi_uid13_fpArctanPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_atanpi_s5
-- VHDL created on Tue Mar 12 11:23:23 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_atanpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_atanpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBiasM2_uid6_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal ooPi_uid9_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal piO2_uid46_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0);
signal piO4_uid47_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid64_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal zS_uid67_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q : std_logic_vector (12 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a : std_logic_vector (23 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 : std_logic_vector (50 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr : UNSIGNED (50 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q : std_logic_vector (50 downto 0);
signal fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (9 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (10 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector (23 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 : std_logic_vector (47 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr : UNSIGNED (47 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (47 downto 0);
signal roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_q : std_logic_vector (40 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_b : std_logic_vector (21 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_s1 : std_logic_vector (36 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_pr : SIGNED (37 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_q : std_logic_vector (36 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid299_atanXOXTabGen_lutmem_ia : std_logic_vector (30 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_iq : std_logic_vector (30 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_q : std_logic_vector (30 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid300_atanXOXTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid301_atanXOXTabGen_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid344_invTabGen_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid345_invTabGen_lutmem_ia : std_logic_vector (19 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_iq : std_logic_vector (19 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_q : std_logic_vector (19 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid346_invTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q : std_logic_vector (19 downto 0);
signal reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q : std_logic_vector (21 downto 0);
signal reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q : std_logic_vector (28 downto 0);
signal reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q : std_logic_vector (30 downto 0);
signal reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (26 downto 0);
signal reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (8 downto 0);
signal reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (31 downto 0);
signal reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (32 downto 0);
signal reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (22 downto 0);
signal reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (22 downto 0);
signal reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (22 downto 0);
signal reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (7 downto 0);
signal reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (7 downto 0);
signal reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (22 downto 0);
signal reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (23 downto 0);
signal reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (34 downto 0);
signal reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (11 downto 0);
signal reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q : std_logic_vector (7 downto 0);
signal ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (7 downto 0);
signal ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (8 downto 0);
signal ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (22 downto 0);
signal ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (7 downto 0);
signal ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (20 downto 0);
signal ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (18 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q : std_logic_vector (12 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 : std_logic;
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : signal is true;
signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : signal is true;
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : signal is true;
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_c : std_logic_vector (0 downto 0);
signal excSelBits_uid114_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a : std_logic_vector(33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b : std_logic_vector(33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o : std_logic_vector (33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q : std_logic_vector (33 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o : std_logic_vector (32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0);
signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid15_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid15_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid16_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid16_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal singX_uid17_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal singX_uid17_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q : std_logic_vector (9 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_a : std_logic_vector(26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_b : std_logic_vector(26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_o : std_logic_vector (26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (26 downto 0);
signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (35 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal fracOOPi_uid10_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracOOPi_uid10_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid80_atanX_uid8_fpArctanPiTest_in : std_logic_vector (49 downto 0);
signal normBit_uid80_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in : std_logic_vector (48 downto 0);
signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in : std_logic_vector (47 downto 0);
signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (47 downto 0);
signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (46 downto 0);
signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (45 downto 0);
signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (21 downto 0);
signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (21 downto 0);
signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in : std_logic_vector (36 downto 0);
signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b : std_logic_vector (22 downto 0);
signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal R_uid221_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (14 downto 0);
signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (14 downto 0);
signal R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal constOut_uid54_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal constOut_uid54_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal u_uid58_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal u_uid58_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal R_uid120_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (16 downto 0);
signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (8 downto 0);
signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in : std_logic_vector (8 downto 0);
signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in : std_logic_vector (25 downto 0);
signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (11 downto 0);
signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (9 downto 0);
signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (33 downto 0);
signal fpOOPi_uid11_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (32 downto 0);
signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0);
signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (28 downto 0);
signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (24 downto 0);
signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (0 downto 0);
signal stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal lowRangeB_uid304_atanXOXPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid304_atanXOXPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid305_atanXOXPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid305_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid310_atanXOXPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid310_atanXOXPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid311_atanXOXPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid311_atanXOXPolyEval_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid349_invPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid349_invPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid350_invPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid350_invPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid355_invPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid355_invPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid356_invPolyEval_in : std_logic_vector (22 downto 0);
signal highBBits_uid356_invPolyEval_b : std_logic_vector (20 downto 0);
signal y_uid73_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal y_uid73_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0);
signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal yT1_uid347_invPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid347_invPolyEval_b : std_logic_vector (11 downto 0);
signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal expU_uid59_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expU_uid59_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracU_uid60_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracU_uid60_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0);
signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b : std_logic_vector (3 downto 0);
signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (1 downto 0);
signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (34 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_a : std_logic_vector(31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_b : std_logic_vector(31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_o : std_logic_vector (31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_q : std_logic_vector (31 downto 0);
signal sumAHighB_uid351_invPolyEval_a : std_logic_vector(20 downto 0);
signal sumAHighB_uid351_invPolyEval_b : std_logic_vector(20 downto 0);
signal sumAHighB_uid351_invPolyEval_o : std_logic_vector (20 downto 0);
signal sumAHighB_uid351_invPolyEval_q : std_logic_vector (20 downto 0);
signal sumAHighB_uid357_invPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid357_invPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid357_invPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid357_invPolyEval_q : std_logic_vector (29 downto 0);
signal yAddr_uid75_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0);
signal yAddr_uid75_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in : std_logic_vector (26 downto 0);
signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b : std_logic_vector (17 downto 0);
signal rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0);
signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b : std_logic_vector (4 downto 0);
signal expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0);
signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal s1_uid304_uid307_atanXOXPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid310_uid313_atanXOXPolyEval_q : std_logic_vector (33 downto 0);
signal s1_uid349_uid352_invPolyEval_q : std_logic_vector (21 downto 0);
signal s2_uid355_uid358_invPolyEval_q : std_logic_vector (31 downto 0);
signal yT1_uid302_atanXOXPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid302_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (20 downto 0);
signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (18 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0);
signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0);
signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (25 downto 0);
begin
--xIn(GPIN,3)@0
--cstAllZWF_uid19_atanX_uid8_fpArctanPiTest(CONSTANT,18)
cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000000";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable(LOGICAL,878)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q <= not ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,1008)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a or ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,1004)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100001";
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,1005)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,1006)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,1009)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,1010)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--fracX_uid16_atanX_uid8_fpArctanPiTest(BITSELECT,15)@0
fracX_uid16_atanX_uid8_fpArctanPiTest_in <= a(22 downto 0);
fracX_uid16_atanX_uid8_fpArctanPiTest_b <= fracX_uid16_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--fracXIsZero_uid35_atanX_uid8_fpArctanPiTest(LOGICAL,34)@0
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b else "0";
--InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest(LOGICAL,36)@0
InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q <= not InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a;
--cstAllOWE_uid18_atanX_uid8_fpArctanPiTest(CONSTANT,17)
cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q <= "11111111";
--expX_uid15_atanX_uid8_fpArctanPiTest(BITSELECT,14)@0
expX_uid15_atanX_uid8_fpArctanPiTest_in <= a(30 downto 0);
expX_uid15_atanX_uid8_fpArctanPiTest_b <= expX_uid15_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--expXIsMax_uid33_atanX_uid8_fpArctanPiTest(LOGICAL,32)@0
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a = expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b else "0";
--exc_N_uid38_atanX_uid8_fpArctanPiTest(LOGICAL,37)@0
exc_N_uid38_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q;
exc_N_uid38_atanX_uid8_fpArctanPiTest_b <= InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q;
exc_N_uid38_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_a and exc_N_uid38_atanX_uid8_fpArctanPiTest_b;
--InvExc_N_uid118_atanX_uid8_fpArctanPiTest(LOGICAL,117)@0
InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q;
InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q <= not InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a;
--singX_uid17_atanX_uid8_fpArctanPiTest(BITSELECT,16)@0
singX_uid17_atanX_uid8_fpArctanPiTest_in <= a;
singX_uid17_atanX_uid8_fpArctanPiTest_b <= singX_uid17_atanX_uid8_fpArctanPiTest_in(31 downto 31);
--signR_uid119_atanX_uid8_fpArctanPiTest(LOGICAL,118)@0
signR_uid119_atanX_uid8_fpArctanPiTest_a <= singX_uid17_atanX_uid8_fpArctanPiTest_b;
signR_uid119_atanX_uid8_fpArctanPiTest_b <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q;
signR_uid119_atanX_uid8_fpArctanPiTest_q <= signR_uid119_atanX_uid8_fpArctanPiTest_a and signR_uid119_atanX_uid8_fpArctanPiTest_b;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,998)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid119_atanX_uid8_fpArctanPiTest_q, xout => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,1000)
-- every=1, low=0, high=33, step=1, init=1
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 32 THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 33;
ELSE
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6));
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,1001)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,1002)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,999)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 34,
width_b => 1,
widthad_b => 6,
numwords_b => 34,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,879)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a or ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,875)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100000";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,876)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,877)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,880)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,881)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,869)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => singX_uid17_atanX_uid8_fpArctanPiTest_b, xout => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,871)
-- every=1, low=0, high=32, step=1, init=1
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 31 THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 32;
ELSE
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6));
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,872)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,873)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,870)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--cstBias_uid22_atanX_uid8_fpArctanPiTest(CONSTANT,21)
cstBias_uid22_atanX_uid8_fpArctanPiTest_q <= "01111111";
--piO2_uid46_atanX_uid8_fpArctanPiTest(CONSTANT,45)
piO2_uid46_atanX_uid8_fpArctanPiTest_q <= "11001001000011111101101011";
--cstPiO2_uid48_atanX_uid8_fpArctanPiTest(BITSELECT,47)@35
cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in <= piO2_uid46_atanX_uid8_fpArctanPiTest_q(24 downto 0);
cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b <= cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in(24 downto 2);
--fpPiO2C_uid49_atanX_uid8_fpArctanPiTest(BITJOIN,48)@35
fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBias_uid22_atanX_uid8_fpArctanPiTest_q & cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b;
--cstBiasM1_uid23_atanX_uid8_fpArctanPiTest(CONSTANT,22)
cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q <= "01111110";
--piO4_uid47_atanX_uid8_fpArctanPiTest(CONSTANT,46)
piO4_uid47_atanX_uid8_fpArctanPiTest_q <= "110010010000111111011011";
--cstPiO4_uid51_atanX_uid8_fpArctanPiTest(BITSELECT,50)@35
cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in <= piO4_uid47_atanX_uid8_fpArctanPiTest_q(22 downto 0);
cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b <= cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--fpPiO4C_uid52_atanX_uid8_fpArctanPiTest(BITJOIN,51)@35
fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q & cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,892)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a or ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b);
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,893)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,894)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b;
--exc_I_uid36_atanX_uid8_fpArctanPiTest(LOGICAL,35)@0
exc_I_uid36_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q;
exc_I_uid36_atanX_uid8_fpArctanPiTest_b <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
exc_I_uid36_atanX_uid8_fpArctanPiTest_q <= exc_I_uid36_atanX_uid8_fpArctanPiTest_a and exc_I_uid36_atanX_uid8_fpArctanPiTest_b;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,882)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid36_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,883)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq,
address_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa,
data_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia
);
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(0 downto 0);
--constOut_uid54_atanX_uid8_fpArctanPiTest(MUX,53)@35
constOut_uid54_atanX_uid8_fpArctanPiTest_s <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q;
constOut_uid54_atanX_uid8_fpArctanPiTest: PROCESS (constOut_uid54_atanX_uid8_fpArctanPiTest_s, en, fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q, fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE constOut_uid54_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expOutCst_uid112_atanX_uid8_fpArctanPiTest(BITSELECT,111)@35
expOutCst_uid112_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expOutCst_uid112_atanX_uid8_fpArctanPiTest_b <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5(REG,428)@35
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--cst01pWShift_uid69_atanX_uid8_fpArctanPiTest(CONSTANT,68)
cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q <= "0000000000000";
--reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2(REG,389)@0
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= signR_uid119_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c(DELAY,707)@1
ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,1022)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a or ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b);
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top(CONSTANT,1018)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q <= "0111";
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp(LOGICAL,1019)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q);
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q <= "1" when ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a = ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b else "0";
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg(REG,1020)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,1023)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,1024)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b;
--cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,230)
cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111110";
--expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest(SUB,259)@0
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q);
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b);
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b));
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,260)@0
expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0);
expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,229)
cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111101";
--expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest(SUB,256)@0
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q);
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b);
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b));
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,257)@0
expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0);
expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,249)@0
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b else "0";
--expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest(MUX,263)@0
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s <= fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q;
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--expXIsZero_uid31_atanX_uid8_fpArctanPiTest(LOGICAL,30)@0
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a = expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b else "0";
--udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,258)@0
udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in <= STD_LOGIC_VECTOR((9 downto 9 => expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(8)) & expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q);
udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in(9 downto 9);
--InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,245)@0
InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a;
--InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,246)@0
InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a <= expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q;
InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a;
--exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,247)@0
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a <= InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b <= InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c;
--xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,264)@0
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q;
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b;
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a and xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b;
--xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,265)@0
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q;
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q <= xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a or xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b;
--excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,266)@0
excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q & expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q & xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q;
--reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0(REG,378)@0
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest(LOOKUP,267)@1
outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest(MUX,269)@1
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q;
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,1012)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt(COUNTER,1014)
-- every=1, low=0, high=7, step=1, init=1
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg(REG,1015)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux(MUX,1016)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,1013)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia
);
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid20_atanX_uid8_fpArctanPiTest(CONSTANT,19)
cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000001";
--oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,248)@0
oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q <= VCC_q & fracX_uid16_atanX_uid8_fpArctanPiTest_b;
--y_uid251_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,250)@0
y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in <= oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q(22 downto 0);
y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,252)@0
yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b;
yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 15);
--reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0(REG,379)@0
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid346_invTabGen_lutmem(DUALMEM,376)@1
memoryC2_uid346_invTabGen_lutmem_ia <= (others => '0');
memoryC2_uid346_invTabGen_lutmem_aa <= (others => '0');
memoryC2_uid346_invTabGen_lutmem_ab <= reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q;
memoryC2_uid346_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC2_uid346_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid346_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid346_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid346_invTabGen_lutmem_iq,
address_a => memoryC2_uid346_invTabGen_lutmem_aa,
data_a => memoryC2_uid346_invTabGen_lutmem_ia
);
memoryC2_uid346_invTabGen_lutmem_reset0 <= areset;
memoryC2_uid346_invTabGen_lutmem_q <= memoryC2_uid346_invTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1(REG,381)@3
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= memoryC2_uid346_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,1011)
ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a(DELAY,680)@0
ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,253)@3
yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in <= ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q(14 downto 0);
yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in(14 downto 0);
--yT1_uid347_invPolyEval(BITSELECT,346)@3
yT1_uid347_invPolyEval_in <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b;
yT1_uid347_invPolyEval_b <= yT1_uid347_invPolyEval_in(14 downto 3);
--reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0(REG,380)@3
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= yT1_uid347_invPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid366_pT1_uid348_invPolyEval(MULT,365)@4
prodXY_uid366_pT1_uid348_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid366_pT1_uid348_invPolyEval_a),13)) * SIGNED(prodXY_uid366_pT1_uid348_invPolyEval_b);
prodXY_uid366_pT1_uid348_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid366_pT1_uid348_invPolyEval_a <= (others => '0');
prodXY_uid366_pT1_uid348_invPolyEval_b <= (others => '0');
prodXY_uid366_pT1_uid348_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid366_pT1_uid348_invPolyEval_a <= reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q;
prodXY_uid366_pT1_uid348_invPolyEval_b <= reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q;
prodXY_uid366_pT1_uid348_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid366_pT1_uid348_invPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid366_pT1_uid348_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid366_pT1_uid348_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid366_pT1_uid348_invPolyEval_q <= prodXY_uid366_pT1_uid348_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid367_pT1_uid348_invPolyEval(BITSELECT,366)@7
prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in <= prodXY_uid366_pT1_uid348_invPolyEval_q;
prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in(23 downto 11);
--highBBits_uid350_invPolyEval(BITSELECT,349)@7
highBBits_uid350_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b;
highBBits_uid350_invPolyEval_b <= highBBits_uid350_invPolyEval_in(12 downto 1);
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a(DELAY,804)@1
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid345_invTabGen_lutmem(DUALMEM,375)@4
memoryC1_uid345_invTabGen_lutmem_ia <= (others => '0');
memoryC1_uid345_invTabGen_lutmem_aa <= (others => '0');
memoryC1_uid345_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q;
memoryC1_uid345_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 20,
widthad_a => 8,
numwords_a => 256,
width_b => 20,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC1_uid345_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid345_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid345_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid345_invTabGen_lutmem_iq,
address_a => memoryC1_uid345_invTabGen_lutmem_aa,
data_a => memoryC1_uid345_invTabGen_lutmem_ia
);
memoryC1_uid345_invTabGen_lutmem_reset0 <= areset;
memoryC1_uid345_invTabGen_lutmem_q <= memoryC1_uid345_invTabGen_lutmem_iq(19 downto 0);
--reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0(REG,383)@6
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= "00000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= memoryC1_uid345_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid351_invPolyEval(ADD,350)@7
sumAHighB_uid351_invPolyEval_a <= STD_LOGIC_VECTOR((20 downto 20 => reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q(19)) & reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q);
sumAHighB_uid351_invPolyEval_b <= STD_LOGIC_VECTOR((20 downto 12 => highBBits_uid350_invPolyEval_b(11)) & highBBits_uid350_invPolyEval_b);
sumAHighB_uid351_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid351_invPolyEval_a) + SIGNED(sumAHighB_uid351_invPolyEval_b));
sumAHighB_uid351_invPolyEval_q <= sumAHighB_uid351_invPolyEval_o(20 downto 0);
--lowRangeB_uid349_invPolyEval(BITSELECT,348)@7
lowRangeB_uid349_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b(0 downto 0);
lowRangeB_uid349_invPolyEval_b <= lowRangeB_uid349_invPolyEval_in(0 downto 0);
--s1_uid349_uid352_invPolyEval(BITJOIN,351)@7
s1_uid349_uid352_invPolyEval_q <= sumAHighB_uid351_invPolyEval_q & lowRangeB_uid349_invPolyEval_b;
--reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1(REG,385)@7
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= "0000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= s1_uid349_uid352_invPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor(LOGICAL,1059)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a or ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b);
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg(REG,966)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena(REG,1060)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q = "1") THEN
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd(LOGICAL,1061)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b <= en;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg(DELAY,1051)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt(COUNTER,962)
-- every=1, low=0, high=1, step=1, init=1
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i,1));
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg(REG,963)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux(MUX,964)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s <= en;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux: PROCESS (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q)
BEGIN
CASE ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s IS
WHEN "0" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
WHEN "1" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q;
WHEN OTHERS => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem(DUALMEM,1052)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia
);
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0(REG,384)@7
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid369_pT2_uid354_invPolyEval(MULT,368)@8
prodXY_uid369_pT2_uid354_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid369_pT2_uid354_invPolyEval_a),16)) * SIGNED(prodXY_uid369_pT2_uid354_invPolyEval_b);
prodXY_uid369_pT2_uid354_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid369_pT2_uid354_invPolyEval_a <= (others => '0');
prodXY_uid369_pT2_uid354_invPolyEval_b <= (others => '0');
prodXY_uid369_pT2_uid354_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid369_pT2_uid354_invPolyEval_a <= reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q;
prodXY_uid369_pT2_uid354_invPolyEval_b <= reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q;
prodXY_uid369_pT2_uid354_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid369_pT2_uid354_invPolyEval_pr,37));
END IF;
END IF;
END PROCESS;
prodXY_uid369_pT2_uid354_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid369_pT2_uid354_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid369_pT2_uid354_invPolyEval_q <= prodXY_uid369_pT2_uid354_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid370_pT2_uid354_invPolyEval(BITSELECT,369)@11
prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in <= prodXY_uid369_pT2_uid354_invPolyEval_q;
prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in(36 downto 14);
--highBBits_uid356_invPolyEval(BITSELECT,355)@11
highBBits_uid356_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b;
highBBits_uid356_invPolyEval_b <= highBBits_uid356_invPolyEval_in(22 downto 2);
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor(LOGICAL,1048)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q <= not (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a or ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b);
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top(CONSTANT,1031)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q <= "0100";
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp(LOGICAL,1032)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q <= "1" when ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a = ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b else "0";
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg(REG,1033)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena(REG,1049)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd(LOGICAL,1050)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a and ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg(DELAY,1038)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt(COUNTER,1027)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i,3));
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg(REG,1028)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux(MUX,1029)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s <= en;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux: PROCESS (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem(DUALMEM,1039)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq(7 downto 0);
--memoryC0_uid344_invTabGen_lutmem(DUALMEM,374)@8
memoryC0_uid344_invTabGen_lutmem_ia <= (others => '0');
memoryC0_uid344_invTabGen_lutmem_aa <= (others => '0');
memoryC0_uid344_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q;
memoryC0_uid344_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC0_uid344_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid344_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid344_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid344_invTabGen_lutmem_iq,
address_a => memoryC0_uid344_invTabGen_lutmem_aa,
data_a => memoryC0_uid344_invTabGen_lutmem_ia
);
memoryC0_uid344_invTabGen_lutmem_reset0 <= areset;
memoryC0_uid344_invTabGen_lutmem_q <= memoryC0_uid344_invTabGen_lutmem_iq(28 downto 0);
--reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0(REG,387)@10
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= "00000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= memoryC0_uid344_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid357_invPolyEval(ADD,356)@11
sumAHighB_uid357_invPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q(28)) & reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q);
sumAHighB_uid357_invPolyEval_b <= STD_LOGIC_VECTOR((29 downto 21 => highBBits_uid356_invPolyEval_b(20)) & highBBits_uid356_invPolyEval_b);
sumAHighB_uid357_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid357_invPolyEval_a) + SIGNED(sumAHighB_uid357_invPolyEval_b));
sumAHighB_uid357_invPolyEval_q <= sumAHighB_uid357_invPolyEval_o(29 downto 0);
--lowRangeB_uid355_invPolyEval(BITSELECT,354)@11
lowRangeB_uid355_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b(1 downto 0);
lowRangeB_uid355_invPolyEval_b <= lowRangeB_uid355_invPolyEval_in(1 downto 0);
--s2_uid355_uid358_invPolyEval(BITJOIN,357)@11
s2_uid355_uid358_invPolyEval_q <= sumAHighB_uid357_invPolyEval_q & lowRangeB_uid355_invPolyEval_b;
--fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,255)@11
fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in <= s2_uid355_uid358_invPolyEval_q(28 downto 0);
fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in(28 downto 5);
--fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,261)@11
fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b(22 downto 0);
fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,688)@0
ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest(MUX,262)@11
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q;
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1(REG,388)@1
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,701)@2
ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 10 )
PORT MAP ( xin => reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest(MUX,268)@12
fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q;
fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid273_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,272)@12
R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q <= ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q & fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,905)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a or ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,901)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "01001";
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,902)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,903)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,906)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,907)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,895)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,897)
-- every=1, low=0, high=9, step=1, init=1
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 8 THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 9;
ELSE
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,4));
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,898)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,899)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,896)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 4,
numwords_a => 10,
width_b => 32,
widthad_b => 4,
numwords_b => 10,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(31 downto 0);
--path2_uid56_atanX_uid8_fpArctanPiTest(COMPARE,55)@0
path2_uid56_atanX_uid8_fpArctanPiTest_cin <= GND_q;
path2_uid56_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid15_atanX_uid8_fpArctanPiTest_b) & '0';
path2_uid56_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q) & path2_uid56_atanX_uid8_fpArctanPiTest_cin(0);
path2_uid56_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_b));
path2_uid56_atanX_uid8_fpArctanPiTest_n(0) <= not path2_uid56_atanX_uid8_fpArctanPiTest_o(10);
--reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1(REG,390)@0
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= path2_uid56_atanX_uid8_fpArctanPiTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b(DELAY,466)@1
ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--u_uid58_atanX_uid8_fpArctanPiTest(MUX,57)@12
u_uid58_atanX_uid8_fpArctanPiTest_s <= ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q;
u_uid58_atanX_uid8_fpArctanPiTest: PROCESS (u_uid58_atanX_uid8_fpArctanPiTest_s, en, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q, R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE u_uid58_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => u_uid58_atanX_uid8_fpArctanPiTest_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q;
WHEN "1" => u_uid58_atanX_uid8_fpArctanPiTest_q <= R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => u_uid58_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracU_uid60_atanX_uid8_fpArctanPiTest(BITSELECT,59)@12
fracU_uid60_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracU_uid60_atanX_uid8_fpArctanPiTest_b <= fracU_uid60_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a(DELAY,471)@12
ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracU_uid60_atanX_uid8_fpArctanPiTest_b, xout => ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest(BITJOIN,60)@13
oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q;
--oFracUExt_uid70_atanX_uid8_fpArctanPiTest(BITJOIN,69)@13
oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q <= cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q & oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q;
--X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,282)@13
X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(24 downto 0);
X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(24 downto 0);
--leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,281)
leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000000000000";
--leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,283)@13
leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5(REG,399)@13
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,279)@13
X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(28 downto 0);
X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(28 downto 0);
--leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,280)@13
leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4(REG,398)@13
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,276)@13
X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(32 downto 0);
X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(32 downto 0);
--leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,275)
leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "0000";
--leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,277)@13
leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3(REG,397)@13
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,396)@13
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--zS_uid67_atanX_uid8_fpArctanPiTest(CONSTANT,66)
zS_uid67_atanX_uid8_fpArctanPiTest_q <= "000000000";
--shiftBias_uid64_atanX_uid8_fpArctanPiTest(CONSTANT,63)
shiftBias_uid64_atanX_uid8_fpArctanPiTest_q <= "01110010";
--expU_uid59_atanX_uid8_fpArctanPiTest(BITSELECT,58)@12
expU_uid59_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expU_uid59_atanX_uid8_fpArctanPiTest_b <= expU_uid59_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1(REG,391)@12
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= expU_uid59_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--shiftValue_uid65_atanX_uid8_fpArctanPiTest(SUB,64)@13
shiftValue_uid65_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q);
shiftValue_uid65_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid64_atanX_uid8_fpArctanPiTest_q);
shiftValue_uid65_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_b));
shiftValue_uid65_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--ShiftValue8_uid66_atanX_uid8_fpArctanPiTest(BITSELECT,65)@13
ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q;
ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in(8 downto 8);
--shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest(MUX,67)@13
shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b;
shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest: PROCESS (shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s, en, shiftValue_uid65_atanX_uid8_fpArctanPiTest_q, zS_uid67_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= zS_uid67_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest(BITSELECT,70)@13
fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in <= shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q(3 downto 0);
fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,284)@13
leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b;
leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,395)@13
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,285)@14
leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q;
leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q, reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q, reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q;
WHEN "11" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,293)@14
LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(33 downto 0);
LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(33 downto 0);
--ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,725)@14
ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,292)
leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000";
--leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,294)@15
leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,290)@14
LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(34 downto 0);
LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(34 downto 0);
--ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,723)@14
ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,289)
leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "00";
--leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,291)@15
leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,287)@14
LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0);
LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(35 downto 0);
--ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,721)@14
ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,288)@15
leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & GND_q;
--reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,401)@14
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,295)@13
leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a(DELAY,829)@13
ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,400)@14
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,296)@15
leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q;
leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid73_atanX_uid8_fpArctanPiTest(BITSELECT,72)@15
y_uid73_atanX_uid8_fpArctanPiTest_in <= leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0);
y_uid73_atanX_uid8_fpArctanPiTest_b <= y_uid73_atanX_uid8_fpArctanPiTest_in(35 downto 1);
--yAddr_uid75_atanX_uid8_fpArctanPiTest(BITSELECT,74)@15
yAddr_uid75_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b;
yAddr_uid75_atanX_uid8_fpArctanPiTest_b <= yAddr_uid75_atanX_uid8_fpArctanPiTest_in(34 downto 27);
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0(REG,402)@15
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= yAddr_uid75_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid301_atanXOXTabGen_lutmem(DUALMEM,373)@16
memoryC2_uid301_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC2_uid301_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC2_uid301_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q;
memoryC2_uid301_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC2_uid301_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid301_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid301_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid301_atanXOXTabGen_lutmem_iq,
address_a => memoryC2_uid301_atanXOXTabGen_lutmem_aa,
data_a => memoryC2_uid301_atanXOXTabGen_lutmem_ia
);
memoryC2_uid301_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC2_uid301_atanXOXTabGen_lutmem_q <= memoryC2_uid301_atanXOXTabGen_lutmem_iq(12 downto 0);
--reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1(REG,404)@18
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= memoryC2_uid301_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--yPPolyEval_uid76_atanX_uid8_fpArctanPiTest(BITSELECT,75)@15
yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b(26 downto 0);
yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in(26 downto 9);
--yT1_uid302_atanXOXPolyEval(BITSELECT,301)@15
yT1_uid302_atanXOXPolyEval_in <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b;
yT1_uid302_atanXOXPolyEval_b <= yT1_uid302_atanXOXPolyEval_in(17 downto 5);
--ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg(DELAY,1062)
ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid302_atanXOXPolyEval_b, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a(DELAY,832)@15
ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0(REG,403)@18
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid360_pT1_uid303_atanXOXPolyEval(MULT,359)@19
prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_a),14)) * SIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_b);
prodXY_uid360_pT1_uid303_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= (others => '0');
prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= (others => '0');
prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q;
prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q;
prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid360_pT1_uid303_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval(BITSELECT,360)@22
prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_q;
prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in(25 downto 12);
--highBBits_uid305_atanXOXPolyEval(BITSELECT,304)@22
highBBits_uid305_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b;
highBBits_uid305_atanXOXPolyEval_b <= highBBits_uid305_atanXOXPolyEval_in(13 downto 1);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a(DELAY,834)@15
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0(REG,405)@18
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid300_atanXOXTabGen_lutmem(DUALMEM,372)@19
memoryC1_uid300_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC1_uid300_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC1_uid300_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q;
memoryC1_uid300_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC1_uid300_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid300_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid300_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid300_atanXOXTabGen_lutmem_iq,
address_a => memoryC1_uid300_atanXOXTabGen_lutmem_aa,
data_a => memoryC1_uid300_atanXOXTabGen_lutmem_ia
);
memoryC1_uid300_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC1_uid300_atanXOXTabGen_lutmem_q <= memoryC1_uid300_atanXOXTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0(REG,406)@21
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= memoryC1_uid300_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid306_atanXOXPolyEval(ADD,305)@22
sumAHighB_uid306_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q(20)) & reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q);
sumAHighB_uid306_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid305_atanXOXPolyEval_b(12)) & highBBits_uid305_atanXOXPolyEval_b);
sumAHighB_uid306_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid306_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid306_atanXOXPolyEval_b));
sumAHighB_uid306_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_o(21 downto 0);
--lowRangeB_uid304_atanXOXPolyEval(BITSELECT,303)@22
lowRangeB_uid304_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b(0 downto 0);
lowRangeB_uid304_atanXOXPolyEval_b <= lowRangeB_uid304_atanXOXPolyEval_in(0 downto 0);
--s1_uid304_uid307_atanXOXPolyEval(BITJOIN,306)@22
s1_uid304_uid307_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_q & lowRangeB_uid304_atanXOXPolyEval_b;
--reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1(REG,408)@22
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= s1_uid304_uid307_atanXOXPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor(LOGICAL,1035)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q <= not (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a or ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b);
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena(REG,1036)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd(LOGICAL,1037)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b <= en;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a and ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b;
--reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0(REG,407)@15
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg(DELAY,1025)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q, xout => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem(DUALMEM,1026)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq,
address_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa,
data_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia
);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid363_pT2_uid309_atanXOXPolyEval(MULT,362)@23
prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_a),19)) * SIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_b);
prodXY_uid363_pT2_uid309_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= (others => '0');
prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= (others => '0');
prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q;
prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q;
prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid363_pT2_uid309_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval(BITSELECT,363)@26
prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_q;
prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in(40 downto 17);
--highBBits_uid311_atanXOXPolyEval(BITSELECT,310)@26
highBBits_uid311_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b;
highBBits_uid311_atanXOXPolyEval_b <= highBBits_uid311_atanXOXPolyEval_in(23 downto 2);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor(LOGICAL,1073)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q <= not (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a or ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena(REG,1074)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q = "1") THEN
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd(LOGICAL,1075)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b <= en;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a and ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b;
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg(DELAY,1063)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem(DUALMEM,1064)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia
);
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0(REG,409)@22
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid299_atanXOXTabGen_lutmem(DUALMEM,371)@23
memoryC0_uid299_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC0_uid299_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC0_uid299_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q;
memoryC0_uid299_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 31,
widthad_a => 8,
numwords_a => 256,
width_b => 31,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC0_uid299_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid299_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid299_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid299_atanXOXTabGen_lutmem_iq,
address_a => memoryC0_uid299_atanXOXTabGen_lutmem_aa,
data_a => memoryC0_uid299_atanXOXTabGen_lutmem_ia
);
memoryC0_uid299_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC0_uid299_atanXOXTabGen_lutmem_q <= memoryC0_uid299_atanXOXTabGen_lutmem_iq(30 downto 0);
--reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0(REG,410)@25
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= memoryC0_uid299_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid312_atanXOXPolyEval(ADD,311)@26
sumAHighB_uid312_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((31 downto 31 => reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q(30)) & reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q);
sumAHighB_uid312_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((31 downto 22 => highBBits_uid311_atanXOXPolyEval_b(21)) & highBBits_uid311_atanXOXPolyEval_b);
sumAHighB_uid312_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid312_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid312_atanXOXPolyEval_b));
sumAHighB_uid312_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_o(31 downto 0);
--lowRangeB_uid310_atanXOXPolyEval(BITSELECT,309)@26
lowRangeB_uid310_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b(1 downto 0);
lowRangeB_uid310_atanXOXPolyEval_b <= lowRangeB_uid310_atanXOXPolyEval_in(1 downto 0);
--s2_uid310_uid313_atanXOXPolyEval(BITJOIN,312)@26
s2_uid310_uid313_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_q & lowRangeB_uid310_atanXOXPolyEval_b;
--fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest(BITSELECT,77)@26
fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in <= s2_uid310_uid313_atanXOXPolyEval_q(31 downto 0);
fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in(31 downto 5);
--reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1(REG,412)@26
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,918)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,914)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01010";
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,915)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,916)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,919)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,920)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0(REG,411)@13
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,908)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,910)
-- every=1, low=0, high=10, step=1, init=1
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 9 THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 10;
ELSE
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4));
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,911)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,912)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,909)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 11,
width_b => 24,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(23 downto 0);
--mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest(MULT,78)@27
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr <= UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a) * UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b);
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= (others => '0');
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= (others => '0');
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr);
END IF;
END IF;
END PROCESS;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid80_atanX_uid8_fpArctanPiTest(BITSELECT,79)@30
normBit_uid80_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(49 downto 0);
normBit_uid80_atanX_uid8_fpArctanPiTest_b <= normBit_uid80_atanX_uid8_fpArctanPiTest_in(49 downto 49);
--InvNormBit_uid84_atanX_uid8_fpArctanPiTest(LOGICAL,83)@30
InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a <= normBit_uid80_atanX_uid8_fpArctanPiTest_b;
InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q <= not InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,931)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,927)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01111";
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,928)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,929)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,932)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,933)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,921)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expU_uid59_atanX_uid8_fpArctanPiTest_b, xout => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,923)
-- every=1, low=0, high=15, step=1, init=1
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4));
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,924)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,925)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,922)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 16,
width_b => 8,
widthad_b => 4,
numwords_b => 16,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(7 downto 0);
--expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest(SUB,84)@30
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q);
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000" & InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q);
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b));
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--fracRPath3High_uid81_atanX_uid8_fpArctanPiTest(BITSELECT,80)@30
fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(48 downto 0);
fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in(48 downto 25);
--fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest(BITSELECT,81)@30
fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(47 downto 0);
fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in(47 downto 24);
--fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest(MUX,82)@30
fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s <= normBit_uid80_atanX_uid8_fpArctanPiTest_b;
fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s, en, fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b, fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b)
BEGIN
CASE fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest(BITJOIN,85)@30
expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q & fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q;
--reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0(REG,420)@30
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest(ADD,86)@31
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q);
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000" & VCC_q);
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b));
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o(33 downto 0);
--expRPath3_uid89_atanX_uid8_fpArctanPiTest(BITSELECT,88)@31
expRPath3_uid89_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(31 downto 0);
expRPath3_uid89_atanX_uid8_fpArctanPiTest_b <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_in(31 downto 24);
--reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4(REG,427)@31
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,971)
ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e(DELAY,534)@32
ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,337)@33
RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 1);
--rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,339)@33
rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= GND_q & RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,333)
rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000";
--rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,322)
rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000000000000000000000";
--X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,321)@32
X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 24);
--rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,323)@32
rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,319)
rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "0000000000000000";
--X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,318)@32
X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 16);
--rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,320)@32
rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,315)@32
X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 8);
--rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,317)@32
rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q & X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a(DELAY,504)@30
ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q, xout => ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest(BITJOIN,93)@32
oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q;
--cstWFP2_uid25_atanX_uid8_fpArctanPiTest(CONSTANT,24)
cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q <= "00011001";
--reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1(REG,413)@30
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest(SUB,89)@31
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q);
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR((10 downto 9 => reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q(8)) & reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q);
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a) - SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b));
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o(9 downto 0);
--shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest(BITSELECT,91)@31
shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q(7 downto 0);
shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest(CONSTANT,23)
cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q <= "01101000";
--shiftOut_uid91_atanX_uid8_fpArctanPiTest(COMPARE,90)@13
shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin <= GND_q;
shiftOut_uid91_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & '0';
shiftOut_uid91_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q) & shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin(0);
shiftOut_uid91_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_b));
shiftOut_uid91_atanX_uid8_fpArctanPiTest_c(0) <= shiftOut_uid91_atanX_uid8_fpArctanPiTest_o(10);
--ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b(DELAY,502)@13
ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => shiftOut_uid91_atanX_uid8_fpArctanPiTest_c, xout => ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--sValPostSOut_uid93_atanX_uid8_fpArctanPiTest(MUX,92)@31
sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s <= ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q;
sValPostSOut_uid93_atanX_uid8_fpArctanPiTest: PROCESS (sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s, en, shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b, cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest(BITSELECT,94)@31
sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in <= sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q(4 downto 0);
sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,324)@31
rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b;
rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,414)@31
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,325)@32
rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q;
rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,332)@32
RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 6);
--ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,762)@32
ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,334)@33
rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,329)@32
RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 4);
--ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,760)@32
ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 21, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,331)@33
rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,326)@32
RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 2);
--ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,758)@32
ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,328)@33
rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2(REG,416)@32
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,335)@31
rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(2 downto 1);
--ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a(DELAY,844)@31
ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,415)@32
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,336)@33
rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q;
rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q, rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,340)@31
rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,417)@31
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b(DELAY,772)@32
ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,341)@33
rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q;
rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest(BITJOIN,96)@33
pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & GND_q;
--reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1(REG,418)@33
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--path2Diff_uid97_atanX_uid8_fpArctanPiTest(SUB,97)@34
path2Diff_uid97_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & piO2_uid46_atanX_uid8_fpArctanPiTest_q);
path2Diff_uid97_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q);
path2Diff_uid97_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_b));
path2Diff_uid97_atanX_uid8_fpArctanPiTest_q <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_o(26 downto 0);
--normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest(BITSELECT,98)@34
normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(25 downto 0);
normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in(25 downto 25);
--expRPath2_uid103_atanX_uid8_fpArctanPiTest(MUX,102)@34
expRPath2_uid103_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b;
expRPath2_uid103_atanX_uid8_fpArctanPiTest: PROCESS (expRPath2_uid103_atanX_uid8_fpArctanPiTest_s, en, cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q, cstBias_uid22_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPath2_uid103_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest(BITSELECT,99)@34
path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(24 downto 0);
path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in(24 downto 1);
--path2DiffLow_uid101_atanX_uid8_fpArctanPiTest(BITSELECT,100)@34
path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(23 downto 0);
path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in(23 downto 0);
--fracRPath2_uid102_atanX_uid8_fpArctanPiTest(MUX,101)@34
fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b;
fracRPath2_uid102_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s, en, path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b, path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b)
BEGIN
CASE fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest(BITJOIN,103)@34
expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q <= expRPath2_uid103_atanX_uid8_fpArctanPiTest_q & fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q;
--reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0(REG,419)@34
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest(ADD,104)@35
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q);
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000" & VCC_q);
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b));
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o(32 downto 0);
--expRPath2_uid107_atanX_uid8_fpArctanPiTest(BITSELECT,106)@35
expRPath2_uid107_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(31 downto 0);
expRPath2_uid107_atanX_uid8_fpArctanPiTest_b <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_in(31 downto 24);
--reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3(REG,426)@35
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor(LOGICAL,1086)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q <= not (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a or ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b);
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena(REG,1087)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q = "1") THEN
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd(LOGICAL,1088)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b <= en;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a and ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg(DELAY,1076)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid15_atanX_uid8_fpArctanPiTest_b, xout => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem(DUALMEM,1077)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 33,
width_b => 8,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq,
address_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa,
data_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia
);
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 <= areset;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq(7 downto 0);
--reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2(REG,425)@35
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,944)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,940)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "010010";
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,941)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,942)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,945)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,946)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--expXIsBias_uid44_atanX_uid8_fpArctanPiTest(LOGICAL,43)@0
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q;
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a = expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b else "0";
--inIsOne_uid45_atanX_uid8_fpArctanPiTest(LOGICAL,44)@0
inIsOne_uid45_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
inIsOne_uid45_atanX_uid8_fpArctanPiTest_b <= expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q;
inIsOne_uid45_atanX_uid8_fpArctanPiTest_q <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_a and inIsOne_uid45_atanX_uid8_fpArctanPiTest_b;
--arctanIsConst_uid55_atanX_uid8_fpArctanPiTest(LOGICAL,54)@0
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_q;
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a or arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c(DELAY,522)@1
ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q, xout => ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasMwShift_uid62_atanX_uid8_fpArctanPiTest(CONSTANT,61)
biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q <= "01110011";
--atanUIsU_uid63_atanX_uid8_fpArctanPiTest(COMPARE,62)@13
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin <= GND_q;
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q) & '0';
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin(0);
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b));
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n(0) <= not atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o(10);
--ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a(DELAY,520)@0
ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => path2_uid56_atanX_uid8_fpArctanPiTest_n, xout => ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--pathSelBits_uid108_atanX_uid8_fpArctanPiTest(BITJOIN,107)@13
pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q <= ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n & ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q;
--reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0(REG,392)@13
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,934)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,936)
-- every=1, low=0, high=18, step=1, init=1
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 17 THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 18;
ELSE
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,5));
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,937)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,938)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,935)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 19,
width_b => 3,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(2 downto 0);
--fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest(LOOKUP,108)@35
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q) IS
WHEN "000" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "001" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "010" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "011" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "110" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "111" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN OTHERS =>
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRCalc_uid113_atanX_uid8_fpArctanPiTest(MUX,112)@36
expRCalc_uid113_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q;
expRCalc_uid113_atanX_uid8_fpArctanPiTest: PROCESS (expRCalc_uid113_atanX_uid8_fpArctanPiTest_s, en, reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q, reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q, ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE expRCalc_uid113_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q;
WHEN "11" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstAllZWE_uid21_atanX_uid8_fpArctanPiTest(CONSTANT,20)
cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q <= "00000000";
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,995)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a or ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,996)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,997)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,985)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid38_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,986)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,982)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,983)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,984)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,972)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q, xout => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,973)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(0 downto 0);
--excSelBits_uid114_atanX_uid8_fpArctanPiTest(BITJOIN,113)@35
excSelBits_uid114_atanX_uid8_fpArctanPiTest_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q & GND_q & ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q;
--reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0(REG,377)@35
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid114_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest(LOOKUP,114)@36
outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid117_atanX_uid8_fpArctanPiTest(MUX,116)@36
expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q;
expRPostExc_uid117_atanX_uid8_fpArctanPiTest: PROCESS (expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, expRCalc_uid113_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid113_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracOutCst_uid110_atanX_uid8_fpArctanPiTest(BITSELECT,109)@35
fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5(REG,424)@35
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor(LOGICAL,968)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q <= not (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a or ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b);
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena(REG,969)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd(LOGICAL,970)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b <= en;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a and ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b;
--fracRPath3_uid88_atanX_uid8_fpArctanPiTest(BITSELECT,87)@31
fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(23 downto 0);
fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in(23 downto 1);
--reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4(REG,423)@31
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,960)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem(DUALMEM,961)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 1,
numwords_a => 2,
width_b => 23,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq,
address_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa,
data_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia
);
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 <= areset;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq(22 downto 0);
--fracRPath2_uid106_atanX_uid8_fpArctanPiTest(BITSELECT,105)@35
fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(23 downto 0);
fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in(23 downto 1);
--reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3(REG,422)@35
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,957)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a or ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,958)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,959)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2(REG,421)@0
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,947)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,948)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 33,
width_b => 23,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(22 downto 0);
--fracRCalc_uid111_atanX_uid8_fpArctanPiTest(MUX,110)@36
fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q;
fracRCalc_uid111_atanX_uid8_fpArctanPiTest: PROCESS (fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s, en, ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q, reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q, reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q;
WHEN "01" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q;
WHEN "11" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid116_atanX_uid8_fpArctanPiTest(MUX,115)@36
fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q;
fracRPostExc_uid116_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid120_atanX_uid8_fpArctanPiTest(BITJOIN,119)@36
R_uid120_atanX_uid8_fpArctanPiTest_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q & expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q & fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q;
--fracX_uid126_rAtanPi_uid13_fpArctanPiTest(BITSELECT,125)@36
fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0);
--reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1(REG,431)@36
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest(LOGICAL,137)@37
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a <= reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q;
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b else "0";
--expX_uid122_rAtanPi_uid13_fpArctanPiTest(BITSELECT,121)@36
expX_uid122_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expX_uid122_rAtanPi_uid13_fpArctanPiTest_b <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23);
--reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1(REG,429)@36
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest(LOGICAL,135)@37
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q;
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b else "0";
--exc_I_uid139_rAtanPi_uid13_fpArctanPiTest(LOGICAL,138)@37
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q;
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q;
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b;
--cstBiasM2_uid6_fpArctanPiTest(CONSTANT,5)
cstBiasM2_uid6_fpArctanPiTest_q <= "01111101";
--ooPi_uid9_fpArctanPiTest(CONSTANT,8)
ooPi_uid9_fpArctanPiTest_q <= "101000101111100110000011";
--fracOOPi_uid10_fpArctanPiTest(BITSELECT,9)@36
fracOOPi_uid10_fpArctanPiTest_in <= ooPi_uid9_fpArctanPiTest_q(22 downto 0);
fracOOPi_uid10_fpArctanPiTest_b <= fracOOPi_uid10_fpArctanPiTest_in(22 downto 0);
--fpOOPi_uid11_fpArctanPiTest(BITJOIN,10)@36
fpOOPi_uid11_fpArctanPiTest_q <= GND_q & cstBiasM2_uid6_fpArctanPiTest_q & fracOOPi_uid10_fpArctanPiTest_b;
--expY_uid123_rAtanPi_uid13_fpArctanPiTest(BITSELECT,122)@36
expY_uid123_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(30 downto 0);
expY_uid123_rAtanPi_uid13_fpArctanPiTest_b <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23);
--expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest(LOGICAL,149)@36
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b;
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a(DELAY,581)@36
ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest(LOGICAL,203)@37
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b;
--fracY_uid128_rAtanPi_uid13_fpArctanPiTest(BITSELECT,127)@36
fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(22 downto 0);
fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0);
--fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest(LOGICAL,153)@36
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b;
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b(DELAY,575)@36
ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest(LOGICAL,151)@36
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b;
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a(DELAY,574)@36
ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid155_rAtanPi_uid13_fpArctanPiTest(LOGICAL,154)@37
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q;
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b <= ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q;
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b;
--expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest(LOGICAL,133)@37
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q;
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b else "0";
--excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest(LOGICAL,204)@37
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b;
--ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest(LOGICAL,205)@37
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q;
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q;
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a or ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b;
--InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest(LOGICAL,155)@36
InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q;
InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a;
--exc_N_uid157_rAtanPi_uid13_fpArctanPiTest(LOGICAL,156)@36
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b;
--ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a(DELAY,579)@36
ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest(LOGICAL,139)@37
InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q;
InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a;
--exc_N_uid141_rAtanPi_uid13_fpArctanPiTest(LOGICAL,140)@37
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b;
--excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest(LOGICAL,206)@37
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c;
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest(LOGICAL,218)@37
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q;
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= not InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a;
END IF;
END PROCESS;
--signY_uid125_rAtanPi_uid13_fpArctanPiTest(BITSELECT,124)@36
signY_uid125_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q;
signY_uid125_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31);
--signX_uid124_rAtanPi_uid13_fpArctanPiTest(BITSELECT,123)@36
signX_uid124_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q;
signX_uid124_rAtanPi_uid13_fpArctanPiTest_b <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31);
--signR_uid190_rAtanPi_uid13_fpArctanPiTest(LOGICAL,189)@36
signR_uid190_rAtanPi_uid13_fpArctanPiTest_a <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_b;
signR_uid190_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_b;
signR_uid190_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= signR_uid190_rAtanPi_uid13_fpArctanPiTest_a xor signR_uid190_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a(DELAY,666)@37
ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid190_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest(LOGICAL,219)@38
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a <= ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q;
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b <= InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q;
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q <= signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a and signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b;
--ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c(DELAY,670)@38
ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest(BITJOIN,128)@36
add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b;
--reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1(REG,433)@36
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest(BITJOIN,126)@36
add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b;
--reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0(REG,432)@36
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--prod_uid165_rAtanPi_uid13_fpArctanPiTest(MULT,164)@37
prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr <= UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_a) * UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_b);
prod_uid165_rAtanPi_uid13_fpArctanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= (others => '0');
prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= (others => '0');
prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q;
prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q;
prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr);
END IF;
END IF;
END PROCESS;
prod_uid165_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1;
END IF;
END IF;
END PROCESS;
--normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest(BITSELECT,165)@40
normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q;
normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in(47 downto 47);
--roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest(CONSTANT,179)
roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q <= "010";
--fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest(BITSELECT,167)@40
fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(46 downto 0);
fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in(46 downto 23);
--fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest(BITSELECT,168)@40
fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(45 downto 0);
fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in(45 downto 22);
--fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest(MUX,169)@40
fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b;
fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s, en, fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b, fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b)
BEGIN
CASE fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "0" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b;
WHEN "1" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b;
WHEN OTHERS => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest(BITSELECT,177)@40
FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in <= fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q(1 downto 0);
FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in(1 downto 0);
--Prod22_uid172_rAtanPi_uid13_fpArctanPiTest(BITSELECT,171)@40
Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(22 downto 0);
Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in(22 downto 22);
--extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest(MUX,172)@40
extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b;
extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest: PROCESS (extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s, en, GND_q, Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b)
BEGIN
CASE extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "0" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b;
WHEN OTHERS => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest(BITSELECT,170)@40
stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(21 downto 0);
stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b <= stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in(21 downto 0);
--stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest(BITJOIN,173)@40
stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q <= extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q & stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b;
--stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest(LOGICAL,175)@40
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a <= stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q;
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q <= "1" when stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a = stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b else "0";
--sticky_uid177_rAtanPi_uid13_fpArctanPiTest(LOGICAL,176)@40
sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a <= stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q;
sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q <= not sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a;
--lrs_uid179_rAtanPi_uid13_fpArctanPiTest(BITJOIN,178)@40
lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b & sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q;
--roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest(LOGICAL,180)@40
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a <= lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q;
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b <= roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q;
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q <= "1" when roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a = roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b else "0";
--roundBit_uid182_rAtanPi_uid13_fpArctanPiTest(LOGICAL,181)@40
roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a <= roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q;
roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q <= not roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a;
--roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest(BITJOIN,184)@40
roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q <= GND_q & normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b & cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q & roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q;
--reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1(REG,436)@40
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--biasInc_uid163_rAtanPi_uid13_fpArctanPiTest(CONSTANT,162)
biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q <= "0001111111";
--ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b(DELAY,586)@36
ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expY_uid123_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expSum_uid162_rAtanPi_uid13_fpArctanPiTest(ADD,161)@37
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q);
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q);
expSum_uid162_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a) + UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q <= expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o(8 downto 0);
--ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a(DELAY,587)@38
ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest(SUB,163)@39
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q);
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q(9)) & biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q);
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b));
END IF;
END IF;
END PROCESS;
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o(10 downto 0);
--expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest(BITJOIN,182)@40
expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q & fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q;
--reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0(REG,435)@40
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest(ADD,185)@41
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q(34)) & reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q);
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q);
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a) + SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b));
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o(35 downto 0);
--expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest(BITSELECT,187)@41
expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q;
expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in(35 downto 24);
--expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest(BITSELECT,188)@41
expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b(7 downto 0);
expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in(7 downto 0);
--ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d(DELAY,664)@41
ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 2 )
PORT MAP ( xin => expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c(DELAY,659)@37
ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1(REG,437)@41
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid193_rAtanPi_uid13_fpArctanPiTest(COMPARE,192)@42
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q;
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & '0';
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q) & expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin(0);
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b));
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o(14);
--InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest(LOGICAL,157)@37
InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q;
InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a;
--InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest(LOGICAL,158)@37
InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a;
--InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest(LOGICAL,159)@37
InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a;
--exc_R_uid161_rAtanPi_uid13_fpArctanPiTest(LOGICAL,160)@37
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c;
--ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b(DELAY,629)@37
ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest(LOGICAL,141)@37
InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a;
--InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest(LOGICAL,142)@37
InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a;
--InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest(LOGICAL,143)@37
InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a;
--exc_R_uid145_rAtanPi_uid13_fpArctanPiTest(LOGICAL,144)@37
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c;
--ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a(DELAY,628)@37
ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest(LOGICAL,201)@42
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c <= expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c;
--excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest(LOGICAL,200)@37
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q;
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q <= excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a and excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c(DELAY,646)@37
ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest(LOGICAL,199)@37
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q;
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q <= excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a and excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b(DELAY,645)@37
ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest(LOGICAL,198)@37
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q <= excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a and excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a(DELAY,644)@37
ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid203_rAtanPi_uid13_fpArctanPiTest(LOGICAL,202)@42
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q <= excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d;
--expUdf_uid191_rAtanPi_uid13_fpArctanPiTest(COMPARE,190)@42
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q;
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0';
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin(0);
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b));
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o(14);
--excZC3_uid197_rAtanPi_uid13_fpArctanPiTest(LOGICAL,196)@42
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c <= expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c;
--excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest(LOGICAL,195)@37
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q;
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c(DELAY,633)@37
ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest(LOGICAL,194)@37
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b(DELAY,632)@37
ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest(LOGICAL,193)@37
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a(DELAY,631)@37
ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid198_rAtanPi_uid13_fpArctanPiTest(LOGICAL,197)@42
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q <= excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d;
--concExc_uid208_rAtanPi_uid13_fpArctanPiTest(BITJOIN,207)@42
concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q <= ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q & excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q & excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q;
--reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0(REG,439)@42
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid209_rAtanPi_uid13_fpArctanPiTest(LOOKUP,208)@43
excREnc_uid209_rAtanPi_uid13_fpArctanPiTest: PROCESS (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q) IS
WHEN "000" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "01";
WHEN "001" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "010" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "10";
WHEN "011" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "100" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "11";
WHEN "101" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "110" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "111" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN OTHERS =>
excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest(MUX,217)@43
expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q;
expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest: PROCESS (expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q;
WHEN "10" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest(BITSELECT,186)@41
fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q(23 downto 0);
fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b <= fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in(23 downto 1);
--ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d(DELAY,662)@41
ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest(MUX,212)@43
fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q;
fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q;
WHEN "10" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid221_rAtanPi_uid13_fpArctanPiTest(BITJOIN,220)@43
R_uid221_rAtanPi_uid13_fpArctanPiTest_q <= ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q & expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q & fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q;
--xOut(GPOUT,4)@43
q <= R_uid221_rAtanPi_uid13_fpArctanPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_atanpi_s5
-- VHDL created on Tue Mar 12 11:23:23 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_atanpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_atanpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBiasM2_uid6_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal ooPi_uid9_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal piO2_uid46_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0);
signal piO4_uid47_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid64_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal zS_uid67_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q : std_logic_vector (12 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a : std_logic_vector (23 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 : std_logic_vector (50 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr : UNSIGNED (50 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q : std_logic_vector (50 downto 0);
signal fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (9 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (10 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector (23 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 : std_logic_vector (47 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr : UNSIGNED (47 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (47 downto 0);
signal roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_q : std_logic_vector (40 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_b : std_logic_vector (21 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_s1 : std_logic_vector (36 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_pr : SIGNED (37 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_q : std_logic_vector (36 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid299_atanXOXTabGen_lutmem_ia : std_logic_vector (30 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_iq : std_logic_vector (30 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_q : std_logic_vector (30 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid300_atanXOXTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid301_atanXOXTabGen_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid344_invTabGen_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid345_invTabGen_lutmem_ia : std_logic_vector (19 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_iq : std_logic_vector (19 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_q : std_logic_vector (19 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid346_invTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q : std_logic_vector (19 downto 0);
signal reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q : std_logic_vector (21 downto 0);
signal reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q : std_logic_vector (28 downto 0);
signal reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q : std_logic_vector (30 downto 0);
signal reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (26 downto 0);
signal reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (8 downto 0);
signal reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (31 downto 0);
signal reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (32 downto 0);
signal reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (22 downto 0);
signal reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (22 downto 0);
signal reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (22 downto 0);
signal reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (7 downto 0);
signal reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (7 downto 0);
signal reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (22 downto 0);
signal reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (23 downto 0);
signal reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (34 downto 0);
signal reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (11 downto 0);
signal reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q : std_logic_vector (7 downto 0);
signal ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (7 downto 0);
signal ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (8 downto 0);
signal ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (22 downto 0);
signal ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (7 downto 0);
signal ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (20 downto 0);
signal ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (18 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q : std_logic_vector (12 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 : std_logic;
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : signal is true;
signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : signal is true;
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : signal is true;
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_c : std_logic_vector (0 downto 0);
signal excSelBits_uid114_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a : std_logic_vector(33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b : std_logic_vector(33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o : std_logic_vector (33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q : std_logic_vector (33 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o : std_logic_vector (32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0);
signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid15_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid15_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid16_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid16_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal singX_uid17_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal singX_uid17_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q : std_logic_vector (9 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_a : std_logic_vector(26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_b : std_logic_vector(26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_o : std_logic_vector (26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (26 downto 0);
signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (35 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal fracOOPi_uid10_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracOOPi_uid10_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid80_atanX_uid8_fpArctanPiTest_in : std_logic_vector (49 downto 0);
signal normBit_uid80_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in : std_logic_vector (48 downto 0);
signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in : std_logic_vector (47 downto 0);
signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (47 downto 0);
signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (46 downto 0);
signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (45 downto 0);
signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (21 downto 0);
signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (21 downto 0);
signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in : std_logic_vector (36 downto 0);
signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b : std_logic_vector (22 downto 0);
signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal R_uid221_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (14 downto 0);
signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (14 downto 0);
signal R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal constOut_uid54_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal constOut_uid54_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal u_uid58_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal u_uid58_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal R_uid120_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (16 downto 0);
signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (8 downto 0);
signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in : std_logic_vector (8 downto 0);
signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in : std_logic_vector (25 downto 0);
signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (11 downto 0);
signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (9 downto 0);
signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (33 downto 0);
signal fpOOPi_uid11_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (32 downto 0);
signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0);
signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (28 downto 0);
signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (24 downto 0);
signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (0 downto 0);
signal stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal lowRangeB_uid304_atanXOXPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid304_atanXOXPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid305_atanXOXPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid305_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid310_atanXOXPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid310_atanXOXPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid311_atanXOXPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid311_atanXOXPolyEval_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid349_invPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid349_invPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid350_invPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid350_invPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid355_invPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid355_invPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid356_invPolyEval_in : std_logic_vector (22 downto 0);
signal highBBits_uid356_invPolyEval_b : std_logic_vector (20 downto 0);
signal y_uid73_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal y_uid73_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0);
signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal yT1_uid347_invPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid347_invPolyEval_b : std_logic_vector (11 downto 0);
signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal expU_uid59_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expU_uid59_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracU_uid60_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracU_uid60_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0);
signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b : std_logic_vector (3 downto 0);
signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (1 downto 0);
signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (34 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_a : std_logic_vector(31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_b : std_logic_vector(31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_o : std_logic_vector (31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_q : std_logic_vector (31 downto 0);
signal sumAHighB_uid351_invPolyEval_a : std_logic_vector(20 downto 0);
signal sumAHighB_uid351_invPolyEval_b : std_logic_vector(20 downto 0);
signal sumAHighB_uid351_invPolyEval_o : std_logic_vector (20 downto 0);
signal sumAHighB_uid351_invPolyEval_q : std_logic_vector (20 downto 0);
signal sumAHighB_uid357_invPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid357_invPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid357_invPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid357_invPolyEval_q : std_logic_vector (29 downto 0);
signal yAddr_uid75_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0);
signal yAddr_uid75_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in : std_logic_vector (26 downto 0);
signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b : std_logic_vector (17 downto 0);
signal rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0);
signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b : std_logic_vector (4 downto 0);
signal expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0);
signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal s1_uid304_uid307_atanXOXPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid310_uid313_atanXOXPolyEval_q : std_logic_vector (33 downto 0);
signal s1_uid349_uid352_invPolyEval_q : std_logic_vector (21 downto 0);
signal s2_uid355_uid358_invPolyEval_q : std_logic_vector (31 downto 0);
signal yT1_uid302_atanXOXPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid302_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (20 downto 0);
signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (18 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0);
signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0);
signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (25 downto 0);
begin
--xIn(GPIN,3)@0
--cstAllZWF_uid19_atanX_uid8_fpArctanPiTest(CONSTANT,18)
cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000000";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable(LOGICAL,878)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q <= not ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,1008)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a or ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,1004)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100001";
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,1005)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,1006)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,1009)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,1010)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--fracX_uid16_atanX_uid8_fpArctanPiTest(BITSELECT,15)@0
fracX_uid16_atanX_uid8_fpArctanPiTest_in <= a(22 downto 0);
fracX_uid16_atanX_uid8_fpArctanPiTest_b <= fracX_uid16_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--fracXIsZero_uid35_atanX_uid8_fpArctanPiTest(LOGICAL,34)@0
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b else "0";
--InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest(LOGICAL,36)@0
InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q <= not InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a;
--cstAllOWE_uid18_atanX_uid8_fpArctanPiTest(CONSTANT,17)
cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q <= "11111111";
--expX_uid15_atanX_uid8_fpArctanPiTest(BITSELECT,14)@0
expX_uid15_atanX_uid8_fpArctanPiTest_in <= a(30 downto 0);
expX_uid15_atanX_uid8_fpArctanPiTest_b <= expX_uid15_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--expXIsMax_uid33_atanX_uid8_fpArctanPiTest(LOGICAL,32)@0
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a = expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b else "0";
--exc_N_uid38_atanX_uid8_fpArctanPiTest(LOGICAL,37)@0
exc_N_uid38_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q;
exc_N_uid38_atanX_uid8_fpArctanPiTest_b <= InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q;
exc_N_uid38_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_a and exc_N_uid38_atanX_uid8_fpArctanPiTest_b;
--InvExc_N_uid118_atanX_uid8_fpArctanPiTest(LOGICAL,117)@0
InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q;
InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q <= not InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a;
--singX_uid17_atanX_uid8_fpArctanPiTest(BITSELECT,16)@0
singX_uid17_atanX_uid8_fpArctanPiTest_in <= a;
singX_uid17_atanX_uid8_fpArctanPiTest_b <= singX_uid17_atanX_uid8_fpArctanPiTest_in(31 downto 31);
--signR_uid119_atanX_uid8_fpArctanPiTest(LOGICAL,118)@0
signR_uid119_atanX_uid8_fpArctanPiTest_a <= singX_uid17_atanX_uid8_fpArctanPiTest_b;
signR_uid119_atanX_uid8_fpArctanPiTest_b <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q;
signR_uid119_atanX_uid8_fpArctanPiTest_q <= signR_uid119_atanX_uid8_fpArctanPiTest_a and signR_uid119_atanX_uid8_fpArctanPiTest_b;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,998)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid119_atanX_uid8_fpArctanPiTest_q, xout => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,1000)
-- every=1, low=0, high=33, step=1, init=1
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 32 THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 33;
ELSE
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6));
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,1001)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,1002)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,999)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 34,
width_b => 1,
widthad_b => 6,
numwords_b => 34,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,879)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a or ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,875)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100000";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,876)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,877)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,880)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,881)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,869)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => singX_uid17_atanX_uid8_fpArctanPiTest_b, xout => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,871)
-- every=1, low=0, high=32, step=1, init=1
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 31 THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 32;
ELSE
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6));
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,872)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,873)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,870)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--cstBias_uid22_atanX_uid8_fpArctanPiTest(CONSTANT,21)
cstBias_uid22_atanX_uid8_fpArctanPiTest_q <= "01111111";
--piO2_uid46_atanX_uid8_fpArctanPiTest(CONSTANT,45)
piO2_uid46_atanX_uid8_fpArctanPiTest_q <= "11001001000011111101101011";
--cstPiO2_uid48_atanX_uid8_fpArctanPiTest(BITSELECT,47)@35
cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in <= piO2_uid46_atanX_uid8_fpArctanPiTest_q(24 downto 0);
cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b <= cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in(24 downto 2);
--fpPiO2C_uid49_atanX_uid8_fpArctanPiTest(BITJOIN,48)@35
fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBias_uid22_atanX_uid8_fpArctanPiTest_q & cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b;
--cstBiasM1_uid23_atanX_uid8_fpArctanPiTest(CONSTANT,22)
cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q <= "01111110";
--piO4_uid47_atanX_uid8_fpArctanPiTest(CONSTANT,46)
piO4_uid47_atanX_uid8_fpArctanPiTest_q <= "110010010000111111011011";
--cstPiO4_uid51_atanX_uid8_fpArctanPiTest(BITSELECT,50)@35
cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in <= piO4_uid47_atanX_uid8_fpArctanPiTest_q(22 downto 0);
cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b <= cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--fpPiO4C_uid52_atanX_uid8_fpArctanPiTest(BITJOIN,51)@35
fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q & cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,892)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a or ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b);
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,893)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,894)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b;
--exc_I_uid36_atanX_uid8_fpArctanPiTest(LOGICAL,35)@0
exc_I_uid36_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q;
exc_I_uid36_atanX_uid8_fpArctanPiTest_b <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
exc_I_uid36_atanX_uid8_fpArctanPiTest_q <= exc_I_uid36_atanX_uid8_fpArctanPiTest_a and exc_I_uid36_atanX_uid8_fpArctanPiTest_b;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,882)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid36_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,883)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq,
address_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa,
data_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia
);
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(0 downto 0);
--constOut_uid54_atanX_uid8_fpArctanPiTest(MUX,53)@35
constOut_uid54_atanX_uid8_fpArctanPiTest_s <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q;
constOut_uid54_atanX_uid8_fpArctanPiTest: PROCESS (constOut_uid54_atanX_uid8_fpArctanPiTest_s, en, fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q, fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE constOut_uid54_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expOutCst_uid112_atanX_uid8_fpArctanPiTest(BITSELECT,111)@35
expOutCst_uid112_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expOutCst_uid112_atanX_uid8_fpArctanPiTest_b <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5(REG,428)@35
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--cst01pWShift_uid69_atanX_uid8_fpArctanPiTest(CONSTANT,68)
cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q <= "0000000000000";
--reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2(REG,389)@0
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= signR_uid119_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c(DELAY,707)@1
ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,1022)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a or ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b);
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top(CONSTANT,1018)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q <= "0111";
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp(LOGICAL,1019)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q);
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q <= "1" when ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a = ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b else "0";
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg(REG,1020)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,1023)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,1024)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b;
--cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,230)
cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111110";
--expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest(SUB,259)@0
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q);
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b);
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b));
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,260)@0
expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0);
expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,229)
cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111101";
--expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest(SUB,256)@0
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q);
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b);
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b));
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,257)@0
expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0);
expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,249)@0
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b else "0";
--expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest(MUX,263)@0
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s <= fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q;
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--expXIsZero_uid31_atanX_uid8_fpArctanPiTest(LOGICAL,30)@0
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a = expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b else "0";
--udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,258)@0
udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in <= STD_LOGIC_VECTOR((9 downto 9 => expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(8)) & expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q);
udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in(9 downto 9);
--InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,245)@0
InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a;
--InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,246)@0
InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a <= expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q;
InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a;
--exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,247)@0
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a <= InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b <= InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c;
--xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,264)@0
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q;
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b;
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a and xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b;
--xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,265)@0
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q;
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q <= xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a or xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b;
--excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,266)@0
excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q & expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q & xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q;
--reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0(REG,378)@0
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest(LOOKUP,267)@1
outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest(MUX,269)@1
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q;
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,1012)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt(COUNTER,1014)
-- every=1, low=0, high=7, step=1, init=1
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg(REG,1015)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux(MUX,1016)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,1013)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia
);
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid20_atanX_uid8_fpArctanPiTest(CONSTANT,19)
cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000001";
--oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,248)@0
oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q <= VCC_q & fracX_uid16_atanX_uid8_fpArctanPiTest_b;
--y_uid251_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,250)@0
y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in <= oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q(22 downto 0);
y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,252)@0
yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b;
yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 15);
--reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0(REG,379)@0
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid346_invTabGen_lutmem(DUALMEM,376)@1
memoryC2_uid346_invTabGen_lutmem_ia <= (others => '0');
memoryC2_uid346_invTabGen_lutmem_aa <= (others => '0');
memoryC2_uid346_invTabGen_lutmem_ab <= reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q;
memoryC2_uid346_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC2_uid346_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid346_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid346_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid346_invTabGen_lutmem_iq,
address_a => memoryC2_uid346_invTabGen_lutmem_aa,
data_a => memoryC2_uid346_invTabGen_lutmem_ia
);
memoryC2_uid346_invTabGen_lutmem_reset0 <= areset;
memoryC2_uid346_invTabGen_lutmem_q <= memoryC2_uid346_invTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1(REG,381)@3
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= memoryC2_uid346_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,1011)
ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a(DELAY,680)@0
ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,253)@3
yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in <= ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q(14 downto 0);
yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in(14 downto 0);
--yT1_uid347_invPolyEval(BITSELECT,346)@3
yT1_uid347_invPolyEval_in <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b;
yT1_uid347_invPolyEval_b <= yT1_uid347_invPolyEval_in(14 downto 3);
--reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0(REG,380)@3
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= yT1_uid347_invPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid366_pT1_uid348_invPolyEval(MULT,365)@4
prodXY_uid366_pT1_uid348_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid366_pT1_uid348_invPolyEval_a),13)) * SIGNED(prodXY_uid366_pT1_uid348_invPolyEval_b);
prodXY_uid366_pT1_uid348_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid366_pT1_uid348_invPolyEval_a <= (others => '0');
prodXY_uid366_pT1_uid348_invPolyEval_b <= (others => '0');
prodXY_uid366_pT1_uid348_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid366_pT1_uid348_invPolyEval_a <= reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q;
prodXY_uid366_pT1_uid348_invPolyEval_b <= reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q;
prodXY_uid366_pT1_uid348_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid366_pT1_uid348_invPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid366_pT1_uid348_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid366_pT1_uid348_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid366_pT1_uid348_invPolyEval_q <= prodXY_uid366_pT1_uid348_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid367_pT1_uid348_invPolyEval(BITSELECT,366)@7
prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in <= prodXY_uid366_pT1_uid348_invPolyEval_q;
prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in(23 downto 11);
--highBBits_uid350_invPolyEval(BITSELECT,349)@7
highBBits_uid350_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b;
highBBits_uid350_invPolyEval_b <= highBBits_uid350_invPolyEval_in(12 downto 1);
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a(DELAY,804)@1
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid345_invTabGen_lutmem(DUALMEM,375)@4
memoryC1_uid345_invTabGen_lutmem_ia <= (others => '0');
memoryC1_uid345_invTabGen_lutmem_aa <= (others => '0');
memoryC1_uid345_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q;
memoryC1_uid345_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 20,
widthad_a => 8,
numwords_a => 256,
width_b => 20,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC1_uid345_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid345_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid345_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid345_invTabGen_lutmem_iq,
address_a => memoryC1_uid345_invTabGen_lutmem_aa,
data_a => memoryC1_uid345_invTabGen_lutmem_ia
);
memoryC1_uid345_invTabGen_lutmem_reset0 <= areset;
memoryC1_uid345_invTabGen_lutmem_q <= memoryC1_uid345_invTabGen_lutmem_iq(19 downto 0);
--reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0(REG,383)@6
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= "00000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= memoryC1_uid345_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid351_invPolyEval(ADD,350)@7
sumAHighB_uid351_invPolyEval_a <= STD_LOGIC_VECTOR((20 downto 20 => reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q(19)) & reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q);
sumAHighB_uid351_invPolyEval_b <= STD_LOGIC_VECTOR((20 downto 12 => highBBits_uid350_invPolyEval_b(11)) & highBBits_uid350_invPolyEval_b);
sumAHighB_uid351_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid351_invPolyEval_a) + SIGNED(sumAHighB_uid351_invPolyEval_b));
sumAHighB_uid351_invPolyEval_q <= sumAHighB_uid351_invPolyEval_o(20 downto 0);
--lowRangeB_uid349_invPolyEval(BITSELECT,348)@7
lowRangeB_uid349_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b(0 downto 0);
lowRangeB_uid349_invPolyEval_b <= lowRangeB_uid349_invPolyEval_in(0 downto 0);
--s1_uid349_uid352_invPolyEval(BITJOIN,351)@7
s1_uid349_uid352_invPolyEval_q <= sumAHighB_uid351_invPolyEval_q & lowRangeB_uid349_invPolyEval_b;
--reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1(REG,385)@7
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= "0000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= s1_uid349_uid352_invPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor(LOGICAL,1059)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a or ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b);
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg(REG,966)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena(REG,1060)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q = "1") THEN
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd(LOGICAL,1061)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b <= en;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg(DELAY,1051)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt(COUNTER,962)
-- every=1, low=0, high=1, step=1, init=1
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i,1));
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg(REG,963)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux(MUX,964)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s <= en;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux: PROCESS (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q)
BEGIN
CASE ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s IS
WHEN "0" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
WHEN "1" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q;
WHEN OTHERS => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem(DUALMEM,1052)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia
);
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0(REG,384)@7
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid369_pT2_uid354_invPolyEval(MULT,368)@8
prodXY_uid369_pT2_uid354_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid369_pT2_uid354_invPolyEval_a),16)) * SIGNED(prodXY_uid369_pT2_uid354_invPolyEval_b);
prodXY_uid369_pT2_uid354_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid369_pT2_uid354_invPolyEval_a <= (others => '0');
prodXY_uid369_pT2_uid354_invPolyEval_b <= (others => '0');
prodXY_uid369_pT2_uid354_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid369_pT2_uid354_invPolyEval_a <= reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q;
prodXY_uid369_pT2_uid354_invPolyEval_b <= reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q;
prodXY_uid369_pT2_uid354_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid369_pT2_uid354_invPolyEval_pr,37));
END IF;
END IF;
END PROCESS;
prodXY_uid369_pT2_uid354_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid369_pT2_uid354_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid369_pT2_uid354_invPolyEval_q <= prodXY_uid369_pT2_uid354_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid370_pT2_uid354_invPolyEval(BITSELECT,369)@11
prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in <= prodXY_uid369_pT2_uid354_invPolyEval_q;
prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in(36 downto 14);
--highBBits_uid356_invPolyEval(BITSELECT,355)@11
highBBits_uid356_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b;
highBBits_uid356_invPolyEval_b <= highBBits_uid356_invPolyEval_in(22 downto 2);
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor(LOGICAL,1048)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q <= not (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a or ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b);
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top(CONSTANT,1031)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q <= "0100";
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp(LOGICAL,1032)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q <= "1" when ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a = ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b else "0";
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg(REG,1033)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena(REG,1049)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd(LOGICAL,1050)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a and ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg(DELAY,1038)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt(COUNTER,1027)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i,3));
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg(REG,1028)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux(MUX,1029)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s <= en;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux: PROCESS (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem(DUALMEM,1039)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq(7 downto 0);
--memoryC0_uid344_invTabGen_lutmem(DUALMEM,374)@8
memoryC0_uid344_invTabGen_lutmem_ia <= (others => '0');
memoryC0_uid344_invTabGen_lutmem_aa <= (others => '0');
memoryC0_uid344_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q;
memoryC0_uid344_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC0_uid344_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid344_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid344_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid344_invTabGen_lutmem_iq,
address_a => memoryC0_uid344_invTabGen_lutmem_aa,
data_a => memoryC0_uid344_invTabGen_lutmem_ia
);
memoryC0_uid344_invTabGen_lutmem_reset0 <= areset;
memoryC0_uid344_invTabGen_lutmem_q <= memoryC0_uid344_invTabGen_lutmem_iq(28 downto 0);
--reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0(REG,387)@10
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= "00000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= memoryC0_uid344_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid357_invPolyEval(ADD,356)@11
sumAHighB_uid357_invPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q(28)) & reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q);
sumAHighB_uid357_invPolyEval_b <= STD_LOGIC_VECTOR((29 downto 21 => highBBits_uid356_invPolyEval_b(20)) & highBBits_uid356_invPolyEval_b);
sumAHighB_uid357_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid357_invPolyEval_a) + SIGNED(sumAHighB_uid357_invPolyEval_b));
sumAHighB_uid357_invPolyEval_q <= sumAHighB_uid357_invPolyEval_o(29 downto 0);
--lowRangeB_uid355_invPolyEval(BITSELECT,354)@11
lowRangeB_uid355_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b(1 downto 0);
lowRangeB_uid355_invPolyEval_b <= lowRangeB_uid355_invPolyEval_in(1 downto 0);
--s2_uid355_uid358_invPolyEval(BITJOIN,357)@11
s2_uid355_uid358_invPolyEval_q <= sumAHighB_uid357_invPolyEval_q & lowRangeB_uid355_invPolyEval_b;
--fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,255)@11
fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in <= s2_uid355_uid358_invPolyEval_q(28 downto 0);
fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in(28 downto 5);
--fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,261)@11
fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b(22 downto 0);
fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,688)@0
ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest(MUX,262)@11
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q;
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1(REG,388)@1
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,701)@2
ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 10 )
PORT MAP ( xin => reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest(MUX,268)@12
fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q;
fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid273_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,272)@12
R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q <= ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q & fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,905)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a or ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,901)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "01001";
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,902)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,903)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,906)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,907)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,895)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,897)
-- every=1, low=0, high=9, step=1, init=1
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 8 THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 9;
ELSE
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,4));
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,898)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,899)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,896)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 4,
numwords_a => 10,
width_b => 32,
widthad_b => 4,
numwords_b => 10,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(31 downto 0);
--path2_uid56_atanX_uid8_fpArctanPiTest(COMPARE,55)@0
path2_uid56_atanX_uid8_fpArctanPiTest_cin <= GND_q;
path2_uid56_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid15_atanX_uid8_fpArctanPiTest_b) & '0';
path2_uid56_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q) & path2_uid56_atanX_uid8_fpArctanPiTest_cin(0);
path2_uid56_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_b));
path2_uid56_atanX_uid8_fpArctanPiTest_n(0) <= not path2_uid56_atanX_uid8_fpArctanPiTest_o(10);
--reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1(REG,390)@0
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= path2_uid56_atanX_uid8_fpArctanPiTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b(DELAY,466)@1
ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--u_uid58_atanX_uid8_fpArctanPiTest(MUX,57)@12
u_uid58_atanX_uid8_fpArctanPiTest_s <= ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q;
u_uid58_atanX_uid8_fpArctanPiTest: PROCESS (u_uid58_atanX_uid8_fpArctanPiTest_s, en, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q, R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE u_uid58_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => u_uid58_atanX_uid8_fpArctanPiTest_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q;
WHEN "1" => u_uid58_atanX_uid8_fpArctanPiTest_q <= R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => u_uid58_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracU_uid60_atanX_uid8_fpArctanPiTest(BITSELECT,59)@12
fracU_uid60_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracU_uid60_atanX_uid8_fpArctanPiTest_b <= fracU_uid60_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a(DELAY,471)@12
ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracU_uid60_atanX_uid8_fpArctanPiTest_b, xout => ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest(BITJOIN,60)@13
oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q;
--oFracUExt_uid70_atanX_uid8_fpArctanPiTest(BITJOIN,69)@13
oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q <= cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q & oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q;
--X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,282)@13
X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(24 downto 0);
X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(24 downto 0);
--leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,281)
leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000000000000";
--leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,283)@13
leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5(REG,399)@13
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,279)@13
X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(28 downto 0);
X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(28 downto 0);
--leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,280)@13
leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4(REG,398)@13
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,276)@13
X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(32 downto 0);
X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(32 downto 0);
--leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,275)
leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "0000";
--leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,277)@13
leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3(REG,397)@13
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,396)@13
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--zS_uid67_atanX_uid8_fpArctanPiTest(CONSTANT,66)
zS_uid67_atanX_uid8_fpArctanPiTest_q <= "000000000";
--shiftBias_uid64_atanX_uid8_fpArctanPiTest(CONSTANT,63)
shiftBias_uid64_atanX_uid8_fpArctanPiTest_q <= "01110010";
--expU_uid59_atanX_uid8_fpArctanPiTest(BITSELECT,58)@12
expU_uid59_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expU_uid59_atanX_uid8_fpArctanPiTest_b <= expU_uid59_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1(REG,391)@12
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= expU_uid59_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--shiftValue_uid65_atanX_uid8_fpArctanPiTest(SUB,64)@13
shiftValue_uid65_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q);
shiftValue_uid65_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid64_atanX_uid8_fpArctanPiTest_q);
shiftValue_uid65_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_b));
shiftValue_uid65_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--ShiftValue8_uid66_atanX_uid8_fpArctanPiTest(BITSELECT,65)@13
ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q;
ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in(8 downto 8);
--shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest(MUX,67)@13
shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b;
shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest: PROCESS (shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s, en, shiftValue_uid65_atanX_uid8_fpArctanPiTest_q, zS_uid67_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= zS_uid67_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest(BITSELECT,70)@13
fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in <= shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q(3 downto 0);
fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,284)@13
leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b;
leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,395)@13
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,285)@14
leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q;
leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q, reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q, reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q;
WHEN "11" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,293)@14
LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(33 downto 0);
LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(33 downto 0);
--ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,725)@14
ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,292)
leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000";
--leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,294)@15
leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,290)@14
LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(34 downto 0);
LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(34 downto 0);
--ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,723)@14
ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,289)
leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "00";
--leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,291)@15
leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,287)@14
LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0);
LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(35 downto 0);
--ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,721)@14
ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,288)@15
leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & GND_q;
--reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,401)@14
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,295)@13
leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a(DELAY,829)@13
ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,400)@14
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,296)@15
leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q;
leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid73_atanX_uid8_fpArctanPiTest(BITSELECT,72)@15
y_uid73_atanX_uid8_fpArctanPiTest_in <= leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0);
y_uid73_atanX_uid8_fpArctanPiTest_b <= y_uid73_atanX_uid8_fpArctanPiTest_in(35 downto 1);
--yAddr_uid75_atanX_uid8_fpArctanPiTest(BITSELECT,74)@15
yAddr_uid75_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b;
yAddr_uid75_atanX_uid8_fpArctanPiTest_b <= yAddr_uid75_atanX_uid8_fpArctanPiTest_in(34 downto 27);
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0(REG,402)@15
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= yAddr_uid75_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid301_atanXOXTabGen_lutmem(DUALMEM,373)@16
memoryC2_uid301_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC2_uid301_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC2_uid301_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q;
memoryC2_uid301_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC2_uid301_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid301_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid301_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid301_atanXOXTabGen_lutmem_iq,
address_a => memoryC2_uid301_atanXOXTabGen_lutmem_aa,
data_a => memoryC2_uid301_atanXOXTabGen_lutmem_ia
);
memoryC2_uid301_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC2_uid301_atanXOXTabGen_lutmem_q <= memoryC2_uid301_atanXOXTabGen_lutmem_iq(12 downto 0);
--reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1(REG,404)@18
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= memoryC2_uid301_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--yPPolyEval_uid76_atanX_uid8_fpArctanPiTest(BITSELECT,75)@15
yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b(26 downto 0);
yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in(26 downto 9);
--yT1_uid302_atanXOXPolyEval(BITSELECT,301)@15
yT1_uid302_atanXOXPolyEval_in <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b;
yT1_uid302_atanXOXPolyEval_b <= yT1_uid302_atanXOXPolyEval_in(17 downto 5);
--ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg(DELAY,1062)
ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid302_atanXOXPolyEval_b, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a(DELAY,832)@15
ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0(REG,403)@18
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid360_pT1_uid303_atanXOXPolyEval(MULT,359)@19
prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_a),14)) * SIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_b);
prodXY_uid360_pT1_uid303_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= (others => '0');
prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= (others => '0');
prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q;
prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q;
prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid360_pT1_uid303_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval(BITSELECT,360)@22
prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_q;
prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in(25 downto 12);
--highBBits_uid305_atanXOXPolyEval(BITSELECT,304)@22
highBBits_uid305_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b;
highBBits_uid305_atanXOXPolyEval_b <= highBBits_uid305_atanXOXPolyEval_in(13 downto 1);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a(DELAY,834)@15
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0(REG,405)@18
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid300_atanXOXTabGen_lutmem(DUALMEM,372)@19
memoryC1_uid300_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC1_uid300_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC1_uid300_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q;
memoryC1_uid300_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC1_uid300_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid300_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid300_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid300_atanXOXTabGen_lutmem_iq,
address_a => memoryC1_uid300_atanXOXTabGen_lutmem_aa,
data_a => memoryC1_uid300_atanXOXTabGen_lutmem_ia
);
memoryC1_uid300_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC1_uid300_atanXOXTabGen_lutmem_q <= memoryC1_uid300_atanXOXTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0(REG,406)@21
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= memoryC1_uid300_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid306_atanXOXPolyEval(ADD,305)@22
sumAHighB_uid306_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q(20)) & reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q);
sumAHighB_uid306_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid305_atanXOXPolyEval_b(12)) & highBBits_uid305_atanXOXPolyEval_b);
sumAHighB_uid306_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid306_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid306_atanXOXPolyEval_b));
sumAHighB_uid306_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_o(21 downto 0);
--lowRangeB_uid304_atanXOXPolyEval(BITSELECT,303)@22
lowRangeB_uid304_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b(0 downto 0);
lowRangeB_uid304_atanXOXPolyEval_b <= lowRangeB_uid304_atanXOXPolyEval_in(0 downto 0);
--s1_uid304_uid307_atanXOXPolyEval(BITJOIN,306)@22
s1_uid304_uid307_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_q & lowRangeB_uid304_atanXOXPolyEval_b;
--reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1(REG,408)@22
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= s1_uid304_uid307_atanXOXPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor(LOGICAL,1035)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q <= not (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a or ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b);
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena(REG,1036)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd(LOGICAL,1037)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b <= en;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a and ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b;
--reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0(REG,407)@15
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg(DELAY,1025)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q, xout => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem(DUALMEM,1026)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq,
address_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa,
data_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia
);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid363_pT2_uid309_atanXOXPolyEval(MULT,362)@23
prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_a),19)) * SIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_b);
prodXY_uid363_pT2_uid309_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= (others => '0');
prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= (others => '0');
prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q;
prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q;
prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid363_pT2_uid309_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval(BITSELECT,363)@26
prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_q;
prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in(40 downto 17);
--highBBits_uid311_atanXOXPolyEval(BITSELECT,310)@26
highBBits_uid311_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b;
highBBits_uid311_atanXOXPolyEval_b <= highBBits_uid311_atanXOXPolyEval_in(23 downto 2);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor(LOGICAL,1073)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q <= not (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a or ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena(REG,1074)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q = "1") THEN
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd(LOGICAL,1075)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b <= en;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a and ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b;
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg(DELAY,1063)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem(DUALMEM,1064)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia
);
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0(REG,409)@22
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid299_atanXOXTabGen_lutmem(DUALMEM,371)@23
memoryC0_uid299_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC0_uid299_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC0_uid299_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q;
memoryC0_uid299_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 31,
widthad_a => 8,
numwords_a => 256,
width_b => 31,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC0_uid299_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid299_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid299_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid299_atanXOXTabGen_lutmem_iq,
address_a => memoryC0_uid299_atanXOXTabGen_lutmem_aa,
data_a => memoryC0_uid299_atanXOXTabGen_lutmem_ia
);
memoryC0_uid299_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC0_uid299_atanXOXTabGen_lutmem_q <= memoryC0_uid299_atanXOXTabGen_lutmem_iq(30 downto 0);
--reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0(REG,410)@25
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= memoryC0_uid299_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid312_atanXOXPolyEval(ADD,311)@26
sumAHighB_uid312_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((31 downto 31 => reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q(30)) & reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q);
sumAHighB_uid312_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((31 downto 22 => highBBits_uid311_atanXOXPolyEval_b(21)) & highBBits_uid311_atanXOXPolyEval_b);
sumAHighB_uid312_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid312_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid312_atanXOXPolyEval_b));
sumAHighB_uid312_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_o(31 downto 0);
--lowRangeB_uid310_atanXOXPolyEval(BITSELECT,309)@26
lowRangeB_uid310_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b(1 downto 0);
lowRangeB_uid310_atanXOXPolyEval_b <= lowRangeB_uid310_atanXOXPolyEval_in(1 downto 0);
--s2_uid310_uid313_atanXOXPolyEval(BITJOIN,312)@26
s2_uid310_uid313_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_q & lowRangeB_uid310_atanXOXPolyEval_b;
--fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest(BITSELECT,77)@26
fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in <= s2_uid310_uid313_atanXOXPolyEval_q(31 downto 0);
fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in(31 downto 5);
--reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1(REG,412)@26
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,918)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,914)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01010";
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,915)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,916)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,919)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,920)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0(REG,411)@13
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,908)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,910)
-- every=1, low=0, high=10, step=1, init=1
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 9 THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 10;
ELSE
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4));
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,911)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,912)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,909)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 11,
width_b => 24,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(23 downto 0);
--mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest(MULT,78)@27
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr <= UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a) * UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b);
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= (others => '0');
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= (others => '0');
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr);
END IF;
END IF;
END PROCESS;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid80_atanX_uid8_fpArctanPiTest(BITSELECT,79)@30
normBit_uid80_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(49 downto 0);
normBit_uid80_atanX_uid8_fpArctanPiTest_b <= normBit_uid80_atanX_uid8_fpArctanPiTest_in(49 downto 49);
--InvNormBit_uid84_atanX_uid8_fpArctanPiTest(LOGICAL,83)@30
InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a <= normBit_uid80_atanX_uid8_fpArctanPiTest_b;
InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q <= not InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,931)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,927)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01111";
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,928)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,929)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,932)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,933)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,921)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expU_uid59_atanX_uid8_fpArctanPiTest_b, xout => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,923)
-- every=1, low=0, high=15, step=1, init=1
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4));
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,924)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,925)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,922)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 16,
width_b => 8,
widthad_b => 4,
numwords_b => 16,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(7 downto 0);
--expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest(SUB,84)@30
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q);
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000" & InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q);
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b));
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--fracRPath3High_uid81_atanX_uid8_fpArctanPiTest(BITSELECT,80)@30
fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(48 downto 0);
fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in(48 downto 25);
--fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest(BITSELECT,81)@30
fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(47 downto 0);
fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in(47 downto 24);
--fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest(MUX,82)@30
fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s <= normBit_uid80_atanX_uid8_fpArctanPiTest_b;
fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s, en, fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b, fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b)
BEGIN
CASE fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest(BITJOIN,85)@30
expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q & fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q;
--reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0(REG,420)@30
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest(ADD,86)@31
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q);
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000" & VCC_q);
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b));
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o(33 downto 0);
--expRPath3_uid89_atanX_uid8_fpArctanPiTest(BITSELECT,88)@31
expRPath3_uid89_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(31 downto 0);
expRPath3_uid89_atanX_uid8_fpArctanPiTest_b <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_in(31 downto 24);
--reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4(REG,427)@31
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,971)
ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e(DELAY,534)@32
ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,337)@33
RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 1);
--rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,339)@33
rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= GND_q & RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,333)
rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000";
--rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,322)
rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000000000000000000000";
--X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,321)@32
X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 24);
--rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,323)@32
rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,319)
rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "0000000000000000";
--X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,318)@32
X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 16);
--rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,320)@32
rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,315)@32
X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 8);
--rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,317)@32
rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q & X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a(DELAY,504)@30
ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q, xout => ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest(BITJOIN,93)@32
oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q;
--cstWFP2_uid25_atanX_uid8_fpArctanPiTest(CONSTANT,24)
cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q <= "00011001";
--reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1(REG,413)@30
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest(SUB,89)@31
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q);
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR((10 downto 9 => reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q(8)) & reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q);
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a) - SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b));
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o(9 downto 0);
--shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest(BITSELECT,91)@31
shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q(7 downto 0);
shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest(CONSTANT,23)
cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q <= "01101000";
--shiftOut_uid91_atanX_uid8_fpArctanPiTest(COMPARE,90)@13
shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin <= GND_q;
shiftOut_uid91_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & '0';
shiftOut_uid91_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q) & shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin(0);
shiftOut_uid91_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_b));
shiftOut_uid91_atanX_uid8_fpArctanPiTest_c(0) <= shiftOut_uid91_atanX_uid8_fpArctanPiTest_o(10);
--ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b(DELAY,502)@13
ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => shiftOut_uid91_atanX_uid8_fpArctanPiTest_c, xout => ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--sValPostSOut_uid93_atanX_uid8_fpArctanPiTest(MUX,92)@31
sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s <= ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q;
sValPostSOut_uid93_atanX_uid8_fpArctanPiTest: PROCESS (sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s, en, shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b, cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest(BITSELECT,94)@31
sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in <= sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q(4 downto 0);
sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,324)@31
rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b;
rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,414)@31
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,325)@32
rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q;
rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,332)@32
RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 6);
--ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,762)@32
ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,334)@33
rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,329)@32
RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 4);
--ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,760)@32
ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 21, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,331)@33
rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,326)@32
RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 2);
--ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,758)@32
ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,328)@33
rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2(REG,416)@32
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,335)@31
rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(2 downto 1);
--ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a(DELAY,844)@31
ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,415)@32
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,336)@33
rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q;
rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q, rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,340)@31
rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,417)@31
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b(DELAY,772)@32
ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,341)@33
rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q;
rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest(BITJOIN,96)@33
pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & GND_q;
--reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1(REG,418)@33
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--path2Diff_uid97_atanX_uid8_fpArctanPiTest(SUB,97)@34
path2Diff_uid97_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & piO2_uid46_atanX_uid8_fpArctanPiTest_q);
path2Diff_uid97_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q);
path2Diff_uid97_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_b));
path2Diff_uid97_atanX_uid8_fpArctanPiTest_q <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_o(26 downto 0);
--normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest(BITSELECT,98)@34
normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(25 downto 0);
normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in(25 downto 25);
--expRPath2_uid103_atanX_uid8_fpArctanPiTest(MUX,102)@34
expRPath2_uid103_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b;
expRPath2_uid103_atanX_uid8_fpArctanPiTest: PROCESS (expRPath2_uid103_atanX_uid8_fpArctanPiTest_s, en, cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q, cstBias_uid22_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPath2_uid103_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest(BITSELECT,99)@34
path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(24 downto 0);
path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in(24 downto 1);
--path2DiffLow_uid101_atanX_uid8_fpArctanPiTest(BITSELECT,100)@34
path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(23 downto 0);
path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in(23 downto 0);
--fracRPath2_uid102_atanX_uid8_fpArctanPiTest(MUX,101)@34
fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b;
fracRPath2_uid102_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s, en, path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b, path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b)
BEGIN
CASE fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest(BITJOIN,103)@34
expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q <= expRPath2_uid103_atanX_uid8_fpArctanPiTest_q & fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q;
--reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0(REG,419)@34
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest(ADD,104)@35
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q);
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000" & VCC_q);
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b));
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o(32 downto 0);
--expRPath2_uid107_atanX_uid8_fpArctanPiTest(BITSELECT,106)@35
expRPath2_uid107_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(31 downto 0);
expRPath2_uid107_atanX_uid8_fpArctanPiTest_b <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_in(31 downto 24);
--reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3(REG,426)@35
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor(LOGICAL,1086)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q <= not (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a or ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b);
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena(REG,1087)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q = "1") THEN
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd(LOGICAL,1088)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b <= en;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a and ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg(DELAY,1076)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid15_atanX_uid8_fpArctanPiTest_b, xout => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem(DUALMEM,1077)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 33,
width_b => 8,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq,
address_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa,
data_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia
);
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 <= areset;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq(7 downto 0);
--reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2(REG,425)@35
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,944)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,940)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "010010";
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,941)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,942)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,945)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,946)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--expXIsBias_uid44_atanX_uid8_fpArctanPiTest(LOGICAL,43)@0
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q;
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a = expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b else "0";
--inIsOne_uid45_atanX_uid8_fpArctanPiTest(LOGICAL,44)@0
inIsOne_uid45_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
inIsOne_uid45_atanX_uid8_fpArctanPiTest_b <= expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q;
inIsOne_uid45_atanX_uid8_fpArctanPiTest_q <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_a and inIsOne_uid45_atanX_uid8_fpArctanPiTest_b;
--arctanIsConst_uid55_atanX_uid8_fpArctanPiTest(LOGICAL,54)@0
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_q;
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a or arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c(DELAY,522)@1
ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q, xout => ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasMwShift_uid62_atanX_uid8_fpArctanPiTest(CONSTANT,61)
biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q <= "01110011";
--atanUIsU_uid63_atanX_uid8_fpArctanPiTest(COMPARE,62)@13
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin <= GND_q;
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q) & '0';
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin(0);
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b));
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n(0) <= not atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o(10);
--ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a(DELAY,520)@0
ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => path2_uid56_atanX_uid8_fpArctanPiTest_n, xout => ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--pathSelBits_uid108_atanX_uid8_fpArctanPiTest(BITJOIN,107)@13
pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q <= ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n & ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q;
--reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0(REG,392)@13
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,934)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,936)
-- every=1, low=0, high=18, step=1, init=1
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 17 THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 18;
ELSE
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,5));
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,937)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,938)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,935)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 19,
width_b => 3,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(2 downto 0);
--fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest(LOOKUP,108)@35
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q) IS
WHEN "000" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "001" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "010" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "011" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "110" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "111" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN OTHERS =>
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRCalc_uid113_atanX_uid8_fpArctanPiTest(MUX,112)@36
expRCalc_uid113_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q;
expRCalc_uid113_atanX_uid8_fpArctanPiTest: PROCESS (expRCalc_uid113_atanX_uid8_fpArctanPiTest_s, en, reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q, reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q, ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE expRCalc_uid113_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q;
WHEN "11" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstAllZWE_uid21_atanX_uid8_fpArctanPiTest(CONSTANT,20)
cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q <= "00000000";
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,995)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a or ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,996)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,997)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,985)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid38_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,986)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,982)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,983)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,984)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,972)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q, xout => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,973)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(0 downto 0);
--excSelBits_uid114_atanX_uid8_fpArctanPiTest(BITJOIN,113)@35
excSelBits_uid114_atanX_uid8_fpArctanPiTest_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q & GND_q & ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q;
--reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0(REG,377)@35
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid114_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest(LOOKUP,114)@36
outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid117_atanX_uid8_fpArctanPiTest(MUX,116)@36
expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q;
expRPostExc_uid117_atanX_uid8_fpArctanPiTest: PROCESS (expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, expRCalc_uid113_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid113_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracOutCst_uid110_atanX_uid8_fpArctanPiTest(BITSELECT,109)@35
fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5(REG,424)@35
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor(LOGICAL,968)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q <= not (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a or ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b);
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena(REG,969)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd(LOGICAL,970)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b <= en;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a and ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b;
--fracRPath3_uid88_atanX_uid8_fpArctanPiTest(BITSELECT,87)@31
fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(23 downto 0);
fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in(23 downto 1);
--reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4(REG,423)@31
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,960)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem(DUALMEM,961)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 1,
numwords_a => 2,
width_b => 23,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq,
address_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa,
data_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia
);
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 <= areset;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq(22 downto 0);
--fracRPath2_uid106_atanX_uid8_fpArctanPiTest(BITSELECT,105)@35
fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(23 downto 0);
fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in(23 downto 1);
--reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3(REG,422)@35
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,957)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a or ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,958)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,959)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2(REG,421)@0
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,947)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,948)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 33,
width_b => 23,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(22 downto 0);
--fracRCalc_uid111_atanX_uid8_fpArctanPiTest(MUX,110)@36
fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q;
fracRCalc_uid111_atanX_uid8_fpArctanPiTest: PROCESS (fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s, en, ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q, reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q, reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q;
WHEN "01" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q;
WHEN "11" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid116_atanX_uid8_fpArctanPiTest(MUX,115)@36
fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q;
fracRPostExc_uid116_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid120_atanX_uid8_fpArctanPiTest(BITJOIN,119)@36
R_uid120_atanX_uid8_fpArctanPiTest_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q & expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q & fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q;
--fracX_uid126_rAtanPi_uid13_fpArctanPiTest(BITSELECT,125)@36
fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0);
--reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1(REG,431)@36
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest(LOGICAL,137)@37
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a <= reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q;
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b else "0";
--expX_uid122_rAtanPi_uid13_fpArctanPiTest(BITSELECT,121)@36
expX_uid122_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expX_uid122_rAtanPi_uid13_fpArctanPiTest_b <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23);
--reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1(REG,429)@36
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest(LOGICAL,135)@37
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q;
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b else "0";
--exc_I_uid139_rAtanPi_uid13_fpArctanPiTest(LOGICAL,138)@37
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q;
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q;
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b;
--cstBiasM2_uid6_fpArctanPiTest(CONSTANT,5)
cstBiasM2_uid6_fpArctanPiTest_q <= "01111101";
--ooPi_uid9_fpArctanPiTest(CONSTANT,8)
ooPi_uid9_fpArctanPiTest_q <= "101000101111100110000011";
--fracOOPi_uid10_fpArctanPiTest(BITSELECT,9)@36
fracOOPi_uid10_fpArctanPiTest_in <= ooPi_uid9_fpArctanPiTest_q(22 downto 0);
fracOOPi_uid10_fpArctanPiTest_b <= fracOOPi_uid10_fpArctanPiTest_in(22 downto 0);
--fpOOPi_uid11_fpArctanPiTest(BITJOIN,10)@36
fpOOPi_uid11_fpArctanPiTest_q <= GND_q & cstBiasM2_uid6_fpArctanPiTest_q & fracOOPi_uid10_fpArctanPiTest_b;
--expY_uid123_rAtanPi_uid13_fpArctanPiTest(BITSELECT,122)@36
expY_uid123_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(30 downto 0);
expY_uid123_rAtanPi_uid13_fpArctanPiTest_b <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23);
--expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest(LOGICAL,149)@36
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b;
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a(DELAY,581)@36
ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest(LOGICAL,203)@37
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b;
--fracY_uid128_rAtanPi_uid13_fpArctanPiTest(BITSELECT,127)@36
fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(22 downto 0);
fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0);
--fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest(LOGICAL,153)@36
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b;
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b(DELAY,575)@36
ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest(LOGICAL,151)@36
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b;
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a(DELAY,574)@36
ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid155_rAtanPi_uid13_fpArctanPiTest(LOGICAL,154)@37
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q;
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b <= ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q;
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b;
--expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest(LOGICAL,133)@37
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q;
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b else "0";
--excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest(LOGICAL,204)@37
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b;
--ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest(LOGICAL,205)@37
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q;
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q;
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a or ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b;
--InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest(LOGICAL,155)@36
InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q;
InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a;
--exc_N_uid157_rAtanPi_uid13_fpArctanPiTest(LOGICAL,156)@36
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b;
--ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a(DELAY,579)@36
ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest(LOGICAL,139)@37
InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q;
InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a;
--exc_N_uid141_rAtanPi_uid13_fpArctanPiTest(LOGICAL,140)@37
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b;
--excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest(LOGICAL,206)@37
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c;
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest(LOGICAL,218)@37
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q;
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= not InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a;
END IF;
END PROCESS;
--signY_uid125_rAtanPi_uid13_fpArctanPiTest(BITSELECT,124)@36
signY_uid125_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q;
signY_uid125_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31);
--signX_uid124_rAtanPi_uid13_fpArctanPiTest(BITSELECT,123)@36
signX_uid124_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q;
signX_uid124_rAtanPi_uid13_fpArctanPiTest_b <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31);
--signR_uid190_rAtanPi_uid13_fpArctanPiTest(LOGICAL,189)@36
signR_uid190_rAtanPi_uid13_fpArctanPiTest_a <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_b;
signR_uid190_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_b;
signR_uid190_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= signR_uid190_rAtanPi_uid13_fpArctanPiTest_a xor signR_uid190_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a(DELAY,666)@37
ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid190_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest(LOGICAL,219)@38
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a <= ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q;
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b <= InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q;
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q <= signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a and signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b;
--ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c(DELAY,670)@38
ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest(BITJOIN,128)@36
add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b;
--reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1(REG,433)@36
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest(BITJOIN,126)@36
add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b;
--reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0(REG,432)@36
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--prod_uid165_rAtanPi_uid13_fpArctanPiTest(MULT,164)@37
prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr <= UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_a) * UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_b);
prod_uid165_rAtanPi_uid13_fpArctanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= (others => '0');
prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= (others => '0');
prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q;
prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q;
prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr);
END IF;
END IF;
END PROCESS;
prod_uid165_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1;
END IF;
END IF;
END PROCESS;
--normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest(BITSELECT,165)@40
normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q;
normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in(47 downto 47);
--roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest(CONSTANT,179)
roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q <= "010";
--fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest(BITSELECT,167)@40
fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(46 downto 0);
fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in(46 downto 23);
--fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest(BITSELECT,168)@40
fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(45 downto 0);
fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in(45 downto 22);
--fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest(MUX,169)@40
fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b;
fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s, en, fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b, fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b)
BEGIN
CASE fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "0" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b;
WHEN "1" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b;
WHEN OTHERS => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest(BITSELECT,177)@40
FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in <= fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q(1 downto 0);
FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in(1 downto 0);
--Prod22_uid172_rAtanPi_uid13_fpArctanPiTest(BITSELECT,171)@40
Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(22 downto 0);
Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in(22 downto 22);
--extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest(MUX,172)@40
extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b;
extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest: PROCESS (extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s, en, GND_q, Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b)
BEGIN
CASE extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "0" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b;
WHEN OTHERS => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest(BITSELECT,170)@40
stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(21 downto 0);
stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b <= stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in(21 downto 0);
--stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest(BITJOIN,173)@40
stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q <= extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q & stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b;
--stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest(LOGICAL,175)@40
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a <= stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q;
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q <= "1" when stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a = stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b else "0";
--sticky_uid177_rAtanPi_uid13_fpArctanPiTest(LOGICAL,176)@40
sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a <= stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q;
sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q <= not sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a;
--lrs_uid179_rAtanPi_uid13_fpArctanPiTest(BITJOIN,178)@40
lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b & sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q;
--roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest(LOGICAL,180)@40
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a <= lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q;
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b <= roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q;
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q <= "1" when roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a = roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b else "0";
--roundBit_uid182_rAtanPi_uid13_fpArctanPiTest(LOGICAL,181)@40
roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a <= roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q;
roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q <= not roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a;
--roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest(BITJOIN,184)@40
roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q <= GND_q & normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b & cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q & roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q;
--reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1(REG,436)@40
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--biasInc_uid163_rAtanPi_uid13_fpArctanPiTest(CONSTANT,162)
biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q <= "0001111111";
--ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b(DELAY,586)@36
ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expY_uid123_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expSum_uid162_rAtanPi_uid13_fpArctanPiTest(ADD,161)@37
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q);
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q);
expSum_uid162_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a) + UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q <= expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o(8 downto 0);
--ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a(DELAY,587)@38
ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest(SUB,163)@39
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q);
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q(9)) & biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q);
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b));
END IF;
END IF;
END PROCESS;
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o(10 downto 0);
--expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest(BITJOIN,182)@40
expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q & fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q;
--reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0(REG,435)@40
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest(ADD,185)@41
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q(34)) & reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q);
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q);
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a) + SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b));
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o(35 downto 0);
--expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest(BITSELECT,187)@41
expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q;
expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in(35 downto 24);
--expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest(BITSELECT,188)@41
expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b(7 downto 0);
expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in(7 downto 0);
--ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d(DELAY,664)@41
ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 2 )
PORT MAP ( xin => expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c(DELAY,659)@37
ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1(REG,437)@41
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid193_rAtanPi_uid13_fpArctanPiTest(COMPARE,192)@42
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q;
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & '0';
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q) & expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin(0);
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b));
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o(14);
--InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest(LOGICAL,157)@37
InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q;
InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a;
--InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest(LOGICAL,158)@37
InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a;
--InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest(LOGICAL,159)@37
InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a;
--exc_R_uid161_rAtanPi_uid13_fpArctanPiTest(LOGICAL,160)@37
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c;
--ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b(DELAY,629)@37
ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest(LOGICAL,141)@37
InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a;
--InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest(LOGICAL,142)@37
InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a;
--InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest(LOGICAL,143)@37
InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a;
--exc_R_uid145_rAtanPi_uid13_fpArctanPiTest(LOGICAL,144)@37
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c;
--ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a(DELAY,628)@37
ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest(LOGICAL,201)@42
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c <= expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c;
--excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest(LOGICAL,200)@37
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q;
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q <= excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a and excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c(DELAY,646)@37
ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest(LOGICAL,199)@37
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q;
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q <= excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a and excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b(DELAY,645)@37
ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest(LOGICAL,198)@37
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q <= excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a and excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a(DELAY,644)@37
ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid203_rAtanPi_uid13_fpArctanPiTest(LOGICAL,202)@42
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q <= excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d;
--expUdf_uid191_rAtanPi_uid13_fpArctanPiTest(COMPARE,190)@42
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q;
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0';
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin(0);
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b));
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o(14);
--excZC3_uid197_rAtanPi_uid13_fpArctanPiTest(LOGICAL,196)@42
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c <= expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c;
--excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest(LOGICAL,195)@37
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q;
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c(DELAY,633)@37
ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest(LOGICAL,194)@37
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b(DELAY,632)@37
ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest(LOGICAL,193)@37
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a(DELAY,631)@37
ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid198_rAtanPi_uid13_fpArctanPiTest(LOGICAL,197)@42
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q <= excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d;
--concExc_uid208_rAtanPi_uid13_fpArctanPiTest(BITJOIN,207)@42
concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q <= ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q & excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q & excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q;
--reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0(REG,439)@42
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid209_rAtanPi_uid13_fpArctanPiTest(LOOKUP,208)@43
excREnc_uid209_rAtanPi_uid13_fpArctanPiTest: PROCESS (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q) IS
WHEN "000" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "01";
WHEN "001" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "010" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "10";
WHEN "011" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "100" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "11";
WHEN "101" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "110" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "111" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN OTHERS =>
excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest(MUX,217)@43
expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q;
expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest: PROCESS (expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q;
WHEN "10" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest(BITSELECT,186)@41
fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q(23 downto 0);
fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b <= fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in(23 downto 1);
--ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d(DELAY,662)@41
ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest(MUX,212)@43
fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q;
fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q;
WHEN "10" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid221_rAtanPi_uid13_fpArctanPiTest(BITJOIN,220)@43
R_uid221_rAtanPi_uid13_fpArctanPiTest_q <= ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q & expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q & fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q;
--xOut(GPOUT,4)@43
q <= R_uid221_rAtanPi_uid13_fpArctanPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_atanpi_s5
-- VHDL created on Tue Mar 12 11:23:23 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_atanpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_atanpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBiasM2_uid6_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal ooPi_uid9_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal piO2_uid46_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0);
signal piO4_uid47_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid64_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal zS_uid67_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q : std_logic_vector (12 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a : std_logic_vector (23 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 : std_logic_vector (50 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr : UNSIGNED (50 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q : std_logic_vector (50 downto 0);
signal fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (9 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (10 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector (23 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 : std_logic_vector (47 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr : UNSIGNED (47 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (47 downto 0);
signal roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_q : std_logic_vector (40 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_b : std_logic_vector (21 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_s1 : std_logic_vector (36 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_pr : SIGNED (37 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_q : std_logic_vector (36 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid299_atanXOXTabGen_lutmem_ia : std_logic_vector (30 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_iq : std_logic_vector (30 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_q : std_logic_vector (30 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid300_atanXOXTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid301_atanXOXTabGen_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid344_invTabGen_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid345_invTabGen_lutmem_ia : std_logic_vector (19 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_iq : std_logic_vector (19 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_q : std_logic_vector (19 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid346_invTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q : std_logic_vector (19 downto 0);
signal reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q : std_logic_vector (21 downto 0);
signal reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q : std_logic_vector (28 downto 0);
signal reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q : std_logic_vector (30 downto 0);
signal reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (26 downto 0);
signal reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (8 downto 0);
signal reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (31 downto 0);
signal reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (32 downto 0);
signal reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (22 downto 0);
signal reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (22 downto 0);
signal reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (22 downto 0);
signal reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (7 downto 0);
signal reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (7 downto 0);
signal reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (22 downto 0);
signal reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (23 downto 0);
signal reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (34 downto 0);
signal reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (11 downto 0);
signal reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q : std_logic_vector (7 downto 0);
signal ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (7 downto 0);
signal ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (8 downto 0);
signal ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (22 downto 0);
signal ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (7 downto 0);
signal ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (20 downto 0);
signal ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (18 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q : std_logic_vector (12 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 : std_logic;
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : signal is true;
signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : signal is true;
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : signal is true;
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_c : std_logic_vector (0 downto 0);
signal excSelBits_uid114_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a : std_logic_vector(33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b : std_logic_vector(33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o : std_logic_vector (33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q : std_logic_vector (33 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o : std_logic_vector (32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0);
signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid15_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid15_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid16_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid16_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal singX_uid17_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal singX_uid17_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q : std_logic_vector (9 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_a : std_logic_vector(26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_b : std_logic_vector(26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_o : std_logic_vector (26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (26 downto 0);
signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (35 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal fracOOPi_uid10_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracOOPi_uid10_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid80_atanX_uid8_fpArctanPiTest_in : std_logic_vector (49 downto 0);
signal normBit_uid80_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in : std_logic_vector (48 downto 0);
signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in : std_logic_vector (47 downto 0);
signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (47 downto 0);
signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (46 downto 0);
signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (45 downto 0);
signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (21 downto 0);
signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (21 downto 0);
signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in : std_logic_vector (36 downto 0);
signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b : std_logic_vector (22 downto 0);
signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal R_uid221_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (14 downto 0);
signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (14 downto 0);
signal R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal constOut_uid54_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal constOut_uid54_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal u_uid58_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal u_uid58_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal R_uid120_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (16 downto 0);
signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (8 downto 0);
signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in : std_logic_vector (8 downto 0);
signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in : std_logic_vector (25 downto 0);
signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (11 downto 0);
signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (9 downto 0);
signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (33 downto 0);
signal fpOOPi_uid11_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (32 downto 0);
signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0);
signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (28 downto 0);
signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (24 downto 0);
signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (0 downto 0);
signal stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal lowRangeB_uid304_atanXOXPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid304_atanXOXPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid305_atanXOXPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid305_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid310_atanXOXPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid310_atanXOXPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid311_atanXOXPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid311_atanXOXPolyEval_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid349_invPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid349_invPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid350_invPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid350_invPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid355_invPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid355_invPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid356_invPolyEval_in : std_logic_vector (22 downto 0);
signal highBBits_uid356_invPolyEval_b : std_logic_vector (20 downto 0);
signal y_uid73_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal y_uid73_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0);
signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal yT1_uid347_invPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid347_invPolyEval_b : std_logic_vector (11 downto 0);
signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal expU_uid59_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expU_uid59_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracU_uid60_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracU_uid60_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0);
signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b : std_logic_vector (3 downto 0);
signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (1 downto 0);
signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (34 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_a : std_logic_vector(31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_b : std_logic_vector(31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_o : std_logic_vector (31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_q : std_logic_vector (31 downto 0);
signal sumAHighB_uid351_invPolyEval_a : std_logic_vector(20 downto 0);
signal sumAHighB_uid351_invPolyEval_b : std_logic_vector(20 downto 0);
signal sumAHighB_uid351_invPolyEval_o : std_logic_vector (20 downto 0);
signal sumAHighB_uid351_invPolyEval_q : std_logic_vector (20 downto 0);
signal sumAHighB_uid357_invPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid357_invPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid357_invPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid357_invPolyEval_q : std_logic_vector (29 downto 0);
signal yAddr_uid75_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0);
signal yAddr_uid75_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in : std_logic_vector (26 downto 0);
signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b : std_logic_vector (17 downto 0);
signal rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0);
signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b : std_logic_vector (4 downto 0);
signal expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0);
signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal s1_uid304_uid307_atanXOXPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid310_uid313_atanXOXPolyEval_q : std_logic_vector (33 downto 0);
signal s1_uid349_uid352_invPolyEval_q : std_logic_vector (21 downto 0);
signal s2_uid355_uid358_invPolyEval_q : std_logic_vector (31 downto 0);
signal yT1_uid302_atanXOXPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid302_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (20 downto 0);
signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (18 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0);
signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0);
signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (25 downto 0);
begin
--xIn(GPIN,3)@0
--cstAllZWF_uid19_atanX_uid8_fpArctanPiTest(CONSTANT,18)
cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000000";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable(LOGICAL,878)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q <= not ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,1008)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a or ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,1004)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100001";
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,1005)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,1006)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,1009)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,1010)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--fracX_uid16_atanX_uid8_fpArctanPiTest(BITSELECT,15)@0
fracX_uid16_atanX_uid8_fpArctanPiTest_in <= a(22 downto 0);
fracX_uid16_atanX_uid8_fpArctanPiTest_b <= fracX_uid16_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--fracXIsZero_uid35_atanX_uid8_fpArctanPiTest(LOGICAL,34)@0
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b else "0";
--InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest(LOGICAL,36)@0
InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q <= not InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a;
--cstAllOWE_uid18_atanX_uid8_fpArctanPiTest(CONSTANT,17)
cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q <= "11111111";
--expX_uid15_atanX_uid8_fpArctanPiTest(BITSELECT,14)@0
expX_uid15_atanX_uid8_fpArctanPiTest_in <= a(30 downto 0);
expX_uid15_atanX_uid8_fpArctanPiTest_b <= expX_uid15_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--expXIsMax_uid33_atanX_uid8_fpArctanPiTest(LOGICAL,32)@0
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a = expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b else "0";
--exc_N_uid38_atanX_uid8_fpArctanPiTest(LOGICAL,37)@0
exc_N_uid38_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q;
exc_N_uid38_atanX_uid8_fpArctanPiTest_b <= InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q;
exc_N_uid38_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_a and exc_N_uid38_atanX_uid8_fpArctanPiTest_b;
--InvExc_N_uid118_atanX_uid8_fpArctanPiTest(LOGICAL,117)@0
InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q;
InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q <= not InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a;
--singX_uid17_atanX_uid8_fpArctanPiTest(BITSELECT,16)@0
singX_uid17_atanX_uid8_fpArctanPiTest_in <= a;
singX_uid17_atanX_uid8_fpArctanPiTest_b <= singX_uid17_atanX_uid8_fpArctanPiTest_in(31 downto 31);
--signR_uid119_atanX_uid8_fpArctanPiTest(LOGICAL,118)@0
signR_uid119_atanX_uid8_fpArctanPiTest_a <= singX_uid17_atanX_uid8_fpArctanPiTest_b;
signR_uid119_atanX_uid8_fpArctanPiTest_b <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q;
signR_uid119_atanX_uid8_fpArctanPiTest_q <= signR_uid119_atanX_uid8_fpArctanPiTest_a and signR_uid119_atanX_uid8_fpArctanPiTest_b;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,998)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid119_atanX_uid8_fpArctanPiTest_q, xout => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,1000)
-- every=1, low=0, high=33, step=1, init=1
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 32 THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 33;
ELSE
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6));
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,1001)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,1002)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,999)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 34,
width_b => 1,
widthad_b => 6,
numwords_b => 34,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,879)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a or ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,875)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100000";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,876)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,877)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,880)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,881)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,869)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => singX_uid17_atanX_uid8_fpArctanPiTest_b, xout => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,871)
-- every=1, low=0, high=32, step=1, init=1
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 31 THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 32;
ELSE
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6));
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,872)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,873)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,870)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--cstBias_uid22_atanX_uid8_fpArctanPiTest(CONSTANT,21)
cstBias_uid22_atanX_uid8_fpArctanPiTest_q <= "01111111";
--piO2_uid46_atanX_uid8_fpArctanPiTest(CONSTANT,45)
piO2_uid46_atanX_uid8_fpArctanPiTest_q <= "11001001000011111101101011";
--cstPiO2_uid48_atanX_uid8_fpArctanPiTest(BITSELECT,47)@35
cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in <= piO2_uid46_atanX_uid8_fpArctanPiTest_q(24 downto 0);
cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b <= cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in(24 downto 2);
--fpPiO2C_uid49_atanX_uid8_fpArctanPiTest(BITJOIN,48)@35
fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBias_uid22_atanX_uid8_fpArctanPiTest_q & cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b;
--cstBiasM1_uid23_atanX_uid8_fpArctanPiTest(CONSTANT,22)
cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q <= "01111110";
--piO4_uid47_atanX_uid8_fpArctanPiTest(CONSTANT,46)
piO4_uid47_atanX_uid8_fpArctanPiTest_q <= "110010010000111111011011";
--cstPiO4_uid51_atanX_uid8_fpArctanPiTest(BITSELECT,50)@35
cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in <= piO4_uid47_atanX_uid8_fpArctanPiTest_q(22 downto 0);
cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b <= cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--fpPiO4C_uid52_atanX_uid8_fpArctanPiTest(BITJOIN,51)@35
fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q & cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,892)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a or ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b);
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,893)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,894)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b;
--exc_I_uid36_atanX_uid8_fpArctanPiTest(LOGICAL,35)@0
exc_I_uid36_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q;
exc_I_uid36_atanX_uid8_fpArctanPiTest_b <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
exc_I_uid36_atanX_uid8_fpArctanPiTest_q <= exc_I_uid36_atanX_uid8_fpArctanPiTest_a and exc_I_uid36_atanX_uid8_fpArctanPiTest_b;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,882)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid36_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,883)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq,
address_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa,
data_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia
);
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(0 downto 0);
--constOut_uid54_atanX_uid8_fpArctanPiTest(MUX,53)@35
constOut_uid54_atanX_uid8_fpArctanPiTest_s <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q;
constOut_uid54_atanX_uid8_fpArctanPiTest: PROCESS (constOut_uid54_atanX_uid8_fpArctanPiTest_s, en, fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q, fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE constOut_uid54_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expOutCst_uid112_atanX_uid8_fpArctanPiTest(BITSELECT,111)@35
expOutCst_uid112_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expOutCst_uid112_atanX_uid8_fpArctanPiTest_b <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5(REG,428)@35
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--cst01pWShift_uid69_atanX_uid8_fpArctanPiTest(CONSTANT,68)
cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q <= "0000000000000";
--reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2(REG,389)@0
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= signR_uid119_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c(DELAY,707)@1
ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,1022)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a or ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b);
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top(CONSTANT,1018)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q <= "0111";
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp(LOGICAL,1019)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q);
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q <= "1" when ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a = ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b else "0";
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg(REG,1020)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,1023)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,1024)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b;
--cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,230)
cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111110";
--expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest(SUB,259)@0
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q);
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b);
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b));
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,260)@0
expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0);
expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,229)
cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111101";
--expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest(SUB,256)@0
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q);
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b);
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b));
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,257)@0
expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0);
expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,249)@0
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b else "0";
--expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest(MUX,263)@0
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s <= fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q;
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--expXIsZero_uid31_atanX_uid8_fpArctanPiTest(LOGICAL,30)@0
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a = expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b else "0";
--udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,258)@0
udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in <= STD_LOGIC_VECTOR((9 downto 9 => expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(8)) & expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q);
udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in(9 downto 9);
--InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,245)@0
InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a;
--InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,246)@0
InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a <= expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q;
InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a;
--exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,247)@0
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a <= InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b <= InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c;
--xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,264)@0
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q;
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b;
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a and xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b;
--xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,265)@0
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q;
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q <= xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a or xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b;
--excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,266)@0
excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q & expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q & xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q;
--reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0(REG,378)@0
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest(LOOKUP,267)@1
outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest(MUX,269)@1
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q;
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,1012)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt(COUNTER,1014)
-- every=1, low=0, high=7, step=1, init=1
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg(REG,1015)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux(MUX,1016)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,1013)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia
);
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid20_atanX_uid8_fpArctanPiTest(CONSTANT,19)
cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000001";
--oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,248)@0
oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q <= VCC_q & fracX_uid16_atanX_uid8_fpArctanPiTest_b;
--y_uid251_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,250)@0
y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in <= oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q(22 downto 0);
y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,252)@0
yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b;
yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 15);
--reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0(REG,379)@0
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid346_invTabGen_lutmem(DUALMEM,376)@1
memoryC2_uid346_invTabGen_lutmem_ia <= (others => '0');
memoryC2_uid346_invTabGen_lutmem_aa <= (others => '0');
memoryC2_uid346_invTabGen_lutmem_ab <= reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q;
memoryC2_uid346_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC2_uid346_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid346_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid346_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid346_invTabGen_lutmem_iq,
address_a => memoryC2_uid346_invTabGen_lutmem_aa,
data_a => memoryC2_uid346_invTabGen_lutmem_ia
);
memoryC2_uid346_invTabGen_lutmem_reset0 <= areset;
memoryC2_uid346_invTabGen_lutmem_q <= memoryC2_uid346_invTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1(REG,381)@3
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= memoryC2_uid346_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,1011)
ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a(DELAY,680)@0
ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,253)@3
yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in <= ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q(14 downto 0);
yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in(14 downto 0);
--yT1_uid347_invPolyEval(BITSELECT,346)@3
yT1_uid347_invPolyEval_in <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b;
yT1_uid347_invPolyEval_b <= yT1_uid347_invPolyEval_in(14 downto 3);
--reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0(REG,380)@3
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= yT1_uid347_invPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid366_pT1_uid348_invPolyEval(MULT,365)@4
prodXY_uid366_pT1_uid348_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid366_pT1_uid348_invPolyEval_a),13)) * SIGNED(prodXY_uid366_pT1_uid348_invPolyEval_b);
prodXY_uid366_pT1_uid348_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid366_pT1_uid348_invPolyEval_a <= (others => '0');
prodXY_uid366_pT1_uid348_invPolyEval_b <= (others => '0');
prodXY_uid366_pT1_uid348_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid366_pT1_uid348_invPolyEval_a <= reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q;
prodXY_uid366_pT1_uid348_invPolyEval_b <= reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q;
prodXY_uid366_pT1_uid348_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid366_pT1_uid348_invPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid366_pT1_uid348_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid366_pT1_uid348_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid366_pT1_uid348_invPolyEval_q <= prodXY_uid366_pT1_uid348_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid367_pT1_uid348_invPolyEval(BITSELECT,366)@7
prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in <= prodXY_uid366_pT1_uid348_invPolyEval_q;
prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in(23 downto 11);
--highBBits_uid350_invPolyEval(BITSELECT,349)@7
highBBits_uid350_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b;
highBBits_uid350_invPolyEval_b <= highBBits_uid350_invPolyEval_in(12 downto 1);
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a(DELAY,804)@1
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid345_invTabGen_lutmem(DUALMEM,375)@4
memoryC1_uid345_invTabGen_lutmem_ia <= (others => '0');
memoryC1_uid345_invTabGen_lutmem_aa <= (others => '0');
memoryC1_uid345_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q;
memoryC1_uid345_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 20,
widthad_a => 8,
numwords_a => 256,
width_b => 20,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC1_uid345_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid345_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid345_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid345_invTabGen_lutmem_iq,
address_a => memoryC1_uid345_invTabGen_lutmem_aa,
data_a => memoryC1_uid345_invTabGen_lutmem_ia
);
memoryC1_uid345_invTabGen_lutmem_reset0 <= areset;
memoryC1_uid345_invTabGen_lutmem_q <= memoryC1_uid345_invTabGen_lutmem_iq(19 downto 0);
--reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0(REG,383)@6
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= "00000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= memoryC1_uid345_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid351_invPolyEval(ADD,350)@7
sumAHighB_uid351_invPolyEval_a <= STD_LOGIC_VECTOR((20 downto 20 => reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q(19)) & reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q);
sumAHighB_uid351_invPolyEval_b <= STD_LOGIC_VECTOR((20 downto 12 => highBBits_uid350_invPolyEval_b(11)) & highBBits_uid350_invPolyEval_b);
sumAHighB_uid351_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid351_invPolyEval_a) + SIGNED(sumAHighB_uid351_invPolyEval_b));
sumAHighB_uid351_invPolyEval_q <= sumAHighB_uid351_invPolyEval_o(20 downto 0);
--lowRangeB_uid349_invPolyEval(BITSELECT,348)@7
lowRangeB_uid349_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b(0 downto 0);
lowRangeB_uid349_invPolyEval_b <= lowRangeB_uid349_invPolyEval_in(0 downto 0);
--s1_uid349_uid352_invPolyEval(BITJOIN,351)@7
s1_uid349_uid352_invPolyEval_q <= sumAHighB_uid351_invPolyEval_q & lowRangeB_uid349_invPolyEval_b;
--reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1(REG,385)@7
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= "0000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= s1_uid349_uid352_invPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor(LOGICAL,1059)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a or ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b);
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg(REG,966)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena(REG,1060)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q = "1") THEN
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd(LOGICAL,1061)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b <= en;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg(DELAY,1051)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt(COUNTER,962)
-- every=1, low=0, high=1, step=1, init=1
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i,1));
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg(REG,963)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux(MUX,964)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s <= en;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux: PROCESS (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q)
BEGIN
CASE ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s IS
WHEN "0" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
WHEN "1" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q;
WHEN OTHERS => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem(DUALMEM,1052)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia
);
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0(REG,384)@7
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid369_pT2_uid354_invPolyEval(MULT,368)@8
prodXY_uid369_pT2_uid354_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid369_pT2_uid354_invPolyEval_a),16)) * SIGNED(prodXY_uid369_pT2_uid354_invPolyEval_b);
prodXY_uid369_pT2_uid354_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid369_pT2_uid354_invPolyEval_a <= (others => '0');
prodXY_uid369_pT2_uid354_invPolyEval_b <= (others => '0');
prodXY_uid369_pT2_uid354_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid369_pT2_uid354_invPolyEval_a <= reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q;
prodXY_uid369_pT2_uid354_invPolyEval_b <= reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q;
prodXY_uid369_pT2_uid354_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid369_pT2_uid354_invPolyEval_pr,37));
END IF;
END IF;
END PROCESS;
prodXY_uid369_pT2_uid354_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid369_pT2_uid354_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid369_pT2_uid354_invPolyEval_q <= prodXY_uid369_pT2_uid354_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid370_pT2_uid354_invPolyEval(BITSELECT,369)@11
prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in <= prodXY_uid369_pT2_uid354_invPolyEval_q;
prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in(36 downto 14);
--highBBits_uid356_invPolyEval(BITSELECT,355)@11
highBBits_uid356_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b;
highBBits_uid356_invPolyEval_b <= highBBits_uid356_invPolyEval_in(22 downto 2);
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor(LOGICAL,1048)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q <= not (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a or ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b);
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top(CONSTANT,1031)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q <= "0100";
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp(LOGICAL,1032)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q <= "1" when ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a = ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b else "0";
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg(REG,1033)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena(REG,1049)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd(LOGICAL,1050)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a and ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg(DELAY,1038)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt(COUNTER,1027)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i,3));
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg(REG,1028)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux(MUX,1029)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s <= en;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux: PROCESS (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem(DUALMEM,1039)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq(7 downto 0);
--memoryC0_uid344_invTabGen_lutmem(DUALMEM,374)@8
memoryC0_uid344_invTabGen_lutmem_ia <= (others => '0');
memoryC0_uid344_invTabGen_lutmem_aa <= (others => '0');
memoryC0_uid344_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q;
memoryC0_uid344_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC0_uid344_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid344_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid344_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid344_invTabGen_lutmem_iq,
address_a => memoryC0_uid344_invTabGen_lutmem_aa,
data_a => memoryC0_uid344_invTabGen_lutmem_ia
);
memoryC0_uid344_invTabGen_lutmem_reset0 <= areset;
memoryC0_uid344_invTabGen_lutmem_q <= memoryC0_uid344_invTabGen_lutmem_iq(28 downto 0);
--reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0(REG,387)@10
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= "00000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= memoryC0_uid344_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid357_invPolyEval(ADD,356)@11
sumAHighB_uid357_invPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q(28)) & reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q);
sumAHighB_uid357_invPolyEval_b <= STD_LOGIC_VECTOR((29 downto 21 => highBBits_uid356_invPolyEval_b(20)) & highBBits_uid356_invPolyEval_b);
sumAHighB_uid357_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid357_invPolyEval_a) + SIGNED(sumAHighB_uid357_invPolyEval_b));
sumAHighB_uid357_invPolyEval_q <= sumAHighB_uid357_invPolyEval_o(29 downto 0);
--lowRangeB_uid355_invPolyEval(BITSELECT,354)@11
lowRangeB_uid355_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b(1 downto 0);
lowRangeB_uid355_invPolyEval_b <= lowRangeB_uid355_invPolyEval_in(1 downto 0);
--s2_uid355_uid358_invPolyEval(BITJOIN,357)@11
s2_uid355_uid358_invPolyEval_q <= sumAHighB_uid357_invPolyEval_q & lowRangeB_uid355_invPolyEval_b;
--fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,255)@11
fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in <= s2_uid355_uid358_invPolyEval_q(28 downto 0);
fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in(28 downto 5);
--fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,261)@11
fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b(22 downto 0);
fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,688)@0
ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest(MUX,262)@11
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q;
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1(REG,388)@1
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,701)@2
ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 10 )
PORT MAP ( xin => reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest(MUX,268)@12
fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q;
fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid273_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,272)@12
R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q <= ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q & fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,905)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a or ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,901)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "01001";
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,902)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,903)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,906)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,907)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,895)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,897)
-- every=1, low=0, high=9, step=1, init=1
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 8 THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 9;
ELSE
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,4));
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,898)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,899)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,896)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 4,
numwords_a => 10,
width_b => 32,
widthad_b => 4,
numwords_b => 10,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(31 downto 0);
--path2_uid56_atanX_uid8_fpArctanPiTest(COMPARE,55)@0
path2_uid56_atanX_uid8_fpArctanPiTest_cin <= GND_q;
path2_uid56_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid15_atanX_uid8_fpArctanPiTest_b) & '0';
path2_uid56_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q) & path2_uid56_atanX_uid8_fpArctanPiTest_cin(0);
path2_uid56_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_b));
path2_uid56_atanX_uid8_fpArctanPiTest_n(0) <= not path2_uid56_atanX_uid8_fpArctanPiTest_o(10);
--reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1(REG,390)@0
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= path2_uid56_atanX_uid8_fpArctanPiTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b(DELAY,466)@1
ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--u_uid58_atanX_uid8_fpArctanPiTest(MUX,57)@12
u_uid58_atanX_uid8_fpArctanPiTest_s <= ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q;
u_uid58_atanX_uid8_fpArctanPiTest: PROCESS (u_uid58_atanX_uid8_fpArctanPiTest_s, en, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q, R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE u_uid58_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => u_uid58_atanX_uid8_fpArctanPiTest_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q;
WHEN "1" => u_uid58_atanX_uid8_fpArctanPiTest_q <= R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => u_uid58_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracU_uid60_atanX_uid8_fpArctanPiTest(BITSELECT,59)@12
fracU_uid60_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracU_uid60_atanX_uid8_fpArctanPiTest_b <= fracU_uid60_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a(DELAY,471)@12
ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracU_uid60_atanX_uid8_fpArctanPiTest_b, xout => ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest(BITJOIN,60)@13
oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q;
--oFracUExt_uid70_atanX_uid8_fpArctanPiTest(BITJOIN,69)@13
oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q <= cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q & oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q;
--X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,282)@13
X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(24 downto 0);
X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(24 downto 0);
--leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,281)
leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000000000000";
--leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,283)@13
leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5(REG,399)@13
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,279)@13
X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(28 downto 0);
X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(28 downto 0);
--leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,280)@13
leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4(REG,398)@13
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,276)@13
X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(32 downto 0);
X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(32 downto 0);
--leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,275)
leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "0000";
--leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,277)@13
leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3(REG,397)@13
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,396)@13
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--zS_uid67_atanX_uid8_fpArctanPiTest(CONSTANT,66)
zS_uid67_atanX_uid8_fpArctanPiTest_q <= "000000000";
--shiftBias_uid64_atanX_uid8_fpArctanPiTest(CONSTANT,63)
shiftBias_uid64_atanX_uid8_fpArctanPiTest_q <= "01110010";
--expU_uid59_atanX_uid8_fpArctanPiTest(BITSELECT,58)@12
expU_uid59_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expU_uid59_atanX_uid8_fpArctanPiTest_b <= expU_uid59_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1(REG,391)@12
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= expU_uid59_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--shiftValue_uid65_atanX_uid8_fpArctanPiTest(SUB,64)@13
shiftValue_uid65_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q);
shiftValue_uid65_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid64_atanX_uid8_fpArctanPiTest_q);
shiftValue_uid65_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_b));
shiftValue_uid65_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--ShiftValue8_uid66_atanX_uid8_fpArctanPiTest(BITSELECT,65)@13
ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q;
ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in(8 downto 8);
--shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest(MUX,67)@13
shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b;
shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest: PROCESS (shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s, en, shiftValue_uid65_atanX_uid8_fpArctanPiTest_q, zS_uid67_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= zS_uid67_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest(BITSELECT,70)@13
fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in <= shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q(3 downto 0);
fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,284)@13
leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b;
leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,395)@13
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,285)@14
leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q;
leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q, reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q, reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q;
WHEN "11" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,293)@14
LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(33 downto 0);
LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(33 downto 0);
--ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,725)@14
ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,292)
leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000";
--leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,294)@15
leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,290)@14
LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(34 downto 0);
LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(34 downto 0);
--ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,723)@14
ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,289)
leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "00";
--leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,291)@15
leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,287)@14
LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0);
LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(35 downto 0);
--ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,721)@14
ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,288)@15
leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & GND_q;
--reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,401)@14
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,295)@13
leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a(DELAY,829)@13
ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,400)@14
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,296)@15
leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q;
leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid73_atanX_uid8_fpArctanPiTest(BITSELECT,72)@15
y_uid73_atanX_uid8_fpArctanPiTest_in <= leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0);
y_uid73_atanX_uid8_fpArctanPiTest_b <= y_uid73_atanX_uid8_fpArctanPiTest_in(35 downto 1);
--yAddr_uid75_atanX_uid8_fpArctanPiTest(BITSELECT,74)@15
yAddr_uid75_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b;
yAddr_uid75_atanX_uid8_fpArctanPiTest_b <= yAddr_uid75_atanX_uid8_fpArctanPiTest_in(34 downto 27);
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0(REG,402)@15
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= yAddr_uid75_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid301_atanXOXTabGen_lutmem(DUALMEM,373)@16
memoryC2_uid301_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC2_uid301_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC2_uid301_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q;
memoryC2_uid301_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC2_uid301_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid301_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid301_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid301_atanXOXTabGen_lutmem_iq,
address_a => memoryC2_uid301_atanXOXTabGen_lutmem_aa,
data_a => memoryC2_uid301_atanXOXTabGen_lutmem_ia
);
memoryC2_uid301_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC2_uid301_atanXOXTabGen_lutmem_q <= memoryC2_uid301_atanXOXTabGen_lutmem_iq(12 downto 0);
--reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1(REG,404)@18
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= memoryC2_uid301_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--yPPolyEval_uid76_atanX_uid8_fpArctanPiTest(BITSELECT,75)@15
yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b(26 downto 0);
yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in(26 downto 9);
--yT1_uid302_atanXOXPolyEval(BITSELECT,301)@15
yT1_uid302_atanXOXPolyEval_in <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b;
yT1_uid302_atanXOXPolyEval_b <= yT1_uid302_atanXOXPolyEval_in(17 downto 5);
--ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg(DELAY,1062)
ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid302_atanXOXPolyEval_b, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a(DELAY,832)@15
ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0(REG,403)@18
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid360_pT1_uid303_atanXOXPolyEval(MULT,359)@19
prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_a),14)) * SIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_b);
prodXY_uid360_pT1_uid303_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= (others => '0');
prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= (others => '0');
prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q;
prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q;
prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid360_pT1_uid303_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval(BITSELECT,360)@22
prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_q;
prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in(25 downto 12);
--highBBits_uid305_atanXOXPolyEval(BITSELECT,304)@22
highBBits_uid305_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b;
highBBits_uid305_atanXOXPolyEval_b <= highBBits_uid305_atanXOXPolyEval_in(13 downto 1);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a(DELAY,834)@15
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0(REG,405)@18
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid300_atanXOXTabGen_lutmem(DUALMEM,372)@19
memoryC1_uid300_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC1_uid300_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC1_uid300_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q;
memoryC1_uid300_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC1_uid300_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid300_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid300_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid300_atanXOXTabGen_lutmem_iq,
address_a => memoryC1_uid300_atanXOXTabGen_lutmem_aa,
data_a => memoryC1_uid300_atanXOXTabGen_lutmem_ia
);
memoryC1_uid300_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC1_uid300_atanXOXTabGen_lutmem_q <= memoryC1_uid300_atanXOXTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0(REG,406)@21
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= memoryC1_uid300_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid306_atanXOXPolyEval(ADD,305)@22
sumAHighB_uid306_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q(20)) & reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q);
sumAHighB_uid306_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid305_atanXOXPolyEval_b(12)) & highBBits_uid305_atanXOXPolyEval_b);
sumAHighB_uid306_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid306_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid306_atanXOXPolyEval_b));
sumAHighB_uid306_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_o(21 downto 0);
--lowRangeB_uid304_atanXOXPolyEval(BITSELECT,303)@22
lowRangeB_uid304_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b(0 downto 0);
lowRangeB_uid304_atanXOXPolyEval_b <= lowRangeB_uid304_atanXOXPolyEval_in(0 downto 0);
--s1_uid304_uid307_atanXOXPolyEval(BITJOIN,306)@22
s1_uid304_uid307_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_q & lowRangeB_uid304_atanXOXPolyEval_b;
--reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1(REG,408)@22
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= s1_uid304_uid307_atanXOXPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor(LOGICAL,1035)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q <= not (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a or ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b);
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena(REG,1036)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd(LOGICAL,1037)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b <= en;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a and ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b;
--reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0(REG,407)@15
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg(DELAY,1025)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q, xout => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem(DUALMEM,1026)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq,
address_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa,
data_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia
);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid363_pT2_uid309_atanXOXPolyEval(MULT,362)@23
prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_a),19)) * SIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_b);
prodXY_uid363_pT2_uid309_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= (others => '0');
prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= (others => '0');
prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q;
prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q;
prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid363_pT2_uid309_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval(BITSELECT,363)@26
prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_q;
prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in(40 downto 17);
--highBBits_uid311_atanXOXPolyEval(BITSELECT,310)@26
highBBits_uid311_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b;
highBBits_uid311_atanXOXPolyEval_b <= highBBits_uid311_atanXOXPolyEval_in(23 downto 2);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor(LOGICAL,1073)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q <= not (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a or ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena(REG,1074)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q = "1") THEN
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd(LOGICAL,1075)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b <= en;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a and ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b;
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg(DELAY,1063)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem(DUALMEM,1064)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia
);
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0(REG,409)@22
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid299_atanXOXTabGen_lutmem(DUALMEM,371)@23
memoryC0_uid299_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC0_uid299_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC0_uid299_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q;
memoryC0_uid299_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 31,
widthad_a => 8,
numwords_a => 256,
width_b => 31,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC0_uid299_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid299_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid299_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid299_atanXOXTabGen_lutmem_iq,
address_a => memoryC0_uid299_atanXOXTabGen_lutmem_aa,
data_a => memoryC0_uid299_atanXOXTabGen_lutmem_ia
);
memoryC0_uid299_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC0_uid299_atanXOXTabGen_lutmem_q <= memoryC0_uid299_atanXOXTabGen_lutmem_iq(30 downto 0);
--reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0(REG,410)@25
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= memoryC0_uid299_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid312_atanXOXPolyEval(ADD,311)@26
sumAHighB_uid312_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((31 downto 31 => reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q(30)) & reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q);
sumAHighB_uid312_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((31 downto 22 => highBBits_uid311_atanXOXPolyEval_b(21)) & highBBits_uid311_atanXOXPolyEval_b);
sumAHighB_uid312_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid312_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid312_atanXOXPolyEval_b));
sumAHighB_uid312_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_o(31 downto 0);
--lowRangeB_uid310_atanXOXPolyEval(BITSELECT,309)@26
lowRangeB_uid310_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b(1 downto 0);
lowRangeB_uid310_atanXOXPolyEval_b <= lowRangeB_uid310_atanXOXPolyEval_in(1 downto 0);
--s2_uid310_uid313_atanXOXPolyEval(BITJOIN,312)@26
s2_uid310_uid313_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_q & lowRangeB_uid310_atanXOXPolyEval_b;
--fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest(BITSELECT,77)@26
fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in <= s2_uid310_uid313_atanXOXPolyEval_q(31 downto 0);
fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in(31 downto 5);
--reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1(REG,412)@26
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,918)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,914)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01010";
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,915)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,916)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,919)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,920)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0(REG,411)@13
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,908)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,910)
-- every=1, low=0, high=10, step=1, init=1
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 9 THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 10;
ELSE
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4));
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,911)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,912)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,909)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 11,
width_b => 24,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(23 downto 0);
--mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest(MULT,78)@27
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr <= UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a) * UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b);
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= (others => '0');
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= (others => '0');
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr);
END IF;
END IF;
END PROCESS;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid80_atanX_uid8_fpArctanPiTest(BITSELECT,79)@30
normBit_uid80_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(49 downto 0);
normBit_uid80_atanX_uid8_fpArctanPiTest_b <= normBit_uid80_atanX_uid8_fpArctanPiTest_in(49 downto 49);
--InvNormBit_uid84_atanX_uid8_fpArctanPiTest(LOGICAL,83)@30
InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a <= normBit_uid80_atanX_uid8_fpArctanPiTest_b;
InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q <= not InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,931)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,927)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01111";
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,928)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,929)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,932)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,933)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,921)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expU_uid59_atanX_uid8_fpArctanPiTest_b, xout => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,923)
-- every=1, low=0, high=15, step=1, init=1
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4));
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,924)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,925)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,922)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 16,
width_b => 8,
widthad_b => 4,
numwords_b => 16,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(7 downto 0);
--expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest(SUB,84)@30
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q);
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000" & InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q);
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b));
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--fracRPath3High_uid81_atanX_uid8_fpArctanPiTest(BITSELECT,80)@30
fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(48 downto 0);
fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in(48 downto 25);
--fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest(BITSELECT,81)@30
fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(47 downto 0);
fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in(47 downto 24);
--fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest(MUX,82)@30
fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s <= normBit_uid80_atanX_uid8_fpArctanPiTest_b;
fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s, en, fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b, fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b)
BEGIN
CASE fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest(BITJOIN,85)@30
expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q & fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q;
--reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0(REG,420)@30
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest(ADD,86)@31
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q);
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000" & VCC_q);
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b));
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o(33 downto 0);
--expRPath3_uid89_atanX_uid8_fpArctanPiTest(BITSELECT,88)@31
expRPath3_uid89_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(31 downto 0);
expRPath3_uid89_atanX_uid8_fpArctanPiTest_b <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_in(31 downto 24);
--reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4(REG,427)@31
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,971)
ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e(DELAY,534)@32
ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,337)@33
RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 1);
--rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,339)@33
rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= GND_q & RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,333)
rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000";
--rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,322)
rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000000000000000000000";
--X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,321)@32
X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 24);
--rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,323)@32
rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,319)
rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "0000000000000000";
--X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,318)@32
X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 16);
--rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,320)@32
rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,315)@32
X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 8);
--rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,317)@32
rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q & X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a(DELAY,504)@30
ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q, xout => ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest(BITJOIN,93)@32
oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q;
--cstWFP2_uid25_atanX_uid8_fpArctanPiTest(CONSTANT,24)
cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q <= "00011001";
--reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1(REG,413)@30
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest(SUB,89)@31
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q);
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR((10 downto 9 => reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q(8)) & reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q);
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a) - SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b));
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o(9 downto 0);
--shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest(BITSELECT,91)@31
shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q(7 downto 0);
shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest(CONSTANT,23)
cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q <= "01101000";
--shiftOut_uid91_atanX_uid8_fpArctanPiTest(COMPARE,90)@13
shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin <= GND_q;
shiftOut_uid91_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & '0';
shiftOut_uid91_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q) & shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin(0);
shiftOut_uid91_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_b));
shiftOut_uid91_atanX_uid8_fpArctanPiTest_c(0) <= shiftOut_uid91_atanX_uid8_fpArctanPiTest_o(10);
--ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b(DELAY,502)@13
ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => shiftOut_uid91_atanX_uid8_fpArctanPiTest_c, xout => ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--sValPostSOut_uid93_atanX_uid8_fpArctanPiTest(MUX,92)@31
sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s <= ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q;
sValPostSOut_uid93_atanX_uid8_fpArctanPiTest: PROCESS (sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s, en, shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b, cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest(BITSELECT,94)@31
sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in <= sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q(4 downto 0);
sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,324)@31
rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b;
rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,414)@31
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,325)@32
rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q;
rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,332)@32
RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 6);
--ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,762)@32
ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,334)@33
rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,329)@32
RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 4);
--ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,760)@32
ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 21, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,331)@33
rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,326)@32
RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 2);
--ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,758)@32
ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,328)@33
rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2(REG,416)@32
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,335)@31
rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(2 downto 1);
--ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a(DELAY,844)@31
ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,415)@32
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,336)@33
rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q;
rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q, rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,340)@31
rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,417)@31
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b(DELAY,772)@32
ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,341)@33
rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q;
rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest(BITJOIN,96)@33
pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & GND_q;
--reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1(REG,418)@33
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--path2Diff_uid97_atanX_uid8_fpArctanPiTest(SUB,97)@34
path2Diff_uid97_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & piO2_uid46_atanX_uid8_fpArctanPiTest_q);
path2Diff_uid97_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q);
path2Diff_uid97_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_b));
path2Diff_uid97_atanX_uid8_fpArctanPiTest_q <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_o(26 downto 0);
--normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest(BITSELECT,98)@34
normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(25 downto 0);
normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in(25 downto 25);
--expRPath2_uid103_atanX_uid8_fpArctanPiTest(MUX,102)@34
expRPath2_uid103_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b;
expRPath2_uid103_atanX_uid8_fpArctanPiTest: PROCESS (expRPath2_uid103_atanX_uid8_fpArctanPiTest_s, en, cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q, cstBias_uid22_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPath2_uid103_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest(BITSELECT,99)@34
path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(24 downto 0);
path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in(24 downto 1);
--path2DiffLow_uid101_atanX_uid8_fpArctanPiTest(BITSELECT,100)@34
path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(23 downto 0);
path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in(23 downto 0);
--fracRPath2_uid102_atanX_uid8_fpArctanPiTest(MUX,101)@34
fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b;
fracRPath2_uid102_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s, en, path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b, path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b)
BEGIN
CASE fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest(BITJOIN,103)@34
expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q <= expRPath2_uid103_atanX_uid8_fpArctanPiTest_q & fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q;
--reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0(REG,419)@34
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest(ADD,104)@35
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q);
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000" & VCC_q);
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b));
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o(32 downto 0);
--expRPath2_uid107_atanX_uid8_fpArctanPiTest(BITSELECT,106)@35
expRPath2_uid107_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(31 downto 0);
expRPath2_uid107_atanX_uid8_fpArctanPiTest_b <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_in(31 downto 24);
--reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3(REG,426)@35
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor(LOGICAL,1086)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q <= not (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a or ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b);
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena(REG,1087)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q = "1") THEN
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd(LOGICAL,1088)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b <= en;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a and ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg(DELAY,1076)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid15_atanX_uid8_fpArctanPiTest_b, xout => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem(DUALMEM,1077)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 33,
width_b => 8,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq,
address_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa,
data_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia
);
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 <= areset;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq(7 downto 0);
--reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2(REG,425)@35
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,944)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,940)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "010010";
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,941)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,942)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,945)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,946)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--expXIsBias_uid44_atanX_uid8_fpArctanPiTest(LOGICAL,43)@0
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q;
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a = expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b else "0";
--inIsOne_uid45_atanX_uid8_fpArctanPiTest(LOGICAL,44)@0
inIsOne_uid45_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
inIsOne_uid45_atanX_uid8_fpArctanPiTest_b <= expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q;
inIsOne_uid45_atanX_uid8_fpArctanPiTest_q <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_a and inIsOne_uid45_atanX_uid8_fpArctanPiTest_b;
--arctanIsConst_uid55_atanX_uid8_fpArctanPiTest(LOGICAL,54)@0
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_q;
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a or arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c(DELAY,522)@1
ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q, xout => ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasMwShift_uid62_atanX_uid8_fpArctanPiTest(CONSTANT,61)
biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q <= "01110011";
--atanUIsU_uid63_atanX_uid8_fpArctanPiTest(COMPARE,62)@13
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin <= GND_q;
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q) & '0';
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin(0);
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b));
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n(0) <= not atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o(10);
--ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a(DELAY,520)@0
ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => path2_uid56_atanX_uid8_fpArctanPiTest_n, xout => ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--pathSelBits_uid108_atanX_uid8_fpArctanPiTest(BITJOIN,107)@13
pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q <= ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n & ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q;
--reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0(REG,392)@13
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,934)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,936)
-- every=1, low=0, high=18, step=1, init=1
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 17 THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 18;
ELSE
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,5));
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,937)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,938)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,935)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 19,
width_b => 3,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(2 downto 0);
--fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest(LOOKUP,108)@35
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q) IS
WHEN "000" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "001" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "010" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "011" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "110" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "111" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN OTHERS =>
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRCalc_uid113_atanX_uid8_fpArctanPiTest(MUX,112)@36
expRCalc_uid113_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q;
expRCalc_uid113_atanX_uid8_fpArctanPiTest: PROCESS (expRCalc_uid113_atanX_uid8_fpArctanPiTest_s, en, reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q, reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q, ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE expRCalc_uid113_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q;
WHEN "11" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstAllZWE_uid21_atanX_uid8_fpArctanPiTest(CONSTANT,20)
cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q <= "00000000";
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,995)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a or ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,996)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,997)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,985)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid38_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,986)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,982)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,983)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,984)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,972)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q, xout => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,973)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(0 downto 0);
--excSelBits_uid114_atanX_uid8_fpArctanPiTest(BITJOIN,113)@35
excSelBits_uid114_atanX_uid8_fpArctanPiTest_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q & GND_q & ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q;
--reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0(REG,377)@35
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid114_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest(LOOKUP,114)@36
outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid117_atanX_uid8_fpArctanPiTest(MUX,116)@36
expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q;
expRPostExc_uid117_atanX_uid8_fpArctanPiTest: PROCESS (expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, expRCalc_uid113_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid113_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracOutCst_uid110_atanX_uid8_fpArctanPiTest(BITSELECT,109)@35
fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5(REG,424)@35
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor(LOGICAL,968)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q <= not (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a or ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b);
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena(REG,969)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd(LOGICAL,970)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b <= en;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a and ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b;
--fracRPath3_uid88_atanX_uid8_fpArctanPiTest(BITSELECT,87)@31
fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(23 downto 0);
fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in(23 downto 1);
--reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4(REG,423)@31
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,960)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem(DUALMEM,961)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 1,
numwords_a => 2,
width_b => 23,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq,
address_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa,
data_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia
);
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 <= areset;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq(22 downto 0);
--fracRPath2_uid106_atanX_uid8_fpArctanPiTest(BITSELECT,105)@35
fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(23 downto 0);
fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in(23 downto 1);
--reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3(REG,422)@35
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,957)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a or ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,958)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,959)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2(REG,421)@0
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,947)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,948)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 33,
width_b => 23,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(22 downto 0);
--fracRCalc_uid111_atanX_uid8_fpArctanPiTest(MUX,110)@36
fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q;
fracRCalc_uid111_atanX_uid8_fpArctanPiTest: PROCESS (fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s, en, ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q, reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q, reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q;
WHEN "01" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q;
WHEN "11" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid116_atanX_uid8_fpArctanPiTest(MUX,115)@36
fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q;
fracRPostExc_uid116_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid120_atanX_uid8_fpArctanPiTest(BITJOIN,119)@36
R_uid120_atanX_uid8_fpArctanPiTest_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q & expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q & fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q;
--fracX_uid126_rAtanPi_uid13_fpArctanPiTest(BITSELECT,125)@36
fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0);
--reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1(REG,431)@36
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest(LOGICAL,137)@37
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a <= reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q;
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b else "0";
--expX_uid122_rAtanPi_uid13_fpArctanPiTest(BITSELECT,121)@36
expX_uid122_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expX_uid122_rAtanPi_uid13_fpArctanPiTest_b <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23);
--reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1(REG,429)@36
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest(LOGICAL,135)@37
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q;
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b else "0";
--exc_I_uid139_rAtanPi_uid13_fpArctanPiTest(LOGICAL,138)@37
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q;
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q;
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b;
--cstBiasM2_uid6_fpArctanPiTest(CONSTANT,5)
cstBiasM2_uid6_fpArctanPiTest_q <= "01111101";
--ooPi_uid9_fpArctanPiTest(CONSTANT,8)
ooPi_uid9_fpArctanPiTest_q <= "101000101111100110000011";
--fracOOPi_uid10_fpArctanPiTest(BITSELECT,9)@36
fracOOPi_uid10_fpArctanPiTest_in <= ooPi_uid9_fpArctanPiTest_q(22 downto 0);
fracOOPi_uid10_fpArctanPiTest_b <= fracOOPi_uid10_fpArctanPiTest_in(22 downto 0);
--fpOOPi_uid11_fpArctanPiTest(BITJOIN,10)@36
fpOOPi_uid11_fpArctanPiTest_q <= GND_q & cstBiasM2_uid6_fpArctanPiTest_q & fracOOPi_uid10_fpArctanPiTest_b;
--expY_uid123_rAtanPi_uid13_fpArctanPiTest(BITSELECT,122)@36
expY_uid123_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(30 downto 0);
expY_uid123_rAtanPi_uid13_fpArctanPiTest_b <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23);
--expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest(LOGICAL,149)@36
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b;
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a(DELAY,581)@36
ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest(LOGICAL,203)@37
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b;
--fracY_uid128_rAtanPi_uid13_fpArctanPiTest(BITSELECT,127)@36
fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(22 downto 0);
fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0);
--fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest(LOGICAL,153)@36
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b;
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b(DELAY,575)@36
ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest(LOGICAL,151)@36
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b;
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a(DELAY,574)@36
ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid155_rAtanPi_uid13_fpArctanPiTest(LOGICAL,154)@37
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q;
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b <= ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q;
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b;
--expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest(LOGICAL,133)@37
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q;
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b else "0";
--excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest(LOGICAL,204)@37
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b;
--ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest(LOGICAL,205)@37
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q;
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q;
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a or ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b;
--InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest(LOGICAL,155)@36
InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q;
InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a;
--exc_N_uid157_rAtanPi_uid13_fpArctanPiTest(LOGICAL,156)@36
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b;
--ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a(DELAY,579)@36
ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest(LOGICAL,139)@37
InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q;
InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a;
--exc_N_uid141_rAtanPi_uid13_fpArctanPiTest(LOGICAL,140)@37
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b;
--excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest(LOGICAL,206)@37
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c;
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest(LOGICAL,218)@37
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q;
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= not InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a;
END IF;
END PROCESS;
--signY_uid125_rAtanPi_uid13_fpArctanPiTest(BITSELECT,124)@36
signY_uid125_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q;
signY_uid125_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31);
--signX_uid124_rAtanPi_uid13_fpArctanPiTest(BITSELECT,123)@36
signX_uid124_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q;
signX_uid124_rAtanPi_uid13_fpArctanPiTest_b <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31);
--signR_uid190_rAtanPi_uid13_fpArctanPiTest(LOGICAL,189)@36
signR_uid190_rAtanPi_uid13_fpArctanPiTest_a <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_b;
signR_uid190_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_b;
signR_uid190_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= signR_uid190_rAtanPi_uid13_fpArctanPiTest_a xor signR_uid190_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a(DELAY,666)@37
ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid190_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest(LOGICAL,219)@38
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a <= ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q;
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b <= InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q;
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q <= signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a and signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b;
--ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c(DELAY,670)@38
ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest(BITJOIN,128)@36
add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b;
--reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1(REG,433)@36
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest(BITJOIN,126)@36
add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b;
--reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0(REG,432)@36
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--prod_uid165_rAtanPi_uid13_fpArctanPiTest(MULT,164)@37
prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr <= UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_a) * UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_b);
prod_uid165_rAtanPi_uid13_fpArctanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= (others => '0');
prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= (others => '0');
prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q;
prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q;
prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr);
END IF;
END IF;
END PROCESS;
prod_uid165_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1;
END IF;
END IF;
END PROCESS;
--normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest(BITSELECT,165)@40
normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q;
normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in(47 downto 47);
--roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest(CONSTANT,179)
roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q <= "010";
--fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest(BITSELECT,167)@40
fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(46 downto 0);
fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in(46 downto 23);
--fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest(BITSELECT,168)@40
fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(45 downto 0);
fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in(45 downto 22);
--fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest(MUX,169)@40
fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b;
fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s, en, fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b, fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b)
BEGIN
CASE fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "0" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b;
WHEN "1" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b;
WHEN OTHERS => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest(BITSELECT,177)@40
FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in <= fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q(1 downto 0);
FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in(1 downto 0);
--Prod22_uid172_rAtanPi_uid13_fpArctanPiTest(BITSELECT,171)@40
Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(22 downto 0);
Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in(22 downto 22);
--extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest(MUX,172)@40
extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b;
extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest: PROCESS (extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s, en, GND_q, Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b)
BEGIN
CASE extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "0" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b;
WHEN OTHERS => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest(BITSELECT,170)@40
stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(21 downto 0);
stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b <= stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in(21 downto 0);
--stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest(BITJOIN,173)@40
stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q <= extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q & stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b;
--stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest(LOGICAL,175)@40
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a <= stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q;
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q <= "1" when stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a = stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b else "0";
--sticky_uid177_rAtanPi_uid13_fpArctanPiTest(LOGICAL,176)@40
sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a <= stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q;
sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q <= not sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a;
--lrs_uid179_rAtanPi_uid13_fpArctanPiTest(BITJOIN,178)@40
lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b & sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q;
--roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest(LOGICAL,180)@40
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a <= lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q;
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b <= roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q;
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q <= "1" when roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a = roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b else "0";
--roundBit_uid182_rAtanPi_uid13_fpArctanPiTest(LOGICAL,181)@40
roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a <= roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q;
roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q <= not roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a;
--roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest(BITJOIN,184)@40
roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q <= GND_q & normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b & cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q & roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q;
--reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1(REG,436)@40
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--biasInc_uid163_rAtanPi_uid13_fpArctanPiTest(CONSTANT,162)
biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q <= "0001111111";
--ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b(DELAY,586)@36
ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expY_uid123_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expSum_uid162_rAtanPi_uid13_fpArctanPiTest(ADD,161)@37
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q);
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q);
expSum_uid162_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a) + UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q <= expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o(8 downto 0);
--ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a(DELAY,587)@38
ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest(SUB,163)@39
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q);
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q(9)) & biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q);
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b));
END IF;
END IF;
END PROCESS;
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o(10 downto 0);
--expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest(BITJOIN,182)@40
expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q & fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q;
--reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0(REG,435)@40
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest(ADD,185)@41
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q(34)) & reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q);
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q);
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a) + SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b));
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o(35 downto 0);
--expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest(BITSELECT,187)@41
expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q;
expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in(35 downto 24);
--expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest(BITSELECT,188)@41
expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b(7 downto 0);
expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in(7 downto 0);
--ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d(DELAY,664)@41
ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 2 )
PORT MAP ( xin => expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c(DELAY,659)@37
ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1(REG,437)@41
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid193_rAtanPi_uid13_fpArctanPiTest(COMPARE,192)@42
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q;
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & '0';
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q) & expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin(0);
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b));
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o(14);
--InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest(LOGICAL,157)@37
InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q;
InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a;
--InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest(LOGICAL,158)@37
InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a;
--InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest(LOGICAL,159)@37
InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a;
--exc_R_uid161_rAtanPi_uid13_fpArctanPiTest(LOGICAL,160)@37
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c;
--ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b(DELAY,629)@37
ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest(LOGICAL,141)@37
InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a;
--InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest(LOGICAL,142)@37
InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a;
--InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest(LOGICAL,143)@37
InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a;
--exc_R_uid145_rAtanPi_uid13_fpArctanPiTest(LOGICAL,144)@37
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c;
--ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a(DELAY,628)@37
ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest(LOGICAL,201)@42
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c <= expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c;
--excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest(LOGICAL,200)@37
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q;
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q <= excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a and excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c(DELAY,646)@37
ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest(LOGICAL,199)@37
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q;
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q <= excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a and excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b(DELAY,645)@37
ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest(LOGICAL,198)@37
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q <= excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a and excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a(DELAY,644)@37
ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid203_rAtanPi_uid13_fpArctanPiTest(LOGICAL,202)@42
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q <= excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d;
--expUdf_uid191_rAtanPi_uid13_fpArctanPiTest(COMPARE,190)@42
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q;
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0';
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin(0);
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b));
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o(14);
--excZC3_uid197_rAtanPi_uid13_fpArctanPiTest(LOGICAL,196)@42
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c <= expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c;
--excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest(LOGICAL,195)@37
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q;
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c(DELAY,633)@37
ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest(LOGICAL,194)@37
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b(DELAY,632)@37
ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest(LOGICAL,193)@37
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a(DELAY,631)@37
ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid198_rAtanPi_uid13_fpArctanPiTest(LOGICAL,197)@42
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q <= excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d;
--concExc_uid208_rAtanPi_uid13_fpArctanPiTest(BITJOIN,207)@42
concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q <= ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q & excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q & excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q;
--reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0(REG,439)@42
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid209_rAtanPi_uid13_fpArctanPiTest(LOOKUP,208)@43
excREnc_uid209_rAtanPi_uid13_fpArctanPiTest: PROCESS (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q) IS
WHEN "000" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "01";
WHEN "001" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "010" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "10";
WHEN "011" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "100" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "11";
WHEN "101" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "110" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "111" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN OTHERS =>
excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest(MUX,217)@43
expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q;
expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest: PROCESS (expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q;
WHEN "10" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest(BITSELECT,186)@41
fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q(23 downto 0);
fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b <= fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in(23 downto 1);
--ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d(DELAY,662)@41
ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest(MUX,212)@43
fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q;
fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q;
WHEN "10" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid221_rAtanPi_uid13_fpArctanPiTest(BITJOIN,220)@43
R_uid221_rAtanPi_uid13_fpArctanPiTest_q <= ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q & expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q & fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q;
--xOut(GPOUT,4)@43
q <= R_uid221_rAtanPi_uid13_fpArctanPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_atanpi_s5
-- VHDL created on Tue Mar 12 11:23:23 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_atanpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_atanpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBiasM2_uid6_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal ooPi_uid9_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal piO2_uid46_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0);
signal piO4_uid47_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid64_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal zS_uid67_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q : std_logic_vector (12 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a : std_logic_vector (23 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 : std_logic_vector (50 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr : UNSIGNED (50 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q : std_logic_vector (50 downto 0);
signal fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (9 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (10 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector (23 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 : std_logic_vector (47 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr : UNSIGNED (47 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (47 downto 0);
signal roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_q : std_logic_vector (40 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_b : std_logic_vector (21 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_s1 : std_logic_vector (36 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_pr : SIGNED (37 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_q : std_logic_vector (36 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid299_atanXOXTabGen_lutmem_ia : std_logic_vector (30 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_iq : std_logic_vector (30 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_q : std_logic_vector (30 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid300_atanXOXTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid301_atanXOXTabGen_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid344_invTabGen_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid345_invTabGen_lutmem_ia : std_logic_vector (19 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_iq : std_logic_vector (19 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_q : std_logic_vector (19 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid346_invTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q : std_logic_vector (19 downto 0);
signal reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q : std_logic_vector (21 downto 0);
signal reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q : std_logic_vector (28 downto 0);
signal reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q : std_logic_vector (30 downto 0);
signal reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (26 downto 0);
signal reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (8 downto 0);
signal reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (31 downto 0);
signal reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (32 downto 0);
signal reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (22 downto 0);
signal reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (22 downto 0);
signal reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (22 downto 0);
signal reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (7 downto 0);
signal reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (7 downto 0);
signal reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (22 downto 0);
signal reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (23 downto 0);
signal reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (34 downto 0);
signal reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (11 downto 0);
signal reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q : std_logic_vector (7 downto 0);
signal ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (7 downto 0);
signal ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (8 downto 0);
signal ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (22 downto 0);
signal ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (7 downto 0);
signal ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (20 downto 0);
signal ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (18 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q : std_logic_vector (12 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 : std_logic;
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : signal is true;
signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : signal is true;
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : signal is true;
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_c : std_logic_vector (0 downto 0);
signal excSelBits_uid114_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a : std_logic_vector(33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b : std_logic_vector(33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o : std_logic_vector (33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q : std_logic_vector (33 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o : std_logic_vector (32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0);
signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid15_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid15_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid16_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid16_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal singX_uid17_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal singX_uid17_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q : std_logic_vector (9 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_a : std_logic_vector(26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_b : std_logic_vector(26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_o : std_logic_vector (26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (26 downto 0);
signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (35 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal fracOOPi_uid10_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracOOPi_uid10_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid80_atanX_uid8_fpArctanPiTest_in : std_logic_vector (49 downto 0);
signal normBit_uid80_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in : std_logic_vector (48 downto 0);
signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in : std_logic_vector (47 downto 0);
signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (47 downto 0);
signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (46 downto 0);
signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (45 downto 0);
signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (21 downto 0);
signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (21 downto 0);
signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in : std_logic_vector (36 downto 0);
signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b : std_logic_vector (22 downto 0);
signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal R_uid221_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (14 downto 0);
signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (14 downto 0);
signal R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal constOut_uid54_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal constOut_uid54_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal u_uid58_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal u_uid58_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal R_uid120_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (16 downto 0);
signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (8 downto 0);
signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in : std_logic_vector (8 downto 0);
signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in : std_logic_vector (25 downto 0);
signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (11 downto 0);
signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (9 downto 0);
signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (33 downto 0);
signal fpOOPi_uid11_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (32 downto 0);
signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0);
signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (28 downto 0);
signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (24 downto 0);
signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (0 downto 0);
signal stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal lowRangeB_uid304_atanXOXPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid304_atanXOXPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid305_atanXOXPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid305_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid310_atanXOXPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid310_atanXOXPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid311_atanXOXPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid311_atanXOXPolyEval_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid349_invPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid349_invPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid350_invPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid350_invPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid355_invPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid355_invPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid356_invPolyEval_in : std_logic_vector (22 downto 0);
signal highBBits_uid356_invPolyEval_b : std_logic_vector (20 downto 0);
signal y_uid73_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal y_uid73_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0);
signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal yT1_uid347_invPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid347_invPolyEval_b : std_logic_vector (11 downto 0);
signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal expU_uid59_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expU_uid59_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracU_uid60_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracU_uid60_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0);
signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b : std_logic_vector (3 downto 0);
signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (1 downto 0);
signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (34 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_a : std_logic_vector(31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_b : std_logic_vector(31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_o : std_logic_vector (31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_q : std_logic_vector (31 downto 0);
signal sumAHighB_uid351_invPolyEval_a : std_logic_vector(20 downto 0);
signal sumAHighB_uid351_invPolyEval_b : std_logic_vector(20 downto 0);
signal sumAHighB_uid351_invPolyEval_o : std_logic_vector (20 downto 0);
signal sumAHighB_uid351_invPolyEval_q : std_logic_vector (20 downto 0);
signal sumAHighB_uid357_invPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid357_invPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid357_invPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid357_invPolyEval_q : std_logic_vector (29 downto 0);
signal yAddr_uid75_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0);
signal yAddr_uid75_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in : std_logic_vector (26 downto 0);
signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b : std_logic_vector (17 downto 0);
signal rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0);
signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b : std_logic_vector (4 downto 0);
signal expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0);
signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal s1_uid304_uid307_atanXOXPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid310_uid313_atanXOXPolyEval_q : std_logic_vector (33 downto 0);
signal s1_uid349_uid352_invPolyEval_q : std_logic_vector (21 downto 0);
signal s2_uid355_uid358_invPolyEval_q : std_logic_vector (31 downto 0);
signal yT1_uid302_atanXOXPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid302_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (20 downto 0);
signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (18 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0);
signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0);
signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (25 downto 0);
begin
--xIn(GPIN,3)@0
--cstAllZWF_uid19_atanX_uid8_fpArctanPiTest(CONSTANT,18)
cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000000";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable(LOGICAL,878)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q <= not ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,1008)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a or ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,1004)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100001";
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,1005)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,1006)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,1009)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,1010)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--fracX_uid16_atanX_uid8_fpArctanPiTest(BITSELECT,15)@0
fracX_uid16_atanX_uid8_fpArctanPiTest_in <= a(22 downto 0);
fracX_uid16_atanX_uid8_fpArctanPiTest_b <= fracX_uid16_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--fracXIsZero_uid35_atanX_uid8_fpArctanPiTest(LOGICAL,34)@0
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b else "0";
--InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest(LOGICAL,36)@0
InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q <= not InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a;
--cstAllOWE_uid18_atanX_uid8_fpArctanPiTest(CONSTANT,17)
cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q <= "11111111";
--expX_uid15_atanX_uid8_fpArctanPiTest(BITSELECT,14)@0
expX_uid15_atanX_uid8_fpArctanPiTest_in <= a(30 downto 0);
expX_uid15_atanX_uid8_fpArctanPiTest_b <= expX_uid15_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--expXIsMax_uid33_atanX_uid8_fpArctanPiTest(LOGICAL,32)@0
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a = expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b else "0";
--exc_N_uid38_atanX_uid8_fpArctanPiTest(LOGICAL,37)@0
exc_N_uid38_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q;
exc_N_uid38_atanX_uid8_fpArctanPiTest_b <= InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q;
exc_N_uid38_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_a and exc_N_uid38_atanX_uid8_fpArctanPiTest_b;
--InvExc_N_uid118_atanX_uid8_fpArctanPiTest(LOGICAL,117)@0
InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q;
InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q <= not InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a;
--singX_uid17_atanX_uid8_fpArctanPiTest(BITSELECT,16)@0
singX_uid17_atanX_uid8_fpArctanPiTest_in <= a;
singX_uid17_atanX_uid8_fpArctanPiTest_b <= singX_uid17_atanX_uid8_fpArctanPiTest_in(31 downto 31);
--signR_uid119_atanX_uid8_fpArctanPiTest(LOGICAL,118)@0
signR_uid119_atanX_uid8_fpArctanPiTest_a <= singX_uid17_atanX_uid8_fpArctanPiTest_b;
signR_uid119_atanX_uid8_fpArctanPiTest_b <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q;
signR_uid119_atanX_uid8_fpArctanPiTest_q <= signR_uid119_atanX_uid8_fpArctanPiTest_a and signR_uid119_atanX_uid8_fpArctanPiTest_b;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,998)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid119_atanX_uid8_fpArctanPiTest_q, xout => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,1000)
-- every=1, low=0, high=33, step=1, init=1
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 32 THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 33;
ELSE
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6));
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,1001)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,1002)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,999)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 34,
width_b => 1,
widthad_b => 6,
numwords_b => 34,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,879)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a or ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,875)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100000";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,876)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,877)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,880)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,881)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,869)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => singX_uid17_atanX_uid8_fpArctanPiTest_b, xout => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,871)
-- every=1, low=0, high=32, step=1, init=1
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 31 THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 32;
ELSE
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6));
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,872)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,873)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,870)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--cstBias_uid22_atanX_uid8_fpArctanPiTest(CONSTANT,21)
cstBias_uid22_atanX_uid8_fpArctanPiTest_q <= "01111111";
--piO2_uid46_atanX_uid8_fpArctanPiTest(CONSTANT,45)
piO2_uid46_atanX_uid8_fpArctanPiTest_q <= "11001001000011111101101011";
--cstPiO2_uid48_atanX_uid8_fpArctanPiTest(BITSELECT,47)@35
cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in <= piO2_uid46_atanX_uid8_fpArctanPiTest_q(24 downto 0);
cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b <= cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in(24 downto 2);
--fpPiO2C_uid49_atanX_uid8_fpArctanPiTest(BITJOIN,48)@35
fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBias_uid22_atanX_uid8_fpArctanPiTest_q & cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b;
--cstBiasM1_uid23_atanX_uid8_fpArctanPiTest(CONSTANT,22)
cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q <= "01111110";
--piO4_uid47_atanX_uid8_fpArctanPiTest(CONSTANT,46)
piO4_uid47_atanX_uid8_fpArctanPiTest_q <= "110010010000111111011011";
--cstPiO4_uid51_atanX_uid8_fpArctanPiTest(BITSELECT,50)@35
cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in <= piO4_uid47_atanX_uid8_fpArctanPiTest_q(22 downto 0);
cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b <= cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--fpPiO4C_uid52_atanX_uid8_fpArctanPiTest(BITJOIN,51)@35
fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q & cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,892)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a or ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b);
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,893)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,894)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b;
--exc_I_uid36_atanX_uid8_fpArctanPiTest(LOGICAL,35)@0
exc_I_uid36_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q;
exc_I_uid36_atanX_uid8_fpArctanPiTest_b <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
exc_I_uid36_atanX_uid8_fpArctanPiTest_q <= exc_I_uid36_atanX_uid8_fpArctanPiTest_a and exc_I_uid36_atanX_uid8_fpArctanPiTest_b;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,882)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid36_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,883)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq,
address_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa,
data_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia
);
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(0 downto 0);
--constOut_uid54_atanX_uid8_fpArctanPiTest(MUX,53)@35
constOut_uid54_atanX_uid8_fpArctanPiTest_s <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q;
constOut_uid54_atanX_uid8_fpArctanPiTest: PROCESS (constOut_uid54_atanX_uid8_fpArctanPiTest_s, en, fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q, fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE constOut_uid54_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expOutCst_uid112_atanX_uid8_fpArctanPiTest(BITSELECT,111)@35
expOutCst_uid112_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expOutCst_uid112_atanX_uid8_fpArctanPiTest_b <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5(REG,428)@35
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--cst01pWShift_uid69_atanX_uid8_fpArctanPiTest(CONSTANT,68)
cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q <= "0000000000000";
--reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2(REG,389)@0
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= signR_uid119_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c(DELAY,707)@1
ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,1022)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a or ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b);
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top(CONSTANT,1018)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q <= "0111";
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp(LOGICAL,1019)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q);
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q <= "1" when ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a = ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b else "0";
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg(REG,1020)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,1023)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,1024)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b;
--cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,230)
cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111110";
--expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest(SUB,259)@0
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q);
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b);
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b));
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,260)@0
expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0);
expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,229)
cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111101";
--expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest(SUB,256)@0
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q);
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b);
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b));
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,257)@0
expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0);
expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,249)@0
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b else "0";
--expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest(MUX,263)@0
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s <= fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q;
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--expXIsZero_uid31_atanX_uid8_fpArctanPiTest(LOGICAL,30)@0
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a = expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b else "0";
--udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,258)@0
udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in <= STD_LOGIC_VECTOR((9 downto 9 => expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(8)) & expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q);
udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in(9 downto 9);
--InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,245)@0
InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a;
--InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,246)@0
InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a <= expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q;
InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a;
--exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,247)@0
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a <= InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b <= InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c;
--xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,264)@0
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q;
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b;
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a and xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b;
--xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,265)@0
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q;
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q <= xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a or xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b;
--excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,266)@0
excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q & expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q & xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q;
--reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0(REG,378)@0
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest(LOOKUP,267)@1
outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest(MUX,269)@1
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q;
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,1012)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt(COUNTER,1014)
-- every=1, low=0, high=7, step=1, init=1
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg(REG,1015)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux(MUX,1016)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,1013)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia
);
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid20_atanX_uid8_fpArctanPiTest(CONSTANT,19)
cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000001";
--oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,248)@0
oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q <= VCC_q & fracX_uid16_atanX_uid8_fpArctanPiTest_b;
--y_uid251_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,250)@0
y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in <= oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q(22 downto 0);
y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,252)@0
yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b;
yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 15);
--reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0(REG,379)@0
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid346_invTabGen_lutmem(DUALMEM,376)@1
memoryC2_uid346_invTabGen_lutmem_ia <= (others => '0');
memoryC2_uid346_invTabGen_lutmem_aa <= (others => '0');
memoryC2_uid346_invTabGen_lutmem_ab <= reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q;
memoryC2_uid346_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC2_uid346_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid346_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid346_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid346_invTabGen_lutmem_iq,
address_a => memoryC2_uid346_invTabGen_lutmem_aa,
data_a => memoryC2_uid346_invTabGen_lutmem_ia
);
memoryC2_uid346_invTabGen_lutmem_reset0 <= areset;
memoryC2_uid346_invTabGen_lutmem_q <= memoryC2_uid346_invTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1(REG,381)@3
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= memoryC2_uid346_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,1011)
ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a(DELAY,680)@0
ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,253)@3
yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in <= ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q(14 downto 0);
yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in(14 downto 0);
--yT1_uid347_invPolyEval(BITSELECT,346)@3
yT1_uid347_invPolyEval_in <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b;
yT1_uid347_invPolyEval_b <= yT1_uid347_invPolyEval_in(14 downto 3);
--reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0(REG,380)@3
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= yT1_uid347_invPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid366_pT1_uid348_invPolyEval(MULT,365)@4
prodXY_uid366_pT1_uid348_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid366_pT1_uid348_invPolyEval_a),13)) * SIGNED(prodXY_uid366_pT1_uid348_invPolyEval_b);
prodXY_uid366_pT1_uid348_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid366_pT1_uid348_invPolyEval_a <= (others => '0');
prodXY_uid366_pT1_uid348_invPolyEval_b <= (others => '0');
prodXY_uid366_pT1_uid348_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid366_pT1_uid348_invPolyEval_a <= reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q;
prodXY_uid366_pT1_uid348_invPolyEval_b <= reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q;
prodXY_uid366_pT1_uid348_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid366_pT1_uid348_invPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid366_pT1_uid348_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid366_pT1_uid348_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid366_pT1_uid348_invPolyEval_q <= prodXY_uid366_pT1_uid348_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid367_pT1_uid348_invPolyEval(BITSELECT,366)@7
prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in <= prodXY_uid366_pT1_uid348_invPolyEval_q;
prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in(23 downto 11);
--highBBits_uid350_invPolyEval(BITSELECT,349)@7
highBBits_uid350_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b;
highBBits_uid350_invPolyEval_b <= highBBits_uid350_invPolyEval_in(12 downto 1);
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a(DELAY,804)@1
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid345_invTabGen_lutmem(DUALMEM,375)@4
memoryC1_uid345_invTabGen_lutmem_ia <= (others => '0');
memoryC1_uid345_invTabGen_lutmem_aa <= (others => '0');
memoryC1_uid345_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q;
memoryC1_uid345_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 20,
widthad_a => 8,
numwords_a => 256,
width_b => 20,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC1_uid345_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid345_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid345_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid345_invTabGen_lutmem_iq,
address_a => memoryC1_uid345_invTabGen_lutmem_aa,
data_a => memoryC1_uid345_invTabGen_lutmem_ia
);
memoryC1_uid345_invTabGen_lutmem_reset0 <= areset;
memoryC1_uid345_invTabGen_lutmem_q <= memoryC1_uid345_invTabGen_lutmem_iq(19 downto 0);
--reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0(REG,383)@6
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= "00000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= memoryC1_uid345_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid351_invPolyEval(ADD,350)@7
sumAHighB_uid351_invPolyEval_a <= STD_LOGIC_VECTOR((20 downto 20 => reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q(19)) & reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q);
sumAHighB_uid351_invPolyEval_b <= STD_LOGIC_VECTOR((20 downto 12 => highBBits_uid350_invPolyEval_b(11)) & highBBits_uid350_invPolyEval_b);
sumAHighB_uid351_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid351_invPolyEval_a) + SIGNED(sumAHighB_uid351_invPolyEval_b));
sumAHighB_uid351_invPolyEval_q <= sumAHighB_uid351_invPolyEval_o(20 downto 0);
--lowRangeB_uid349_invPolyEval(BITSELECT,348)@7
lowRangeB_uid349_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b(0 downto 0);
lowRangeB_uid349_invPolyEval_b <= lowRangeB_uid349_invPolyEval_in(0 downto 0);
--s1_uid349_uid352_invPolyEval(BITJOIN,351)@7
s1_uid349_uid352_invPolyEval_q <= sumAHighB_uid351_invPolyEval_q & lowRangeB_uid349_invPolyEval_b;
--reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1(REG,385)@7
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= "0000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= s1_uid349_uid352_invPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor(LOGICAL,1059)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a or ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b);
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg(REG,966)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena(REG,1060)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q = "1") THEN
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd(LOGICAL,1061)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b <= en;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg(DELAY,1051)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt(COUNTER,962)
-- every=1, low=0, high=1, step=1, init=1
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i,1));
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg(REG,963)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux(MUX,964)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s <= en;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux: PROCESS (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q)
BEGIN
CASE ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s IS
WHEN "0" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
WHEN "1" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q;
WHEN OTHERS => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem(DUALMEM,1052)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia
);
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0(REG,384)@7
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid369_pT2_uid354_invPolyEval(MULT,368)@8
prodXY_uid369_pT2_uid354_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid369_pT2_uid354_invPolyEval_a),16)) * SIGNED(prodXY_uid369_pT2_uid354_invPolyEval_b);
prodXY_uid369_pT2_uid354_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid369_pT2_uid354_invPolyEval_a <= (others => '0');
prodXY_uid369_pT2_uid354_invPolyEval_b <= (others => '0');
prodXY_uid369_pT2_uid354_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid369_pT2_uid354_invPolyEval_a <= reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q;
prodXY_uid369_pT2_uid354_invPolyEval_b <= reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q;
prodXY_uid369_pT2_uid354_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid369_pT2_uid354_invPolyEval_pr,37));
END IF;
END IF;
END PROCESS;
prodXY_uid369_pT2_uid354_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid369_pT2_uid354_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid369_pT2_uid354_invPolyEval_q <= prodXY_uid369_pT2_uid354_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid370_pT2_uid354_invPolyEval(BITSELECT,369)@11
prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in <= prodXY_uid369_pT2_uid354_invPolyEval_q;
prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in(36 downto 14);
--highBBits_uid356_invPolyEval(BITSELECT,355)@11
highBBits_uid356_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b;
highBBits_uid356_invPolyEval_b <= highBBits_uid356_invPolyEval_in(22 downto 2);
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor(LOGICAL,1048)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q <= not (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a or ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b);
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top(CONSTANT,1031)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q <= "0100";
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp(LOGICAL,1032)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q <= "1" when ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a = ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b else "0";
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg(REG,1033)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena(REG,1049)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd(LOGICAL,1050)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a and ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg(DELAY,1038)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt(COUNTER,1027)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i,3));
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg(REG,1028)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux(MUX,1029)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s <= en;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux: PROCESS (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem(DUALMEM,1039)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq(7 downto 0);
--memoryC0_uid344_invTabGen_lutmem(DUALMEM,374)@8
memoryC0_uid344_invTabGen_lutmem_ia <= (others => '0');
memoryC0_uid344_invTabGen_lutmem_aa <= (others => '0');
memoryC0_uid344_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q;
memoryC0_uid344_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC0_uid344_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid344_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid344_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid344_invTabGen_lutmem_iq,
address_a => memoryC0_uid344_invTabGen_lutmem_aa,
data_a => memoryC0_uid344_invTabGen_lutmem_ia
);
memoryC0_uid344_invTabGen_lutmem_reset0 <= areset;
memoryC0_uid344_invTabGen_lutmem_q <= memoryC0_uid344_invTabGen_lutmem_iq(28 downto 0);
--reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0(REG,387)@10
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= "00000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= memoryC0_uid344_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid357_invPolyEval(ADD,356)@11
sumAHighB_uid357_invPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q(28)) & reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q);
sumAHighB_uid357_invPolyEval_b <= STD_LOGIC_VECTOR((29 downto 21 => highBBits_uid356_invPolyEval_b(20)) & highBBits_uid356_invPolyEval_b);
sumAHighB_uid357_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid357_invPolyEval_a) + SIGNED(sumAHighB_uid357_invPolyEval_b));
sumAHighB_uid357_invPolyEval_q <= sumAHighB_uid357_invPolyEval_o(29 downto 0);
--lowRangeB_uid355_invPolyEval(BITSELECT,354)@11
lowRangeB_uid355_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b(1 downto 0);
lowRangeB_uid355_invPolyEval_b <= lowRangeB_uid355_invPolyEval_in(1 downto 0);
--s2_uid355_uid358_invPolyEval(BITJOIN,357)@11
s2_uid355_uid358_invPolyEval_q <= sumAHighB_uid357_invPolyEval_q & lowRangeB_uid355_invPolyEval_b;
--fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,255)@11
fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in <= s2_uid355_uid358_invPolyEval_q(28 downto 0);
fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in(28 downto 5);
--fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,261)@11
fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b(22 downto 0);
fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,688)@0
ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest(MUX,262)@11
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q;
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1(REG,388)@1
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,701)@2
ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 10 )
PORT MAP ( xin => reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest(MUX,268)@12
fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q;
fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid273_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,272)@12
R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q <= ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q & fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,905)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a or ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,901)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "01001";
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,902)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,903)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,906)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,907)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,895)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,897)
-- every=1, low=0, high=9, step=1, init=1
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 8 THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 9;
ELSE
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,4));
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,898)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,899)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,896)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 4,
numwords_a => 10,
width_b => 32,
widthad_b => 4,
numwords_b => 10,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(31 downto 0);
--path2_uid56_atanX_uid8_fpArctanPiTest(COMPARE,55)@0
path2_uid56_atanX_uid8_fpArctanPiTest_cin <= GND_q;
path2_uid56_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid15_atanX_uid8_fpArctanPiTest_b) & '0';
path2_uid56_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q) & path2_uid56_atanX_uid8_fpArctanPiTest_cin(0);
path2_uid56_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_b));
path2_uid56_atanX_uid8_fpArctanPiTest_n(0) <= not path2_uid56_atanX_uid8_fpArctanPiTest_o(10);
--reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1(REG,390)@0
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= path2_uid56_atanX_uid8_fpArctanPiTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b(DELAY,466)@1
ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--u_uid58_atanX_uid8_fpArctanPiTest(MUX,57)@12
u_uid58_atanX_uid8_fpArctanPiTest_s <= ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q;
u_uid58_atanX_uid8_fpArctanPiTest: PROCESS (u_uid58_atanX_uid8_fpArctanPiTest_s, en, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q, R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE u_uid58_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => u_uid58_atanX_uid8_fpArctanPiTest_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q;
WHEN "1" => u_uid58_atanX_uid8_fpArctanPiTest_q <= R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => u_uid58_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracU_uid60_atanX_uid8_fpArctanPiTest(BITSELECT,59)@12
fracU_uid60_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracU_uid60_atanX_uid8_fpArctanPiTest_b <= fracU_uid60_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a(DELAY,471)@12
ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracU_uid60_atanX_uid8_fpArctanPiTest_b, xout => ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest(BITJOIN,60)@13
oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q;
--oFracUExt_uid70_atanX_uid8_fpArctanPiTest(BITJOIN,69)@13
oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q <= cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q & oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q;
--X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,282)@13
X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(24 downto 0);
X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(24 downto 0);
--leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,281)
leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000000000000";
--leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,283)@13
leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5(REG,399)@13
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,279)@13
X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(28 downto 0);
X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(28 downto 0);
--leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,280)@13
leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4(REG,398)@13
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,276)@13
X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(32 downto 0);
X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(32 downto 0);
--leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,275)
leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "0000";
--leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,277)@13
leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3(REG,397)@13
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,396)@13
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--zS_uid67_atanX_uid8_fpArctanPiTest(CONSTANT,66)
zS_uid67_atanX_uid8_fpArctanPiTest_q <= "000000000";
--shiftBias_uid64_atanX_uid8_fpArctanPiTest(CONSTANT,63)
shiftBias_uid64_atanX_uid8_fpArctanPiTest_q <= "01110010";
--expU_uid59_atanX_uid8_fpArctanPiTest(BITSELECT,58)@12
expU_uid59_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expU_uid59_atanX_uid8_fpArctanPiTest_b <= expU_uid59_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1(REG,391)@12
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= expU_uid59_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--shiftValue_uid65_atanX_uid8_fpArctanPiTest(SUB,64)@13
shiftValue_uid65_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q);
shiftValue_uid65_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid64_atanX_uid8_fpArctanPiTest_q);
shiftValue_uid65_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_b));
shiftValue_uid65_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--ShiftValue8_uid66_atanX_uid8_fpArctanPiTest(BITSELECT,65)@13
ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q;
ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in(8 downto 8);
--shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest(MUX,67)@13
shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b;
shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest: PROCESS (shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s, en, shiftValue_uid65_atanX_uid8_fpArctanPiTest_q, zS_uid67_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= zS_uid67_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest(BITSELECT,70)@13
fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in <= shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q(3 downto 0);
fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,284)@13
leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b;
leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,395)@13
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,285)@14
leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q;
leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q, reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q, reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q;
WHEN "11" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,293)@14
LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(33 downto 0);
LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(33 downto 0);
--ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,725)@14
ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,292)
leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000";
--leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,294)@15
leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,290)@14
LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(34 downto 0);
LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(34 downto 0);
--ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,723)@14
ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,289)
leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "00";
--leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,291)@15
leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,287)@14
LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0);
LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(35 downto 0);
--ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,721)@14
ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,288)@15
leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & GND_q;
--reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,401)@14
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,295)@13
leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a(DELAY,829)@13
ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,400)@14
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,296)@15
leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q;
leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid73_atanX_uid8_fpArctanPiTest(BITSELECT,72)@15
y_uid73_atanX_uid8_fpArctanPiTest_in <= leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0);
y_uid73_atanX_uid8_fpArctanPiTest_b <= y_uid73_atanX_uid8_fpArctanPiTest_in(35 downto 1);
--yAddr_uid75_atanX_uid8_fpArctanPiTest(BITSELECT,74)@15
yAddr_uid75_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b;
yAddr_uid75_atanX_uid8_fpArctanPiTest_b <= yAddr_uid75_atanX_uid8_fpArctanPiTest_in(34 downto 27);
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0(REG,402)@15
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= yAddr_uid75_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid301_atanXOXTabGen_lutmem(DUALMEM,373)@16
memoryC2_uid301_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC2_uid301_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC2_uid301_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q;
memoryC2_uid301_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC2_uid301_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid301_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid301_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid301_atanXOXTabGen_lutmem_iq,
address_a => memoryC2_uid301_atanXOXTabGen_lutmem_aa,
data_a => memoryC2_uid301_atanXOXTabGen_lutmem_ia
);
memoryC2_uid301_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC2_uid301_atanXOXTabGen_lutmem_q <= memoryC2_uid301_atanXOXTabGen_lutmem_iq(12 downto 0);
--reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1(REG,404)@18
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= memoryC2_uid301_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--yPPolyEval_uid76_atanX_uid8_fpArctanPiTest(BITSELECT,75)@15
yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b(26 downto 0);
yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in(26 downto 9);
--yT1_uid302_atanXOXPolyEval(BITSELECT,301)@15
yT1_uid302_atanXOXPolyEval_in <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b;
yT1_uid302_atanXOXPolyEval_b <= yT1_uid302_atanXOXPolyEval_in(17 downto 5);
--ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg(DELAY,1062)
ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid302_atanXOXPolyEval_b, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a(DELAY,832)@15
ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0(REG,403)@18
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid360_pT1_uid303_atanXOXPolyEval(MULT,359)@19
prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_a),14)) * SIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_b);
prodXY_uid360_pT1_uid303_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= (others => '0');
prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= (others => '0');
prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q;
prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q;
prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid360_pT1_uid303_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval(BITSELECT,360)@22
prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_q;
prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in(25 downto 12);
--highBBits_uid305_atanXOXPolyEval(BITSELECT,304)@22
highBBits_uid305_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b;
highBBits_uid305_atanXOXPolyEval_b <= highBBits_uid305_atanXOXPolyEval_in(13 downto 1);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a(DELAY,834)@15
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0(REG,405)@18
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid300_atanXOXTabGen_lutmem(DUALMEM,372)@19
memoryC1_uid300_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC1_uid300_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC1_uid300_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q;
memoryC1_uid300_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC1_uid300_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid300_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid300_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid300_atanXOXTabGen_lutmem_iq,
address_a => memoryC1_uid300_atanXOXTabGen_lutmem_aa,
data_a => memoryC1_uid300_atanXOXTabGen_lutmem_ia
);
memoryC1_uid300_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC1_uid300_atanXOXTabGen_lutmem_q <= memoryC1_uid300_atanXOXTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0(REG,406)@21
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= memoryC1_uid300_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid306_atanXOXPolyEval(ADD,305)@22
sumAHighB_uid306_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q(20)) & reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q);
sumAHighB_uid306_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid305_atanXOXPolyEval_b(12)) & highBBits_uid305_atanXOXPolyEval_b);
sumAHighB_uid306_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid306_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid306_atanXOXPolyEval_b));
sumAHighB_uid306_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_o(21 downto 0);
--lowRangeB_uid304_atanXOXPolyEval(BITSELECT,303)@22
lowRangeB_uid304_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b(0 downto 0);
lowRangeB_uid304_atanXOXPolyEval_b <= lowRangeB_uid304_atanXOXPolyEval_in(0 downto 0);
--s1_uid304_uid307_atanXOXPolyEval(BITJOIN,306)@22
s1_uid304_uid307_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_q & lowRangeB_uid304_atanXOXPolyEval_b;
--reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1(REG,408)@22
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= s1_uid304_uid307_atanXOXPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor(LOGICAL,1035)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q <= not (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a or ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b);
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena(REG,1036)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd(LOGICAL,1037)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b <= en;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a and ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b;
--reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0(REG,407)@15
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg(DELAY,1025)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q, xout => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem(DUALMEM,1026)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq,
address_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa,
data_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia
);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid363_pT2_uid309_atanXOXPolyEval(MULT,362)@23
prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_a),19)) * SIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_b);
prodXY_uid363_pT2_uid309_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= (others => '0');
prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= (others => '0');
prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q;
prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q;
prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid363_pT2_uid309_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval(BITSELECT,363)@26
prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_q;
prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in(40 downto 17);
--highBBits_uid311_atanXOXPolyEval(BITSELECT,310)@26
highBBits_uid311_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b;
highBBits_uid311_atanXOXPolyEval_b <= highBBits_uid311_atanXOXPolyEval_in(23 downto 2);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor(LOGICAL,1073)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q <= not (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a or ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena(REG,1074)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q = "1") THEN
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd(LOGICAL,1075)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b <= en;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a and ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b;
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg(DELAY,1063)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem(DUALMEM,1064)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia
);
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0(REG,409)@22
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid299_atanXOXTabGen_lutmem(DUALMEM,371)@23
memoryC0_uid299_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC0_uid299_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC0_uid299_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q;
memoryC0_uid299_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 31,
widthad_a => 8,
numwords_a => 256,
width_b => 31,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC0_uid299_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid299_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid299_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid299_atanXOXTabGen_lutmem_iq,
address_a => memoryC0_uid299_atanXOXTabGen_lutmem_aa,
data_a => memoryC0_uid299_atanXOXTabGen_lutmem_ia
);
memoryC0_uid299_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC0_uid299_atanXOXTabGen_lutmem_q <= memoryC0_uid299_atanXOXTabGen_lutmem_iq(30 downto 0);
--reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0(REG,410)@25
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= memoryC0_uid299_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid312_atanXOXPolyEval(ADD,311)@26
sumAHighB_uid312_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((31 downto 31 => reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q(30)) & reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q);
sumAHighB_uid312_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((31 downto 22 => highBBits_uid311_atanXOXPolyEval_b(21)) & highBBits_uid311_atanXOXPolyEval_b);
sumAHighB_uid312_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid312_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid312_atanXOXPolyEval_b));
sumAHighB_uid312_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_o(31 downto 0);
--lowRangeB_uid310_atanXOXPolyEval(BITSELECT,309)@26
lowRangeB_uid310_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b(1 downto 0);
lowRangeB_uid310_atanXOXPolyEval_b <= lowRangeB_uid310_atanXOXPolyEval_in(1 downto 0);
--s2_uid310_uid313_atanXOXPolyEval(BITJOIN,312)@26
s2_uid310_uid313_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_q & lowRangeB_uid310_atanXOXPolyEval_b;
--fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest(BITSELECT,77)@26
fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in <= s2_uid310_uid313_atanXOXPolyEval_q(31 downto 0);
fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in(31 downto 5);
--reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1(REG,412)@26
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,918)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,914)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01010";
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,915)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,916)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,919)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,920)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0(REG,411)@13
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,908)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,910)
-- every=1, low=0, high=10, step=1, init=1
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 9 THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 10;
ELSE
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4));
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,911)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,912)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,909)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 11,
width_b => 24,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(23 downto 0);
--mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest(MULT,78)@27
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr <= UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a) * UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b);
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= (others => '0');
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= (others => '0');
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr);
END IF;
END IF;
END PROCESS;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid80_atanX_uid8_fpArctanPiTest(BITSELECT,79)@30
normBit_uid80_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(49 downto 0);
normBit_uid80_atanX_uid8_fpArctanPiTest_b <= normBit_uid80_atanX_uid8_fpArctanPiTest_in(49 downto 49);
--InvNormBit_uid84_atanX_uid8_fpArctanPiTest(LOGICAL,83)@30
InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a <= normBit_uid80_atanX_uid8_fpArctanPiTest_b;
InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q <= not InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,931)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,927)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01111";
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,928)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,929)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,932)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,933)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,921)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expU_uid59_atanX_uid8_fpArctanPiTest_b, xout => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,923)
-- every=1, low=0, high=15, step=1, init=1
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4));
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,924)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,925)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,922)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 16,
width_b => 8,
widthad_b => 4,
numwords_b => 16,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(7 downto 0);
--expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest(SUB,84)@30
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q);
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000" & InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q);
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b));
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--fracRPath3High_uid81_atanX_uid8_fpArctanPiTest(BITSELECT,80)@30
fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(48 downto 0);
fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in(48 downto 25);
--fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest(BITSELECT,81)@30
fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(47 downto 0);
fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in(47 downto 24);
--fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest(MUX,82)@30
fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s <= normBit_uid80_atanX_uid8_fpArctanPiTest_b;
fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s, en, fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b, fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b)
BEGIN
CASE fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest(BITJOIN,85)@30
expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q & fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q;
--reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0(REG,420)@30
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest(ADD,86)@31
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q);
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000" & VCC_q);
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b));
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o(33 downto 0);
--expRPath3_uid89_atanX_uid8_fpArctanPiTest(BITSELECT,88)@31
expRPath3_uid89_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(31 downto 0);
expRPath3_uid89_atanX_uid8_fpArctanPiTest_b <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_in(31 downto 24);
--reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4(REG,427)@31
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,971)
ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e(DELAY,534)@32
ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,337)@33
RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 1);
--rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,339)@33
rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= GND_q & RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,333)
rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000";
--rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,322)
rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000000000000000000000";
--X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,321)@32
X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 24);
--rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,323)@32
rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,319)
rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "0000000000000000";
--X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,318)@32
X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 16);
--rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,320)@32
rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,315)@32
X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 8);
--rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,317)@32
rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q & X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a(DELAY,504)@30
ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q, xout => ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest(BITJOIN,93)@32
oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q;
--cstWFP2_uid25_atanX_uid8_fpArctanPiTest(CONSTANT,24)
cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q <= "00011001";
--reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1(REG,413)@30
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest(SUB,89)@31
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q);
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR((10 downto 9 => reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q(8)) & reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q);
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a) - SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b));
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o(9 downto 0);
--shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest(BITSELECT,91)@31
shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q(7 downto 0);
shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest(CONSTANT,23)
cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q <= "01101000";
--shiftOut_uid91_atanX_uid8_fpArctanPiTest(COMPARE,90)@13
shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin <= GND_q;
shiftOut_uid91_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & '0';
shiftOut_uid91_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q) & shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin(0);
shiftOut_uid91_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_b));
shiftOut_uid91_atanX_uid8_fpArctanPiTest_c(0) <= shiftOut_uid91_atanX_uid8_fpArctanPiTest_o(10);
--ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b(DELAY,502)@13
ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => shiftOut_uid91_atanX_uid8_fpArctanPiTest_c, xout => ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--sValPostSOut_uid93_atanX_uid8_fpArctanPiTest(MUX,92)@31
sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s <= ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q;
sValPostSOut_uid93_atanX_uid8_fpArctanPiTest: PROCESS (sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s, en, shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b, cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest(BITSELECT,94)@31
sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in <= sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q(4 downto 0);
sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,324)@31
rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b;
rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,414)@31
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,325)@32
rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q;
rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,332)@32
RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 6);
--ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,762)@32
ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,334)@33
rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,329)@32
RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 4);
--ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,760)@32
ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 21, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,331)@33
rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,326)@32
RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 2);
--ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,758)@32
ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,328)@33
rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2(REG,416)@32
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,335)@31
rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(2 downto 1);
--ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a(DELAY,844)@31
ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,415)@32
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,336)@33
rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q;
rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q, rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,340)@31
rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,417)@31
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b(DELAY,772)@32
ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,341)@33
rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q;
rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest(BITJOIN,96)@33
pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & GND_q;
--reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1(REG,418)@33
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--path2Diff_uid97_atanX_uid8_fpArctanPiTest(SUB,97)@34
path2Diff_uid97_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & piO2_uid46_atanX_uid8_fpArctanPiTest_q);
path2Diff_uid97_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q);
path2Diff_uid97_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_b));
path2Diff_uid97_atanX_uid8_fpArctanPiTest_q <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_o(26 downto 0);
--normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest(BITSELECT,98)@34
normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(25 downto 0);
normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in(25 downto 25);
--expRPath2_uid103_atanX_uid8_fpArctanPiTest(MUX,102)@34
expRPath2_uid103_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b;
expRPath2_uid103_atanX_uid8_fpArctanPiTest: PROCESS (expRPath2_uid103_atanX_uid8_fpArctanPiTest_s, en, cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q, cstBias_uid22_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPath2_uid103_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest(BITSELECT,99)@34
path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(24 downto 0);
path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in(24 downto 1);
--path2DiffLow_uid101_atanX_uid8_fpArctanPiTest(BITSELECT,100)@34
path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(23 downto 0);
path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in(23 downto 0);
--fracRPath2_uid102_atanX_uid8_fpArctanPiTest(MUX,101)@34
fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b;
fracRPath2_uid102_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s, en, path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b, path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b)
BEGIN
CASE fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest(BITJOIN,103)@34
expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q <= expRPath2_uid103_atanX_uid8_fpArctanPiTest_q & fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q;
--reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0(REG,419)@34
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest(ADD,104)@35
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q);
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000" & VCC_q);
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b));
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o(32 downto 0);
--expRPath2_uid107_atanX_uid8_fpArctanPiTest(BITSELECT,106)@35
expRPath2_uid107_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(31 downto 0);
expRPath2_uid107_atanX_uid8_fpArctanPiTest_b <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_in(31 downto 24);
--reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3(REG,426)@35
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor(LOGICAL,1086)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q <= not (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a or ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b);
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena(REG,1087)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q = "1") THEN
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd(LOGICAL,1088)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b <= en;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a and ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg(DELAY,1076)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid15_atanX_uid8_fpArctanPiTest_b, xout => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem(DUALMEM,1077)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 33,
width_b => 8,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq,
address_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa,
data_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia
);
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 <= areset;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq(7 downto 0);
--reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2(REG,425)@35
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,944)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,940)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "010010";
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,941)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,942)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,945)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,946)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--expXIsBias_uid44_atanX_uid8_fpArctanPiTest(LOGICAL,43)@0
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q;
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a = expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b else "0";
--inIsOne_uid45_atanX_uid8_fpArctanPiTest(LOGICAL,44)@0
inIsOne_uid45_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
inIsOne_uid45_atanX_uid8_fpArctanPiTest_b <= expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q;
inIsOne_uid45_atanX_uid8_fpArctanPiTest_q <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_a and inIsOne_uid45_atanX_uid8_fpArctanPiTest_b;
--arctanIsConst_uid55_atanX_uid8_fpArctanPiTest(LOGICAL,54)@0
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_q;
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a or arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c(DELAY,522)@1
ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q, xout => ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasMwShift_uid62_atanX_uid8_fpArctanPiTest(CONSTANT,61)
biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q <= "01110011";
--atanUIsU_uid63_atanX_uid8_fpArctanPiTest(COMPARE,62)@13
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin <= GND_q;
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q) & '0';
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin(0);
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b));
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n(0) <= not atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o(10);
--ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a(DELAY,520)@0
ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => path2_uid56_atanX_uid8_fpArctanPiTest_n, xout => ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--pathSelBits_uid108_atanX_uid8_fpArctanPiTest(BITJOIN,107)@13
pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q <= ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n & ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q;
--reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0(REG,392)@13
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,934)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,936)
-- every=1, low=0, high=18, step=1, init=1
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 17 THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 18;
ELSE
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,5));
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,937)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,938)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,935)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 19,
width_b => 3,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(2 downto 0);
--fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest(LOOKUP,108)@35
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q) IS
WHEN "000" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "001" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "010" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "011" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "110" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "111" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN OTHERS =>
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRCalc_uid113_atanX_uid8_fpArctanPiTest(MUX,112)@36
expRCalc_uid113_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q;
expRCalc_uid113_atanX_uid8_fpArctanPiTest: PROCESS (expRCalc_uid113_atanX_uid8_fpArctanPiTest_s, en, reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q, reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q, ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE expRCalc_uid113_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q;
WHEN "11" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstAllZWE_uid21_atanX_uid8_fpArctanPiTest(CONSTANT,20)
cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q <= "00000000";
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,995)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a or ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,996)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,997)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,985)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid38_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,986)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,982)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,983)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,984)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,972)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q, xout => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,973)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(0 downto 0);
--excSelBits_uid114_atanX_uid8_fpArctanPiTest(BITJOIN,113)@35
excSelBits_uid114_atanX_uid8_fpArctanPiTest_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q & GND_q & ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q;
--reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0(REG,377)@35
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid114_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest(LOOKUP,114)@36
outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid117_atanX_uid8_fpArctanPiTest(MUX,116)@36
expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q;
expRPostExc_uid117_atanX_uid8_fpArctanPiTest: PROCESS (expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, expRCalc_uid113_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid113_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracOutCst_uid110_atanX_uid8_fpArctanPiTest(BITSELECT,109)@35
fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5(REG,424)@35
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor(LOGICAL,968)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q <= not (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a or ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b);
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena(REG,969)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd(LOGICAL,970)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b <= en;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a and ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b;
--fracRPath3_uid88_atanX_uid8_fpArctanPiTest(BITSELECT,87)@31
fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(23 downto 0);
fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in(23 downto 1);
--reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4(REG,423)@31
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,960)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem(DUALMEM,961)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 1,
numwords_a => 2,
width_b => 23,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq,
address_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa,
data_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia
);
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 <= areset;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq(22 downto 0);
--fracRPath2_uid106_atanX_uid8_fpArctanPiTest(BITSELECT,105)@35
fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(23 downto 0);
fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in(23 downto 1);
--reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3(REG,422)@35
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,957)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a or ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,958)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,959)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2(REG,421)@0
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,947)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,948)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 33,
width_b => 23,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(22 downto 0);
--fracRCalc_uid111_atanX_uid8_fpArctanPiTest(MUX,110)@36
fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q;
fracRCalc_uid111_atanX_uid8_fpArctanPiTest: PROCESS (fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s, en, ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q, reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q, reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q;
WHEN "01" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q;
WHEN "11" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid116_atanX_uid8_fpArctanPiTest(MUX,115)@36
fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q;
fracRPostExc_uid116_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid120_atanX_uid8_fpArctanPiTest(BITJOIN,119)@36
R_uid120_atanX_uid8_fpArctanPiTest_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q & expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q & fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q;
--fracX_uid126_rAtanPi_uid13_fpArctanPiTest(BITSELECT,125)@36
fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0);
--reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1(REG,431)@36
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest(LOGICAL,137)@37
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a <= reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q;
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b else "0";
--expX_uid122_rAtanPi_uid13_fpArctanPiTest(BITSELECT,121)@36
expX_uid122_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expX_uid122_rAtanPi_uid13_fpArctanPiTest_b <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23);
--reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1(REG,429)@36
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest(LOGICAL,135)@37
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q;
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b else "0";
--exc_I_uid139_rAtanPi_uid13_fpArctanPiTest(LOGICAL,138)@37
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q;
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q;
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b;
--cstBiasM2_uid6_fpArctanPiTest(CONSTANT,5)
cstBiasM2_uid6_fpArctanPiTest_q <= "01111101";
--ooPi_uid9_fpArctanPiTest(CONSTANT,8)
ooPi_uid9_fpArctanPiTest_q <= "101000101111100110000011";
--fracOOPi_uid10_fpArctanPiTest(BITSELECT,9)@36
fracOOPi_uid10_fpArctanPiTest_in <= ooPi_uid9_fpArctanPiTest_q(22 downto 0);
fracOOPi_uid10_fpArctanPiTest_b <= fracOOPi_uid10_fpArctanPiTest_in(22 downto 0);
--fpOOPi_uid11_fpArctanPiTest(BITJOIN,10)@36
fpOOPi_uid11_fpArctanPiTest_q <= GND_q & cstBiasM2_uid6_fpArctanPiTest_q & fracOOPi_uid10_fpArctanPiTest_b;
--expY_uid123_rAtanPi_uid13_fpArctanPiTest(BITSELECT,122)@36
expY_uid123_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(30 downto 0);
expY_uid123_rAtanPi_uid13_fpArctanPiTest_b <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23);
--expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest(LOGICAL,149)@36
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b;
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a(DELAY,581)@36
ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest(LOGICAL,203)@37
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b;
--fracY_uid128_rAtanPi_uid13_fpArctanPiTest(BITSELECT,127)@36
fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(22 downto 0);
fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0);
--fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest(LOGICAL,153)@36
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b;
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b(DELAY,575)@36
ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest(LOGICAL,151)@36
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b;
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a(DELAY,574)@36
ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid155_rAtanPi_uid13_fpArctanPiTest(LOGICAL,154)@37
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q;
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b <= ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q;
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b;
--expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest(LOGICAL,133)@37
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q;
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b else "0";
--excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest(LOGICAL,204)@37
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b;
--ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest(LOGICAL,205)@37
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q;
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q;
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a or ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b;
--InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest(LOGICAL,155)@36
InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q;
InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a;
--exc_N_uid157_rAtanPi_uid13_fpArctanPiTest(LOGICAL,156)@36
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b;
--ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a(DELAY,579)@36
ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest(LOGICAL,139)@37
InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q;
InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a;
--exc_N_uid141_rAtanPi_uid13_fpArctanPiTest(LOGICAL,140)@37
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b;
--excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest(LOGICAL,206)@37
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c;
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest(LOGICAL,218)@37
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q;
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= not InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a;
END IF;
END PROCESS;
--signY_uid125_rAtanPi_uid13_fpArctanPiTest(BITSELECT,124)@36
signY_uid125_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q;
signY_uid125_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31);
--signX_uid124_rAtanPi_uid13_fpArctanPiTest(BITSELECT,123)@36
signX_uid124_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q;
signX_uid124_rAtanPi_uid13_fpArctanPiTest_b <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31);
--signR_uid190_rAtanPi_uid13_fpArctanPiTest(LOGICAL,189)@36
signR_uid190_rAtanPi_uid13_fpArctanPiTest_a <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_b;
signR_uid190_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_b;
signR_uid190_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= signR_uid190_rAtanPi_uid13_fpArctanPiTest_a xor signR_uid190_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a(DELAY,666)@37
ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid190_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest(LOGICAL,219)@38
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a <= ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q;
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b <= InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q;
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q <= signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a and signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b;
--ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c(DELAY,670)@38
ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest(BITJOIN,128)@36
add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b;
--reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1(REG,433)@36
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest(BITJOIN,126)@36
add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b;
--reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0(REG,432)@36
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--prod_uid165_rAtanPi_uid13_fpArctanPiTest(MULT,164)@37
prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr <= UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_a) * UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_b);
prod_uid165_rAtanPi_uid13_fpArctanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= (others => '0');
prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= (others => '0');
prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q;
prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q;
prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr);
END IF;
END IF;
END PROCESS;
prod_uid165_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1;
END IF;
END IF;
END PROCESS;
--normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest(BITSELECT,165)@40
normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q;
normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in(47 downto 47);
--roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest(CONSTANT,179)
roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q <= "010";
--fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest(BITSELECT,167)@40
fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(46 downto 0);
fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in(46 downto 23);
--fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest(BITSELECT,168)@40
fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(45 downto 0);
fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in(45 downto 22);
--fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest(MUX,169)@40
fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b;
fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s, en, fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b, fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b)
BEGIN
CASE fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "0" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b;
WHEN "1" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b;
WHEN OTHERS => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest(BITSELECT,177)@40
FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in <= fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q(1 downto 0);
FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in(1 downto 0);
--Prod22_uid172_rAtanPi_uid13_fpArctanPiTest(BITSELECT,171)@40
Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(22 downto 0);
Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in(22 downto 22);
--extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest(MUX,172)@40
extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b;
extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest: PROCESS (extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s, en, GND_q, Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b)
BEGIN
CASE extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "0" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b;
WHEN OTHERS => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest(BITSELECT,170)@40
stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(21 downto 0);
stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b <= stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in(21 downto 0);
--stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest(BITJOIN,173)@40
stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q <= extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q & stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b;
--stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest(LOGICAL,175)@40
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a <= stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q;
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q <= "1" when stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a = stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b else "0";
--sticky_uid177_rAtanPi_uid13_fpArctanPiTest(LOGICAL,176)@40
sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a <= stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q;
sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q <= not sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a;
--lrs_uid179_rAtanPi_uid13_fpArctanPiTest(BITJOIN,178)@40
lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b & sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q;
--roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest(LOGICAL,180)@40
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a <= lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q;
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b <= roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q;
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q <= "1" when roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a = roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b else "0";
--roundBit_uid182_rAtanPi_uid13_fpArctanPiTest(LOGICAL,181)@40
roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a <= roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q;
roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q <= not roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a;
--roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest(BITJOIN,184)@40
roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q <= GND_q & normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b & cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q & roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q;
--reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1(REG,436)@40
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--biasInc_uid163_rAtanPi_uid13_fpArctanPiTest(CONSTANT,162)
biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q <= "0001111111";
--ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b(DELAY,586)@36
ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expY_uid123_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expSum_uid162_rAtanPi_uid13_fpArctanPiTest(ADD,161)@37
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q);
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q);
expSum_uid162_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a) + UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q <= expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o(8 downto 0);
--ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a(DELAY,587)@38
ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest(SUB,163)@39
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q);
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q(9)) & biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q);
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b));
END IF;
END IF;
END PROCESS;
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o(10 downto 0);
--expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest(BITJOIN,182)@40
expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q & fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q;
--reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0(REG,435)@40
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest(ADD,185)@41
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q(34)) & reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q);
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q);
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a) + SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b));
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o(35 downto 0);
--expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest(BITSELECT,187)@41
expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q;
expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in(35 downto 24);
--expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest(BITSELECT,188)@41
expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b(7 downto 0);
expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in(7 downto 0);
--ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d(DELAY,664)@41
ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 2 )
PORT MAP ( xin => expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c(DELAY,659)@37
ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1(REG,437)@41
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid193_rAtanPi_uid13_fpArctanPiTest(COMPARE,192)@42
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q;
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & '0';
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q) & expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin(0);
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b));
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o(14);
--InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest(LOGICAL,157)@37
InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q;
InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a;
--InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest(LOGICAL,158)@37
InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a;
--InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest(LOGICAL,159)@37
InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a;
--exc_R_uid161_rAtanPi_uid13_fpArctanPiTest(LOGICAL,160)@37
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c;
--ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b(DELAY,629)@37
ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest(LOGICAL,141)@37
InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a;
--InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest(LOGICAL,142)@37
InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a;
--InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest(LOGICAL,143)@37
InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a;
--exc_R_uid145_rAtanPi_uid13_fpArctanPiTest(LOGICAL,144)@37
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c;
--ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a(DELAY,628)@37
ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest(LOGICAL,201)@42
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c <= expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c;
--excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest(LOGICAL,200)@37
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q;
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q <= excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a and excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c(DELAY,646)@37
ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest(LOGICAL,199)@37
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q;
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q <= excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a and excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b(DELAY,645)@37
ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest(LOGICAL,198)@37
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q <= excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a and excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a(DELAY,644)@37
ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid203_rAtanPi_uid13_fpArctanPiTest(LOGICAL,202)@42
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q <= excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d;
--expUdf_uid191_rAtanPi_uid13_fpArctanPiTest(COMPARE,190)@42
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q;
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0';
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin(0);
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b));
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o(14);
--excZC3_uid197_rAtanPi_uid13_fpArctanPiTest(LOGICAL,196)@42
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c <= expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c;
--excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest(LOGICAL,195)@37
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q;
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c(DELAY,633)@37
ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest(LOGICAL,194)@37
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b(DELAY,632)@37
ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest(LOGICAL,193)@37
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a(DELAY,631)@37
ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid198_rAtanPi_uid13_fpArctanPiTest(LOGICAL,197)@42
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q <= excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d;
--concExc_uid208_rAtanPi_uid13_fpArctanPiTest(BITJOIN,207)@42
concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q <= ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q & excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q & excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q;
--reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0(REG,439)@42
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid209_rAtanPi_uid13_fpArctanPiTest(LOOKUP,208)@43
excREnc_uid209_rAtanPi_uid13_fpArctanPiTest: PROCESS (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q) IS
WHEN "000" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "01";
WHEN "001" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "010" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "10";
WHEN "011" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "100" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "11";
WHEN "101" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "110" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "111" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN OTHERS =>
excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest(MUX,217)@43
expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q;
expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest: PROCESS (expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q;
WHEN "10" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest(BITSELECT,186)@41
fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q(23 downto 0);
fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b <= fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in(23 downto 1);
--ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d(DELAY,662)@41
ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest(MUX,212)@43
fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q;
fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q;
WHEN "10" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid221_rAtanPi_uid13_fpArctanPiTest(BITJOIN,220)@43
R_uid221_rAtanPi_uid13_fpArctanPiTest_q <= ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q & expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q & fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q;
--xOut(GPOUT,4)@43
q <= R_uid221_rAtanPi_uid13_fpArctanPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_atanpi_s5
-- VHDL created on Tue Mar 12 11:23:23 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_atanpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_atanpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBiasM2_uid6_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal ooPi_uid9_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal piO2_uid46_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0);
signal piO4_uid47_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid64_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal zS_uid67_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q : std_logic_vector (12 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a : std_logic_vector (23 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 : std_logic_vector (50 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr : UNSIGNED (50 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q : std_logic_vector (50 downto 0);
signal fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (9 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (10 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector (23 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 : std_logic_vector (47 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr : UNSIGNED (47 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (47 downto 0);
signal roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_q : std_logic_vector (40 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_b : std_logic_vector (21 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_s1 : std_logic_vector (36 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_pr : SIGNED (37 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_q : std_logic_vector (36 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid299_atanXOXTabGen_lutmem_ia : std_logic_vector (30 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_iq : std_logic_vector (30 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_q : std_logic_vector (30 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid300_atanXOXTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid301_atanXOXTabGen_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid344_invTabGen_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid345_invTabGen_lutmem_ia : std_logic_vector (19 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_iq : std_logic_vector (19 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_q : std_logic_vector (19 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid346_invTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q : std_logic_vector (19 downto 0);
signal reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q : std_logic_vector (21 downto 0);
signal reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q : std_logic_vector (28 downto 0);
signal reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q : std_logic_vector (30 downto 0);
signal reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (26 downto 0);
signal reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (8 downto 0);
signal reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (31 downto 0);
signal reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (32 downto 0);
signal reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (22 downto 0);
signal reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (22 downto 0);
signal reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (22 downto 0);
signal reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (7 downto 0);
signal reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (7 downto 0);
signal reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (22 downto 0);
signal reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (23 downto 0);
signal reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (34 downto 0);
signal reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (11 downto 0);
signal reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q : std_logic_vector (7 downto 0);
signal ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (7 downto 0);
signal ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (8 downto 0);
signal ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (22 downto 0);
signal ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (7 downto 0);
signal ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (20 downto 0);
signal ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (18 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q : std_logic_vector (12 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 : std_logic;
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : signal is true;
signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : signal is true;
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : signal is true;
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_c : std_logic_vector (0 downto 0);
signal excSelBits_uid114_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a : std_logic_vector(33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b : std_logic_vector(33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o : std_logic_vector (33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q : std_logic_vector (33 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o : std_logic_vector (32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0);
signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid15_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid15_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid16_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid16_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal singX_uid17_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal singX_uid17_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q : std_logic_vector (9 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_a : std_logic_vector(26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_b : std_logic_vector(26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_o : std_logic_vector (26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (26 downto 0);
signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (35 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal fracOOPi_uid10_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracOOPi_uid10_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid80_atanX_uid8_fpArctanPiTest_in : std_logic_vector (49 downto 0);
signal normBit_uid80_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in : std_logic_vector (48 downto 0);
signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in : std_logic_vector (47 downto 0);
signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (47 downto 0);
signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (46 downto 0);
signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (45 downto 0);
signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (21 downto 0);
signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (21 downto 0);
signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in : std_logic_vector (36 downto 0);
signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b : std_logic_vector (22 downto 0);
signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal R_uid221_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (14 downto 0);
signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (14 downto 0);
signal R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal constOut_uid54_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal constOut_uid54_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal u_uid58_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal u_uid58_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal R_uid120_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (16 downto 0);
signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (8 downto 0);
signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in : std_logic_vector (8 downto 0);
signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in : std_logic_vector (25 downto 0);
signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (11 downto 0);
signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (9 downto 0);
signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (33 downto 0);
signal fpOOPi_uid11_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (32 downto 0);
signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0);
signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (28 downto 0);
signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (24 downto 0);
signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (0 downto 0);
signal stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal lowRangeB_uid304_atanXOXPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid304_atanXOXPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid305_atanXOXPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid305_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid310_atanXOXPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid310_atanXOXPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid311_atanXOXPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid311_atanXOXPolyEval_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid349_invPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid349_invPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid350_invPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid350_invPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid355_invPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid355_invPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid356_invPolyEval_in : std_logic_vector (22 downto 0);
signal highBBits_uid356_invPolyEval_b : std_logic_vector (20 downto 0);
signal y_uid73_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal y_uid73_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0);
signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal yT1_uid347_invPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid347_invPolyEval_b : std_logic_vector (11 downto 0);
signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal expU_uid59_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expU_uid59_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracU_uid60_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracU_uid60_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0);
signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b : std_logic_vector (3 downto 0);
signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (1 downto 0);
signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (34 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_a : std_logic_vector(31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_b : std_logic_vector(31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_o : std_logic_vector (31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_q : std_logic_vector (31 downto 0);
signal sumAHighB_uid351_invPolyEval_a : std_logic_vector(20 downto 0);
signal sumAHighB_uid351_invPolyEval_b : std_logic_vector(20 downto 0);
signal sumAHighB_uid351_invPolyEval_o : std_logic_vector (20 downto 0);
signal sumAHighB_uid351_invPolyEval_q : std_logic_vector (20 downto 0);
signal sumAHighB_uid357_invPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid357_invPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid357_invPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid357_invPolyEval_q : std_logic_vector (29 downto 0);
signal yAddr_uid75_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0);
signal yAddr_uid75_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in : std_logic_vector (26 downto 0);
signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b : std_logic_vector (17 downto 0);
signal rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0);
signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b : std_logic_vector (4 downto 0);
signal expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0);
signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal s1_uid304_uid307_atanXOXPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid310_uid313_atanXOXPolyEval_q : std_logic_vector (33 downto 0);
signal s1_uid349_uid352_invPolyEval_q : std_logic_vector (21 downto 0);
signal s2_uid355_uid358_invPolyEval_q : std_logic_vector (31 downto 0);
signal yT1_uid302_atanXOXPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid302_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (20 downto 0);
signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (18 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0);
signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0);
signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (25 downto 0);
begin
--xIn(GPIN,3)@0
--cstAllZWF_uid19_atanX_uid8_fpArctanPiTest(CONSTANT,18)
cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000000";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable(LOGICAL,878)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q <= not ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,1008)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a or ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,1004)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100001";
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,1005)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,1006)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,1009)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,1010)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--fracX_uid16_atanX_uid8_fpArctanPiTest(BITSELECT,15)@0
fracX_uid16_atanX_uid8_fpArctanPiTest_in <= a(22 downto 0);
fracX_uid16_atanX_uid8_fpArctanPiTest_b <= fracX_uid16_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--fracXIsZero_uid35_atanX_uid8_fpArctanPiTest(LOGICAL,34)@0
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b else "0";
--InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest(LOGICAL,36)@0
InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q <= not InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a;
--cstAllOWE_uid18_atanX_uid8_fpArctanPiTest(CONSTANT,17)
cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q <= "11111111";
--expX_uid15_atanX_uid8_fpArctanPiTest(BITSELECT,14)@0
expX_uid15_atanX_uid8_fpArctanPiTest_in <= a(30 downto 0);
expX_uid15_atanX_uid8_fpArctanPiTest_b <= expX_uid15_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--expXIsMax_uid33_atanX_uid8_fpArctanPiTest(LOGICAL,32)@0
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a = expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b else "0";
--exc_N_uid38_atanX_uid8_fpArctanPiTest(LOGICAL,37)@0
exc_N_uid38_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q;
exc_N_uid38_atanX_uid8_fpArctanPiTest_b <= InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q;
exc_N_uid38_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_a and exc_N_uid38_atanX_uid8_fpArctanPiTest_b;
--InvExc_N_uid118_atanX_uid8_fpArctanPiTest(LOGICAL,117)@0
InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q;
InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q <= not InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a;
--singX_uid17_atanX_uid8_fpArctanPiTest(BITSELECT,16)@0
singX_uid17_atanX_uid8_fpArctanPiTest_in <= a;
singX_uid17_atanX_uid8_fpArctanPiTest_b <= singX_uid17_atanX_uid8_fpArctanPiTest_in(31 downto 31);
--signR_uid119_atanX_uid8_fpArctanPiTest(LOGICAL,118)@0
signR_uid119_atanX_uid8_fpArctanPiTest_a <= singX_uid17_atanX_uid8_fpArctanPiTest_b;
signR_uid119_atanX_uid8_fpArctanPiTest_b <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q;
signR_uid119_atanX_uid8_fpArctanPiTest_q <= signR_uid119_atanX_uid8_fpArctanPiTest_a and signR_uid119_atanX_uid8_fpArctanPiTest_b;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,998)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid119_atanX_uid8_fpArctanPiTest_q, xout => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,1000)
-- every=1, low=0, high=33, step=1, init=1
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 32 THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 33;
ELSE
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6));
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,1001)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,1002)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,999)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 34,
width_b => 1,
widthad_b => 6,
numwords_b => 34,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,879)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a or ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,875)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100000";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,876)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,877)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,880)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,881)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,869)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => singX_uid17_atanX_uid8_fpArctanPiTest_b, xout => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,871)
-- every=1, low=0, high=32, step=1, init=1
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 31 THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 32;
ELSE
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6));
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,872)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,873)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,870)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--cstBias_uid22_atanX_uid8_fpArctanPiTest(CONSTANT,21)
cstBias_uid22_atanX_uid8_fpArctanPiTest_q <= "01111111";
--piO2_uid46_atanX_uid8_fpArctanPiTest(CONSTANT,45)
piO2_uid46_atanX_uid8_fpArctanPiTest_q <= "11001001000011111101101011";
--cstPiO2_uid48_atanX_uid8_fpArctanPiTest(BITSELECT,47)@35
cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in <= piO2_uid46_atanX_uid8_fpArctanPiTest_q(24 downto 0);
cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b <= cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in(24 downto 2);
--fpPiO2C_uid49_atanX_uid8_fpArctanPiTest(BITJOIN,48)@35
fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBias_uid22_atanX_uid8_fpArctanPiTest_q & cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b;
--cstBiasM1_uid23_atanX_uid8_fpArctanPiTest(CONSTANT,22)
cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q <= "01111110";
--piO4_uid47_atanX_uid8_fpArctanPiTest(CONSTANT,46)
piO4_uid47_atanX_uid8_fpArctanPiTest_q <= "110010010000111111011011";
--cstPiO4_uid51_atanX_uid8_fpArctanPiTest(BITSELECT,50)@35
cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in <= piO4_uid47_atanX_uid8_fpArctanPiTest_q(22 downto 0);
cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b <= cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--fpPiO4C_uid52_atanX_uid8_fpArctanPiTest(BITJOIN,51)@35
fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q & cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,892)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a or ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b);
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,893)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,894)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b;
--exc_I_uid36_atanX_uid8_fpArctanPiTest(LOGICAL,35)@0
exc_I_uid36_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q;
exc_I_uid36_atanX_uid8_fpArctanPiTest_b <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
exc_I_uid36_atanX_uid8_fpArctanPiTest_q <= exc_I_uid36_atanX_uid8_fpArctanPiTest_a and exc_I_uid36_atanX_uid8_fpArctanPiTest_b;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,882)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid36_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,883)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq,
address_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa,
data_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia
);
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(0 downto 0);
--constOut_uid54_atanX_uid8_fpArctanPiTest(MUX,53)@35
constOut_uid54_atanX_uid8_fpArctanPiTest_s <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q;
constOut_uid54_atanX_uid8_fpArctanPiTest: PROCESS (constOut_uid54_atanX_uid8_fpArctanPiTest_s, en, fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q, fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE constOut_uid54_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expOutCst_uid112_atanX_uid8_fpArctanPiTest(BITSELECT,111)@35
expOutCst_uid112_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expOutCst_uid112_atanX_uid8_fpArctanPiTest_b <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5(REG,428)@35
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--cst01pWShift_uid69_atanX_uid8_fpArctanPiTest(CONSTANT,68)
cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q <= "0000000000000";
--reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2(REG,389)@0
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= signR_uid119_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c(DELAY,707)@1
ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,1022)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a or ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b);
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top(CONSTANT,1018)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q <= "0111";
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp(LOGICAL,1019)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q);
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q <= "1" when ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a = ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b else "0";
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg(REG,1020)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,1023)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,1024)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b;
--cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,230)
cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111110";
--expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest(SUB,259)@0
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q);
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b);
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b));
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,260)@0
expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0);
expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,229)
cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111101";
--expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest(SUB,256)@0
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q);
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b);
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b));
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,257)@0
expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0);
expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,249)@0
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b else "0";
--expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest(MUX,263)@0
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s <= fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q;
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--expXIsZero_uid31_atanX_uid8_fpArctanPiTest(LOGICAL,30)@0
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a = expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b else "0";
--udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,258)@0
udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in <= STD_LOGIC_VECTOR((9 downto 9 => expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(8)) & expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q);
udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in(9 downto 9);
--InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,245)@0
InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a;
--InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,246)@0
InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a <= expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q;
InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a;
--exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,247)@0
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a <= InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b <= InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c;
--xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,264)@0
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q;
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b;
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a and xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b;
--xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,265)@0
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q;
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q <= xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a or xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b;
--excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,266)@0
excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q & expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q & xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q;
--reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0(REG,378)@0
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest(LOOKUP,267)@1
outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest(MUX,269)@1
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q;
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,1012)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt(COUNTER,1014)
-- every=1, low=0, high=7, step=1, init=1
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg(REG,1015)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux(MUX,1016)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,1013)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia
);
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid20_atanX_uid8_fpArctanPiTest(CONSTANT,19)
cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000001";
--oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,248)@0
oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q <= VCC_q & fracX_uid16_atanX_uid8_fpArctanPiTest_b;
--y_uid251_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,250)@0
y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in <= oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q(22 downto 0);
y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,252)@0
yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b;
yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 15);
--reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0(REG,379)@0
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid346_invTabGen_lutmem(DUALMEM,376)@1
memoryC2_uid346_invTabGen_lutmem_ia <= (others => '0');
memoryC2_uid346_invTabGen_lutmem_aa <= (others => '0');
memoryC2_uid346_invTabGen_lutmem_ab <= reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q;
memoryC2_uid346_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC2_uid346_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid346_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid346_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid346_invTabGen_lutmem_iq,
address_a => memoryC2_uid346_invTabGen_lutmem_aa,
data_a => memoryC2_uid346_invTabGen_lutmem_ia
);
memoryC2_uid346_invTabGen_lutmem_reset0 <= areset;
memoryC2_uid346_invTabGen_lutmem_q <= memoryC2_uid346_invTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1(REG,381)@3
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= memoryC2_uid346_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,1011)
ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a(DELAY,680)@0
ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,253)@3
yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in <= ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q(14 downto 0);
yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in(14 downto 0);
--yT1_uid347_invPolyEval(BITSELECT,346)@3
yT1_uid347_invPolyEval_in <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b;
yT1_uid347_invPolyEval_b <= yT1_uid347_invPolyEval_in(14 downto 3);
--reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0(REG,380)@3
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= yT1_uid347_invPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid366_pT1_uid348_invPolyEval(MULT,365)@4
prodXY_uid366_pT1_uid348_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid366_pT1_uid348_invPolyEval_a),13)) * SIGNED(prodXY_uid366_pT1_uid348_invPolyEval_b);
prodXY_uid366_pT1_uid348_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid366_pT1_uid348_invPolyEval_a <= (others => '0');
prodXY_uid366_pT1_uid348_invPolyEval_b <= (others => '0');
prodXY_uid366_pT1_uid348_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid366_pT1_uid348_invPolyEval_a <= reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q;
prodXY_uid366_pT1_uid348_invPolyEval_b <= reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q;
prodXY_uid366_pT1_uid348_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid366_pT1_uid348_invPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid366_pT1_uid348_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid366_pT1_uid348_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid366_pT1_uid348_invPolyEval_q <= prodXY_uid366_pT1_uid348_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid367_pT1_uid348_invPolyEval(BITSELECT,366)@7
prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in <= prodXY_uid366_pT1_uid348_invPolyEval_q;
prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in(23 downto 11);
--highBBits_uid350_invPolyEval(BITSELECT,349)@7
highBBits_uid350_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b;
highBBits_uid350_invPolyEval_b <= highBBits_uid350_invPolyEval_in(12 downto 1);
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a(DELAY,804)@1
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid345_invTabGen_lutmem(DUALMEM,375)@4
memoryC1_uid345_invTabGen_lutmem_ia <= (others => '0');
memoryC1_uid345_invTabGen_lutmem_aa <= (others => '0');
memoryC1_uid345_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q;
memoryC1_uid345_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 20,
widthad_a => 8,
numwords_a => 256,
width_b => 20,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC1_uid345_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid345_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid345_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid345_invTabGen_lutmem_iq,
address_a => memoryC1_uid345_invTabGen_lutmem_aa,
data_a => memoryC1_uid345_invTabGen_lutmem_ia
);
memoryC1_uid345_invTabGen_lutmem_reset0 <= areset;
memoryC1_uid345_invTabGen_lutmem_q <= memoryC1_uid345_invTabGen_lutmem_iq(19 downto 0);
--reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0(REG,383)@6
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= "00000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= memoryC1_uid345_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid351_invPolyEval(ADD,350)@7
sumAHighB_uid351_invPolyEval_a <= STD_LOGIC_VECTOR((20 downto 20 => reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q(19)) & reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q);
sumAHighB_uid351_invPolyEval_b <= STD_LOGIC_VECTOR((20 downto 12 => highBBits_uid350_invPolyEval_b(11)) & highBBits_uid350_invPolyEval_b);
sumAHighB_uid351_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid351_invPolyEval_a) + SIGNED(sumAHighB_uid351_invPolyEval_b));
sumAHighB_uid351_invPolyEval_q <= sumAHighB_uid351_invPolyEval_o(20 downto 0);
--lowRangeB_uid349_invPolyEval(BITSELECT,348)@7
lowRangeB_uid349_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b(0 downto 0);
lowRangeB_uid349_invPolyEval_b <= lowRangeB_uid349_invPolyEval_in(0 downto 0);
--s1_uid349_uid352_invPolyEval(BITJOIN,351)@7
s1_uid349_uid352_invPolyEval_q <= sumAHighB_uid351_invPolyEval_q & lowRangeB_uid349_invPolyEval_b;
--reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1(REG,385)@7
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= "0000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= s1_uid349_uid352_invPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor(LOGICAL,1059)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a or ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b);
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg(REG,966)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena(REG,1060)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q = "1") THEN
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd(LOGICAL,1061)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b <= en;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg(DELAY,1051)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt(COUNTER,962)
-- every=1, low=0, high=1, step=1, init=1
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i,1));
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg(REG,963)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux(MUX,964)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s <= en;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux: PROCESS (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q)
BEGIN
CASE ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s IS
WHEN "0" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
WHEN "1" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q;
WHEN OTHERS => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem(DUALMEM,1052)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia
);
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0(REG,384)@7
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid369_pT2_uid354_invPolyEval(MULT,368)@8
prodXY_uid369_pT2_uid354_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid369_pT2_uid354_invPolyEval_a),16)) * SIGNED(prodXY_uid369_pT2_uid354_invPolyEval_b);
prodXY_uid369_pT2_uid354_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid369_pT2_uid354_invPolyEval_a <= (others => '0');
prodXY_uid369_pT2_uid354_invPolyEval_b <= (others => '0');
prodXY_uid369_pT2_uid354_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid369_pT2_uid354_invPolyEval_a <= reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q;
prodXY_uid369_pT2_uid354_invPolyEval_b <= reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q;
prodXY_uid369_pT2_uid354_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid369_pT2_uid354_invPolyEval_pr,37));
END IF;
END IF;
END PROCESS;
prodXY_uid369_pT2_uid354_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid369_pT2_uid354_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid369_pT2_uid354_invPolyEval_q <= prodXY_uid369_pT2_uid354_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid370_pT2_uid354_invPolyEval(BITSELECT,369)@11
prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in <= prodXY_uid369_pT2_uid354_invPolyEval_q;
prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in(36 downto 14);
--highBBits_uid356_invPolyEval(BITSELECT,355)@11
highBBits_uid356_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b;
highBBits_uid356_invPolyEval_b <= highBBits_uid356_invPolyEval_in(22 downto 2);
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor(LOGICAL,1048)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q <= not (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a or ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b);
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top(CONSTANT,1031)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q <= "0100";
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp(LOGICAL,1032)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q <= "1" when ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a = ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b else "0";
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg(REG,1033)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena(REG,1049)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd(LOGICAL,1050)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a and ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg(DELAY,1038)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt(COUNTER,1027)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i,3));
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg(REG,1028)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux(MUX,1029)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s <= en;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux: PROCESS (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem(DUALMEM,1039)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq(7 downto 0);
--memoryC0_uid344_invTabGen_lutmem(DUALMEM,374)@8
memoryC0_uid344_invTabGen_lutmem_ia <= (others => '0');
memoryC0_uid344_invTabGen_lutmem_aa <= (others => '0');
memoryC0_uid344_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q;
memoryC0_uid344_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC0_uid344_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid344_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid344_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid344_invTabGen_lutmem_iq,
address_a => memoryC0_uid344_invTabGen_lutmem_aa,
data_a => memoryC0_uid344_invTabGen_lutmem_ia
);
memoryC0_uid344_invTabGen_lutmem_reset0 <= areset;
memoryC0_uid344_invTabGen_lutmem_q <= memoryC0_uid344_invTabGen_lutmem_iq(28 downto 0);
--reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0(REG,387)@10
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= "00000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= memoryC0_uid344_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid357_invPolyEval(ADD,356)@11
sumAHighB_uid357_invPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q(28)) & reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q);
sumAHighB_uid357_invPolyEval_b <= STD_LOGIC_VECTOR((29 downto 21 => highBBits_uid356_invPolyEval_b(20)) & highBBits_uid356_invPolyEval_b);
sumAHighB_uid357_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid357_invPolyEval_a) + SIGNED(sumAHighB_uid357_invPolyEval_b));
sumAHighB_uid357_invPolyEval_q <= sumAHighB_uid357_invPolyEval_o(29 downto 0);
--lowRangeB_uid355_invPolyEval(BITSELECT,354)@11
lowRangeB_uid355_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b(1 downto 0);
lowRangeB_uid355_invPolyEval_b <= lowRangeB_uid355_invPolyEval_in(1 downto 0);
--s2_uid355_uid358_invPolyEval(BITJOIN,357)@11
s2_uid355_uid358_invPolyEval_q <= sumAHighB_uid357_invPolyEval_q & lowRangeB_uid355_invPolyEval_b;
--fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,255)@11
fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in <= s2_uid355_uid358_invPolyEval_q(28 downto 0);
fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in(28 downto 5);
--fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,261)@11
fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b(22 downto 0);
fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,688)@0
ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest(MUX,262)@11
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q;
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1(REG,388)@1
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,701)@2
ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 10 )
PORT MAP ( xin => reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest(MUX,268)@12
fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q;
fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid273_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,272)@12
R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q <= ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q & fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,905)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a or ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,901)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "01001";
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,902)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,903)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,906)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,907)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,895)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,897)
-- every=1, low=0, high=9, step=1, init=1
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 8 THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 9;
ELSE
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,4));
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,898)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,899)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,896)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 4,
numwords_a => 10,
width_b => 32,
widthad_b => 4,
numwords_b => 10,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(31 downto 0);
--path2_uid56_atanX_uid8_fpArctanPiTest(COMPARE,55)@0
path2_uid56_atanX_uid8_fpArctanPiTest_cin <= GND_q;
path2_uid56_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid15_atanX_uid8_fpArctanPiTest_b) & '0';
path2_uid56_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q) & path2_uid56_atanX_uid8_fpArctanPiTest_cin(0);
path2_uid56_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_b));
path2_uid56_atanX_uid8_fpArctanPiTest_n(0) <= not path2_uid56_atanX_uid8_fpArctanPiTest_o(10);
--reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1(REG,390)@0
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= path2_uid56_atanX_uid8_fpArctanPiTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b(DELAY,466)@1
ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--u_uid58_atanX_uid8_fpArctanPiTest(MUX,57)@12
u_uid58_atanX_uid8_fpArctanPiTest_s <= ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q;
u_uid58_atanX_uid8_fpArctanPiTest: PROCESS (u_uid58_atanX_uid8_fpArctanPiTest_s, en, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q, R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE u_uid58_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => u_uid58_atanX_uid8_fpArctanPiTest_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q;
WHEN "1" => u_uid58_atanX_uid8_fpArctanPiTest_q <= R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => u_uid58_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracU_uid60_atanX_uid8_fpArctanPiTest(BITSELECT,59)@12
fracU_uid60_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracU_uid60_atanX_uid8_fpArctanPiTest_b <= fracU_uid60_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a(DELAY,471)@12
ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracU_uid60_atanX_uid8_fpArctanPiTest_b, xout => ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest(BITJOIN,60)@13
oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q;
--oFracUExt_uid70_atanX_uid8_fpArctanPiTest(BITJOIN,69)@13
oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q <= cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q & oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q;
--X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,282)@13
X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(24 downto 0);
X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(24 downto 0);
--leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,281)
leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000000000000";
--leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,283)@13
leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5(REG,399)@13
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,279)@13
X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(28 downto 0);
X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(28 downto 0);
--leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,280)@13
leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4(REG,398)@13
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,276)@13
X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(32 downto 0);
X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(32 downto 0);
--leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,275)
leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "0000";
--leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,277)@13
leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3(REG,397)@13
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,396)@13
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--zS_uid67_atanX_uid8_fpArctanPiTest(CONSTANT,66)
zS_uid67_atanX_uid8_fpArctanPiTest_q <= "000000000";
--shiftBias_uid64_atanX_uid8_fpArctanPiTest(CONSTANT,63)
shiftBias_uid64_atanX_uid8_fpArctanPiTest_q <= "01110010";
--expU_uid59_atanX_uid8_fpArctanPiTest(BITSELECT,58)@12
expU_uid59_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expU_uid59_atanX_uid8_fpArctanPiTest_b <= expU_uid59_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1(REG,391)@12
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= expU_uid59_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--shiftValue_uid65_atanX_uid8_fpArctanPiTest(SUB,64)@13
shiftValue_uid65_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q);
shiftValue_uid65_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid64_atanX_uid8_fpArctanPiTest_q);
shiftValue_uid65_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_b));
shiftValue_uid65_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--ShiftValue8_uid66_atanX_uid8_fpArctanPiTest(BITSELECT,65)@13
ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q;
ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in(8 downto 8);
--shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest(MUX,67)@13
shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b;
shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest: PROCESS (shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s, en, shiftValue_uid65_atanX_uid8_fpArctanPiTest_q, zS_uid67_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= zS_uid67_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest(BITSELECT,70)@13
fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in <= shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q(3 downto 0);
fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,284)@13
leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b;
leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,395)@13
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,285)@14
leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q;
leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q, reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q, reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q;
WHEN "11" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,293)@14
LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(33 downto 0);
LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(33 downto 0);
--ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,725)@14
ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,292)
leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000";
--leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,294)@15
leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,290)@14
LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(34 downto 0);
LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(34 downto 0);
--ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,723)@14
ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,289)
leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "00";
--leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,291)@15
leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,287)@14
LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0);
LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(35 downto 0);
--ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,721)@14
ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,288)@15
leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & GND_q;
--reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,401)@14
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,295)@13
leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a(DELAY,829)@13
ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,400)@14
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,296)@15
leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q;
leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid73_atanX_uid8_fpArctanPiTest(BITSELECT,72)@15
y_uid73_atanX_uid8_fpArctanPiTest_in <= leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0);
y_uid73_atanX_uid8_fpArctanPiTest_b <= y_uid73_atanX_uid8_fpArctanPiTest_in(35 downto 1);
--yAddr_uid75_atanX_uid8_fpArctanPiTest(BITSELECT,74)@15
yAddr_uid75_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b;
yAddr_uid75_atanX_uid8_fpArctanPiTest_b <= yAddr_uid75_atanX_uid8_fpArctanPiTest_in(34 downto 27);
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0(REG,402)@15
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= yAddr_uid75_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid301_atanXOXTabGen_lutmem(DUALMEM,373)@16
memoryC2_uid301_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC2_uid301_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC2_uid301_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q;
memoryC2_uid301_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC2_uid301_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid301_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid301_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid301_atanXOXTabGen_lutmem_iq,
address_a => memoryC2_uid301_atanXOXTabGen_lutmem_aa,
data_a => memoryC2_uid301_atanXOXTabGen_lutmem_ia
);
memoryC2_uid301_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC2_uid301_atanXOXTabGen_lutmem_q <= memoryC2_uid301_atanXOXTabGen_lutmem_iq(12 downto 0);
--reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1(REG,404)@18
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= memoryC2_uid301_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--yPPolyEval_uid76_atanX_uid8_fpArctanPiTest(BITSELECT,75)@15
yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b(26 downto 0);
yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in(26 downto 9);
--yT1_uid302_atanXOXPolyEval(BITSELECT,301)@15
yT1_uid302_atanXOXPolyEval_in <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b;
yT1_uid302_atanXOXPolyEval_b <= yT1_uid302_atanXOXPolyEval_in(17 downto 5);
--ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg(DELAY,1062)
ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid302_atanXOXPolyEval_b, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a(DELAY,832)@15
ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0(REG,403)@18
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid360_pT1_uid303_atanXOXPolyEval(MULT,359)@19
prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_a),14)) * SIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_b);
prodXY_uid360_pT1_uid303_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= (others => '0');
prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= (others => '0');
prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q;
prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q;
prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid360_pT1_uid303_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval(BITSELECT,360)@22
prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_q;
prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in(25 downto 12);
--highBBits_uid305_atanXOXPolyEval(BITSELECT,304)@22
highBBits_uid305_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b;
highBBits_uid305_atanXOXPolyEval_b <= highBBits_uid305_atanXOXPolyEval_in(13 downto 1);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a(DELAY,834)@15
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0(REG,405)@18
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid300_atanXOXTabGen_lutmem(DUALMEM,372)@19
memoryC1_uid300_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC1_uid300_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC1_uid300_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q;
memoryC1_uid300_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC1_uid300_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid300_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid300_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid300_atanXOXTabGen_lutmem_iq,
address_a => memoryC1_uid300_atanXOXTabGen_lutmem_aa,
data_a => memoryC1_uid300_atanXOXTabGen_lutmem_ia
);
memoryC1_uid300_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC1_uid300_atanXOXTabGen_lutmem_q <= memoryC1_uid300_atanXOXTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0(REG,406)@21
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= memoryC1_uid300_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid306_atanXOXPolyEval(ADD,305)@22
sumAHighB_uid306_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q(20)) & reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q);
sumAHighB_uid306_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid305_atanXOXPolyEval_b(12)) & highBBits_uid305_atanXOXPolyEval_b);
sumAHighB_uid306_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid306_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid306_atanXOXPolyEval_b));
sumAHighB_uid306_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_o(21 downto 0);
--lowRangeB_uid304_atanXOXPolyEval(BITSELECT,303)@22
lowRangeB_uid304_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b(0 downto 0);
lowRangeB_uid304_atanXOXPolyEval_b <= lowRangeB_uid304_atanXOXPolyEval_in(0 downto 0);
--s1_uid304_uid307_atanXOXPolyEval(BITJOIN,306)@22
s1_uid304_uid307_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_q & lowRangeB_uid304_atanXOXPolyEval_b;
--reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1(REG,408)@22
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= s1_uid304_uid307_atanXOXPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor(LOGICAL,1035)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q <= not (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a or ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b);
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena(REG,1036)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd(LOGICAL,1037)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b <= en;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a and ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b;
--reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0(REG,407)@15
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg(DELAY,1025)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q, xout => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem(DUALMEM,1026)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq,
address_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa,
data_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia
);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid363_pT2_uid309_atanXOXPolyEval(MULT,362)@23
prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_a),19)) * SIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_b);
prodXY_uid363_pT2_uid309_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= (others => '0');
prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= (others => '0');
prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q;
prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q;
prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid363_pT2_uid309_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval(BITSELECT,363)@26
prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_q;
prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in(40 downto 17);
--highBBits_uid311_atanXOXPolyEval(BITSELECT,310)@26
highBBits_uid311_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b;
highBBits_uid311_atanXOXPolyEval_b <= highBBits_uid311_atanXOXPolyEval_in(23 downto 2);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor(LOGICAL,1073)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q <= not (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a or ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena(REG,1074)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q = "1") THEN
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd(LOGICAL,1075)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b <= en;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a and ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b;
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg(DELAY,1063)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem(DUALMEM,1064)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia
);
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0(REG,409)@22
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid299_atanXOXTabGen_lutmem(DUALMEM,371)@23
memoryC0_uid299_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC0_uid299_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC0_uid299_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q;
memoryC0_uid299_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 31,
widthad_a => 8,
numwords_a => 256,
width_b => 31,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC0_uid299_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid299_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid299_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid299_atanXOXTabGen_lutmem_iq,
address_a => memoryC0_uid299_atanXOXTabGen_lutmem_aa,
data_a => memoryC0_uid299_atanXOXTabGen_lutmem_ia
);
memoryC0_uid299_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC0_uid299_atanXOXTabGen_lutmem_q <= memoryC0_uid299_atanXOXTabGen_lutmem_iq(30 downto 0);
--reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0(REG,410)@25
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= memoryC0_uid299_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid312_atanXOXPolyEval(ADD,311)@26
sumAHighB_uid312_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((31 downto 31 => reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q(30)) & reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q);
sumAHighB_uid312_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((31 downto 22 => highBBits_uid311_atanXOXPolyEval_b(21)) & highBBits_uid311_atanXOXPolyEval_b);
sumAHighB_uid312_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid312_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid312_atanXOXPolyEval_b));
sumAHighB_uid312_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_o(31 downto 0);
--lowRangeB_uid310_atanXOXPolyEval(BITSELECT,309)@26
lowRangeB_uid310_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b(1 downto 0);
lowRangeB_uid310_atanXOXPolyEval_b <= lowRangeB_uid310_atanXOXPolyEval_in(1 downto 0);
--s2_uid310_uid313_atanXOXPolyEval(BITJOIN,312)@26
s2_uid310_uid313_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_q & lowRangeB_uid310_atanXOXPolyEval_b;
--fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest(BITSELECT,77)@26
fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in <= s2_uid310_uid313_atanXOXPolyEval_q(31 downto 0);
fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in(31 downto 5);
--reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1(REG,412)@26
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,918)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,914)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01010";
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,915)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,916)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,919)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,920)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0(REG,411)@13
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,908)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,910)
-- every=1, low=0, high=10, step=1, init=1
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 9 THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 10;
ELSE
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4));
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,911)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,912)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,909)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 11,
width_b => 24,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(23 downto 0);
--mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest(MULT,78)@27
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr <= UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a) * UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b);
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= (others => '0');
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= (others => '0');
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr);
END IF;
END IF;
END PROCESS;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid80_atanX_uid8_fpArctanPiTest(BITSELECT,79)@30
normBit_uid80_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(49 downto 0);
normBit_uid80_atanX_uid8_fpArctanPiTest_b <= normBit_uid80_atanX_uid8_fpArctanPiTest_in(49 downto 49);
--InvNormBit_uid84_atanX_uid8_fpArctanPiTest(LOGICAL,83)@30
InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a <= normBit_uid80_atanX_uid8_fpArctanPiTest_b;
InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q <= not InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,931)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,927)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01111";
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,928)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,929)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,932)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,933)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,921)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expU_uid59_atanX_uid8_fpArctanPiTest_b, xout => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,923)
-- every=1, low=0, high=15, step=1, init=1
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4));
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,924)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,925)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,922)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 16,
width_b => 8,
widthad_b => 4,
numwords_b => 16,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(7 downto 0);
--expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest(SUB,84)@30
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q);
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000" & InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q);
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b));
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--fracRPath3High_uid81_atanX_uid8_fpArctanPiTest(BITSELECT,80)@30
fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(48 downto 0);
fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in(48 downto 25);
--fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest(BITSELECT,81)@30
fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(47 downto 0);
fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in(47 downto 24);
--fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest(MUX,82)@30
fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s <= normBit_uid80_atanX_uid8_fpArctanPiTest_b;
fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s, en, fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b, fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b)
BEGIN
CASE fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest(BITJOIN,85)@30
expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q & fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q;
--reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0(REG,420)@30
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest(ADD,86)@31
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q);
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000" & VCC_q);
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b));
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o(33 downto 0);
--expRPath3_uid89_atanX_uid8_fpArctanPiTest(BITSELECT,88)@31
expRPath3_uid89_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(31 downto 0);
expRPath3_uid89_atanX_uid8_fpArctanPiTest_b <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_in(31 downto 24);
--reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4(REG,427)@31
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,971)
ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e(DELAY,534)@32
ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,337)@33
RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 1);
--rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,339)@33
rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= GND_q & RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,333)
rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000";
--rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,322)
rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000000000000000000000";
--X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,321)@32
X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 24);
--rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,323)@32
rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,319)
rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "0000000000000000";
--X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,318)@32
X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 16);
--rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,320)@32
rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,315)@32
X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 8);
--rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,317)@32
rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q & X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a(DELAY,504)@30
ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q, xout => ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest(BITJOIN,93)@32
oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q;
--cstWFP2_uid25_atanX_uid8_fpArctanPiTest(CONSTANT,24)
cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q <= "00011001";
--reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1(REG,413)@30
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest(SUB,89)@31
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q);
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR((10 downto 9 => reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q(8)) & reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q);
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a) - SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b));
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o(9 downto 0);
--shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest(BITSELECT,91)@31
shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q(7 downto 0);
shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest(CONSTANT,23)
cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q <= "01101000";
--shiftOut_uid91_atanX_uid8_fpArctanPiTest(COMPARE,90)@13
shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin <= GND_q;
shiftOut_uid91_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & '0';
shiftOut_uid91_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q) & shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin(0);
shiftOut_uid91_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_b));
shiftOut_uid91_atanX_uid8_fpArctanPiTest_c(0) <= shiftOut_uid91_atanX_uid8_fpArctanPiTest_o(10);
--ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b(DELAY,502)@13
ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => shiftOut_uid91_atanX_uid8_fpArctanPiTest_c, xout => ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--sValPostSOut_uid93_atanX_uid8_fpArctanPiTest(MUX,92)@31
sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s <= ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q;
sValPostSOut_uid93_atanX_uid8_fpArctanPiTest: PROCESS (sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s, en, shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b, cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest(BITSELECT,94)@31
sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in <= sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q(4 downto 0);
sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,324)@31
rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b;
rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,414)@31
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,325)@32
rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q;
rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,332)@32
RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 6);
--ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,762)@32
ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,334)@33
rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,329)@32
RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 4);
--ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,760)@32
ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 21, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,331)@33
rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,326)@32
RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 2);
--ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,758)@32
ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,328)@33
rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2(REG,416)@32
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,335)@31
rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(2 downto 1);
--ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a(DELAY,844)@31
ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,415)@32
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,336)@33
rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q;
rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q, rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,340)@31
rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,417)@31
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b(DELAY,772)@32
ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,341)@33
rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q;
rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest(BITJOIN,96)@33
pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & GND_q;
--reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1(REG,418)@33
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--path2Diff_uid97_atanX_uid8_fpArctanPiTest(SUB,97)@34
path2Diff_uid97_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & piO2_uid46_atanX_uid8_fpArctanPiTest_q);
path2Diff_uid97_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q);
path2Diff_uid97_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_b));
path2Diff_uid97_atanX_uid8_fpArctanPiTest_q <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_o(26 downto 0);
--normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest(BITSELECT,98)@34
normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(25 downto 0);
normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in(25 downto 25);
--expRPath2_uid103_atanX_uid8_fpArctanPiTest(MUX,102)@34
expRPath2_uid103_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b;
expRPath2_uid103_atanX_uid8_fpArctanPiTest: PROCESS (expRPath2_uid103_atanX_uid8_fpArctanPiTest_s, en, cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q, cstBias_uid22_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPath2_uid103_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest(BITSELECT,99)@34
path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(24 downto 0);
path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in(24 downto 1);
--path2DiffLow_uid101_atanX_uid8_fpArctanPiTest(BITSELECT,100)@34
path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(23 downto 0);
path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in(23 downto 0);
--fracRPath2_uid102_atanX_uid8_fpArctanPiTest(MUX,101)@34
fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b;
fracRPath2_uid102_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s, en, path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b, path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b)
BEGIN
CASE fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest(BITJOIN,103)@34
expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q <= expRPath2_uid103_atanX_uid8_fpArctanPiTest_q & fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q;
--reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0(REG,419)@34
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest(ADD,104)@35
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q);
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000" & VCC_q);
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b));
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o(32 downto 0);
--expRPath2_uid107_atanX_uid8_fpArctanPiTest(BITSELECT,106)@35
expRPath2_uid107_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(31 downto 0);
expRPath2_uid107_atanX_uid8_fpArctanPiTest_b <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_in(31 downto 24);
--reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3(REG,426)@35
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor(LOGICAL,1086)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q <= not (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a or ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b);
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena(REG,1087)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q = "1") THEN
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd(LOGICAL,1088)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b <= en;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a and ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg(DELAY,1076)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid15_atanX_uid8_fpArctanPiTest_b, xout => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem(DUALMEM,1077)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 33,
width_b => 8,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq,
address_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa,
data_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia
);
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 <= areset;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq(7 downto 0);
--reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2(REG,425)@35
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,944)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,940)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "010010";
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,941)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,942)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,945)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,946)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--expXIsBias_uid44_atanX_uid8_fpArctanPiTest(LOGICAL,43)@0
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q;
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a = expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b else "0";
--inIsOne_uid45_atanX_uid8_fpArctanPiTest(LOGICAL,44)@0
inIsOne_uid45_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
inIsOne_uid45_atanX_uid8_fpArctanPiTest_b <= expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q;
inIsOne_uid45_atanX_uid8_fpArctanPiTest_q <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_a and inIsOne_uid45_atanX_uid8_fpArctanPiTest_b;
--arctanIsConst_uid55_atanX_uid8_fpArctanPiTest(LOGICAL,54)@0
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_q;
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a or arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c(DELAY,522)@1
ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q, xout => ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasMwShift_uid62_atanX_uid8_fpArctanPiTest(CONSTANT,61)
biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q <= "01110011";
--atanUIsU_uid63_atanX_uid8_fpArctanPiTest(COMPARE,62)@13
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin <= GND_q;
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q) & '0';
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin(0);
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b));
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n(0) <= not atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o(10);
--ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a(DELAY,520)@0
ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => path2_uid56_atanX_uid8_fpArctanPiTest_n, xout => ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--pathSelBits_uid108_atanX_uid8_fpArctanPiTest(BITJOIN,107)@13
pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q <= ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n & ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q;
--reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0(REG,392)@13
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,934)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,936)
-- every=1, low=0, high=18, step=1, init=1
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 17 THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 18;
ELSE
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,5));
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,937)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,938)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,935)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 19,
width_b => 3,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(2 downto 0);
--fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest(LOOKUP,108)@35
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q) IS
WHEN "000" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "001" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "010" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "011" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "110" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "111" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN OTHERS =>
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRCalc_uid113_atanX_uid8_fpArctanPiTest(MUX,112)@36
expRCalc_uid113_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q;
expRCalc_uid113_atanX_uid8_fpArctanPiTest: PROCESS (expRCalc_uid113_atanX_uid8_fpArctanPiTest_s, en, reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q, reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q, ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE expRCalc_uid113_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q;
WHEN "11" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstAllZWE_uid21_atanX_uid8_fpArctanPiTest(CONSTANT,20)
cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q <= "00000000";
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,995)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a or ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,996)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,997)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,985)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid38_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,986)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,982)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,983)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,984)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,972)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q, xout => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,973)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(0 downto 0);
--excSelBits_uid114_atanX_uid8_fpArctanPiTest(BITJOIN,113)@35
excSelBits_uid114_atanX_uid8_fpArctanPiTest_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q & GND_q & ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q;
--reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0(REG,377)@35
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid114_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest(LOOKUP,114)@36
outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid117_atanX_uid8_fpArctanPiTest(MUX,116)@36
expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q;
expRPostExc_uid117_atanX_uid8_fpArctanPiTest: PROCESS (expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, expRCalc_uid113_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid113_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracOutCst_uid110_atanX_uid8_fpArctanPiTest(BITSELECT,109)@35
fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5(REG,424)@35
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor(LOGICAL,968)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q <= not (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a or ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b);
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena(REG,969)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd(LOGICAL,970)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b <= en;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a and ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b;
--fracRPath3_uid88_atanX_uid8_fpArctanPiTest(BITSELECT,87)@31
fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(23 downto 0);
fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in(23 downto 1);
--reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4(REG,423)@31
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,960)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem(DUALMEM,961)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 1,
numwords_a => 2,
width_b => 23,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq,
address_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa,
data_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia
);
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 <= areset;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq(22 downto 0);
--fracRPath2_uid106_atanX_uid8_fpArctanPiTest(BITSELECT,105)@35
fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(23 downto 0);
fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in(23 downto 1);
--reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3(REG,422)@35
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,957)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a or ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,958)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,959)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2(REG,421)@0
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,947)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,948)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 33,
width_b => 23,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(22 downto 0);
--fracRCalc_uid111_atanX_uid8_fpArctanPiTest(MUX,110)@36
fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q;
fracRCalc_uid111_atanX_uid8_fpArctanPiTest: PROCESS (fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s, en, ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q, reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q, reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q;
WHEN "01" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q;
WHEN "11" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid116_atanX_uid8_fpArctanPiTest(MUX,115)@36
fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q;
fracRPostExc_uid116_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid120_atanX_uid8_fpArctanPiTest(BITJOIN,119)@36
R_uid120_atanX_uid8_fpArctanPiTest_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q & expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q & fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q;
--fracX_uid126_rAtanPi_uid13_fpArctanPiTest(BITSELECT,125)@36
fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0);
--reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1(REG,431)@36
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest(LOGICAL,137)@37
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a <= reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q;
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b else "0";
--expX_uid122_rAtanPi_uid13_fpArctanPiTest(BITSELECT,121)@36
expX_uid122_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expX_uid122_rAtanPi_uid13_fpArctanPiTest_b <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23);
--reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1(REG,429)@36
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest(LOGICAL,135)@37
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q;
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b else "0";
--exc_I_uid139_rAtanPi_uid13_fpArctanPiTest(LOGICAL,138)@37
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q;
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q;
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b;
--cstBiasM2_uid6_fpArctanPiTest(CONSTANT,5)
cstBiasM2_uid6_fpArctanPiTest_q <= "01111101";
--ooPi_uid9_fpArctanPiTest(CONSTANT,8)
ooPi_uid9_fpArctanPiTest_q <= "101000101111100110000011";
--fracOOPi_uid10_fpArctanPiTest(BITSELECT,9)@36
fracOOPi_uid10_fpArctanPiTest_in <= ooPi_uid9_fpArctanPiTest_q(22 downto 0);
fracOOPi_uid10_fpArctanPiTest_b <= fracOOPi_uid10_fpArctanPiTest_in(22 downto 0);
--fpOOPi_uid11_fpArctanPiTest(BITJOIN,10)@36
fpOOPi_uid11_fpArctanPiTest_q <= GND_q & cstBiasM2_uid6_fpArctanPiTest_q & fracOOPi_uid10_fpArctanPiTest_b;
--expY_uid123_rAtanPi_uid13_fpArctanPiTest(BITSELECT,122)@36
expY_uid123_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(30 downto 0);
expY_uid123_rAtanPi_uid13_fpArctanPiTest_b <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23);
--expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest(LOGICAL,149)@36
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b;
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a(DELAY,581)@36
ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest(LOGICAL,203)@37
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b;
--fracY_uid128_rAtanPi_uid13_fpArctanPiTest(BITSELECT,127)@36
fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(22 downto 0);
fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0);
--fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest(LOGICAL,153)@36
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b;
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b(DELAY,575)@36
ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest(LOGICAL,151)@36
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b;
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a(DELAY,574)@36
ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid155_rAtanPi_uid13_fpArctanPiTest(LOGICAL,154)@37
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q;
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b <= ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q;
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b;
--expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest(LOGICAL,133)@37
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q;
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b else "0";
--excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest(LOGICAL,204)@37
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b;
--ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest(LOGICAL,205)@37
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q;
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q;
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a or ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b;
--InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest(LOGICAL,155)@36
InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q;
InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a;
--exc_N_uid157_rAtanPi_uid13_fpArctanPiTest(LOGICAL,156)@36
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b;
--ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a(DELAY,579)@36
ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest(LOGICAL,139)@37
InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q;
InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a;
--exc_N_uid141_rAtanPi_uid13_fpArctanPiTest(LOGICAL,140)@37
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b;
--excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest(LOGICAL,206)@37
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c;
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest(LOGICAL,218)@37
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q;
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= not InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a;
END IF;
END PROCESS;
--signY_uid125_rAtanPi_uid13_fpArctanPiTest(BITSELECT,124)@36
signY_uid125_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q;
signY_uid125_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31);
--signX_uid124_rAtanPi_uid13_fpArctanPiTest(BITSELECT,123)@36
signX_uid124_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q;
signX_uid124_rAtanPi_uid13_fpArctanPiTest_b <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31);
--signR_uid190_rAtanPi_uid13_fpArctanPiTest(LOGICAL,189)@36
signR_uid190_rAtanPi_uid13_fpArctanPiTest_a <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_b;
signR_uid190_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_b;
signR_uid190_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= signR_uid190_rAtanPi_uid13_fpArctanPiTest_a xor signR_uid190_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a(DELAY,666)@37
ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid190_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest(LOGICAL,219)@38
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a <= ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q;
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b <= InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q;
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q <= signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a and signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b;
--ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c(DELAY,670)@38
ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest(BITJOIN,128)@36
add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b;
--reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1(REG,433)@36
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest(BITJOIN,126)@36
add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b;
--reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0(REG,432)@36
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--prod_uid165_rAtanPi_uid13_fpArctanPiTest(MULT,164)@37
prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr <= UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_a) * UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_b);
prod_uid165_rAtanPi_uid13_fpArctanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= (others => '0');
prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= (others => '0');
prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q;
prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q;
prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr);
END IF;
END IF;
END PROCESS;
prod_uid165_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1;
END IF;
END IF;
END PROCESS;
--normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest(BITSELECT,165)@40
normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q;
normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in(47 downto 47);
--roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest(CONSTANT,179)
roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q <= "010";
--fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest(BITSELECT,167)@40
fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(46 downto 0);
fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in(46 downto 23);
--fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest(BITSELECT,168)@40
fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(45 downto 0);
fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in(45 downto 22);
--fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest(MUX,169)@40
fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b;
fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s, en, fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b, fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b)
BEGIN
CASE fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "0" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b;
WHEN "1" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b;
WHEN OTHERS => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest(BITSELECT,177)@40
FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in <= fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q(1 downto 0);
FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in(1 downto 0);
--Prod22_uid172_rAtanPi_uid13_fpArctanPiTest(BITSELECT,171)@40
Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(22 downto 0);
Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in(22 downto 22);
--extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest(MUX,172)@40
extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b;
extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest: PROCESS (extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s, en, GND_q, Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b)
BEGIN
CASE extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "0" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b;
WHEN OTHERS => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest(BITSELECT,170)@40
stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(21 downto 0);
stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b <= stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in(21 downto 0);
--stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest(BITJOIN,173)@40
stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q <= extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q & stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b;
--stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest(LOGICAL,175)@40
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a <= stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q;
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q <= "1" when stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a = stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b else "0";
--sticky_uid177_rAtanPi_uid13_fpArctanPiTest(LOGICAL,176)@40
sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a <= stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q;
sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q <= not sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a;
--lrs_uid179_rAtanPi_uid13_fpArctanPiTest(BITJOIN,178)@40
lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b & sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q;
--roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest(LOGICAL,180)@40
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a <= lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q;
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b <= roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q;
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q <= "1" when roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a = roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b else "0";
--roundBit_uid182_rAtanPi_uid13_fpArctanPiTest(LOGICAL,181)@40
roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a <= roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q;
roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q <= not roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a;
--roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest(BITJOIN,184)@40
roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q <= GND_q & normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b & cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q & roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q;
--reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1(REG,436)@40
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--biasInc_uid163_rAtanPi_uid13_fpArctanPiTest(CONSTANT,162)
biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q <= "0001111111";
--ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b(DELAY,586)@36
ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expY_uid123_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expSum_uid162_rAtanPi_uid13_fpArctanPiTest(ADD,161)@37
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q);
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q);
expSum_uid162_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a) + UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q <= expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o(8 downto 0);
--ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a(DELAY,587)@38
ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest(SUB,163)@39
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q);
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q(9)) & biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q);
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b));
END IF;
END IF;
END PROCESS;
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o(10 downto 0);
--expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest(BITJOIN,182)@40
expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q & fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q;
--reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0(REG,435)@40
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest(ADD,185)@41
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q(34)) & reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q);
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q);
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a) + SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b));
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o(35 downto 0);
--expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest(BITSELECT,187)@41
expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q;
expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in(35 downto 24);
--expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest(BITSELECT,188)@41
expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b(7 downto 0);
expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in(7 downto 0);
--ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d(DELAY,664)@41
ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 2 )
PORT MAP ( xin => expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c(DELAY,659)@37
ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1(REG,437)@41
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid193_rAtanPi_uid13_fpArctanPiTest(COMPARE,192)@42
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q;
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & '0';
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q) & expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin(0);
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b));
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o(14);
--InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest(LOGICAL,157)@37
InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q;
InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a;
--InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest(LOGICAL,158)@37
InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a;
--InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest(LOGICAL,159)@37
InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a;
--exc_R_uid161_rAtanPi_uid13_fpArctanPiTest(LOGICAL,160)@37
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c;
--ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b(DELAY,629)@37
ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest(LOGICAL,141)@37
InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a;
--InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest(LOGICAL,142)@37
InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a;
--InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest(LOGICAL,143)@37
InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a;
--exc_R_uid145_rAtanPi_uid13_fpArctanPiTest(LOGICAL,144)@37
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c;
--ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a(DELAY,628)@37
ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest(LOGICAL,201)@42
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c <= expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c;
--excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest(LOGICAL,200)@37
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q;
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q <= excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a and excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c(DELAY,646)@37
ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest(LOGICAL,199)@37
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q;
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q <= excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a and excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b(DELAY,645)@37
ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest(LOGICAL,198)@37
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q <= excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a and excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a(DELAY,644)@37
ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid203_rAtanPi_uid13_fpArctanPiTest(LOGICAL,202)@42
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q <= excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d;
--expUdf_uid191_rAtanPi_uid13_fpArctanPiTest(COMPARE,190)@42
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q;
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0';
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin(0);
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b));
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o(14);
--excZC3_uid197_rAtanPi_uid13_fpArctanPiTest(LOGICAL,196)@42
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c <= expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c;
--excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest(LOGICAL,195)@37
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q;
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c(DELAY,633)@37
ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest(LOGICAL,194)@37
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b(DELAY,632)@37
ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest(LOGICAL,193)@37
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a(DELAY,631)@37
ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid198_rAtanPi_uid13_fpArctanPiTest(LOGICAL,197)@42
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q <= excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d;
--concExc_uid208_rAtanPi_uid13_fpArctanPiTest(BITJOIN,207)@42
concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q <= ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q & excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q & excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q;
--reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0(REG,439)@42
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid209_rAtanPi_uid13_fpArctanPiTest(LOOKUP,208)@43
excREnc_uid209_rAtanPi_uid13_fpArctanPiTest: PROCESS (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q) IS
WHEN "000" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "01";
WHEN "001" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "010" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "10";
WHEN "011" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "100" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "11";
WHEN "101" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "110" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "111" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN OTHERS =>
excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest(MUX,217)@43
expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q;
expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest: PROCESS (expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q;
WHEN "10" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest(BITSELECT,186)@41
fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q(23 downto 0);
fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b <= fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in(23 downto 1);
--ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d(DELAY,662)@41
ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest(MUX,212)@43
fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q;
fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q;
WHEN "10" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid221_rAtanPi_uid13_fpArctanPiTest(BITJOIN,220)@43
R_uid221_rAtanPi_uid13_fpArctanPiTest_q <= ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q & expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q & fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q;
--xOut(GPOUT,4)@43
q <= R_uid221_rAtanPi_uid13_fpArctanPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_atanpi_s5
-- VHDL created on Tue Mar 12 11:23:23 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_atanpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_atanpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBiasM2_uid6_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal ooPi_uid9_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal piO2_uid46_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0);
signal piO4_uid47_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid64_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal zS_uid67_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q : std_logic_vector (12 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a : std_logic_vector (23 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 : std_logic_vector (50 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr : UNSIGNED (50 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q : std_logic_vector (50 downto 0);
signal fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (9 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (10 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector (23 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 : std_logic_vector (47 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr : UNSIGNED (47 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (47 downto 0);
signal roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_q : std_logic_vector (40 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_b : std_logic_vector (21 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_s1 : std_logic_vector (36 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_pr : SIGNED (37 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_q : std_logic_vector (36 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid299_atanXOXTabGen_lutmem_ia : std_logic_vector (30 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_iq : std_logic_vector (30 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_q : std_logic_vector (30 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid300_atanXOXTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid301_atanXOXTabGen_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid344_invTabGen_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid345_invTabGen_lutmem_ia : std_logic_vector (19 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_iq : std_logic_vector (19 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_q : std_logic_vector (19 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid346_invTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q : std_logic_vector (19 downto 0);
signal reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q : std_logic_vector (21 downto 0);
signal reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q : std_logic_vector (28 downto 0);
signal reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q : std_logic_vector (30 downto 0);
signal reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (26 downto 0);
signal reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (8 downto 0);
signal reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (31 downto 0);
signal reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (32 downto 0);
signal reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (22 downto 0);
signal reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (22 downto 0);
signal reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (22 downto 0);
signal reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (7 downto 0);
signal reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (7 downto 0);
signal reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (22 downto 0);
signal reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (23 downto 0);
signal reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (34 downto 0);
signal reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (11 downto 0);
signal reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q : std_logic_vector (7 downto 0);
signal ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (7 downto 0);
signal ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (8 downto 0);
signal ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (22 downto 0);
signal ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (7 downto 0);
signal ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (20 downto 0);
signal ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (18 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q : std_logic_vector (12 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 : std_logic;
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : signal is true;
signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : signal is true;
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : signal is true;
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_c : std_logic_vector (0 downto 0);
signal excSelBits_uid114_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a : std_logic_vector(33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b : std_logic_vector(33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o : std_logic_vector (33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q : std_logic_vector (33 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o : std_logic_vector (32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0);
signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid15_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid15_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid16_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid16_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal singX_uid17_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal singX_uid17_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q : std_logic_vector (9 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_a : std_logic_vector(26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_b : std_logic_vector(26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_o : std_logic_vector (26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (26 downto 0);
signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (35 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal fracOOPi_uid10_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracOOPi_uid10_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid80_atanX_uid8_fpArctanPiTest_in : std_logic_vector (49 downto 0);
signal normBit_uid80_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in : std_logic_vector (48 downto 0);
signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in : std_logic_vector (47 downto 0);
signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (47 downto 0);
signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (46 downto 0);
signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (45 downto 0);
signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (21 downto 0);
signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (21 downto 0);
signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in : std_logic_vector (36 downto 0);
signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b : std_logic_vector (22 downto 0);
signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal R_uid221_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (14 downto 0);
signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (14 downto 0);
signal R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal constOut_uid54_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal constOut_uid54_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal u_uid58_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal u_uid58_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal R_uid120_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (16 downto 0);
signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (8 downto 0);
signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in : std_logic_vector (8 downto 0);
signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in : std_logic_vector (25 downto 0);
signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (11 downto 0);
signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (9 downto 0);
signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (33 downto 0);
signal fpOOPi_uid11_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (32 downto 0);
signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0);
signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (28 downto 0);
signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (24 downto 0);
signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (0 downto 0);
signal stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal lowRangeB_uid304_atanXOXPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid304_atanXOXPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid305_atanXOXPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid305_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid310_atanXOXPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid310_atanXOXPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid311_atanXOXPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid311_atanXOXPolyEval_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid349_invPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid349_invPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid350_invPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid350_invPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid355_invPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid355_invPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid356_invPolyEval_in : std_logic_vector (22 downto 0);
signal highBBits_uid356_invPolyEval_b : std_logic_vector (20 downto 0);
signal y_uid73_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal y_uid73_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0);
signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal yT1_uid347_invPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid347_invPolyEval_b : std_logic_vector (11 downto 0);
signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal expU_uid59_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expU_uid59_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracU_uid60_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracU_uid60_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0);
signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b : std_logic_vector (3 downto 0);
signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (1 downto 0);
signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (34 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_a : std_logic_vector(31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_b : std_logic_vector(31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_o : std_logic_vector (31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_q : std_logic_vector (31 downto 0);
signal sumAHighB_uid351_invPolyEval_a : std_logic_vector(20 downto 0);
signal sumAHighB_uid351_invPolyEval_b : std_logic_vector(20 downto 0);
signal sumAHighB_uid351_invPolyEval_o : std_logic_vector (20 downto 0);
signal sumAHighB_uid351_invPolyEval_q : std_logic_vector (20 downto 0);
signal sumAHighB_uid357_invPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid357_invPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid357_invPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid357_invPolyEval_q : std_logic_vector (29 downto 0);
signal yAddr_uid75_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0);
signal yAddr_uid75_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in : std_logic_vector (26 downto 0);
signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b : std_logic_vector (17 downto 0);
signal rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0);
signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b : std_logic_vector (4 downto 0);
signal expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0);
signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal s1_uid304_uid307_atanXOXPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid310_uid313_atanXOXPolyEval_q : std_logic_vector (33 downto 0);
signal s1_uid349_uid352_invPolyEval_q : std_logic_vector (21 downto 0);
signal s2_uid355_uid358_invPolyEval_q : std_logic_vector (31 downto 0);
signal yT1_uid302_atanXOXPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid302_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (20 downto 0);
signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (18 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0);
signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0);
signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (25 downto 0);
begin
--xIn(GPIN,3)@0
--cstAllZWF_uid19_atanX_uid8_fpArctanPiTest(CONSTANT,18)
cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000000";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable(LOGICAL,878)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q <= not ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,1008)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a or ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,1004)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100001";
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,1005)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,1006)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,1009)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,1010)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--fracX_uid16_atanX_uid8_fpArctanPiTest(BITSELECT,15)@0
fracX_uid16_atanX_uid8_fpArctanPiTest_in <= a(22 downto 0);
fracX_uid16_atanX_uid8_fpArctanPiTest_b <= fracX_uid16_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--fracXIsZero_uid35_atanX_uid8_fpArctanPiTest(LOGICAL,34)@0
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b else "0";
--InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest(LOGICAL,36)@0
InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q <= not InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a;
--cstAllOWE_uid18_atanX_uid8_fpArctanPiTest(CONSTANT,17)
cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q <= "11111111";
--expX_uid15_atanX_uid8_fpArctanPiTest(BITSELECT,14)@0
expX_uid15_atanX_uid8_fpArctanPiTest_in <= a(30 downto 0);
expX_uid15_atanX_uid8_fpArctanPiTest_b <= expX_uid15_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--expXIsMax_uid33_atanX_uid8_fpArctanPiTest(LOGICAL,32)@0
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a = expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b else "0";
--exc_N_uid38_atanX_uid8_fpArctanPiTest(LOGICAL,37)@0
exc_N_uid38_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q;
exc_N_uid38_atanX_uid8_fpArctanPiTest_b <= InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q;
exc_N_uid38_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_a and exc_N_uid38_atanX_uid8_fpArctanPiTest_b;
--InvExc_N_uid118_atanX_uid8_fpArctanPiTest(LOGICAL,117)@0
InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q;
InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q <= not InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a;
--singX_uid17_atanX_uid8_fpArctanPiTest(BITSELECT,16)@0
singX_uid17_atanX_uid8_fpArctanPiTest_in <= a;
singX_uid17_atanX_uid8_fpArctanPiTest_b <= singX_uid17_atanX_uid8_fpArctanPiTest_in(31 downto 31);
--signR_uid119_atanX_uid8_fpArctanPiTest(LOGICAL,118)@0
signR_uid119_atanX_uid8_fpArctanPiTest_a <= singX_uid17_atanX_uid8_fpArctanPiTest_b;
signR_uid119_atanX_uid8_fpArctanPiTest_b <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q;
signR_uid119_atanX_uid8_fpArctanPiTest_q <= signR_uid119_atanX_uid8_fpArctanPiTest_a and signR_uid119_atanX_uid8_fpArctanPiTest_b;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,998)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid119_atanX_uid8_fpArctanPiTest_q, xout => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,1000)
-- every=1, low=0, high=33, step=1, init=1
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 32 THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 33;
ELSE
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6));
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,1001)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,1002)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,999)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 34,
width_b => 1,
widthad_b => 6,
numwords_b => 34,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,879)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a or ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,875)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100000";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,876)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,877)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,880)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,881)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,869)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => singX_uid17_atanX_uid8_fpArctanPiTest_b, xout => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,871)
-- every=1, low=0, high=32, step=1, init=1
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 31 THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 32;
ELSE
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6));
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,872)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,873)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,870)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--cstBias_uid22_atanX_uid8_fpArctanPiTest(CONSTANT,21)
cstBias_uid22_atanX_uid8_fpArctanPiTest_q <= "01111111";
--piO2_uid46_atanX_uid8_fpArctanPiTest(CONSTANT,45)
piO2_uid46_atanX_uid8_fpArctanPiTest_q <= "11001001000011111101101011";
--cstPiO2_uid48_atanX_uid8_fpArctanPiTest(BITSELECT,47)@35
cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in <= piO2_uid46_atanX_uid8_fpArctanPiTest_q(24 downto 0);
cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b <= cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in(24 downto 2);
--fpPiO2C_uid49_atanX_uid8_fpArctanPiTest(BITJOIN,48)@35
fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBias_uid22_atanX_uid8_fpArctanPiTest_q & cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b;
--cstBiasM1_uid23_atanX_uid8_fpArctanPiTest(CONSTANT,22)
cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q <= "01111110";
--piO4_uid47_atanX_uid8_fpArctanPiTest(CONSTANT,46)
piO4_uid47_atanX_uid8_fpArctanPiTest_q <= "110010010000111111011011";
--cstPiO4_uid51_atanX_uid8_fpArctanPiTest(BITSELECT,50)@35
cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in <= piO4_uid47_atanX_uid8_fpArctanPiTest_q(22 downto 0);
cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b <= cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--fpPiO4C_uid52_atanX_uid8_fpArctanPiTest(BITJOIN,51)@35
fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q & cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,892)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a or ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b);
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,893)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,894)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b;
--exc_I_uid36_atanX_uid8_fpArctanPiTest(LOGICAL,35)@0
exc_I_uid36_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q;
exc_I_uid36_atanX_uid8_fpArctanPiTest_b <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
exc_I_uid36_atanX_uid8_fpArctanPiTest_q <= exc_I_uid36_atanX_uid8_fpArctanPiTest_a and exc_I_uid36_atanX_uid8_fpArctanPiTest_b;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,882)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid36_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,883)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq,
address_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa,
data_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia
);
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(0 downto 0);
--constOut_uid54_atanX_uid8_fpArctanPiTest(MUX,53)@35
constOut_uid54_atanX_uid8_fpArctanPiTest_s <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q;
constOut_uid54_atanX_uid8_fpArctanPiTest: PROCESS (constOut_uid54_atanX_uid8_fpArctanPiTest_s, en, fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q, fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE constOut_uid54_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expOutCst_uid112_atanX_uid8_fpArctanPiTest(BITSELECT,111)@35
expOutCst_uid112_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expOutCst_uid112_atanX_uid8_fpArctanPiTest_b <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5(REG,428)@35
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--cst01pWShift_uid69_atanX_uid8_fpArctanPiTest(CONSTANT,68)
cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q <= "0000000000000";
--reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2(REG,389)@0
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= signR_uid119_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c(DELAY,707)@1
ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,1022)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a or ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b);
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top(CONSTANT,1018)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q <= "0111";
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp(LOGICAL,1019)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q);
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q <= "1" when ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a = ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b else "0";
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg(REG,1020)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,1023)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,1024)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b;
--cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,230)
cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111110";
--expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest(SUB,259)@0
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q);
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b);
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b));
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,260)@0
expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0);
expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,229)
cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111101";
--expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest(SUB,256)@0
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q);
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b);
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b));
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,257)@0
expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0);
expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,249)@0
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b else "0";
--expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest(MUX,263)@0
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s <= fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q;
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--expXIsZero_uid31_atanX_uid8_fpArctanPiTest(LOGICAL,30)@0
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a = expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b else "0";
--udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,258)@0
udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in <= STD_LOGIC_VECTOR((9 downto 9 => expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(8)) & expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q);
udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in(9 downto 9);
--InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,245)@0
InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a;
--InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,246)@0
InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a <= expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q;
InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a;
--exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,247)@0
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a <= InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b <= InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c;
--xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,264)@0
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q;
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b;
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a and xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b;
--xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,265)@0
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q;
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q <= xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a or xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b;
--excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,266)@0
excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q & expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q & xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q;
--reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0(REG,378)@0
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest(LOOKUP,267)@1
outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest(MUX,269)@1
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q;
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,1012)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt(COUNTER,1014)
-- every=1, low=0, high=7, step=1, init=1
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg(REG,1015)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux(MUX,1016)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,1013)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia
);
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid20_atanX_uid8_fpArctanPiTest(CONSTANT,19)
cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000001";
--oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,248)@0
oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q <= VCC_q & fracX_uid16_atanX_uid8_fpArctanPiTest_b;
--y_uid251_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,250)@0
y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in <= oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q(22 downto 0);
y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,252)@0
yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b;
yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 15);
--reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0(REG,379)@0
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid346_invTabGen_lutmem(DUALMEM,376)@1
memoryC2_uid346_invTabGen_lutmem_ia <= (others => '0');
memoryC2_uid346_invTabGen_lutmem_aa <= (others => '0');
memoryC2_uid346_invTabGen_lutmem_ab <= reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q;
memoryC2_uid346_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC2_uid346_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid346_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid346_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid346_invTabGen_lutmem_iq,
address_a => memoryC2_uid346_invTabGen_lutmem_aa,
data_a => memoryC2_uid346_invTabGen_lutmem_ia
);
memoryC2_uid346_invTabGen_lutmem_reset0 <= areset;
memoryC2_uid346_invTabGen_lutmem_q <= memoryC2_uid346_invTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1(REG,381)@3
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= memoryC2_uid346_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,1011)
ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a(DELAY,680)@0
ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,253)@3
yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in <= ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q(14 downto 0);
yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in(14 downto 0);
--yT1_uid347_invPolyEval(BITSELECT,346)@3
yT1_uid347_invPolyEval_in <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b;
yT1_uid347_invPolyEval_b <= yT1_uid347_invPolyEval_in(14 downto 3);
--reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0(REG,380)@3
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= yT1_uid347_invPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid366_pT1_uid348_invPolyEval(MULT,365)@4
prodXY_uid366_pT1_uid348_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid366_pT1_uid348_invPolyEval_a),13)) * SIGNED(prodXY_uid366_pT1_uid348_invPolyEval_b);
prodXY_uid366_pT1_uid348_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid366_pT1_uid348_invPolyEval_a <= (others => '0');
prodXY_uid366_pT1_uid348_invPolyEval_b <= (others => '0');
prodXY_uid366_pT1_uid348_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid366_pT1_uid348_invPolyEval_a <= reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q;
prodXY_uid366_pT1_uid348_invPolyEval_b <= reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q;
prodXY_uid366_pT1_uid348_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid366_pT1_uid348_invPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid366_pT1_uid348_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid366_pT1_uid348_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid366_pT1_uid348_invPolyEval_q <= prodXY_uid366_pT1_uid348_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid367_pT1_uid348_invPolyEval(BITSELECT,366)@7
prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in <= prodXY_uid366_pT1_uid348_invPolyEval_q;
prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in(23 downto 11);
--highBBits_uid350_invPolyEval(BITSELECT,349)@7
highBBits_uid350_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b;
highBBits_uid350_invPolyEval_b <= highBBits_uid350_invPolyEval_in(12 downto 1);
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a(DELAY,804)@1
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid345_invTabGen_lutmem(DUALMEM,375)@4
memoryC1_uid345_invTabGen_lutmem_ia <= (others => '0');
memoryC1_uid345_invTabGen_lutmem_aa <= (others => '0');
memoryC1_uid345_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q;
memoryC1_uid345_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 20,
widthad_a => 8,
numwords_a => 256,
width_b => 20,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC1_uid345_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid345_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid345_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid345_invTabGen_lutmem_iq,
address_a => memoryC1_uid345_invTabGen_lutmem_aa,
data_a => memoryC1_uid345_invTabGen_lutmem_ia
);
memoryC1_uid345_invTabGen_lutmem_reset0 <= areset;
memoryC1_uid345_invTabGen_lutmem_q <= memoryC1_uid345_invTabGen_lutmem_iq(19 downto 0);
--reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0(REG,383)@6
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= "00000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= memoryC1_uid345_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid351_invPolyEval(ADD,350)@7
sumAHighB_uid351_invPolyEval_a <= STD_LOGIC_VECTOR((20 downto 20 => reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q(19)) & reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q);
sumAHighB_uid351_invPolyEval_b <= STD_LOGIC_VECTOR((20 downto 12 => highBBits_uid350_invPolyEval_b(11)) & highBBits_uid350_invPolyEval_b);
sumAHighB_uid351_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid351_invPolyEval_a) + SIGNED(sumAHighB_uid351_invPolyEval_b));
sumAHighB_uid351_invPolyEval_q <= sumAHighB_uid351_invPolyEval_o(20 downto 0);
--lowRangeB_uid349_invPolyEval(BITSELECT,348)@7
lowRangeB_uid349_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b(0 downto 0);
lowRangeB_uid349_invPolyEval_b <= lowRangeB_uid349_invPolyEval_in(0 downto 0);
--s1_uid349_uid352_invPolyEval(BITJOIN,351)@7
s1_uid349_uid352_invPolyEval_q <= sumAHighB_uid351_invPolyEval_q & lowRangeB_uid349_invPolyEval_b;
--reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1(REG,385)@7
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= "0000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= s1_uid349_uid352_invPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor(LOGICAL,1059)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a or ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b);
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg(REG,966)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena(REG,1060)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q = "1") THEN
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd(LOGICAL,1061)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b <= en;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg(DELAY,1051)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt(COUNTER,962)
-- every=1, low=0, high=1, step=1, init=1
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i,1));
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg(REG,963)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux(MUX,964)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s <= en;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux: PROCESS (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q)
BEGIN
CASE ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s IS
WHEN "0" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
WHEN "1" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q;
WHEN OTHERS => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem(DUALMEM,1052)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia
);
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0(REG,384)@7
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid369_pT2_uid354_invPolyEval(MULT,368)@8
prodXY_uid369_pT2_uid354_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid369_pT2_uid354_invPolyEval_a),16)) * SIGNED(prodXY_uid369_pT2_uid354_invPolyEval_b);
prodXY_uid369_pT2_uid354_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid369_pT2_uid354_invPolyEval_a <= (others => '0');
prodXY_uid369_pT2_uid354_invPolyEval_b <= (others => '0');
prodXY_uid369_pT2_uid354_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid369_pT2_uid354_invPolyEval_a <= reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q;
prodXY_uid369_pT2_uid354_invPolyEval_b <= reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q;
prodXY_uid369_pT2_uid354_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid369_pT2_uid354_invPolyEval_pr,37));
END IF;
END IF;
END PROCESS;
prodXY_uid369_pT2_uid354_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid369_pT2_uid354_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid369_pT2_uid354_invPolyEval_q <= prodXY_uid369_pT2_uid354_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid370_pT2_uid354_invPolyEval(BITSELECT,369)@11
prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in <= prodXY_uid369_pT2_uid354_invPolyEval_q;
prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in(36 downto 14);
--highBBits_uid356_invPolyEval(BITSELECT,355)@11
highBBits_uid356_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b;
highBBits_uid356_invPolyEval_b <= highBBits_uid356_invPolyEval_in(22 downto 2);
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor(LOGICAL,1048)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q <= not (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a or ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b);
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top(CONSTANT,1031)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q <= "0100";
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp(LOGICAL,1032)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q <= "1" when ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a = ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b else "0";
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg(REG,1033)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena(REG,1049)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd(LOGICAL,1050)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a and ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg(DELAY,1038)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt(COUNTER,1027)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i,3));
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg(REG,1028)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux(MUX,1029)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s <= en;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux: PROCESS (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem(DUALMEM,1039)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq(7 downto 0);
--memoryC0_uid344_invTabGen_lutmem(DUALMEM,374)@8
memoryC0_uid344_invTabGen_lutmem_ia <= (others => '0');
memoryC0_uid344_invTabGen_lutmem_aa <= (others => '0');
memoryC0_uid344_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q;
memoryC0_uid344_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC0_uid344_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid344_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid344_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid344_invTabGen_lutmem_iq,
address_a => memoryC0_uid344_invTabGen_lutmem_aa,
data_a => memoryC0_uid344_invTabGen_lutmem_ia
);
memoryC0_uid344_invTabGen_lutmem_reset0 <= areset;
memoryC0_uid344_invTabGen_lutmem_q <= memoryC0_uid344_invTabGen_lutmem_iq(28 downto 0);
--reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0(REG,387)@10
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= "00000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= memoryC0_uid344_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid357_invPolyEval(ADD,356)@11
sumAHighB_uid357_invPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q(28)) & reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q);
sumAHighB_uid357_invPolyEval_b <= STD_LOGIC_VECTOR((29 downto 21 => highBBits_uid356_invPolyEval_b(20)) & highBBits_uid356_invPolyEval_b);
sumAHighB_uid357_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid357_invPolyEval_a) + SIGNED(sumAHighB_uid357_invPolyEval_b));
sumAHighB_uid357_invPolyEval_q <= sumAHighB_uid357_invPolyEval_o(29 downto 0);
--lowRangeB_uid355_invPolyEval(BITSELECT,354)@11
lowRangeB_uid355_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b(1 downto 0);
lowRangeB_uid355_invPolyEval_b <= lowRangeB_uid355_invPolyEval_in(1 downto 0);
--s2_uid355_uid358_invPolyEval(BITJOIN,357)@11
s2_uid355_uid358_invPolyEval_q <= sumAHighB_uid357_invPolyEval_q & lowRangeB_uid355_invPolyEval_b;
--fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,255)@11
fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in <= s2_uid355_uid358_invPolyEval_q(28 downto 0);
fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in(28 downto 5);
--fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,261)@11
fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b(22 downto 0);
fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,688)@0
ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest(MUX,262)@11
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q;
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1(REG,388)@1
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,701)@2
ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 10 )
PORT MAP ( xin => reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest(MUX,268)@12
fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q;
fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid273_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,272)@12
R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q <= ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q & fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,905)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a or ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,901)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "01001";
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,902)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,903)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,906)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,907)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,895)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,897)
-- every=1, low=0, high=9, step=1, init=1
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 8 THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 9;
ELSE
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,4));
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,898)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,899)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,896)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 4,
numwords_a => 10,
width_b => 32,
widthad_b => 4,
numwords_b => 10,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(31 downto 0);
--path2_uid56_atanX_uid8_fpArctanPiTest(COMPARE,55)@0
path2_uid56_atanX_uid8_fpArctanPiTest_cin <= GND_q;
path2_uid56_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid15_atanX_uid8_fpArctanPiTest_b) & '0';
path2_uid56_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q) & path2_uid56_atanX_uid8_fpArctanPiTest_cin(0);
path2_uid56_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_b));
path2_uid56_atanX_uid8_fpArctanPiTest_n(0) <= not path2_uid56_atanX_uid8_fpArctanPiTest_o(10);
--reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1(REG,390)@0
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= path2_uid56_atanX_uid8_fpArctanPiTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b(DELAY,466)@1
ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--u_uid58_atanX_uid8_fpArctanPiTest(MUX,57)@12
u_uid58_atanX_uid8_fpArctanPiTest_s <= ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q;
u_uid58_atanX_uid8_fpArctanPiTest: PROCESS (u_uid58_atanX_uid8_fpArctanPiTest_s, en, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q, R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE u_uid58_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => u_uid58_atanX_uid8_fpArctanPiTest_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q;
WHEN "1" => u_uid58_atanX_uid8_fpArctanPiTest_q <= R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => u_uid58_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracU_uid60_atanX_uid8_fpArctanPiTest(BITSELECT,59)@12
fracU_uid60_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracU_uid60_atanX_uid8_fpArctanPiTest_b <= fracU_uid60_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a(DELAY,471)@12
ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracU_uid60_atanX_uid8_fpArctanPiTest_b, xout => ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest(BITJOIN,60)@13
oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q;
--oFracUExt_uid70_atanX_uid8_fpArctanPiTest(BITJOIN,69)@13
oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q <= cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q & oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q;
--X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,282)@13
X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(24 downto 0);
X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(24 downto 0);
--leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,281)
leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000000000000";
--leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,283)@13
leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5(REG,399)@13
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,279)@13
X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(28 downto 0);
X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(28 downto 0);
--leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,280)@13
leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4(REG,398)@13
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,276)@13
X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(32 downto 0);
X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(32 downto 0);
--leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,275)
leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "0000";
--leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,277)@13
leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3(REG,397)@13
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,396)@13
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--zS_uid67_atanX_uid8_fpArctanPiTest(CONSTANT,66)
zS_uid67_atanX_uid8_fpArctanPiTest_q <= "000000000";
--shiftBias_uid64_atanX_uid8_fpArctanPiTest(CONSTANT,63)
shiftBias_uid64_atanX_uid8_fpArctanPiTest_q <= "01110010";
--expU_uid59_atanX_uid8_fpArctanPiTest(BITSELECT,58)@12
expU_uid59_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expU_uid59_atanX_uid8_fpArctanPiTest_b <= expU_uid59_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1(REG,391)@12
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= expU_uid59_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--shiftValue_uid65_atanX_uid8_fpArctanPiTest(SUB,64)@13
shiftValue_uid65_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q);
shiftValue_uid65_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid64_atanX_uid8_fpArctanPiTest_q);
shiftValue_uid65_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_b));
shiftValue_uid65_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--ShiftValue8_uid66_atanX_uid8_fpArctanPiTest(BITSELECT,65)@13
ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q;
ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in(8 downto 8);
--shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest(MUX,67)@13
shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b;
shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest: PROCESS (shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s, en, shiftValue_uid65_atanX_uid8_fpArctanPiTest_q, zS_uid67_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= zS_uid67_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest(BITSELECT,70)@13
fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in <= shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q(3 downto 0);
fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,284)@13
leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b;
leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,395)@13
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,285)@14
leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q;
leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q, reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q, reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q;
WHEN "11" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,293)@14
LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(33 downto 0);
LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(33 downto 0);
--ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,725)@14
ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,292)
leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000";
--leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,294)@15
leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,290)@14
LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(34 downto 0);
LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(34 downto 0);
--ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,723)@14
ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,289)
leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "00";
--leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,291)@15
leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,287)@14
LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0);
LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(35 downto 0);
--ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,721)@14
ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,288)@15
leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & GND_q;
--reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,401)@14
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,295)@13
leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a(DELAY,829)@13
ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,400)@14
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,296)@15
leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q;
leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid73_atanX_uid8_fpArctanPiTest(BITSELECT,72)@15
y_uid73_atanX_uid8_fpArctanPiTest_in <= leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0);
y_uid73_atanX_uid8_fpArctanPiTest_b <= y_uid73_atanX_uid8_fpArctanPiTest_in(35 downto 1);
--yAddr_uid75_atanX_uid8_fpArctanPiTest(BITSELECT,74)@15
yAddr_uid75_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b;
yAddr_uid75_atanX_uid8_fpArctanPiTest_b <= yAddr_uid75_atanX_uid8_fpArctanPiTest_in(34 downto 27);
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0(REG,402)@15
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= yAddr_uid75_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid301_atanXOXTabGen_lutmem(DUALMEM,373)@16
memoryC2_uid301_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC2_uid301_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC2_uid301_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q;
memoryC2_uid301_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC2_uid301_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid301_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid301_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid301_atanXOXTabGen_lutmem_iq,
address_a => memoryC2_uid301_atanXOXTabGen_lutmem_aa,
data_a => memoryC2_uid301_atanXOXTabGen_lutmem_ia
);
memoryC2_uid301_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC2_uid301_atanXOXTabGen_lutmem_q <= memoryC2_uid301_atanXOXTabGen_lutmem_iq(12 downto 0);
--reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1(REG,404)@18
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= memoryC2_uid301_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--yPPolyEval_uid76_atanX_uid8_fpArctanPiTest(BITSELECT,75)@15
yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b(26 downto 0);
yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in(26 downto 9);
--yT1_uid302_atanXOXPolyEval(BITSELECT,301)@15
yT1_uid302_atanXOXPolyEval_in <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b;
yT1_uid302_atanXOXPolyEval_b <= yT1_uid302_atanXOXPolyEval_in(17 downto 5);
--ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg(DELAY,1062)
ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid302_atanXOXPolyEval_b, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a(DELAY,832)@15
ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0(REG,403)@18
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid360_pT1_uid303_atanXOXPolyEval(MULT,359)@19
prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_a),14)) * SIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_b);
prodXY_uid360_pT1_uid303_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= (others => '0');
prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= (others => '0');
prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q;
prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q;
prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid360_pT1_uid303_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval(BITSELECT,360)@22
prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_q;
prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in(25 downto 12);
--highBBits_uid305_atanXOXPolyEval(BITSELECT,304)@22
highBBits_uid305_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b;
highBBits_uid305_atanXOXPolyEval_b <= highBBits_uid305_atanXOXPolyEval_in(13 downto 1);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a(DELAY,834)@15
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0(REG,405)@18
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid300_atanXOXTabGen_lutmem(DUALMEM,372)@19
memoryC1_uid300_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC1_uid300_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC1_uid300_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q;
memoryC1_uid300_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC1_uid300_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid300_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid300_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid300_atanXOXTabGen_lutmem_iq,
address_a => memoryC1_uid300_atanXOXTabGen_lutmem_aa,
data_a => memoryC1_uid300_atanXOXTabGen_lutmem_ia
);
memoryC1_uid300_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC1_uid300_atanXOXTabGen_lutmem_q <= memoryC1_uid300_atanXOXTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0(REG,406)@21
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= memoryC1_uid300_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid306_atanXOXPolyEval(ADD,305)@22
sumAHighB_uid306_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q(20)) & reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q);
sumAHighB_uid306_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid305_atanXOXPolyEval_b(12)) & highBBits_uid305_atanXOXPolyEval_b);
sumAHighB_uid306_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid306_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid306_atanXOXPolyEval_b));
sumAHighB_uid306_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_o(21 downto 0);
--lowRangeB_uid304_atanXOXPolyEval(BITSELECT,303)@22
lowRangeB_uid304_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b(0 downto 0);
lowRangeB_uid304_atanXOXPolyEval_b <= lowRangeB_uid304_atanXOXPolyEval_in(0 downto 0);
--s1_uid304_uid307_atanXOXPolyEval(BITJOIN,306)@22
s1_uid304_uid307_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_q & lowRangeB_uid304_atanXOXPolyEval_b;
--reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1(REG,408)@22
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= s1_uid304_uid307_atanXOXPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor(LOGICAL,1035)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q <= not (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a or ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b);
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena(REG,1036)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd(LOGICAL,1037)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b <= en;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a and ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b;
--reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0(REG,407)@15
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg(DELAY,1025)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q, xout => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem(DUALMEM,1026)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq,
address_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa,
data_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia
);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid363_pT2_uid309_atanXOXPolyEval(MULT,362)@23
prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_a),19)) * SIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_b);
prodXY_uid363_pT2_uid309_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= (others => '0');
prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= (others => '0');
prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q;
prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q;
prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid363_pT2_uid309_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval(BITSELECT,363)@26
prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_q;
prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in(40 downto 17);
--highBBits_uid311_atanXOXPolyEval(BITSELECT,310)@26
highBBits_uid311_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b;
highBBits_uid311_atanXOXPolyEval_b <= highBBits_uid311_atanXOXPolyEval_in(23 downto 2);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor(LOGICAL,1073)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q <= not (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a or ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena(REG,1074)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q = "1") THEN
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd(LOGICAL,1075)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b <= en;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a and ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b;
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg(DELAY,1063)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem(DUALMEM,1064)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia
);
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0(REG,409)@22
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid299_atanXOXTabGen_lutmem(DUALMEM,371)@23
memoryC0_uid299_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC0_uid299_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC0_uid299_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q;
memoryC0_uid299_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 31,
widthad_a => 8,
numwords_a => 256,
width_b => 31,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC0_uid299_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid299_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid299_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid299_atanXOXTabGen_lutmem_iq,
address_a => memoryC0_uid299_atanXOXTabGen_lutmem_aa,
data_a => memoryC0_uid299_atanXOXTabGen_lutmem_ia
);
memoryC0_uid299_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC0_uid299_atanXOXTabGen_lutmem_q <= memoryC0_uid299_atanXOXTabGen_lutmem_iq(30 downto 0);
--reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0(REG,410)@25
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= memoryC0_uid299_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid312_atanXOXPolyEval(ADD,311)@26
sumAHighB_uid312_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((31 downto 31 => reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q(30)) & reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q);
sumAHighB_uid312_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((31 downto 22 => highBBits_uid311_atanXOXPolyEval_b(21)) & highBBits_uid311_atanXOXPolyEval_b);
sumAHighB_uid312_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid312_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid312_atanXOXPolyEval_b));
sumAHighB_uid312_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_o(31 downto 0);
--lowRangeB_uid310_atanXOXPolyEval(BITSELECT,309)@26
lowRangeB_uid310_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b(1 downto 0);
lowRangeB_uid310_atanXOXPolyEval_b <= lowRangeB_uid310_atanXOXPolyEval_in(1 downto 0);
--s2_uid310_uid313_atanXOXPolyEval(BITJOIN,312)@26
s2_uid310_uid313_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_q & lowRangeB_uid310_atanXOXPolyEval_b;
--fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest(BITSELECT,77)@26
fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in <= s2_uid310_uid313_atanXOXPolyEval_q(31 downto 0);
fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in(31 downto 5);
--reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1(REG,412)@26
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,918)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,914)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01010";
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,915)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,916)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,919)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,920)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0(REG,411)@13
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,908)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,910)
-- every=1, low=0, high=10, step=1, init=1
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 9 THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 10;
ELSE
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4));
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,911)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,912)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,909)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 11,
width_b => 24,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(23 downto 0);
--mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest(MULT,78)@27
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr <= UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a) * UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b);
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= (others => '0');
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= (others => '0');
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr);
END IF;
END IF;
END PROCESS;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid80_atanX_uid8_fpArctanPiTest(BITSELECT,79)@30
normBit_uid80_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(49 downto 0);
normBit_uid80_atanX_uid8_fpArctanPiTest_b <= normBit_uid80_atanX_uid8_fpArctanPiTest_in(49 downto 49);
--InvNormBit_uid84_atanX_uid8_fpArctanPiTest(LOGICAL,83)@30
InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a <= normBit_uid80_atanX_uid8_fpArctanPiTest_b;
InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q <= not InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,931)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,927)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01111";
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,928)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,929)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,932)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,933)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,921)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expU_uid59_atanX_uid8_fpArctanPiTest_b, xout => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,923)
-- every=1, low=0, high=15, step=1, init=1
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4));
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,924)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,925)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,922)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 16,
width_b => 8,
widthad_b => 4,
numwords_b => 16,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(7 downto 0);
--expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest(SUB,84)@30
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q);
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000" & InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q);
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b));
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--fracRPath3High_uid81_atanX_uid8_fpArctanPiTest(BITSELECT,80)@30
fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(48 downto 0);
fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in(48 downto 25);
--fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest(BITSELECT,81)@30
fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(47 downto 0);
fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in(47 downto 24);
--fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest(MUX,82)@30
fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s <= normBit_uid80_atanX_uid8_fpArctanPiTest_b;
fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s, en, fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b, fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b)
BEGIN
CASE fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest(BITJOIN,85)@30
expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q & fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q;
--reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0(REG,420)@30
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest(ADD,86)@31
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q);
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000" & VCC_q);
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b));
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o(33 downto 0);
--expRPath3_uid89_atanX_uid8_fpArctanPiTest(BITSELECT,88)@31
expRPath3_uid89_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(31 downto 0);
expRPath3_uid89_atanX_uid8_fpArctanPiTest_b <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_in(31 downto 24);
--reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4(REG,427)@31
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,971)
ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e(DELAY,534)@32
ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,337)@33
RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 1);
--rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,339)@33
rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= GND_q & RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,333)
rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000";
--rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,322)
rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000000000000000000000";
--X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,321)@32
X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 24);
--rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,323)@32
rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,319)
rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "0000000000000000";
--X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,318)@32
X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 16);
--rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,320)@32
rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,315)@32
X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 8);
--rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,317)@32
rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q & X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a(DELAY,504)@30
ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q, xout => ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest(BITJOIN,93)@32
oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q;
--cstWFP2_uid25_atanX_uid8_fpArctanPiTest(CONSTANT,24)
cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q <= "00011001";
--reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1(REG,413)@30
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest(SUB,89)@31
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q);
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR((10 downto 9 => reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q(8)) & reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q);
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a) - SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b));
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o(9 downto 0);
--shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest(BITSELECT,91)@31
shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q(7 downto 0);
shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest(CONSTANT,23)
cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q <= "01101000";
--shiftOut_uid91_atanX_uid8_fpArctanPiTest(COMPARE,90)@13
shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin <= GND_q;
shiftOut_uid91_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & '0';
shiftOut_uid91_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q) & shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin(0);
shiftOut_uid91_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_b));
shiftOut_uid91_atanX_uid8_fpArctanPiTest_c(0) <= shiftOut_uid91_atanX_uid8_fpArctanPiTest_o(10);
--ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b(DELAY,502)@13
ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => shiftOut_uid91_atanX_uid8_fpArctanPiTest_c, xout => ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--sValPostSOut_uid93_atanX_uid8_fpArctanPiTest(MUX,92)@31
sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s <= ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q;
sValPostSOut_uid93_atanX_uid8_fpArctanPiTest: PROCESS (sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s, en, shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b, cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest(BITSELECT,94)@31
sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in <= sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q(4 downto 0);
sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,324)@31
rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b;
rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,414)@31
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,325)@32
rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q;
rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,332)@32
RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 6);
--ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,762)@32
ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,334)@33
rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,329)@32
RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 4);
--ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,760)@32
ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 21, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,331)@33
rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,326)@32
RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 2);
--ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,758)@32
ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,328)@33
rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2(REG,416)@32
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,335)@31
rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(2 downto 1);
--ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a(DELAY,844)@31
ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,415)@32
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,336)@33
rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q;
rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q, rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,340)@31
rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,417)@31
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b(DELAY,772)@32
ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,341)@33
rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q;
rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest(BITJOIN,96)@33
pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & GND_q;
--reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1(REG,418)@33
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--path2Diff_uid97_atanX_uid8_fpArctanPiTest(SUB,97)@34
path2Diff_uid97_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & piO2_uid46_atanX_uid8_fpArctanPiTest_q);
path2Diff_uid97_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q);
path2Diff_uid97_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_b));
path2Diff_uid97_atanX_uid8_fpArctanPiTest_q <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_o(26 downto 0);
--normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest(BITSELECT,98)@34
normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(25 downto 0);
normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in(25 downto 25);
--expRPath2_uid103_atanX_uid8_fpArctanPiTest(MUX,102)@34
expRPath2_uid103_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b;
expRPath2_uid103_atanX_uid8_fpArctanPiTest: PROCESS (expRPath2_uid103_atanX_uid8_fpArctanPiTest_s, en, cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q, cstBias_uid22_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPath2_uid103_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest(BITSELECT,99)@34
path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(24 downto 0);
path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in(24 downto 1);
--path2DiffLow_uid101_atanX_uid8_fpArctanPiTest(BITSELECT,100)@34
path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(23 downto 0);
path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in(23 downto 0);
--fracRPath2_uid102_atanX_uid8_fpArctanPiTest(MUX,101)@34
fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b;
fracRPath2_uid102_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s, en, path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b, path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b)
BEGIN
CASE fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest(BITJOIN,103)@34
expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q <= expRPath2_uid103_atanX_uid8_fpArctanPiTest_q & fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q;
--reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0(REG,419)@34
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest(ADD,104)@35
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q);
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000" & VCC_q);
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b));
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o(32 downto 0);
--expRPath2_uid107_atanX_uid8_fpArctanPiTest(BITSELECT,106)@35
expRPath2_uid107_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(31 downto 0);
expRPath2_uid107_atanX_uid8_fpArctanPiTest_b <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_in(31 downto 24);
--reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3(REG,426)@35
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor(LOGICAL,1086)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q <= not (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a or ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b);
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena(REG,1087)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q = "1") THEN
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd(LOGICAL,1088)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b <= en;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a and ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg(DELAY,1076)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid15_atanX_uid8_fpArctanPiTest_b, xout => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem(DUALMEM,1077)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 33,
width_b => 8,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq,
address_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa,
data_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia
);
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 <= areset;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq(7 downto 0);
--reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2(REG,425)@35
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,944)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,940)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "010010";
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,941)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,942)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,945)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,946)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--expXIsBias_uid44_atanX_uid8_fpArctanPiTest(LOGICAL,43)@0
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q;
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a = expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b else "0";
--inIsOne_uid45_atanX_uid8_fpArctanPiTest(LOGICAL,44)@0
inIsOne_uid45_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
inIsOne_uid45_atanX_uid8_fpArctanPiTest_b <= expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q;
inIsOne_uid45_atanX_uid8_fpArctanPiTest_q <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_a and inIsOne_uid45_atanX_uid8_fpArctanPiTest_b;
--arctanIsConst_uid55_atanX_uid8_fpArctanPiTest(LOGICAL,54)@0
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_q;
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a or arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c(DELAY,522)@1
ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q, xout => ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasMwShift_uid62_atanX_uid8_fpArctanPiTest(CONSTANT,61)
biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q <= "01110011";
--atanUIsU_uid63_atanX_uid8_fpArctanPiTest(COMPARE,62)@13
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin <= GND_q;
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q) & '0';
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin(0);
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b));
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n(0) <= not atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o(10);
--ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a(DELAY,520)@0
ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => path2_uid56_atanX_uid8_fpArctanPiTest_n, xout => ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--pathSelBits_uid108_atanX_uid8_fpArctanPiTest(BITJOIN,107)@13
pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q <= ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n & ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q;
--reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0(REG,392)@13
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,934)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,936)
-- every=1, low=0, high=18, step=1, init=1
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 17 THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 18;
ELSE
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,5));
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,937)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,938)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,935)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 19,
width_b => 3,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(2 downto 0);
--fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest(LOOKUP,108)@35
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q) IS
WHEN "000" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "001" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "010" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "011" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "110" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "111" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN OTHERS =>
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRCalc_uid113_atanX_uid8_fpArctanPiTest(MUX,112)@36
expRCalc_uid113_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q;
expRCalc_uid113_atanX_uid8_fpArctanPiTest: PROCESS (expRCalc_uid113_atanX_uid8_fpArctanPiTest_s, en, reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q, reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q, ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE expRCalc_uid113_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q;
WHEN "11" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstAllZWE_uid21_atanX_uid8_fpArctanPiTest(CONSTANT,20)
cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q <= "00000000";
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,995)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a or ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,996)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,997)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,985)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid38_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,986)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,982)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,983)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,984)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,972)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q, xout => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,973)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(0 downto 0);
--excSelBits_uid114_atanX_uid8_fpArctanPiTest(BITJOIN,113)@35
excSelBits_uid114_atanX_uid8_fpArctanPiTest_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q & GND_q & ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q;
--reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0(REG,377)@35
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid114_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest(LOOKUP,114)@36
outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid117_atanX_uid8_fpArctanPiTest(MUX,116)@36
expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q;
expRPostExc_uid117_atanX_uid8_fpArctanPiTest: PROCESS (expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, expRCalc_uid113_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid113_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracOutCst_uid110_atanX_uid8_fpArctanPiTest(BITSELECT,109)@35
fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5(REG,424)@35
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor(LOGICAL,968)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q <= not (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a or ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b);
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena(REG,969)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd(LOGICAL,970)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b <= en;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a and ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b;
--fracRPath3_uid88_atanX_uid8_fpArctanPiTest(BITSELECT,87)@31
fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(23 downto 0);
fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in(23 downto 1);
--reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4(REG,423)@31
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,960)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem(DUALMEM,961)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 1,
numwords_a => 2,
width_b => 23,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq,
address_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa,
data_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia
);
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 <= areset;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq(22 downto 0);
--fracRPath2_uid106_atanX_uid8_fpArctanPiTest(BITSELECT,105)@35
fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(23 downto 0);
fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in(23 downto 1);
--reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3(REG,422)@35
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,957)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a or ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,958)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,959)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2(REG,421)@0
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,947)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,948)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 33,
width_b => 23,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(22 downto 0);
--fracRCalc_uid111_atanX_uid8_fpArctanPiTest(MUX,110)@36
fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q;
fracRCalc_uid111_atanX_uid8_fpArctanPiTest: PROCESS (fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s, en, ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q, reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q, reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q;
WHEN "01" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q;
WHEN "11" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid116_atanX_uid8_fpArctanPiTest(MUX,115)@36
fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q;
fracRPostExc_uid116_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid120_atanX_uid8_fpArctanPiTest(BITJOIN,119)@36
R_uid120_atanX_uid8_fpArctanPiTest_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q & expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q & fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q;
--fracX_uid126_rAtanPi_uid13_fpArctanPiTest(BITSELECT,125)@36
fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0);
--reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1(REG,431)@36
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest(LOGICAL,137)@37
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a <= reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q;
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b else "0";
--expX_uid122_rAtanPi_uid13_fpArctanPiTest(BITSELECT,121)@36
expX_uid122_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expX_uid122_rAtanPi_uid13_fpArctanPiTest_b <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23);
--reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1(REG,429)@36
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest(LOGICAL,135)@37
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q;
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b else "0";
--exc_I_uid139_rAtanPi_uid13_fpArctanPiTest(LOGICAL,138)@37
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q;
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q;
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b;
--cstBiasM2_uid6_fpArctanPiTest(CONSTANT,5)
cstBiasM2_uid6_fpArctanPiTest_q <= "01111101";
--ooPi_uid9_fpArctanPiTest(CONSTANT,8)
ooPi_uid9_fpArctanPiTest_q <= "101000101111100110000011";
--fracOOPi_uid10_fpArctanPiTest(BITSELECT,9)@36
fracOOPi_uid10_fpArctanPiTest_in <= ooPi_uid9_fpArctanPiTest_q(22 downto 0);
fracOOPi_uid10_fpArctanPiTest_b <= fracOOPi_uid10_fpArctanPiTest_in(22 downto 0);
--fpOOPi_uid11_fpArctanPiTest(BITJOIN,10)@36
fpOOPi_uid11_fpArctanPiTest_q <= GND_q & cstBiasM2_uid6_fpArctanPiTest_q & fracOOPi_uid10_fpArctanPiTest_b;
--expY_uid123_rAtanPi_uid13_fpArctanPiTest(BITSELECT,122)@36
expY_uid123_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(30 downto 0);
expY_uid123_rAtanPi_uid13_fpArctanPiTest_b <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23);
--expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest(LOGICAL,149)@36
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b;
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a(DELAY,581)@36
ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest(LOGICAL,203)@37
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b;
--fracY_uid128_rAtanPi_uid13_fpArctanPiTest(BITSELECT,127)@36
fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(22 downto 0);
fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0);
--fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest(LOGICAL,153)@36
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b;
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b(DELAY,575)@36
ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest(LOGICAL,151)@36
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b;
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a(DELAY,574)@36
ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid155_rAtanPi_uid13_fpArctanPiTest(LOGICAL,154)@37
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q;
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b <= ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q;
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b;
--expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest(LOGICAL,133)@37
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q;
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b else "0";
--excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest(LOGICAL,204)@37
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b;
--ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest(LOGICAL,205)@37
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q;
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q;
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a or ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b;
--InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest(LOGICAL,155)@36
InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q;
InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a;
--exc_N_uid157_rAtanPi_uid13_fpArctanPiTest(LOGICAL,156)@36
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b;
--ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a(DELAY,579)@36
ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest(LOGICAL,139)@37
InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q;
InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a;
--exc_N_uid141_rAtanPi_uid13_fpArctanPiTest(LOGICAL,140)@37
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b;
--excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest(LOGICAL,206)@37
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c;
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest(LOGICAL,218)@37
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q;
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= not InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a;
END IF;
END PROCESS;
--signY_uid125_rAtanPi_uid13_fpArctanPiTest(BITSELECT,124)@36
signY_uid125_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q;
signY_uid125_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31);
--signX_uid124_rAtanPi_uid13_fpArctanPiTest(BITSELECT,123)@36
signX_uid124_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q;
signX_uid124_rAtanPi_uid13_fpArctanPiTest_b <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31);
--signR_uid190_rAtanPi_uid13_fpArctanPiTest(LOGICAL,189)@36
signR_uid190_rAtanPi_uid13_fpArctanPiTest_a <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_b;
signR_uid190_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_b;
signR_uid190_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= signR_uid190_rAtanPi_uid13_fpArctanPiTest_a xor signR_uid190_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a(DELAY,666)@37
ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid190_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest(LOGICAL,219)@38
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a <= ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q;
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b <= InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q;
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q <= signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a and signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b;
--ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c(DELAY,670)@38
ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest(BITJOIN,128)@36
add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b;
--reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1(REG,433)@36
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest(BITJOIN,126)@36
add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b;
--reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0(REG,432)@36
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--prod_uid165_rAtanPi_uid13_fpArctanPiTest(MULT,164)@37
prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr <= UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_a) * UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_b);
prod_uid165_rAtanPi_uid13_fpArctanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= (others => '0');
prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= (others => '0');
prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q;
prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q;
prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr);
END IF;
END IF;
END PROCESS;
prod_uid165_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1;
END IF;
END IF;
END PROCESS;
--normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest(BITSELECT,165)@40
normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q;
normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in(47 downto 47);
--roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest(CONSTANT,179)
roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q <= "010";
--fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest(BITSELECT,167)@40
fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(46 downto 0);
fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in(46 downto 23);
--fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest(BITSELECT,168)@40
fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(45 downto 0);
fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in(45 downto 22);
--fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest(MUX,169)@40
fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b;
fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s, en, fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b, fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b)
BEGIN
CASE fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "0" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b;
WHEN "1" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b;
WHEN OTHERS => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest(BITSELECT,177)@40
FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in <= fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q(1 downto 0);
FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in(1 downto 0);
--Prod22_uid172_rAtanPi_uid13_fpArctanPiTest(BITSELECT,171)@40
Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(22 downto 0);
Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in(22 downto 22);
--extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest(MUX,172)@40
extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b;
extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest: PROCESS (extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s, en, GND_q, Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b)
BEGIN
CASE extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "0" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b;
WHEN OTHERS => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest(BITSELECT,170)@40
stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(21 downto 0);
stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b <= stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in(21 downto 0);
--stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest(BITJOIN,173)@40
stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q <= extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q & stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b;
--stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest(LOGICAL,175)@40
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a <= stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q;
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q <= "1" when stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a = stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b else "0";
--sticky_uid177_rAtanPi_uid13_fpArctanPiTest(LOGICAL,176)@40
sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a <= stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q;
sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q <= not sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a;
--lrs_uid179_rAtanPi_uid13_fpArctanPiTest(BITJOIN,178)@40
lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b & sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q;
--roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest(LOGICAL,180)@40
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a <= lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q;
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b <= roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q;
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q <= "1" when roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a = roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b else "0";
--roundBit_uid182_rAtanPi_uid13_fpArctanPiTest(LOGICAL,181)@40
roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a <= roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q;
roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q <= not roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a;
--roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest(BITJOIN,184)@40
roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q <= GND_q & normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b & cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q & roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q;
--reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1(REG,436)@40
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--biasInc_uid163_rAtanPi_uid13_fpArctanPiTest(CONSTANT,162)
biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q <= "0001111111";
--ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b(DELAY,586)@36
ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expY_uid123_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expSum_uid162_rAtanPi_uid13_fpArctanPiTest(ADD,161)@37
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q);
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q);
expSum_uid162_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a) + UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q <= expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o(8 downto 0);
--ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a(DELAY,587)@38
ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest(SUB,163)@39
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q);
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q(9)) & biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q);
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b));
END IF;
END IF;
END PROCESS;
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o(10 downto 0);
--expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest(BITJOIN,182)@40
expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q & fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q;
--reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0(REG,435)@40
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest(ADD,185)@41
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q(34)) & reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q);
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q);
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a) + SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b));
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o(35 downto 0);
--expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest(BITSELECT,187)@41
expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q;
expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in(35 downto 24);
--expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest(BITSELECT,188)@41
expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b(7 downto 0);
expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in(7 downto 0);
--ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d(DELAY,664)@41
ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 2 )
PORT MAP ( xin => expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c(DELAY,659)@37
ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1(REG,437)@41
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid193_rAtanPi_uid13_fpArctanPiTest(COMPARE,192)@42
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q;
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & '0';
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q) & expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin(0);
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b));
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o(14);
--InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest(LOGICAL,157)@37
InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q;
InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a;
--InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest(LOGICAL,158)@37
InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a;
--InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest(LOGICAL,159)@37
InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a;
--exc_R_uid161_rAtanPi_uid13_fpArctanPiTest(LOGICAL,160)@37
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c;
--ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b(DELAY,629)@37
ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest(LOGICAL,141)@37
InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a;
--InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest(LOGICAL,142)@37
InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a;
--InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest(LOGICAL,143)@37
InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a;
--exc_R_uid145_rAtanPi_uid13_fpArctanPiTest(LOGICAL,144)@37
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c;
--ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a(DELAY,628)@37
ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest(LOGICAL,201)@42
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c <= expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c;
--excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest(LOGICAL,200)@37
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q;
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q <= excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a and excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c(DELAY,646)@37
ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest(LOGICAL,199)@37
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q;
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q <= excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a and excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b(DELAY,645)@37
ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest(LOGICAL,198)@37
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q <= excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a and excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a(DELAY,644)@37
ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid203_rAtanPi_uid13_fpArctanPiTest(LOGICAL,202)@42
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q <= excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d;
--expUdf_uid191_rAtanPi_uid13_fpArctanPiTest(COMPARE,190)@42
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q;
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0';
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin(0);
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b));
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o(14);
--excZC3_uid197_rAtanPi_uid13_fpArctanPiTest(LOGICAL,196)@42
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c <= expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c;
--excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest(LOGICAL,195)@37
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q;
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c(DELAY,633)@37
ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest(LOGICAL,194)@37
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b(DELAY,632)@37
ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest(LOGICAL,193)@37
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a(DELAY,631)@37
ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid198_rAtanPi_uid13_fpArctanPiTest(LOGICAL,197)@42
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q <= excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d;
--concExc_uid208_rAtanPi_uid13_fpArctanPiTest(BITJOIN,207)@42
concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q <= ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q & excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q & excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q;
--reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0(REG,439)@42
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid209_rAtanPi_uid13_fpArctanPiTest(LOOKUP,208)@43
excREnc_uid209_rAtanPi_uid13_fpArctanPiTest: PROCESS (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q) IS
WHEN "000" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "01";
WHEN "001" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "010" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "10";
WHEN "011" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "100" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "11";
WHEN "101" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "110" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "111" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN OTHERS =>
excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest(MUX,217)@43
expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q;
expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest: PROCESS (expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q;
WHEN "10" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest(BITSELECT,186)@41
fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q(23 downto 0);
fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b <= fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in(23 downto 1);
--ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d(DELAY,662)@41
ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest(MUX,212)@43
fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q;
fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q;
WHEN "10" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid221_rAtanPi_uid13_fpArctanPiTest(BITJOIN,220)@43
R_uid221_rAtanPi_uid13_fpArctanPiTest_q <= ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q & expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q & fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q;
--xOut(GPOUT,4)@43
q <= R_uid221_rAtanPi_uid13_fpArctanPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_atanpi_s5
-- VHDL created on Tue Mar 12 11:23:23 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_atanpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_atanpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBiasM2_uid6_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal ooPi_uid9_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal piO2_uid46_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0);
signal piO4_uid47_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid64_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal zS_uid67_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q : std_logic_vector (12 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a : std_logic_vector (23 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 : std_logic_vector (50 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr : UNSIGNED (50 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q : std_logic_vector (50 downto 0);
signal fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (9 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (10 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector (23 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 : std_logic_vector (47 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr : UNSIGNED (47 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (47 downto 0);
signal roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_q : std_logic_vector (40 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_b : std_logic_vector (21 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_s1 : std_logic_vector (36 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_pr : SIGNED (37 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_q : std_logic_vector (36 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid299_atanXOXTabGen_lutmem_ia : std_logic_vector (30 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_iq : std_logic_vector (30 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_q : std_logic_vector (30 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid300_atanXOXTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid301_atanXOXTabGen_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid344_invTabGen_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid345_invTabGen_lutmem_ia : std_logic_vector (19 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_iq : std_logic_vector (19 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_q : std_logic_vector (19 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid346_invTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q : std_logic_vector (19 downto 0);
signal reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q : std_logic_vector (21 downto 0);
signal reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q : std_logic_vector (28 downto 0);
signal reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q : std_logic_vector (30 downto 0);
signal reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (26 downto 0);
signal reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (8 downto 0);
signal reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (31 downto 0);
signal reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (32 downto 0);
signal reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (22 downto 0);
signal reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (22 downto 0);
signal reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (22 downto 0);
signal reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (7 downto 0);
signal reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (7 downto 0);
signal reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (22 downto 0);
signal reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (23 downto 0);
signal reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (34 downto 0);
signal reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (11 downto 0);
signal reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q : std_logic_vector (7 downto 0);
signal ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (7 downto 0);
signal ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (8 downto 0);
signal ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (22 downto 0);
signal ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (7 downto 0);
signal ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (20 downto 0);
signal ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (18 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q : std_logic_vector (12 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 : std_logic;
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : signal is true;
signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : signal is true;
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : signal is true;
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_c : std_logic_vector (0 downto 0);
signal excSelBits_uid114_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a : std_logic_vector(33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b : std_logic_vector(33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o : std_logic_vector (33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q : std_logic_vector (33 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o : std_logic_vector (32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0);
signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid15_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid15_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid16_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid16_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal singX_uid17_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal singX_uid17_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q : std_logic_vector (9 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_a : std_logic_vector(26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_b : std_logic_vector(26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_o : std_logic_vector (26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (26 downto 0);
signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (35 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal fracOOPi_uid10_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracOOPi_uid10_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid80_atanX_uid8_fpArctanPiTest_in : std_logic_vector (49 downto 0);
signal normBit_uid80_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in : std_logic_vector (48 downto 0);
signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in : std_logic_vector (47 downto 0);
signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (47 downto 0);
signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (46 downto 0);
signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (45 downto 0);
signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (21 downto 0);
signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (21 downto 0);
signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in : std_logic_vector (36 downto 0);
signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b : std_logic_vector (22 downto 0);
signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal R_uid221_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (14 downto 0);
signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (14 downto 0);
signal R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal constOut_uid54_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal constOut_uid54_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal u_uid58_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal u_uid58_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal R_uid120_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (16 downto 0);
signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (8 downto 0);
signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in : std_logic_vector (8 downto 0);
signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in : std_logic_vector (25 downto 0);
signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (11 downto 0);
signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (9 downto 0);
signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (33 downto 0);
signal fpOOPi_uid11_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (32 downto 0);
signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0);
signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (28 downto 0);
signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (24 downto 0);
signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (0 downto 0);
signal stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal lowRangeB_uid304_atanXOXPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid304_atanXOXPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid305_atanXOXPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid305_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid310_atanXOXPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid310_atanXOXPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid311_atanXOXPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid311_atanXOXPolyEval_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid349_invPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid349_invPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid350_invPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid350_invPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid355_invPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid355_invPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid356_invPolyEval_in : std_logic_vector (22 downto 0);
signal highBBits_uid356_invPolyEval_b : std_logic_vector (20 downto 0);
signal y_uid73_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal y_uid73_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0);
signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal yT1_uid347_invPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid347_invPolyEval_b : std_logic_vector (11 downto 0);
signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal expU_uid59_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expU_uid59_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracU_uid60_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracU_uid60_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0);
signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b : std_logic_vector (3 downto 0);
signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (1 downto 0);
signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (34 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_a : std_logic_vector(31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_b : std_logic_vector(31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_o : std_logic_vector (31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_q : std_logic_vector (31 downto 0);
signal sumAHighB_uid351_invPolyEval_a : std_logic_vector(20 downto 0);
signal sumAHighB_uid351_invPolyEval_b : std_logic_vector(20 downto 0);
signal sumAHighB_uid351_invPolyEval_o : std_logic_vector (20 downto 0);
signal sumAHighB_uid351_invPolyEval_q : std_logic_vector (20 downto 0);
signal sumAHighB_uid357_invPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid357_invPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid357_invPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid357_invPolyEval_q : std_logic_vector (29 downto 0);
signal yAddr_uid75_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0);
signal yAddr_uid75_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in : std_logic_vector (26 downto 0);
signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b : std_logic_vector (17 downto 0);
signal rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0);
signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b : std_logic_vector (4 downto 0);
signal expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0);
signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal s1_uid304_uid307_atanXOXPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid310_uid313_atanXOXPolyEval_q : std_logic_vector (33 downto 0);
signal s1_uid349_uid352_invPolyEval_q : std_logic_vector (21 downto 0);
signal s2_uid355_uid358_invPolyEval_q : std_logic_vector (31 downto 0);
signal yT1_uid302_atanXOXPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid302_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (20 downto 0);
signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (18 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0);
signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0);
signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (25 downto 0);
begin
--xIn(GPIN,3)@0
--cstAllZWF_uid19_atanX_uid8_fpArctanPiTest(CONSTANT,18)
cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000000";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable(LOGICAL,878)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q <= not ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,1008)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a or ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,1004)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100001";
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,1005)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,1006)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,1009)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,1010)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--fracX_uid16_atanX_uid8_fpArctanPiTest(BITSELECT,15)@0
fracX_uid16_atanX_uid8_fpArctanPiTest_in <= a(22 downto 0);
fracX_uid16_atanX_uid8_fpArctanPiTest_b <= fracX_uid16_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--fracXIsZero_uid35_atanX_uid8_fpArctanPiTest(LOGICAL,34)@0
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b else "0";
--InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest(LOGICAL,36)@0
InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q <= not InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a;
--cstAllOWE_uid18_atanX_uid8_fpArctanPiTest(CONSTANT,17)
cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q <= "11111111";
--expX_uid15_atanX_uid8_fpArctanPiTest(BITSELECT,14)@0
expX_uid15_atanX_uid8_fpArctanPiTest_in <= a(30 downto 0);
expX_uid15_atanX_uid8_fpArctanPiTest_b <= expX_uid15_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--expXIsMax_uid33_atanX_uid8_fpArctanPiTest(LOGICAL,32)@0
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a = expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b else "0";
--exc_N_uid38_atanX_uid8_fpArctanPiTest(LOGICAL,37)@0
exc_N_uid38_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q;
exc_N_uid38_atanX_uid8_fpArctanPiTest_b <= InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q;
exc_N_uid38_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_a and exc_N_uid38_atanX_uid8_fpArctanPiTest_b;
--InvExc_N_uid118_atanX_uid8_fpArctanPiTest(LOGICAL,117)@0
InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q;
InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q <= not InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a;
--singX_uid17_atanX_uid8_fpArctanPiTest(BITSELECT,16)@0
singX_uid17_atanX_uid8_fpArctanPiTest_in <= a;
singX_uid17_atanX_uid8_fpArctanPiTest_b <= singX_uid17_atanX_uid8_fpArctanPiTest_in(31 downto 31);
--signR_uid119_atanX_uid8_fpArctanPiTest(LOGICAL,118)@0
signR_uid119_atanX_uid8_fpArctanPiTest_a <= singX_uid17_atanX_uid8_fpArctanPiTest_b;
signR_uid119_atanX_uid8_fpArctanPiTest_b <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q;
signR_uid119_atanX_uid8_fpArctanPiTest_q <= signR_uid119_atanX_uid8_fpArctanPiTest_a and signR_uid119_atanX_uid8_fpArctanPiTest_b;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,998)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid119_atanX_uid8_fpArctanPiTest_q, xout => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,1000)
-- every=1, low=0, high=33, step=1, init=1
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 32 THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 33;
ELSE
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6));
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,1001)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,1002)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,999)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 34,
width_b => 1,
widthad_b => 6,
numwords_b => 34,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,879)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a or ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,875)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100000";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,876)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,877)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,880)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,881)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,869)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => singX_uid17_atanX_uid8_fpArctanPiTest_b, xout => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,871)
-- every=1, low=0, high=32, step=1, init=1
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 31 THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 32;
ELSE
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6));
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,872)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,873)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,870)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--cstBias_uid22_atanX_uid8_fpArctanPiTest(CONSTANT,21)
cstBias_uid22_atanX_uid8_fpArctanPiTest_q <= "01111111";
--piO2_uid46_atanX_uid8_fpArctanPiTest(CONSTANT,45)
piO2_uid46_atanX_uid8_fpArctanPiTest_q <= "11001001000011111101101011";
--cstPiO2_uid48_atanX_uid8_fpArctanPiTest(BITSELECT,47)@35
cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in <= piO2_uid46_atanX_uid8_fpArctanPiTest_q(24 downto 0);
cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b <= cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in(24 downto 2);
--fpPiO2C_uid49_atanX_uid8_fpArctanPiTest(BITJOIN,48)@35
fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBias_uid22_atanX_uid8_fpArctanPiTest_q & cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b;
--cstBiasM1_uid23_atanX_uid8_fpArctanPiTest(CONSTANT,22)
cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q <= "01111110";
--piO4_uid47_atanX_uid8_fpArctanPiTest(CONSTANT,46)
piO4_uid47_atanX_uid8_fpArctanPiTest_q <= "110010010000111111011011";
--cstPiO4_uid51_atanX_uid8_fpArctanPiTest(BITSELECT,50)@35
cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in <= piO4_uid47_atanX_uid8_fpArctanPiTest_q(22 downto 0);
cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b <= cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--fpPiO4C_uid52_atanX_uid8_fpArctanPiTest(BITJOIN,51)@35
fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q & cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,892)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a or ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b);
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,893)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,894)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b;
--exc_I_uid36_atanX_uid8_fpArctanPiTest(LOGICAL,35)@0
exc_I_uid36_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q;
exc_I_uid36_atanX_uid8_fpArctanPiTest_b <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
exc_I_uid36_atanX_uid8_fpArctanPiTest_q <= exc_I_uid36_atanX_uid8_fpArctanPiTest_a and exc_I_uid36_atanX_uid8_fpArctanPiTest_b;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,882)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid36_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,883)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq,
address_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa,
data_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia
);
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(0 downto 0);
--constOut_uid54_atanX_uid8_fpArctanPiTest(MUX,53)@35
constOut_uid54_atanX_uid8_fpArctanPiTest_s <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q;
constOut_uid54_atanX_uid8_fpArctanPiTest: PROCESS (constOut_uid54_atanX_uid8_fpArctanPiTest_s, en, fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q, fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE constOut_uid54_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expOutCst_uid112_atanX_uid8_fpArctanPiTest(BITSELECT,111)@35
expOutCst_uid112_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expOutCst_uid112_atanX_uid8_fpArctanPiTest_b <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5(REG,428)@35
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--cst01pWShift_uid69_atanX_uid8_fpArctanPiTest(CONSTANT,68)
cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q <= "0000000000000";
--reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2(REG,389)@0
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= signR_uid119_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c(DELAY,707)@1
ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,1022)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a or ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b);
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top(CONSTANT,1018)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q <= "0111";
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp(LOGICAL,1019)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q);
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q <= "1" when ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a = ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b else "0";
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg(REG,1020)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,1023)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,1024)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b;
--cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,230)
cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111110";
--expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest(SUB,259)@0
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q);
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b);
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b));
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,260)@0
expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0);
expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,229)
cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111101";
--expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest(SUB,256)@0
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q);
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b);
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b));
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,257)@0
expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0);
expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,249)@0
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b else "0";
--expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest(MUX,263)@0
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s <= fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q;
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--expXIsZero_uid31_atanX_uid8_fpArctanPiTest(LOGICAL,30)@0
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a = expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b else "0";
--udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,258)@0
udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in <= STD_LOGIC_VECTOR((9 downto 9 => expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(8)) & expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q);
udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in(9 downto 9);
--InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,245)@0
InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a;
--InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,246)@0
InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a <= expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q;
InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a;
--exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,247)@0
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a <= InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b <= InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c;
--xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,264)@0
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q;
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b;
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a and xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b;
--xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,265)@0
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q;
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q <= xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a or xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b;
--excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,266)@0
excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q & expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q & xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q;
--reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0(REG,378)@0
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest(LOOKUP,267)@1
outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest(MUX,269)@1
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q;
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,1012)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt(COUNTER,1014)
-- every=1, low=0, high=7, step=1, init=1
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg(REG,1015)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux(MUX,1016)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,1013)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia
);
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid20_atanX_uid8_fpArctanPiTest(CONSTANT,19)
cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000001";
--oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,248)@0
oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q <= VCC_q & fracX_uid16_atanX_uid8_fpArctanPiTest_b;
--y_uid251_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,250)@0
y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in <= oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q(22 downto 0);
y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,252)@0
yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b;
yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 15);
--reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0(REG,379)@0
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid346_invTabGen_lutmem(DUALMEM,376)@1
memoryC2_uid346_invTabGen_lutmem_ia <= (others => '0');
memoryC2_uid346_invTabGen_lutmem_aa <= (others => '0');
memoryC2_uid346_invTabGen_lutmem_ab <= reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q;
memoryC2_uid346_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC2_uid346_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid346_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid346_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid346_invTabGen_lutmem_iq,
address_a => memoryC2_uid346_invTabGen_lutmem_aa,
data_a => memoryC2_uid346_invTabGen_lutmem_ia
);
memoryC2_uid346_invTabGen_lutmem_reset0 <= areset;
memoryC2_uid346_invTabGen_lutmem_q <= memoryC2_uid346_invTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1(REG,381)@3
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= memoryC2_uid346_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,1011)
ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a(DELAY,680)@0
ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,253)@3
yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in <= ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q(14 downto 0);
yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in(14 downto 0);
--yT1_uid347_invPolyEval(BITSELECT,346)@3
yT1_uid347_invPolyEval_in <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b;
yT1_uid347_invPolyEval_b <= yT1_uid347_invPolyEval_in(14 downto 3);
--reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0(REG,380)@3
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= yT1_uid347_invPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid366_pT1_uid348_invPolyEval(MULT,365)@4
prodXY_uid366_pT1_uid348_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid366_pT1_uid348_invPolyEval_a),13)) * SIGNED(prodXY_uid366_pT1_uid348_invPolyEval_b);
prodXY_uid366_pT1_uid348_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid366_pT1_uid348_invPolyEval_a <= (others => '0');
prodXY_uid366_pT1_uid348_invPolyEval_b <= (others => '0');
prodXY_uid366_pT1_uid348_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid366_pT1_uid348_invPolyEval_a <= reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q;
prodXY_uid366_pT1_uid348_invPolyEval_b <= reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q;
prodXY_uid366_pT1_uid348_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid366_pT1_uid348_invPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid366_pT1_uid348_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid366_pT1_uid348_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid366_pT1_uid348_invPolyEval_q <= prodXY_uid366_pT1_uid348_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid367_pT1_uid348_invPolyEval(BITSELECT,366)@7
prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in <= prodXY_uid366_pT1_uid348_invPolyEval_q;
prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in(23 downto 11);
--highBBits_uid350_invPolyEval(BITSELECT,349)@7
highBBits_uid350_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b;
highBBits_uid350_invPolyEval_b <= highBBits_uid350_invPolyEval_in(12 downto 1);
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a(DELAY,804)@1
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid345_invTabGen_lutmem(DUALMEM,375)@4
memoryC1_uid345_invTabGen_lutmem_ia <= (others => '0');
memoryC1_uid345_invTabGen_lutmem_aa <= (others => '0');
memoryC1_uid345_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q;
memoryC1_uid345_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 20,
widthad_a => 8,
numwords_a => 256,
width_b => 20,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC1_uid345_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid345_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid345_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid345_invTabGen_lutmem_iq,
address_a => memoryC1_uid345_invTabGen_lutmem_aa,
data_a => memoryC1_uid345_invTabGen_lutmem_ia
);
memoryC1_uid345_invTabGen_lutmem_reset0 <= areset;
memoryC1_uid345_invTabGen_lutmem_q <= memoryC1_uid345_invTabGen_lutmem_iq(19 downto 0);
--reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0(REG,383)@6
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= "00000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= memoryC1_uid345_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid351_invPolyEval(ADD,350)@7
sumAHighB_uid351_invPolyEval_a <= STD_LOGIC_VECTOR((20 downto 20 => reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q(19)) & reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q);
sumAHighB_uid351_invPolyEval_b <= STD_LOGIC_VECTOR((20 downto 12 => highBBits_uid350_invPolyEval_b(11)) & highBBits_uid350_invPolyEval_b);
sumAHighB_uid351_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid351_invPolyEval_a) + SIGNED(sumAHighB_uid351_invPolyEval_b));
sumAHighB_uid351_invPolyEval_q <= sumAHighB_uid351_invPolyEval_o(20 downto 0);
--lowRangeB_uid349_invPolyEval(BITSELECT,348)@7
lowRangeB_uid349_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b(0 downto 0);
lowRangeB_uid349_invPolyEval_b <= lowRangeB_uid349_invPolyEval_in(0 downto 0);
--s1_uid349_uid352_invPolyEval(BITJOIN,351)@7
s1_uid349_uid352_invPolyEval_q <= sumAHighB_uid351_invPolyEval_q & lowRangeB_uid349_invPolyEval_b;
--reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1(REG,385)@7
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= "0000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= s1_uid349_uid352_invPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor(LOGICAL,1059)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a or ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b);
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg(REG,966)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena(REG,1060)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q = "1") THEN
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd(LOGICAL,1061)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b <= en;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg(DELAY,1051)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt(COUNTER,962)
-- every=1, low=0, high=1, step=1, init=1
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i,1));
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg(REG,963)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux(MUX,964)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s <= en;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux: PROCESS (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q)
BEGIN
CASE ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s IS
WHEN "0" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
WHEN "1" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q;
WHEN OTHERS => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem(DUALMEM,1052)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia
);
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0(REG,384)@7
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid369_pT2_uid354_invPolyEval(MULT,368)@8
prodXY_uid369_pT2_uid354_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid369_pT2_uid354_invPolyEval_a),16)) * SIGNED(prodXY_uid369_pT2_uid354_invPolyEval_b);
prodXY_uid369_pT2_uid354_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid369_pT2_uid354_invPolyEval_a <= (others => '0');
prodXY_uid369_pT2_uid354_invPolyEval_b <= (others => '0');
prodXY_uid369_pT2_uid354_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid369_pT2_uid354_invPolyEval_a <= reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q;
prodXY_uid369_pT2_uid354_invPolyEval_b <= reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q;
prodXY_uid369_pT2_uid354_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid369_pT2_uid354_invPolyEval_pr,37));
END IF;
END IF;
END PROCESS;
prodXY_uid369_pT2_uid354_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid369_pT2_uid354_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid369_pT2_uid354_invPolyEval_q <= prodXY_uid369_pT2_uid354_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid370_pT2_uid354_invPolyEval(BITSELECT,369)@11
prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in <= prodXY_uid369_pT2_uid354_invPolyEval_q;
prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in(36 downto 14);
--highBBits_uid356_invPolyEval(BITSELECT,355)@11
highBBits_uid356_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b;
highBBits_uid356_invPolyEval_b <= highBBits_uid356_invPolyEval_in(22 downto 2);
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor(LOGICAL,1048)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q <= not (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a or ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b);
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top(CONSTANT,1031)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q <= "0100";
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp(LOGICAL,1032)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q <= "1" when ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a = ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b else "0";
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg(REG,1033)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena(REG,1049)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd(LOGICAL,1050)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a and ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg(DELAY,1038)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt(COUNTER,1027)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i,3));
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg(REG,1028)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux(MUX,1029)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s <= en;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux: PROCESS (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem(DUALMEM,1039)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq(7 downto 0);
--memoryC0_uid344_invTabGen_lutmem(DUALMEM,374)@8
memoryC0_uid344_invTabGen_lutmem_ia <= (others => '0');
memoryC0_uid344_invTabGen_lutmem_aa <= (others => '0');
memoryC0_uid344_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q;
memoryC0_uid344_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC0_uid344_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid344_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid344_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid344_invTabGen_lutmem_iq,
address_a => memoryC0_uid344_invTabGen_lutmem_aa,
data_a => memoryC0_uid344_invTabGen_lutmem_ia
);
memoryC0_uid344_invTabGen_lutmem_reset0 <= areset;
memoryC0_uid344_invTabGen_lutmem_q <= memoryC0_uid344_invTabGen_lutmem_iq(28 downto 0);
--reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0(REG,387)@10
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= "00000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= memoryC0_uid344_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid357_invPolyEval(ADD,356)@11
sumAHighB_uid357_invPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q(28)) & reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q);
sumAHighB_uid357_invPolyEval_b <= STD_LOGIC_VECTOR((29 downto 21 => highBBits_uid356_invPolyEval_b(20)) & highBBits_uid356_invPolyEval_b);
sumAHighB_uid357_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid357_invPolyEval_a) + SIGNED(sumAHighB_uid357_invPolyEval_b));
sumAHighB_uid357_invPolyEval_q <= sumAHighB_uid357_invPolyEval_o(29 downto 0);
--lowRangeB_uid355_invPolyEval(BITSELECT,354)@11
lowRangeB_uid355_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b(1 downto 0);
lowRangeB_uid355_invPolyEval_b <= lowRangeB_uid355_invPolyEval_in(1 downto 0);
--s2_uid355_uid358_invPolyEval(BITJOIN,357)@11
s2_uid355_uid358_invPolyEval_q <= sumAHighB_uid357_invPolyEval_q & lowRangeB_uid355_invPolyEval_b;
--fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,255)@11
fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in <= s2_uid355_uid358_invPolyEval_q(28 downto 0);
fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in(28 downto 5);
--fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,261)@11
fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b(22 downto 0);
fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,688)@0
ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest(MUX,262)@11
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q;
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1(REG,388)@1
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,701)@2
ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 10 )
PORT MAP ( xin => reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest(MUX,268)@12
fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q;
fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid273_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,272)@12
R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q <= ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q & fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,905)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a or ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,901)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "01001";
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,902)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,903)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,906)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,907)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,895)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,897)
-- every=1, low=0, high=9, step=1, init=1
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 8 THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 9;
ELSE
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,4));
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,898)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,899)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,896)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 4,
numwords_a => 10,
width_b => 32,
widthad_b => 4,
numwords_b => 10,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(31 downto 0);
--path2_uid56_atanX_uid8_fpArctanPiTest(COMPARE,55)@0
path2_uid56_atanX_uid8_fpArctanPiTest_cin <= GND_q;
path2_uid56_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid15_atanX_uid8_fpArctanPiTest_b) & '0';
path2_uid56_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q) & path2_uid56_atanX_uid8_fpArctanPiTest_cin(0);
path2_uid56_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_b));
path2_uid56_atanX_uid8_fpArctanPiTest_n(0) <= not path2_uid56_atanX_uid8_fpArctanPiTest_o(10);
--reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1(REG,390)@0
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= path2_uid56_atanX_uid8_fpArctanPiTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b(DELAY,466)@1
ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--u_uid58_atanX_uid8_fpArctanPiTest(MUX,57)@12
u_uid58_atanX_uid8_fpArctanPiTest_s <= ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q;
u_uid58_atanX_uid8_fpArctanPiTest: PROCESS (u_uid58_atanX_uid8_fpArctanPiTest_s, en, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q, R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE u_uid58_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => u_uid58_atanX_uid8_fpArctanPiTest_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q;
WHEN "1" => u_uid58_atanX_uid8_fpArctanPiTest_q <= R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => u_uid58_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracU_uid60_atanX_uid8_fpArctanPiTest(BITSELECT,59)@12
fracU_uid60_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracU_uid60_atanX_uid8_fpArctanPiTest_b <= fracU_uid60_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a(DELAY,471)@12
ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracU_uid60_atanX_uid8_fpArctanPiTest_b, xout => ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest(BITJOIN,60)@13
oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q;
--oFracUExt_uid70_atanX_uid8_fpArctanPiTest(BITJOIN,69)@13
oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q <= cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q & oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q;
--X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,282)@13
X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(24 downto 0);
X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(24 downto 0);
--leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,281)
leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000000000000";
--leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,283)@13
leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5(REG,399)@13
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,279)@13
X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(28 downto 0);
X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(28 downto 0);
--leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,280)@13
leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4(REG,398)@13
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,276)@13
X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(32 downto 0);
X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(32 downto 0);
--leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,275)
leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "0000";
--leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,277)@13
leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3(REG,397)@13
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,396)@13
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--zS_uid67_atanX_uid8_fpArctanPiTest(CONSTANT,66)
zS_uid67_atanX_uid8_fpArctanPiTest_q <= "000000000";
--shiftBias_uid64_atanX_uid8_fpArctanPiTest(CONSTANT,63)
shiftBias_uid64_atanX_uid8_fpArctanPiTest_q <= "01110010";
--expU_uid59_atanX_uid8_fpArctanPiTest(BITSELECT,58)@12
expU_uid59_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expU_uid59_atanX_uid8_fpArctanPiTest_b <= expU_uid59_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1(REG,391)@12
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= expU_uid59_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--shiftValue_uid65_atanX_uid8_fpArctanPiTest(SUB,64)@13
shiftValue_uid65_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q);
shiftValue_uid65_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid64_atanX_uid8_fpArctanPiTest_q);
shiftValue_uid65_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_b));
shiftValue_uid65_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--ShiftValue8_uid66_atanX_uid8_fpArctanPiTest(BITSELECT,65)@13
ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q;
ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in(8 downto 8);
--shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest(MUX,67)@13
shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b;
shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest: PROCESS (shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s, en, shiftValue_uid65_atanX_uid8_fpArctanPiTest_q, zS_uid67_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= zS_uid67_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest(BITSELECT,70)@13
fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in <= shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q(3 downto 0);
fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,284)@13
leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b;
leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,395)@13
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,285)@14
leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q;
leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q, reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q, reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q;
WHEN "11" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,293)@14
LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(33 downto 0);
LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(33 downto 0);
--ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,725)@14
ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,292)
leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000";
--leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,294)@15
leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,290)@14
LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(34 downto 0);
LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(34 downto 0);
--ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,723)@14
ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,289)
leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "00";
--leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,291)@15
leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,287)@14
LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0);
LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(35 downto 0);
--ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,721)@14
ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,288)@15
leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & GND_q;
--reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,401)@14
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,295)@13
leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a(DELAY,829)@13
ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,400)@14
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,296)@15
leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q;
leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid73_atanX_uid8_fpArctanPiTest(BITSELECT,72)@15
y_uid73_atanX_uid8_fpArctanPiTest_in <= leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0);
y_uid73_atanX_uid8_fpArctanPiTest_b <= y_uid73_atanX_uid8_fpArctanPiTest_in(35 downto 1);
--yAddr_uid75_atanX_uid8_fpArctanPiTest(BITSELECT,74)@15
yAddr_uid75_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b;
yAddr_uid75_atanX_uid8_fpArctanPiTest_b <= yAddr_uid75_atanX_uid8_fpArctanPiTest_in(34 downto 27);
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0(REG,402)@15
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= yAddr_uid75_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid301_atanXOXTabGen_lutmem(DUALMEM,373)@16
memoryC2_uid301_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC2_uid301_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC2_uid301_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q;
memoryC2_uid301_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC2_uid301_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid301_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid301_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid301_atanXOXTabGen_lutmem_iq,
address_a => memoryC2_uid301_atanXOXTabGen_lutmem_aa,
data_a => memoryC2_uid301_atanXOXTabGen_lutmem_ia
);
memoryC2_uid301_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC2_uid301_atanXOXTabGen_lutmem_q <= memoryC2_uid301_atanXOXTabGen_lutmem_iq(12 downto 0);
--reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1(REG,404)@18
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= memoryC2_uid301_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--yPPolyEval_uid76_atanX_uid8_fpArctanPiTest(BITSELECT,75)@15
yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b(26 downto 0);
yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in(26 downto 9);
--yT1_uid302_atanXOXPolyEval(BITSELECT,301)@15
yT1_uid302_atanXOXPolyEval_in <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b;
yT1_uid302_atanXOXPolyEval_b <= yT1_uid302_atanXOXPolyEval_in(17 downto 5);
--ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg(DELAY,1062)
ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid302_atanXOXPolyEval_b, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a(DELAY,832)@15
ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0(REG,403)@18
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid360_pT1_uid303_atanXOXPolyEval(MULT,359)@19
prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_a),14)) * SIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_b);
prodXY_uid360_pT1_uid303_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= (others => '0');
prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= (others => '0');
prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q;
prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q;
prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid360_pT1_uid303_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval(BITSELECT,360)@22
prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_q;
prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in(25 downto 12);
--highBBits_uid305_atanXOXPolyEval(BITSELECT,304)@22
highBBits_uid305_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b;
highBBits_uid305_atanXOXPolyEval_b <= highBBits_uid305_atanXOXPolyEval_in(13 downto 1);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a(DELAY,834)@15
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0(REG,405)@18
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid300_atanXOXTabGen_lutmem(DUALMEM,372)@19
memoryC1_uid300_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC1_uid300_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC1_uid300_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q;
memoryC1_uid300_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC1_uid300_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid300_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid300_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid300_atanXOXTabGen_lutmem_iq,
address_a => memoryC1_uid300_atanXOXTabGen_lutmem_aa,
data_a => memoryC1_uid300_atanXOXTabGen_lutmem_ia
);
memoryC1_uid300_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC1_uid300_atanXOXTabGen_lutmem_q <= memoryC1_uid300_atanXOXTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0(REG,406)@21
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= memoryC1_uid300_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid306_atanXOXPolyEval(ADD,305)@22
sumAHighB_uid306_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q(20)) & reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q);
sumAHighB_uid306_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid305_atanXOXPolyEval_b(12)) & highBBits_uid305_atanXOXPolyEval_b);
sumAHighB_uid306_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid306_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid306_atanXOXPolyEval_b));
sumAHighB_uid306_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_o(21 downto 0);
--lowRangeB_uid304_atanXOXPolyEval(BITSELECT,303)@22
lowRangeB_uid304_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b(0 downto 0);
lowRangeB_uid304_atanXOXPolyEval_b <= lowRangeB_uid304_atanXOXPolyEval_in(0 downto 0);
--s1_uid304_uid307_atanXOXPolyEval(BITJOIN,306)@22
s1_uid304_uid307_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_q & lowRangeB_uid304_atanXOXPolyEval_b;
--reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1(REG,408)@22
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= s1_uid304_uid307_atanXOXPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor(LOGICAL,1035)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q <= not (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a or ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b);
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena(REG,1036)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd(LOGICAL,1037)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b <= en;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a and ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b;
--reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0(REG,407)@15
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg(DELAY,1025)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q, xout => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem(DUALMEM,1026)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq,
address_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa,
data_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia
);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid363_pT2_uid309_atanXOXPolyEval(MULT,362)@23
prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_a),19)) * SIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_b);
prodXY_uid363_pT2_uid309_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= (others => '0');
prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= (others => '0');
prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q;
prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q;
prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid363_pT2_uid309_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval(BITSELECT,363)@26
prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_q;
prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in(40 downto 17);
--highBBits_uid311_atanXOXPolyEval(BITSELECT,310)@26
highBBits_uid311_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b;
highBBits_uid311_atanXOXPolyEval_b <= highBBits_uid311_atanXOXPolyEval_in(23 downto 2);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor(LOGICAL,1073)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q <= not (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a or ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena(REG,1074)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q = "1") THEN
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd(LOGICAL,1075)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b <= en;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a and ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b;
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg(DELAY,1063)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem(DUALMEM,1064)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia
);
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0(REG,409)@22
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid299_atanXOXTabGen_lutmem(DUALMEM,371)@23
memoryC0_uid299_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC0_uid299_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC0_uid299_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q;
memoryC0_uid299_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 31,
widthad_a => 8,
numwords_a => 256,
width_b => 31,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC0_uid299_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid299_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid299_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid299_atanXOXTabGen_lutmem_iq,
address_a => memoryC0_uid299_atanXOXTabGen_lutmem_aa,
data_a => memoryC0_uid299_atanXOXTabGen_lutmem_ia
);
memoryC0_uid299_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC0_uid299_atanXOXTabGen_lutmem_q <= memoryC0_uid299_atanXOXTabGen_lutmem_iq(30 downto 0);
--reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0(REG,410)@25
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= memoryC0_uid299_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid312_atanXOXPolyEval(ADD,311)@26
sumAHighB_uid312_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((31 downto 31 => reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q(30)) & reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q);
sumAHighB_uid312_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((31 downto 22 => highBBits_uid311_atanXOXPolyEval_b(21)) & highBBits_uid311_atanXOXPolyEval_b);
sumAHighB_uid312_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid312_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid312_atanXOXPolyEval_b));
sumAHighB_uid312_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_o(31 downto 0);
--lowRangeB_uid310_atanXOXPolyEval(BITSELECT,309)@26
lowRangeB_uid310_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b(1 downto 0);
lowRangeB_uid310_atanXOXPolyEval_b <= lowRangeB_uid310_atanXOXPolyEval_in(1 downto 0);
--s2_uid310_uid313_atanXOXPolyEval(BITJOIN,312)@26
s2_uid310_uid313_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_q & lowRangeB_uid310_atanXOXPolyEval_b;
--fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest(BITSELECT,77)@26
fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in <= s2_uid310_uid313_atanXOXPolyEval_q(31 downto 0);
fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in(31 downto 5);
--reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1(REG,412)@26
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,918)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,914)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01010";
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,915)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,916)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,919)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,920)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0(REG,411)@13
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,908)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,910)
-- every=1, low=0, high=10, step=1, init=1
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 9 THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 10;
ELSE
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4));
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,911)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,912)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,909)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 11,
width_b => 24,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(23 downto 0);
--mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest(MULT,78)@27
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr <= UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a) * UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b);
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= (others => '0');
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= (others => '0');
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr);
END IF;
END IF;
END PROCESS;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid80_atanX_uid8_fpArctanPiTest(BITSELECT,79)@30
normBit_uid80_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(49 downto 0);
normBit_uid80_atanX_uid8_fpArctanPiTest_b <= normBit_uid80_atanX_uid8_fpArctanPiTest_in(49 downto 49);
--InvNormBit_uid84_atanX_uid8_fpArctanPiTest(LOGICAL,83)@30
InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a <= normBit_uid80_atanX_uid8_fpArctanPiTest_b;
InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q <= not InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,931)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,927)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01111";
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,928)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,929)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,932)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,933)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,921)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expU_uid59_atanX_uid8_fpArctanPiTest_b, xout => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,923)
-- every=1, low=0, high=15, step=1, init=1
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4));
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,924)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,925)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,922)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 16,
width_b => 8,
widthad_b => 4,
numwords_b => 16,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(7 downto 0);
--expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest(SUB,84)@30
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q);
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000" & InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q);
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b));
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--fracRPath3High_uid81_atanX_uid8_fpArctanPiTest(BITSELECT,80)@30
fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(48 downto 0);
fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in(48 downto 25);
--fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest(BITSELECT,81)@30
fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(47 downto 0);
fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in(47 downto 24);
--fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest(MUX,82)@30
fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s <= normBit_uid80_atanX_uid8_fpArctanPiTest_b;
fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s, en, fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b, fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b)
BEGIN
CASE fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest(BITJOIN,85)@30
expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q & fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q;
--reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0(REG,420)@30
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest(ADD,86)@31
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q);
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000" & VCC_q);
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b));
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o(33 downto 0);
--expRPath3_uid89_atanX_uid8_fpArctanPiTest(BITSELECT,88)@31
expRPath3_uid89_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(31 downto 0);
expRPath3_uid89_atanX_uid8_fpArctanPiTest_b <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_in(31 downto 24);
--reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4(REG,427)@31
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,971)
ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e(DELAY,534)@32
ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,337)@33
RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 1);
--rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,339)@33
rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= GND_q & RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,333)
rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000";
--rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,322)
rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000000000000000000000";
--X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,321)@32
X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 24);
--rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,323)@32
rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,319)
rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "0000000000000000";
--X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,318)@32
X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 16);
--rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,320)@32
rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,315)@32
X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 8);
--rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,317)@32
rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q & X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a(DELAY,504)@30
ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q, xout => ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest(BITJOIN,93)@32
oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q;
--cstWFP2_uid25_atanX_uid8_fpArctanPiTest(CONSTANT,24)
cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q <= "00011001";
--reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1(REG,413)@30
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest(SUB,89)@31
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q);
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR((10 downto 9 => reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q(8)) & reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q);
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a) - SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b));
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o(9 downto 0);
--shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest(BITSELECT,91)@31
shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q(7 downto 0);
shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest(CONSTANT,23)
cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q <= "01101000";
--shiftOut_uid91_atanX_uid8_fpArctanPiTest(COMPARE,90)@13
shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin <= GND_q;
shiftOut_uid91_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & '0';
shiftOut_uid91_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q) & shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin(0);
shiftOut_uid91_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_b));
shiftOut_uid91_atanX_uid8_fpArctanPiTest_c(0) <= shiftOut_uid91_atanX_uid8_fpArctanPiTest_o(10);
--ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b(DELAY,502)@13
ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => shiftOut_uid91_atanX_uid8_fpArctanPiTest_c, xout => ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--sValPostSOut_uid93_atanX_uid8_fpArctanPiTest(MUX,92)@31
sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s <= ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q;
sValPostSOut_uid93_atanX_uid8_fpArctanPiTest: PROCESS (sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s, en, shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b, cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest(BITSELECT,94)@31
sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in <= sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q(4 downto 0);
sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,324)@31
rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b;
rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,414)@31
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,325)@32
rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q;
rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,332)@32
RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 6);
--ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,762)@32
ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,334)@33
rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,329)@32
RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 4);
--ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,760)@32
ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 21, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,331)@33
rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,326)@32
RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 2);
--ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,758)@32
ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,328)@33
rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2(REG,416)@32
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,335)@31
rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(2 downto 1);
--ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a(DELAY,844)@31
ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,415)@32
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,336)@33
rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q;
rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q, rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,340)@31
rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,417)@31
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b(DELAY,772)@32
ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,341)@33
rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q;
rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest(BITJOIN,96)@33
pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & GND_q;
--reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1(REG,418)@33
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--path2Diff_uid97_atanX_uid8_fpArctanPiTest(SUB,97)@34
path2Diff_uid97_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & piO2_uid46_atanX_uid8_fpArctanPiTest_q);
path2Diff_uid97_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q);
path2Diff_uid97_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_b));
path2Diff_uid97_atanX_uid8_fpArctanPiTest_q <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_o(26 downto 0);
--normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest(BITSELECT,98)@34
normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(25 downto 0);
normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in(25 downto 25);
--expRPath2_uid103_atanX_uid8_fpArctanPiTest(MUX,102)@34
expRPath2_uid103_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b;
expRPath2_uid103_atanX_uid8_fpArctanPiTest: PROCESS (expRPath2_uid103_atanX_uid8_fpArctanPiTest_s, en, cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q, cstBias_uid22_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPath2_uid103_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest(BITSELECT,99)@34
path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(24 downto 0);
path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in(24 downto 1);
--path2DiffLow_uid101_atanX_uid8_fpArctanPiTest(BITSELECT,100)@34
path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(23 downto 0);
path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in(23 downto 0);
--fracRPath2_uid102_atanX_uid8_fpArctanPiTest(MUX,101)@34
fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b;
fracRPath2_uid102_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s, en, path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b, path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b)
BEGIN
CASE fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest(BITJOIN,103)@34
expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q <= expRPath2_uid103_atanX_uid8_fpArctanPiTest_q & fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q;
--reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0(REG,419)@34
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest(ADD,104)@35
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q);
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000" & VCC_q);
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b));
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o(32 downto 0);
--expRPath2_uid107_atanX_uid8_fpArctanPiTest(BITSELECT,106)@35
expRPath2_uid107_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(31 downto 0);
expRPath2_uid107_atanX_uid8_fpArctanPiTest_b <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_in(31 downto 24);
--reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3(REG,426)@35
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor(LOGICAL,1086)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q <= not (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a or ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b);
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena(REG,1087)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q = "1") THEN
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd(LOGICAL,1088)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b <= en;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a and ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg(DELAY,1076)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid15_atanX_uid8_fpArctanPiTest_b, xout => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem(DUALMEM,1077)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 33,
width_b => 8,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq,
address_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa,
data_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia
);
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 <= areset;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq(7 downto 0);
--reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2(REG,425)@35
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,944)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,940)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "010010";
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,941)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,942)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,945)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,946)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--expXIsBias_uid44_atanX_uid8_fpArctanPiTest(LOGICAL,43)@0
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q;
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a = expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b else "0";
--inIsOne_uid45_atanX_uid8_fpArctanPiTest(LOGICAL,44)@0
inIsOne_uid45_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
inIsOne_uid45_atanX_uid8_fpArctanPiTest_b <= expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q;
inIsOne_uid45_atanX_uid8_fpArctanPiTest_q <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_a and inIsOne_uid45_atanX_uid8_fpArctanPiTest_b;
--arctanIsConst_uid55_atanX_uid8_fpArctanPiTest(LOGICAL,54)@0
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_q;
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a or arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c(DELAY,522)@1
ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q, xout => ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasMwShift_uid62_atanX_uid8_fpArctanPiTest(CONSTANT,61)
biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q <= "01110011";
--atanUIsU_uid63_atanX_uid8_fpArctanPiTest(COMPARE,62)@13
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin <= GND_q;
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q) & '0';
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin(0);
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b));
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n(0) <= not atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o(10);
--ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a(DELAY,520)@0
ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => path2_uid56_atanX_uid8_fpArctanPiTest_n, xout => ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--pathSelBits_uid108_atanX_uid8_fpArctanPiTest(BITJOIN,107)@13
pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q <= ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n & ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q;
--reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0(REG,392)@13
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,934)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,936)
-- every=1, low=0, high=18, step=1, init=1
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 17 THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 18;
ELSE
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,5));
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,937)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,938)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,935)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 19,
width_b => 3,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(2 downto 0);
--fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest(LOOKUP,108)@35
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q) IS
WHEN "000" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "001" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "010" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "011" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "110" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "111" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN OTHERS =>
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRCalc_uid113_atanX_uid8_fpArctanPiTest(MUX,112)@36
expRCalc_uid113_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q;
expRCalc_uid113_atanX_uid8_fpArctanPiTest: PROCESS (expRCalc_uid113_atanX_uid8_fpArctanPiTest_s, en, reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q, reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q, ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE expRCalc_uid113_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q;
WHEN "11" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstAllZWE_uid21_atanX_uid8_fpArctanPiTest(CONSTANT,20)
cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q <= "00000000";
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,995)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a or ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,996)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,997)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,985)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid38_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,986)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,982)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,983)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,984)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,972)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q, xout => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,973)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(0 downto 0);
--excSelBits_uid114_atanX_uid8_fpArctanPiTest(BITJOIN,113)@35
excSelBits_uid114_atanX_uid8_fpArctanPiTest_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q & GND_q & ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q;
--reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0(REG,377)@35
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid114_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest(LOOKUP,114)@36
outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid117_atanX_uid8_fpArctanPiTest(MUX,116)@36
expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q;
expRPostExc_uid117_atanX_uid8_fpArctanPiTest: PROCESS (expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, expRCalc_uid113_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid113_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracOutCst_uid110_atanX_uid8_fpArctanPiTest(BITSELECT,109)@35
fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5(REG,424)@35
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor(LOGICAL,968)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q <= not (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a or ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b);
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena(REG,969)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd(LOGICAL,970)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b <= en;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a and ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b;
--fracRPath3_uid88_atanX_uid8_fpArctanPiTest(BITSELECT,87)@31
fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(23 downto 0);
fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in(23 downto 1);
--reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4(REG,423)@31
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,960)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem(DUALMEM,961)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 1,
numwords_a => 2,
width_b => 23,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq,
address_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa,
data_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia
);
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 <= areset;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq(22 downto 0);
--fracRPath2_uid106_atanX_uid8_fpArctanPiTest(BITSELECT,105)@35
fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(23 downto 0);
fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in(23 downto 1);
--reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3(REG,422)@35
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,957)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a or ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,958)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,959)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2(REG,421)@0
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,947)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,948)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 33,
width_b => 23,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(22 downto 0);
--fracRCalc_uid111_atanX_uid8_fpArctanPiTest(MUX,110)@36
fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q;
fracRCalc_uid111_atanX_uid8_fpArctanPiTest: PROCESS (fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s, en, ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q, reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q, reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q;
WHEN "01" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q;
WHEN "11" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid116_atanX_uid8_fpArctanPiTest(MUX,115)@36
fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q;
fracRPostExc_uid116_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid120_atanX_uid8_fpArctanPiTest(BITJOIN,119)@36
R_uid120_atanX_uid8_fpArctanPiTest_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q & expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q & fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q;
--fracX_uid126_rAtanPi_uid13_fpArctanPiTest(BITSELECT,125)@36
fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0);
--reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1(REG,431)@36
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest(LOGICAL,137)@37
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a <= reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q;
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b else "0";
--expX_uid122_rAtanPi_uid13_fpArctanPiTest(BITSELECT,121)@36
expX_uid122_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expX_uid122_rAtanPi_uid13_fpArctanPiTest_b <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23);
--reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1(REG,429)@36
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest(LOGICAL,135)@37
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q;
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b else "0";
--exc_I_uid139_rAtanPi_uid13_fpArctanPiTest(LOGICAL,138)@37
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q;
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q;
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b;
--cstBiasM2_uid6_fpArctanPiTest(CONSTANT,5)
cstBiasM2_uid6_fpArctanPiTest_q <= "01111101";
--ooPi_uid9_fpArctanPiTest(CONSTANT,8)
ooPi_uid9_fpArctanPiTest_q <= "101000101111100110000011";
--fracOOPi_uid10_fpArctanPiTest(BITSELECT,9)@36
fracOOPi_uid10_fpArctanPiTest_in <= ooPi_uid9_fpArctanPiTest_q(22 downto 0);
fracOOPi_uid10_fpArctanPiTest_b <= fracOOPi_uid10_fpArctanPiTest_in(22 downto 0);
--fpOOPi_uid11_fpArctanPiTest(BITJOIN,10)@36
fpOOPi_uid11_fpArctanPiTest_q <= GND_q & cstBiasM2_uid6_fpArctanPiTest_q & fracOOPi_uid10_fpArctanPiTest_b;
--expY_uid123_rAtanPi_uid13_fpArctanPiTest(BITSELECT,122)@36
expY_uid123_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(30 downto 0);
expY_uid123_rAtanPi_uid13_fpArctanPiTest_b <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23);
--expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest(LOGICAL,149)@36
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b;
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a(DELAY,581)@36
ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest(LOGICAL,203)@37
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b;
--fracY_uid128_rAtanPi_uid13_fpArctanPiTest(BITSELECT,127)@36
fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(22 downto 0);
fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0);
--fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest(LOGICAL,153)@36
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b;
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b(DELAY,575)@36
ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest(LOGICAL,151)@36
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b;
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a(DELAY,574)@36
ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid155_rAtanPi_uid13_fpArctanPiTest(LOGICAL,154)@37
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q;
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b <= ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q;
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b;
--expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest(LOGICAL,133)@37
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q;
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b else "0";
--excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest(LOGICAL,204)@37
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b;
--ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest(LOGICAL,205)@37
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q;
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q;
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a or ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b;
--InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest(LOGICAL,155)@36
InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q;
InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a;
--exc_N_uid157_rAtanPi_uid13_fpArctanPiTest(LOGICAL,156)@36
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b;
--ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a(DELAY,579)@36
ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest(LOGICAL,139)@37
InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q;
InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a;
--exc_N_uid141_rAtanPi_uid13_fpArctanPiTest(LOGICAL,140)@37
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b;
--excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest(LOGICAL,206)@37
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c;
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest(LOGICAL,218)@37
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q;
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= not InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a;
END IF;
END PROCESS;
--signY_uid125_rAtanPi_uid13_fpArctanPiTest(BITSELECT,124)@36
signY_uid125_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q;
signY_uid125_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31);
--signX_uid124_rAtanPi_uid13_fpArctanPiTest(BITSELECT,123)@36
signX_uid124_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q;
signX_uid124_rAtanPi_uid13_fpArctanPiTest_b <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31);
--signR_uid190_rAtanPi_uid13_fpArctanPiTest(LOGICAL,189)@36
signR_uid190_rAtanPi_uid13_fpArctanPiTest_a <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_b;
signR_uid190_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_b;
signR_uid190_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= signR_uid190_rAtanPi_uid13_fpArctanPiTest_a xor signR_uid190_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a(DELAY,666)@37
ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid190_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest(LOGICAL,219)@38
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a <= ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q;
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b <= InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q;
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q <= signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a and signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b;
--ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c(DELAY,670)@38
ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest(BITJOIN,128)@36
add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b;
--reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1(REG,433)@36
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest(BITJOIN,126)@36
add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b;
--reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0(REG,432)@36
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--prod_uid165_rAtanPi_uid13_fpArctanPiTest(MULT,164)@37
prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr <= UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_a) * UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_b);
prod_uid165_rAtanPi_uid13_fpArctanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= (others => '0');
prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= (others => '0');
prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q;
prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q;
prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr);
END IF;
END IF;
END PROCESS;
prod_uid165_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1;
END IF;
END IF;
END PROCESS;
--normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest(BITSELECT,165)@40
normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q;
normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in(47 downto 47);
--roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest(CONSTANT,179)
roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q <= "010";
--fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest(BITSELECT,167)@40
fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(46 downto 0);
fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in(46 downto 23);
--fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest(BITSELECT,168)@40
fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(45 downto 0);
fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in(45 downto 22);
--fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest(MUX,169)@40
fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b;
fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s, en, fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b, fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b)
BEGIN
CASE fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "0" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b;
WHEN "1" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b;
WHEN OTHERS => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest(BITSELECT,177)@40
FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in <= fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q(1 downto 0);
FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in(1 downto 0);
--Prod22_uid172_rAtanPi_uid13_fpArctanPiTest(BITSELECT,171)@40
Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(22 downto 0);
Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in(22 downto 22);
--extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest(MUX,172)@40
extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b;
extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest: PROCESS (extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s, en, GND_q, Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b)
BEGIN
CASE extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "0" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b;
WHEN OTHERS => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest(BITSELECT,170)@40
stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(21 downto 0);
stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b <= stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in(21 downto 0);
--stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest(BITJOIN,173)@40
stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q <= extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q & stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b;
--stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest(LOGICAL,175)@40
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a <= stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q;
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q <= "1" when stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a = stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b else "0";
--sticky_uid177_rAtanPi_uid13_fpArctanPiTest(LOGICAL,176)@40
sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a <= stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q;
sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q <= not sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a;
--lrs_uid179_rAtanPi_uid13_fpArctanPiTest(BITJOIN,178)@40
lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b & sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q;
--roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest(LOGICAL,180)@40
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a <= lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q;
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b <= roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q;
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q <= "1" when roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a = roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b else "0";
--roundBit_uid182_rAtanPi_uid13_fpArctanPiTest(LOGICAL,181)@40
roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a <= roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q;
roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q <= not roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a;
--roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest(BITJOIN,184)@40
roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q <= GND_q & normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b & cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q & roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q;
--reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1(REG,436)@40
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--biasInc_uid163_rAtanPi_uid13_fpArctanPiTest(CONSTANT,162)
biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q <= "0001111111";
--ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b(DELAY,586)@36
ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expY_uid123_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expSum_uid162_rAtanPi_uid13_fpArctanPiTest(ADD,161)@37
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q);
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q);
expSum_uid162_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a) + UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q <= expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o(8 downto 0);
--ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a(DELAY,587)@38
ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest(SUB,163)@39
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q);
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q(9)) & biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q);
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b));
END IF;
END IF;
END PROCESS;
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o(10 downto 0);
--expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest(BITJOIN,182)@40
expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q & fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q;
--reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0(REG,435)@40
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest(ADD,185)@41
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q(34)) & reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q);
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q);
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a) + SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b));
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o(35 downto 0);
--expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest(BITSELECT,187)@41
expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q;
expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in(35 downto 24);
--expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest(BITSELECT,188)@41
expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b(7 downto 0);
expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in(7 downto 0);
--ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d(DELAY,664)@41
ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 2 )
PORT MAP ( xin => expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c(DELAY,659)@37
ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1(REG,437)@41
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid193_rAtanPi_uid13_fpArctanPiTest(COMPARE,192)@42
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q;
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & '0';
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q) & expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin(0);
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b));
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o(14);
--InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest(LOGICAL,157)@37
InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q;
InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a;
--InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest(LOGICAL,158)@37
InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a;
--InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest(LOGICAL,159)@37
InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a;
--exc_R_uid161_rAtanPi_uid13_fpArctanPiTest(LOGICAL,160)@37
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c;
--ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b(DELAY,629)@37
ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest(LOGICAL,141)@37
InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a;
--InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest(LOGICAL,142)@37
InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a;
--InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest(LOGICAL,143)@37
InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a;
--exc_R_uid145_rAtanPi_uid13_fpArctanPiTest(LOGICAL,144)@37
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c;
--ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a(DELAY,628)@37
ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest(LOGICAL,201)@42
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c <= expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c;
--excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest(LOGICAL,200)@37
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q;
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q <= excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a and excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c(DELAY,646)@37
ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest(LOGICAL,199)@37
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q;
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q <= excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a and excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b(DELAY,645)@37
ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest(LOGICAL,198)@37
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q <= excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a and excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a(DELAY,644)@37
ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid203_rAtanPi_uid13_fpArctanPiTest(LOGICAL,202)@42
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q <= excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d;
--expUdf_uid191_rAtanPi_uid13_fpArctanPiTest(COMPARE,190)@42
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q;
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0';
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin(0);
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b));
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o(14);
--excZC3_uid197_rAtanPi_uid13_fpArctanPiTest(LOGICAL,196)@42
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c <= expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c;
--excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest(LOGICAL,195)@37
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q;
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c(DELAY,633)@37
ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest(LOGICAL,194)@37
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b(DELAY,632)@37
ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest(LOGICAL,193)@37
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a(DELAY,631)@37
ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid198_rAtanPi_uid13_fpArctanPiTest(LOGICAL,197)@42
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q <= excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d;
--concExc_uid208_rAtanPi_uid13_fpArctanPiTest(BITJOIN,207)@42
concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q <= ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q & excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q & excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q;
--reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0(REG,439)@42
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid209_rAtanPi_uid13_fpArctanPiTest(LOOKUP,208)@43
excREnc_uid209_rAtanPi_uid13_fpArctanPiTest: PROCESS (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q) IS
WHEN "000" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "01";
WHEN "001" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "010" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "10";
WHEN "011" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "100" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "11";
WHEN "101" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "110" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "111" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN OTHERS =>
excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest(MUX,217)@43
expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q;
expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest: PROCESS (expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q;
WHEN "10" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest(BITSELECT,186)@41
fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q(23 downto 0);
fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b <= fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in(23 downto 1);
--ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d(DELAY,662)@41
ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest(MUX,212)@43
fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q;
fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q;
WHEN "10" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid221_rAtanPi_uid13_fpArctanPiTest(BITJOIN,220)@43
R_uid221_rAtanPi_uid13_fpArctanPiTest_q <= ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q & expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q & fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q;
--xOut(GPOUT,4)@43
q <= R_uid221_rAtanPi_uid13_fpArctanPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_atanpi_s5
-- VHDL created on Tue Mar 12 11:23:23 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_atanpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_atanpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBiasM2_uid6_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal ooPi_uid9_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal piO2_uid46_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0);
signal piO4_uid47_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid64_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal zS_uid67_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q : std_logic_vector (12 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a : std_logic_vector (23 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 : std_logic_vector (50 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr : UNSIGNED (50 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q : std_logic_vector (50 downto 0);
signal fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (9 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (10 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector (23 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 : std_logic_vector (47 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr : UNSIGNED (47 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (47 downto 0);
signal roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_q : std_logic_vector (40 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_b : std_logic_vector (21 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_s1 : std_logic_vector (36 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_pr : SIGNED (37 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_q : std_logic_vector (36 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid299_atanXOXTabGen_lutmem_ia : std_logic_vector (30 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_iq : std_logic_vector (30 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_q : std_logic_vector (30 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid300_atanXOXTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid301_atanXOXTabGen_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid344_invTabGen_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid345_invTabGen_lutmem_ia : std_logic_vector (19 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_iq : std_logic_vector (19 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_q : std_logic_vector (19 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid346_invTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q : std_logic_vector (19 downto 0);
signal reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q : std_logic_vector (21 downto 0);
signal reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q : std_logic_vector (28 downto 0);
signal reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q : std_logic_vector (30 downto 0);
signal reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (26 downto 0);
signal reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (8 downto 0);
signal reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (31 downto 0);
signal reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (32 downto 0);
signal reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (22 downto 0);
signal reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (22 downto 0);
signal reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (22 downto 0);
signal reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (7 downto 0);
signal reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (7 downto 0);
signal reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (22 downto 0);
signal reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (23 downto 0);
signal reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (34 downto 0);
signal reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (11 downto 0);
signal reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q : std_logic_vector (7 downto 0);
signal ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (7 downto 0);
signal ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (8 downto 0);
signal ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (22 downto 0);
signal ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (7 downto 0);
signal ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (20 downto 0);
signal ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (18 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q : std_logic_vector (12 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 : std_logic;
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : signal is true;
signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : signal is true;
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : signal is true;
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_c : std_logic_vector (0 downto 0);
signal excSelBits_uid114_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a : std_logic_vector(33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b : std_logic_vector(33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o : std_logic_vector (33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q : std_logic_vector (33 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o : std_logic_vector (32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0);
signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid15_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid15_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid16_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid16_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal singX_uid17_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal singX_uid17_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q : std_logic_vector (9 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_a : std_logic_vector(26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_b : std_logic_vector(26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_o : std_logic_vector (26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (26 downto 0);
signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (35 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal fracOOPi_uid10_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracOOPi_uid10_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid80_atanX_uid8_fpArctanPiTest_in : std_logic_vector (49 downto 0);
signal normBit_uid80_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in : std_logic_vector (48 downto 0);
signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in : std_logic_vector (47 downto 0);
signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (47 downto 0);
signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (46 downto 0);
signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (45 downto 0);
signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (21 downto 0);
signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (21 downto 0);
signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in : std_logic_vector (36 downto 0);
signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b : std_logic_vector (22 downto 0);
signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal R_uid221_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (14 downto 0);
signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (14 downto 0);
signal R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal constOut_uid54_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal constOut_uid54_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal u_uid58_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal u_uid58_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal R_uid120_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (16 downto 0);
signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (8 downto 0);
signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in : std_logic_vector (8 downto 0);
signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in : std_logic_vector (25 downto 0);
signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (11 downto 0);
signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (9 downto 0);
signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (33 downto 0);
signal fpOOPi_uid11_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (32 downto 0);
signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0);
signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (28 downto 0);
signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (24 downto 0);
signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (0 downto 0);
signal stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal lowRangeB_uid304_atanXOXPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid304_atanXOXPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid305_atanXOXPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid305_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid310_atanXOXPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid310_atanXOXPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid311_atanXOXPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid311_atanXOXPolyEval_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid349_invPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid349_invPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid350_invPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid350_invPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid355_invPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid355_invPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid356_invPolyEval_in : std_logic_vector (22 downto 0);
signal highBBits_uid356_invPolyEval_b : std_logic_vector (20 downto 0);
signal y_uid73_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal y_uid73_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0);
signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal yT1_uid347_invPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid347_invPolyEval_b : std_logic_vector (11 downto 0);
signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal expU_uid59_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expU_uid59_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracU_uid60_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracU_uid60_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0);
signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b : std_logic_vector (3 downto 0);
signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (1 downto 0);
signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (34 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_a : std_logic_vector(31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_b : std_logic_vector(31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_o : std_logic_vector (31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_q : std_logic_vector (31 downto 0);
signal sumAHighB_uid351_invPolyEval_a : std_logic_vector(20 downto 0);
signal sumAHighB_uid351_invPolyEval_b : std_logic_vector(20 downto 0);
signal sumAHighB_uid351_invPolyEval_o : std_logic_vector (20 downto 0);
signal sumAHighB_uid351_invPolyEval_q : std_logic_vector (20 downto 0);
signal sumAHighB_uid357_invPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid357_invPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid357_invPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid357_invPolyEval_q : std_logic_vector (29 downto 0);
signal yAddr_uid75_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0);
signal yAddr_uid75_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in : std_logic_vector (26 downto 0);
signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b : std_logic_vector (17 downto 0);
signal rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0);
signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b : std_logic_vector (4 downto 0);
signal expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0);
signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal s1_uid304_uid307_atanXOXPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid310_uid313_atanXOXPolyEval_q : std_logic_vector (33 downto 0);
signal s1_uid349_uid352_invPolyEval_q : std_logic_vector (21 downto 0);
signal s2_uid355_uid358_invPolyEval_q : std_logic_vector (31 downto 0);
signal yT1_uid302_atanXOXPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid302_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (20 downto 0);
signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (18 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0);
signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0);
signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (25 downto 0);
begin
--xIn(GPIN,3)@0
--cstAllZWF_uid19_atanX_uid8_fpArctanPiTest(CONSTANT,18)
cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000000";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable(LOGICAL,878)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q <= not ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,1008)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a or ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,1004)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100001";
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,1005)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,1006)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,1009)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,1010)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--fracX_uid16_atanX_uid8_fpArctanPiTest(BITSELECT,15)@0
fracX_uid16_atanX_uid8_fpArctanPiTest_in <= a(22 downto 0);
fracX_uid16_atanX_uid8_fpArctanPiTest_b <= fracX_uid16_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--fracXIsZero_uid35_atanX_uid8_fpArctanPiTest(LOGICAL,34)@0
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b else "0";
--InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest(LOGICAL,36)@0
InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q <= not InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a;
--cstAllOWE_uid18_atanX_uid8_fpArctanPiTest(CONSTANT,17)
cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q <= "11111111";
--expX_uid15_atanX_uid8_fpArctanPiTest(BITSELECT,14)@0
expX_uid15_atanX_uid8_fpArctanPiTest_in <= a(30 downto 0);
expX_uid15_atanX_uid8_fpArctanPiTest_b <= expX_uid15_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--expXIsMax_uid33_atanX_uid8_fpArctanPiTest(LOGICAL,32)@0
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a = expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b else "0";
--exc_N_uid38_atanX_uid8_fpArctanPiTest(LOGICAL,37)@0
exc_N_uid38_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q;
exc_N_uid38_atanX_uid8_fpArctanPiTest_b <= InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q;
exc_N_uid38_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_a and exc_N_uid38_atanX_uid8_fpArctanPiTest_b;
--InvExc_N_uid118_atanX_uid8_fpArctanPiTest(LOGICAL,117)@0
InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q;
InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q <= not InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a;
--singX_uid17_atanX_uid8_fpArctanPiTest(BITSELECT,16)@0
singX_uid17_atanX_uid8_fpArctanPiTest_in <= a;
singX_uid17_atanX_uid8_fpArctanPiTest_b <= singX_uid17_atanX_uid8_fpArctanPiTest_in(31 downto 31);
--signR_uid119_atanX_uid8_fpArctanPiTest(LOGICAL,118)@0
signR_uid119_atanX_uid8_fpArctanPiTest_a <= singX_uid17_atanX_uid8_fpArctanPiTest_b;
signR_uid119_atanX_uid8_fpArctanPiTest_b <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q;
signR_uid119_atanX_uid8_fpArctanPiTest_q <= signR_uid119_atanX_uid8_fpArctanPiTest_a and signR_uid119_atanX_uid8_fpArctanPiTest_b;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,998)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid119_atanX_uid8_fpArctanPiTest_q, xout => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,1000)
-- every=1, low=0, high=33, step=1, init=1
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 32 THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 33;
ELSE
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6));
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,1001)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,1002)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,999)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 34,
width_b => 1,
widthad_b => 6,
numwords_b => 34,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,879)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a or ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,875)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100000";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,876)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,877)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,880)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,881)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,869)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => singX_uid17_atanX_uid8_fpArctanPiTest_b, xout => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,871)
-- every=1, low=0, high=32, step=1, init=1
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 31 THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 32;
ELSE
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6));
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,872)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,873)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,870)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--cstBias_uid22_atanX_uid8_fpArctanPiTest(CONSTANT,21)
cstBias_uid22_atanX_uid8_fpArctanPiTest_q <= "01111111";
--piO2_uid46_atanX_uid8_fpArctanPiTest(CONSTANT,45)
piO2_uid46_atanX_uid8_fpArctanPiTest_q <= "11001001000011111101101011";
--cstPiO2_uid48_atanX_uid8_fpArctanPiTest(BITSELECT,47)@35
cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in <= piO2_uid46_atanX_uid8_fpArctanPiTest_q(24 downto 0);
cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b <= cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in(24 downto 2);
--fpPiO2C_uid49_atanX_uid8_fpArctanPiTest(BITJOIN,48)@35
fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBias_uid22_atanX_uid8_fpArctanPiTest_q & cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b;
--cstBiasM1_uid23_atanX_uid8_fpArctanPiTest(CONSTANT,22)
cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q <= "01111110";
--piO4_uid47_atanX_uid8_fpArctanPiTest(CONSTANT,46)
piO4_uid47_atanX_uid8_fpArctanPiTest_q <= "110010010000111111011011";
--cstPiO4_uid51_atanX_uid8_fpArctanPiTest(BITSELECT,50)@35
cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in <= piO4_uid47_atanX_uid8_fpArctanPiTest_q(22 downto 0);
cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b <= cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--fpPiO4C_uid52_atanX_uid8_fpArctanPiTest(BITJOIN,51)@35
fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q & cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,892)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a or ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b);
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,893)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,894)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b;
--exc_I_uid36_atanX_uid8_fpArctanPiTest(LOGICAL,35)@0
exc_I_uid36_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q;
exc_I_uid36_atanX_uid8_fpArctanPiTest_b <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
exc_I_uid36_atanX_uid8_fpArctanPiTest_q <= exc_I_uid36_atanX_uid8_fpArctanPiTest_a and exc_I_uid36_atanX_uid8_fpArctanPiTest_b;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,882)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid36_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,883)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq,
address_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa,
data_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia
);
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(0 downto 0);
--constOut_uid54_atanX_uid8_fpArctanPiTest(MUX,53)@35
constOut_uid54_atanX_uid8_fpArctanPiTest_s <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q;
constOut_uid54_atanX_uid8_fpArctanPiTest: PROCESS (constOut_uid54_atanX_uid8_fpArctanPiTest_s, en, fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q, fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE constOut_uid54_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expOutCst_uid112_atanX_uid8_fpArctanPiTest(BITSELECT,111)@35
expOutCst_uid112_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expOutCst_uid112_atanX_uid8_fpArctanPiTest_b <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5(REG,428)@35
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--cst01pWShift_uid69_atanX_uid8_fpArctanPiTest(CONSTANT,68)
cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q <= "0000000000000";
--reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2(REG,389)@0
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= signR_uid119_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c(DELAY,707)@1
ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,1022)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a or ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b);
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top(CONSTANT,1018)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q <= "0111";
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp(LOGICAL,1019)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q);
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q <= "1" when ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a = ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b else "0";
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg(REG,1020)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,1023)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,1024)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b;
--cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,230)
cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111110";
--expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest(SUB,259)@0
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q);
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b);
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b));
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,260)@0
expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0);
expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,229)
cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111101";
--expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest(SUB,256)@0
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q);
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b);
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b));
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,257)@0
expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0);
expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,249)@0
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b else "0";
--expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest(MUX,263)@0
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s <= fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q;
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--expXIsZero_uid31_atanX_uid8_fpArctanPiTest(LOGICAL,30)@0
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a = expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b else "0";
--udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,258)@0
udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in <= STD_LOGIC_VECTOR((9 downto 9 => expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(8)) & expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q);
udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in(9 downto 9);
--InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,245)@0
InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a;
--InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,246)@0
InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a <= expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q;
InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a;
--exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,247)@0
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a <= InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b <= InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c;
--xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,264)@0
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q;
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b;
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a and xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b;
--xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,265)@0
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q;
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q <= xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a or xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b;
--excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,266)@0
excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q & expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q & xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q;
--reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0(REG,378)@0
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest(LOOKUP,267)@1
outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest(MUX,269)@1
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q;
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,1012)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt(COUNTER,1014)
-- every=1, low=0, high=7, step=1, init=1
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg(REG,1015)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux(MUX,1016)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,1013)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia
);
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid20_atanX_uid8_fpArctanPiTest(CONSTANT,19)
cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000001";
--oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,248)@0
oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q <= VCC_q & fracX_uid16_atanX_uid8_fpArctanPiTest_b;
--y_uid251_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,250)@0
y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in <= oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q(22 downto 0);
y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,252)@0
yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b;
yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 15);
--reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0(REG,379)@0
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid346_invTabGen_lutmem(DUALMEM,376)@1
memoryC2_uid346_invTabGen_lutmem_ia <= (others => '0');
memoryC2_uid346_invTabGen_lutmem_aa <= (others => '0');
memoryC2_uid346_invTabGen_lutmem_ab <= reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q;
memoryC2_uid346_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC2_uid346_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid346_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid346_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid346_invTabGen_lutmem_iq,
address_a => memoryC2_uid346_invTabGen_lutmem_aa,
data_a => memoryC2_uid346_invTabGen_lutmem_ia
);
memoryC2_uid346_invTabGen_lutmem_reset0 <= areset;
memoryC2_uid346_invTabGen_lutmem_q <= memoryC2_uid346_invTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1(REG,381)@3
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= memoryC2_uid346_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,1011)
ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a(DELAY,680)@0
ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,253)@3
yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in <= ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q(14 downto 0);
yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in(14 downto 0);
--yT1_uid347_invPolyEval(BITSELECT,346)@3
yT1_uid347_invPolyEval_in <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b;
yT1_uid347_invPolyEval_b <= yT1_uid347_invPolyEval_in(14 downto 3);
--reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0(REG,380)@3
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= yT1_uid347_invPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid366_pT1_uid348_invPolyEval(MULT,365)@4
prodXY_uid366_pT1_uid348_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid366_pT1_uid348_invPolyEval_a),13)) * SIGNED(prodXY_uid366_pT1_uid348_invPolyEval_b);
prodXY_uid366_pT1_uid348_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid366_pT1_uid348_invPolyEval_a <= (others => '0');
prodXY_uid366_pT1_uid348_invPolyEval_b <= (others => '0');
prodXY_uid366_pT1_uid348_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid366_pT1_uid348_invPolyEval_a <= reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q;
prodXY_uid366_pT1_uid348_invPolyEval_b <= reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q;
prodXY_uid366_pT1_uid348_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid366_pT1_uid348_invPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid366_pT1_uid348_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid366_pT1_uid348_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid366_pT1_uid348_invPolyEval_q <= prodXY_uid366_pT1_uid348_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid367_pT1_uid348_invPolyEval(BITSELECT,366)@7
prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in <= prodXY_uid366_pT1_uid348_invPolyEval_q;
prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in(23 downto 11);
--highBBits_uid350_invPolyEval(BITSELECT,349)@7
highBBits_uid350_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b;
highBBits_uid350_invPolyEval_b <= highBBits_uid350_invPolyEval_in(12 downto 1);
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a(DELAY,804)@1
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid345_invTabGen_lutmem(DUALMEM,375)@4
memoryC1_uid345_invTabGen_lutmem_ia <= (others => '0');
memoryC1_uid345_invTabGen_lutmem_aa <= (others => '0');
memoryC1_uid345_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q;
memoryC1_uid345_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 20,
widthad_a => 8,
numwords_a => 256,
width_b => 20,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC1_uid345_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid345_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid345_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid345_invTabGen_lutmem_iq,
address_a => memoryC1_uid345_invTabGen_lutmem_aa,
data_a => memoryC1_uid345_invTabGen_lutmem_ia
);
memoryC1_uid345_invTabGen_lutmem_reset0 <= areset;
memoryC1_uid345_invTabGen_lutmem_q <= memoryC1_uid345_invTabGen_lutmem_iq(19 downto 0);
--reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0(REG,383)@6
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= "00000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= memoryC1_uid345_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid351_invPolyEval(ADD,350)@7
sumAHighB_uid351_invPolyEval_a <= STD_LOGIC_VECTOR((20 downto 20 => reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q(19)) & reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q);
sumAHighB_uid351_invPolyEval_b <= STD_LOGIC_VECTOR((20 downto 12 => highBBits_uid350_invPolyEval_b(11)) & highBBits_uid350_invPolyEval_b);
sumAHighB_uid351_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid351_invPolyEval_a) + SIGNED(sumAHighB_uid351_invPolyEval_b));
sumAHighB_uid351_invPolyEval_q <= sumAHighB_uid351_invPolyEval_o(20 downto 0);
--lowRangeB_uid349_invPolyEval(BITSELECT,348)@7
lowRangeB_uid349_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b(0 downto 0);
lowRangeB_uid349_invPolyEval_b <= lowRangeB_uid349_invPolyEval_in(0 downto 0);
--s1_uid349_uid352_invPolyEval(BITJOIN,351)@7
s1_uid349_uid352_invPolyEval_q <= sumAHighB_uid351_invPolyEval_q & lowRangeB_uid349_invPolyEval_b;
--reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1(REG,385)@7
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= "0000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= s1_uid349_uid352_invPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor(LOGICAL,1059)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a or ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b);
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg(REG,966)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena(REG,1060)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q = "1") THEN
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd(LOGICAL,1061)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b <= en;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg(DELAY,1051)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt(COUNTER,962)
-- every=1, low=0, high=1, step=1, init=1
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i,1));
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg(REG,963)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux(MUX,964)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s <= en;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux: PROCESS (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q)
BEGIN
CASE ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s IS
WHEN "0" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
WHEN "1" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q;
WHEN OTHERS => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem(DUALMEM,1052)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia
);
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0(REG,384)@7
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid369_pT2_uid354_invPolyEval(MULT,368)@8
prodXY_uid369_pT2_uid354_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid369_pT2_uid354_invPolyEval_a),16)) * SIGNED(prodXY_uid369_pT2_uid354_invPolyEval_b);
prodXY_uid369_pT2_uid354_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid369_pT2_uid354_invPolyEval_a <= (others => '0');
prodXY_uid369_pT2_uid354_invPolyEval_b <= (others => '0');
prodXY_uid369_pT2_uid354_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid369_pT2_uid354_invPolyEval_a <= reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q;
prodXY_uid369_pT2_uid354_invPolyEval_b <= reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q;
prodXY_uid369_pT2_uid354_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid369_pT2_uid354_invPolyEval_pr,37));
END IF;
END IF;
END PROCESS;
prodXY_uid369_pT2_uid354_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid369_pT2_uid354_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid369_pT2_uid354_invPolyEval_q <= prodXY_uid369_pT2_uid354_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid370_pT2_uid354_invPolyEval(BITSELECT,369)@11
prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in <= prodXY_uid369_pT2_uid354_invPolyEval_q;
prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in(36 downto 14);
--highBBits_uid356_invPolyEval(BITSELECT,355)@11
highBBits_uid356_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b;
highBBits_uid356_invPolyEval_b <= highBBits_uid356_invPolyEval_in(22 downto 2);
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor(LOGICAL,1048)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q <= not (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a or ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b);
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top(CONSTANT,1031)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q <= "0100";
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp(LOGICAL,1032)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q <= "1" when ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a = ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b else "0";
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg(REG,1033)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena(REG,1049)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd(LOGICAL,1050)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a and ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg(DELAY,1038)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt(COUNTER,1027)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i,3));
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg(REG,1028)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux(MUX,1029)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s <= en;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux: PROCESS (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem(DUALMEM,1039)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq(7 downto 0);
--memoryC0_uid344_invTabGen_lutmem(DUALMEM,374)@8
memoryC0_uid344_invTabGen_lutmem_ia <= (others => '0');
memoryC0_uid344_invTabGen_lutmem_aa <= (others => '0');
memoryC0_uid344_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q;
memoryC0_uid344_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC0_uid344_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid344_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid344_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid344_invTabGen_lutmem_iq,
address_a => memoryC0_uid344_invTabGen_lutmem_aa,
data_a => memoryC0_uid344_invTabGen_lutmem_ia
);
memoryC0_uid344_invTabGen_lutmem_reset0 <= areset;
memoryC0_uid344_invTabGen_lutmem_q <= memoryC0_uid344_invTabGen_lutmem_iq(28 downto 0);
--reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0(REG,387)@10
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= "00000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= memoryC0_uid344_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid357_invPolyEval(ADD,356)@11
sumAHighB_uid357_invPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q(28)) & reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q);
sumAHighB_uid357_invPolyEval_b <= STD_LOGIC_VECTOR((29 downto 21 => highBBits_uid356_invPolyEval_b(20)) & highBBits_uid356_invPolyEval_b);
sumAHighB_uid357_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid357_invPolyEval_a) + SIGNED(sumAHighB_uid357_invPolyEval_b));
sumAHighB_uid357_invPolyEval_q <= sumAHighB_uid357_invPolyEval_o(29 downto 0);
--lowRangeB_uid355_invPolyEval(BITSELECT,354)@11
lowRangeB_uid355_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b(1 downto 0);
lowRangeB_uid355_invPolyEval_b <= lowRangeB_uid355_invPolyEval_in(1 downto 0);
--s2_uid355_uid358_invPolyEval(BITJOIN,357)@11
s2_uid355_uid358_invPolyEval_q <= sumAHighB_uid357_invPolyEval_q & lowRangeB_uid355_invPolyEval_b;
--fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,255)@11
fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in <= s2_uid355_uid358_invPolyEval_q(28 downto 0);
fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in(28 downto 5);
--fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,261)@11
fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b(22 downto 0);
fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,688)@0
ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest(MUX,262)@11
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q;
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1(REG,388)@1
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,701)@2
ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 10 )
PORT MAP ( xin => reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest(MUX,268)@12
fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q;
fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid273_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,272)@12
R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q <= ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q & fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,905)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a or ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,901)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "01001";
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,902)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,903)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,906)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,907)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,895)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,897)
-- every=1, low=0, high=9, step=1, init=1
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 8 THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 9;
ELSE
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,4));
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,898)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,899)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,896)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 4,
numwords_a => 10,
width_b => 32,
widthad_b => 4,
numwords_b => 10,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(31 downto 0);
--path2_uid56_atanX_uid8_fpArctanPiTest(COMPARE,55)@0
path2_uid56_atanX_uid8_fpArctanPiTest_cin <= GND_q;
path2_uid56_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid15_atanX_uid8_fpArctanPiTest_b) & '0';
path2_uid56_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q) & path2_uid56_atanX_uid8_fpArctanPiTest_cin(0);
path2_uid56_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_b));
path2_uid56_atanX_uid8_fpArctanPiTest_n(0) <= not path2_uid56_atanX_uid8_fpArctanPiTest_o(10);
--reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1(REG,390)@0
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= path2_uid56_atanX_uid8_fpArctanPiTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b(DELAY,466)@1
ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--u_uid58_atanX_uid8_fpArctanPiTest(MUX,57)@12
u_uid58_atanX_uid8_fpArctanPiTest_s <= ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q;
u_uid58_atanX_uid8_fpArctanPiTest: PROCESS (u_uid58_atanX_uid8_fpArctanPiTest_s, en, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q, R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE u_uid58_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => u_uid58_atanX_uid8_fpArctanPiTest_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q;
WHEN "1" => u_uid58_atanX_uid8_fpArctanPiTest_q <= R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => u_uid58_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracU_uid60_atanX_uid8_fpArctanPiTest(BITSELECT,59)@12
fracU_uid60_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracU_uid60_atanX_uid8_fpArctanPiTest_b <= fracU_uid60_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a(DELAY,471)@12
ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracU_uid60_atanX_uid8_fpArctanPiTest_b, xout => ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest(BITJOIN,60)@13
oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q;
--oFracUExt_uid70_atanX_uid8_fpArctanPiTest(BITJOIN,69)@13
oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q <= cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q & oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q;
--X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,282)@13
X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(24 downto 0);
X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(24 downto 0);
--leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,281)
leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000000000000";
--leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,283)@13
leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5(REG,399)@13
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,279)@13
X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(28 downto 0);
X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(28 downto 0);
--leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,280)@13
leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4(REG,398)@13
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,276)@13
X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(32 downto 0);
X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(32 downto 0);
--leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,275)
leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "0000";
--leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,277)@13
leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3(REG,397)@13
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,396)@13
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--zS_uid67_atanX_uid8_fpArctanPiTest(CONSTANT,66)
zS_uid67_atanX_uid8_fpArctanPiTest_q <= "000000000";
--shiftBias_uid64_atanX_uid8_fpArctanPiTest(CONSTANT,63)
shiftBias_uid64_atanX_uid8_fpArctanPiTest_q <= "01110010";
--expU_uid59_atanX_uid8_fpArctanPiTest(BITSELECT,58)@12
expU_uid59_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expU_uid59_atanX_uid8_fpArctanPiTest_b <= expU_uid59_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1(REG,391)@12
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= expU_uid59_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--shiftValue_uid65_atanX_uid8_fpArctanPiTest(SUB,64)@13
shiftValue_uid65_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q);
shiftValue_uid65_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid64_atanX_uid8_fpArctanPiTest_q);
shiftValue_uid65_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_b));
shiftValue_uid65_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--ShiftValue8_uid66_atanX_uid8_fpArctanPiTest(BITSELECT,65)@13
ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q;
ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in(8 downto 8);
--shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest(MUX,67)@13
shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b;
shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest: PROCESS (shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s, en, shiftValue_uid65_atanX_uid8_fpArctanPiTest_q, zS_uid67_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= zS_uid67_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest(BITSELECT,70)@13
fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in <= shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q(3 downto 0);
fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,284)@13
leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b;
leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,395)@13
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,285)@14
leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q;
leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q, reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q, reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q;
WHEN "11" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,293)@14
LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(33 downto 0);
LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(33 downto 0);
--ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,725)@14
ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,292)
leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000";
--leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,294)@15
leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,290)@14
LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(34 downto 0);
LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(34 downto 0);
--ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,723)@14
ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,289)
leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "00";
--leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,291)@15
leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,287)@14
LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0);
LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(35 downto 0);
--ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,721)@14
ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,288)@15
leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & GND_q;
--reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,401)@14
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,295)@13
leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a(DELAY,829)@13
ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,400)@14
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,296)@15
leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q;
leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid73_atanX_uid8_fpArctanPiTest(BITSELECT,72)@15
y_uid73_atanX_uid8_fpArctanPiTest_in <= leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0);
y_uid73_atanX_uid8_fpArctanPiTest_b <= y_uid73_atanX_uid8_fpArctanPiTest_in(35 downto 1);
--yAddr_uid75_atanX_uid8_fpArctanPiTest(BITSELECT,74)@15
yAddr_uid75_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b;
yAddr_uid75_atanX_uid8_fpArctanPiTest_b <= yAddr_uid75_atanX_uid8_fpArctanPiTest_in(34 downto 27);
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0(REG,402)@15
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= yAddr_uid75_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid301_atanXOXTabGen_lutmem(DUALMEM,373)@16
memoryC2_uid301_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC2_uid301_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC2_uid301_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q;
memoryC2_uid301_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC2_uid301_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid301_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid301_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid301_atanXOXTabGen_lutmem_iq,
address_a => memoryC2_uid301_atanXOXTabGen_lutmem_aa,
data_a => memoryC2_uid301_atanXOXTabGen_lutmem_ia
);
memoryC2_uid301_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC2_uid301_atanXOXTabGen_lutmem_q <= memoryC2_uid301_atanXOXTabGen_lutmem_iq(12 downto 0);
--reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1(REG,404)@18
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= memoryC2_uid301_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--yPPolyEval_uid76_atanX_uid8_fpArctanPiTest(BITSELECT,75)@15
yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b(26 downto 0);
yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in(26 downto 9);
--yT1_uid302_atanXOXPolyEval(BITSELECT,301)@15
yT1_uid302_atanXOXPolyEval_in <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b;
yT1_uid302_atanXOXPolyEval_b <= yT1_uid302_atanXOXPolyEval_in(17 downto 5);
--ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg(DELAY,1062)
ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid302_atanXOXPolyEval_b, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a(DELAY,832)@15
ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0(REG,403)@18
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid360_pT1_uid303_atanXOXPolyEval(MULT,359)@19
prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_a),14)) * SIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_b);
prodXY_uid360_pT1_uid303_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= (others => '0');
prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= (others => '0');
prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q;
prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q;
prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid360_pT1_uid303_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval(BITSELECT,360)@22
prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_q;
prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in(25 downto 12);
--highBBits_uid305_atanXOXPolyEval(BITSELECT,304)@22
highBBits_uid305_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b;
highBBits_uid305_atanXOXPolyEval_b <= highBBits_uid305_atanXOXPolyEval_in(13 downto 1);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a(DELAY,834)@15
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0(REG,405)@18
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid300_atanXOXTabGen_lutmem(DUALMEM,372)@19
memoryC1_uid300_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC1_uid300_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC1_uid300_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q;
memoryC1_uid300_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC1_uid300_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid300_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid300_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid300_atanXOXTabGen_lutmem_iq,
address_a => memoryC1_uid300_atanXOXTabGen_lutmem_aa,
data_a => memoryC1_uid300_atanXOXTabGen_lutmem_ia
);
memoryC1_uid300_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC1_uid300_atanXOXTabGen_lutmem_q <= memoryC1_uid300_atanXOXTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0(REG,406)@21
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= memoryC1_uid300_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid306_atanXOXPolyEval(ADD,305)@22
sumAHighB_uid306_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q(20)) & reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q);
sumAHighB_uid306_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid305_atanXOXPolyEval_b(12)) & highBBits_uid305_atanXOXPolyEval_b);
sumAHighB_uid306_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid306_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid306_atanXOXPolyEval_b));
sumAHighB_uid306_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_o(21 downto 0);
--lowRangeB_uid304_atanXOXPolyEval(BITSELECT,303)@22
lowRangeB_uid304_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b(0 downto 0);
lowRangeB_uid304_atanXOXPolyEval_b <= lowRangeB_uid304_atanXOXPolyEval_in(0 downto 0);
--s1_uid304_uid307_atanXOXPolyEval(BITJOIN,306)@22
s1_uid304_uid307_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_q & lowRangeB_uid304_atanXOXPolyEval_b;
--reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1(REG,408)@22
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= s1_uid304_uid307_atanXOXPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor(LOGICAL,1035)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q <= not (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a or ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b);
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena(REG,1036)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd(LOGICAL,1037)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b <= en;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a and ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b;
--reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0(REG,407)@15
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg(DELAY,1025)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q, xout => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem(DUALMEM,1026)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq,
address_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa,
data_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia
);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid363_pT2_uid309_atanXOXPolyEval(MULT,362)@23
prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_a),19)) * SIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_b);
prodXY_uid363_pT2_uid309_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= (others => '0');
prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= (others => '0');
prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q;
prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q;
prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid363_pT2_uid309_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval(BITSELECT,363)@26
prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_q;
prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in(40 downto 17);
--highBBits_uid311_atanXOXPolyEval(BITSELECT,310)@26
highBBits_uid311_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b;
highBBits_uid311_atanXOXPolyEval_b <= highBBits_uid311_atanXOXPolyEval_in(23 downto 2);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor(LOGICAL,1073)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q <= not (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a or ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena(REG,1074)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q = "1") THEN
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd(LOGICAL,1075)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b <= en;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a and ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b;
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg(DELAY,1063)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem(DUALMEM,1064)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia
);
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0(REG,409)@22
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid299_atanXOXTabGen_lutmem(DUALMEM,371)@23
memoryC0_uid299_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC0_uid299_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC0_uid299_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q;
memoryC0_uid299_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 31,
widthad_a => 8,
numwords_a => 256,
width_b => 31,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC0_uid299_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid299_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid299_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid299_atanXOXTabGen_lutmem_iq,
address_a => memoryC0_uid299_atanXOXTabGen_lutmem_aa,
data_a => memoryC0_uid299_atanXOXTabGen_lutmem_ia
);
memoryC0_uid299_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC0_uid299_atanXOXTabGen_lutmem_q <= memoryC0_uid299_atanXOXTabGen_lutmem_iq(30 downto 0);
--reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0(REG,410)@25
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= memoryC0_uid299_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid312_atanXOXPolyEval(ADD,311)@26
sumAHighB_uid312_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((31 downto 31 => reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q(30)) & reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q);
sumAHighB_uid312_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((31 downto 22 => highBBits_uid311_atanXOXPolyEval_b(21)) & highBBits_uid311_atanXOXPolyEval_b);
sumAHighB_uid312_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid312_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid312_atanXOXPolyEval_b));
sumAHighB_uid312_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_o(31 downto 0);
--lowRangeB_uid310_atanXOXPolyEval(BITSELECT,309)@26
lowRangeB_uid310_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b(1 downto 0);
lowRangeB_uid310_atanXOXPolyEval_b <= lowRangeB_uid310_atanXOXPolyEval_in(1 downto 0);
--s2_uid310_uid313_atanXOXPolyEval(BITJOIN,312)@26
s2_uid310_uid313_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_q & lowRangeB_uid310_atanXOXPolyEval_b;
--fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest(BITSELECT,77)@26
fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in <= s2_uid310_uid313_atanXOXPolyEval_q(31 downto 0);
fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in(31 downto 5);
--reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1(REG,412)@26
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,918)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,914)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01010";
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,915)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,916)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,919)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,920)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0(REG,411)@13
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,908)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,910)
-- every=1, low=0, high=10, step=1, init=1
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 9 THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 10;
ELSE
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4));
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,911)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,912)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,909)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 11,
width_b => 24,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(23 downto 0);
--mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest(MULT,78)@27
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr <= UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a) * UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b);
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= (others => '0');
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= (others => '0');
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr);
END IF;
END IF;
END PROCESS;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid80_atanX_uid8_fpArctanPiTest(BITSELECT,79)@30
normBit_uid80_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(49 downto 0);
normBit_uid80_atanX_uid8_fpArctanPiTest_b <= normBit_uid80_atanX_uid8_fpArctanPiTest_in(49 downto 49);
--InvNormBit_uid84_atanX_uid8_fpArctanPiTest(LOGICAL,83)@30
InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a <= normBit_uid80_atanX_uid8_fpArctanPiTest_b;
InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q <= not InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,931)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,927)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01111";
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,928)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,929)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,932)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,933)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,921)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expU_uid59_atanX_uid8_fpArctanPiTest_b, xout => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,923)
-- every=1, low=0, high=15, step=1, init=1
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4));
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,924)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,925)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,922)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 16,
width_b => 8,
widthad_b => 4,
numwords_b => 16,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(7 downto 0);
--expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest(SUB,84)@30
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q);
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000" & InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q);
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b));
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--fracRPath3High_uid81_atanX_uid8_fpArctanPiTest(BITSELECT,80)@30
fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(48 downto 0);
fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in(48 downto 25);
--fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest(BITSELECT,81)@30
fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(47 downto 0);
fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in(47 downto 24);
--fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest(MUX,82)@30
fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s <= normBit_uid80_atanX_uid8_fpArctanPiTest_b;
fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s, en, fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b, fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b)
BEGIN
CASE fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest(BITJOIN,85)@30
expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q & fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q;
--reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0(REG,420)@30
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest(ADD,86)@31
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q);
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000" & VCC_q);
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b));
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o(33 downto 0);
--expRPath3_uid89_atanX_uid8_fpArctanPiTest(BITSELECT,88)@31
expRPath3_uid89_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(31 downto 0);
expRPath3_uid89_atanX_uid8_fpArctanPiTest_b <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_in(31 downto 24);
--reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4(REG,427)@31
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,971)
ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e(DELAY,534)@32
ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,337)@33
RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 1);
--rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,339)@33
rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= GND_q & RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,333)
rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000";
--rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,322)
rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000000000000000000000";
--X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,321)@32
X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 24);
--rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,323)@32
rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,319)
rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "0000000000000000";
--X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,318)@32
X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 16);
--rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,320)@32
rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,315)@32
X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 8);
--rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,317)@32
rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q & X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a(DELAY,504)@30
ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q, xout => ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest(BITJOIN,93)@32
oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q;
--cstWFP2_uid25_atanX_uid8_fpArctanPiTest(CONSTANT,24)
cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q <= "00011001";
--reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1(REG,413)@30
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest(SUB,89)@31
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q);
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR((10 downto 9 => reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q(8)) & reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q);
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a) - SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b));
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o(9 downto 0);
--shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest(BITSELECT,91)@31
shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q(7 downto 0);
shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest(CONSTANT,23)
cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q <= "01101000";
--shiftOut_uid91_atanX_uid8_fpArctanPiTest(COMPARE,90)@13
shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin <= GND_q;
shiftOut_uid91_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & '0';
shiftOut_uid91_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q) & shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin(0);
shiftOut_uid91_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_b));
shiftOut_uid91_atanX_uid8_fpArctanPiTest_c(0) <= shiftOut_uid91_atanX_uid8_fpArctanPiTest_o(10);
--ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b(DELAY,502)@13
ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => shiftOut_uid91_atanX_uid8_fpArctanPiTest_c, xout => ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--sValPostSOut_uid93_atanX_uid8_fpArctanPiTest(MUX,92)@31
sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s <= ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q;
sValPostSOut_uid93_atanX_uid8_fpArctanPiTest: PROCESS (sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s, en, shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b, cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest(BITSELECT,94)@31
sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in <= sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q(4 downto 0);
sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,324)@31
rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b;
rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,414)@31
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,325)@32
rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q;
rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,332)@32
RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 6);
--ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,762)@32
ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,334)@33
rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,329)@32
RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 4);
--ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,760)@32
ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 21, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,331)@33
rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,326)@32
RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 2);
--ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,758)@32
ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,328)@33
rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2(REG,416)@32
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,335)@31
rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(2 downto 1);
--ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a(DELAY,844)@31
ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,415)@32
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,336)@33
rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q;
rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q, rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,340)@31
rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,417)@31
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b(DELAY,772)@32
ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,341)@33
rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q;
rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest(BITJOIN,96)@33
pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & GND_q;
--reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1(REG,418)@33
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--path2Diff_uid97_atanX_uid8_fpArctanPiTest(SUB,97)@34
path2Diff_uid97_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & piO2_uid46_atanX_uid8_fpArctanPiTest_q);
path2Diff_uid97_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q);
path2Diff_uid97_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_b));
path2Diff_uid97_atanX_uid8_fpArctanPiTest_q <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_o(26 downto 0);
--normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest(BITSELECT,98)@34
normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(25 downto 0);
normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in(25 downto 25);
--expRPath2_uid103_atanX_uid8_fpArctanPiTest(MUX,102)@34
expRPath2_uid103_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b;
expRPath2_uid103_atanX_uid8_fpArctanPiTest: PROCESS (expRPath2_uid103_atanX_uid8_fpArctanPiTest_s, en, cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q, cstBias_uid22_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPath2_uid103_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest(BITSELECT,99)@34
path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(24 downto 0);
path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in(24 downto 1);
--path2DiffLow_uid101_atanX_uid8_fpArctanPiTest(BITSELECT,100)@34
path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(23 downto 0);
path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in(23 downto 0);
--fracRPath2_uid102_atanX_uid8_fpArctanPiTest(MUX,101)@34
fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b;
fracRPath2_uid102_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s, en, path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b, path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b)
BEGIN
CASE fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest(BITJOIN,103)@34
expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q <= expRPath2_uid103_atanX_uid8_fpArctanPiTest_q & fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q;
--reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0(REG,419)@34
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest(ADD,104)@35
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q);
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000" & VCC_q);
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b));
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o(32 downto 0);
--expRPath2_uid107_atanX_uid8_fpArctanPiTest(BITSELECT,106)@35
expRPath2_uid107_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(31 downto 0);
expRPath2_uid107_atanX_uid8_fpArctanPiTest_b <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_in(31 downto 24);
--reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3(REG,426)@35
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor(LOGICAL,1086)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q <= not (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a or ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b);
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena(REG,1087)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q = "1") THEN
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd(LOGICAL,1088)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b <= en;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a and ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg(DELAY,1076)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid15_atanX_uid8_fpArctanPiTest_b, xout => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem(DUALMEM,1077)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 33,
width_b => 8,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq,
address_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa,
data_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia
);
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 <= areset;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq(7 downto 0);
--reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2(REG,425)@35
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,944)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,940)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "010010";
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,941)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,942)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,945)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,946)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--expXIsBias_uid44_atanX_uid8_fpArctanPiTest(LOGICAL,43)@0
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q;
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a = expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b else "0";
--inIsOne_uid45_atanX_uid8_fpArctanPiTest(LOGICAL,44)@0
inIsOne_uid45_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
inIsOne_uid45_atanX_uid8_fpArctanPiTest_b <= expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q;
inIsOne_uid45_atanX_uid8_fpArctanPiTest_q <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_a and inIsOne_uid45_atanX_uid8_fpArctanPiTest_b;
--arctanIsConst_uid55_atanX_uid8_fpArctanPiTest(LOGICAL,54)@0
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_q;
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a or arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c(DELAY,522)@1
ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q, xout => ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasMwShift_uid62_atanX_uid8_fpArctanPiTest(CONSTANT,61)
biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q <= "01110011";
--atanUIsU_uid63_atanX_uid8_fpArctanPiTest(COMPARE,62)@13
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin <= GND_q;
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q) & '0';
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin(0);
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b));
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n(0) <= not atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o(10);
--ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a(DELAY,520)@0
ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => path2_uid56_atanX_uid8_fpArctanPiTest_n, xout => ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--pathSelBits_uid108_atanX_uid8_fpArctanPiTest(BITJOIN,107)@13
pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q <= ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n & ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q;
--reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0(REG,392)@13
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,934)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,936)
-- every=1, low=0, high=18, step=1, init=1
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 17 THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 18;
ELSE
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,5));
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,937)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,938)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,935)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 19,
width_b => 3,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(2 downto 0);
--fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest(LOOKUP,108)@35
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q) IS
WHEN "000" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "001" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "010" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "011" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "110" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "111" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN OTHERS =>
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRCalc_uid113_atanX_uid8_fpArctanPiTest(MUX,112)@36
expRCalc_uid113_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q;
expRCalc_uid113_atanX_uid8_fpArctanPiTest: PROCESS (expRCalc_uid113_atanX_uid8_fpArctanPiTest_s, en, reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q, reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q, ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE expRCalc_uid113_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q;
WHEN "11" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstAllZWE_uid21_atanX_uid8_fpArctanPiTest(CONSTANT,20)
cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q <= "00000000";
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,995)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a or ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,996)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,997)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,985)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid38_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,986)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,982)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,983)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,984)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,972)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q, xout => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,973)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(0 downto 0);
--excSelBits_uid114_atanX_uid8_fpArctanPiTest(BITJOIN,113)@35
excSelBits_uid114_atanX_uid8_fpArctanPiTest_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q & GND_q & ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q;
--reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0(REG,377)@35
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid114_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest(LOOKUP,114)@36
outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid117_atanX_uid8_fpArctanPiTest(MUX,116)@36
expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q;
expRPostExc_uid117_atanX_uid8_fpArctanPiTest: PROCESS (expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, expRCalc_uid113_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid113_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracOutCst_uid110_atanX_uid8_fpArctanPiTest(BITSELECT,109)@35
fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5(REG,424)@35
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor(LOGICAL,968)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q <= not (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a or ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b);
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena(REG,969)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd(LOGICAL,970)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b <= en;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a and ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b;
--fracRPath3_uid88_atanX_uid8_fpArctanPiTest(BITSELECT,87)@31
fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(23 downto 0);
fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in(23 downto 1);
--reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4(REG,423)@31
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,960)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem(DUALMEM,961)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 1,
numwords_a => 2,
width_b => 23,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq,
address_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa,
data_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia
);
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 <= areset;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq(22 downto 0);
--fracRPath2_uid106_atanX_uid8_fpArctanPiTest(BITSELECT,105)@35
fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(23 downto 0);
fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in(23 downto 1);
--reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3(REG,422)@35
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,957)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a or ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,958)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,959)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2(REG,421)@0
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,947)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,948)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 33,
width_b => 23,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(22 downto 0);
--fracRCalc_uid111_atanX_uid8_fpArctanPiTest(MUX,110)@36
fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q;
fracRCalc_uid111_atanX_uid8_fpArctanPiTest: PROCESS (fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s, en, ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q, reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q, reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q;
WHEN "01" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q;
WHEN "11" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid116_atanX_uid8_fpArctanPiTest(MUX,115)@36
fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q;
fracRPostExc_uid116_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid120_atanX_uid8_fpArctanPiTest(BITJOIN,119)@36
R_uid120_atanX_uid8_fpArctanPiTest_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q & expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q & fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q;
--fracX_uid126_rAtanPi_uid13_fpArctanPiTest(BITSELECT,125)@36
fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0);
--reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1(REG,431)@36
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest(LOGICAL,137)@37
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a <= reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q;
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b else "0";
--expX_uid122_rAtanPi_uid13_fpArctanPiTest(BITSELECT,121)@36
expX_uid122_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expX_uid122_rAtanPi_uid13_fpArctanPiTest_b <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23);
--reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1(REG,429)@36
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest(LOGICAL,135)@37
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q;
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b else "0";
--exc_I_uid139_rAtanPi_uid13_fpArctanPiTest(LOGICAL,138)@37
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q;
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q;
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b;
--cstBiasM2_uid6_fpArctanPiTest(CONSTANT,5)
cstBiasM2_uid6_fpArctanPiTest_q <= "01111101";
--ooPi_uid9_fpArctanPiTest(CONSTANT,8)
ooPi_uid9_fpArctanPiTest_q <= "101000101111100110000011";
--fracOOPi_uid10_fpArctanPiTest(BITSELECT,9)@36
fracOOPi_uid10_fpArctanPiTest_in <= ooPi_uid9_fpArctanPiTest_q(22 downto 0);
fracOOPi_uid10_fpArctanPiTest_b <= fracOOPi_uid10_fpArctanPiTest_in(22 downto 0);
--fpOOPi_uid11_fpArctanPiTest(BITJOIN,10)@36
fpOOPi_uid11_fpArctanPiTest_q <= GND_q & cstBiasM2_uid6_fpArctanPiTest_q & fracOOPi_uid10_fpArctanPiTest_b;
--expY_uid123_rAtanPi_uid13_fpArctanPiTest(BITSELECT,122)@36
expY_uid123_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(30 downto 0);
expY_uid123_rAtanPi_uid13_fpArctanPiTest_b <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23);
--expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest(LOGICAL,149)@36
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b;
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a(DELAY,581)@36
ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest(LOGICAL,203)@37
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b;
--fracY_uid128_rAtanPi_uid13_fpArctanPiTest(BITSELECT,127)@36
fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(22 downto 0);
fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0);
--fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest(LOGICAL,153)@36
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b;
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b(DELAY,575)@36
ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest(LOGICAL,151)@36
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b;
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a(DELAY,574)@36
ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid155_rAtanPi_uid13_fpArctanPiTest(LOGICAL,154)@37
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q;
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b <= ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q;
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b;
--expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest(LOGICAL,133)@37
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q;
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b else "0";
--excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest(LOGICAL,204)@37
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b;
--ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest(LOGICAL,205)@37
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q;
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q;
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a or ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b;
--InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest(LOGICAL,155)@36
InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q;
InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a;
--exc_N_uid157_rAtanPi_uid13_fpArctanPiTest(LOGICAL,156)@36
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b;
--ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a(DELAY,579)@36
ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest(LOGICAL,139)@37
InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q;
InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a;
--exc_N_uid141_rAtanPi_uid13_fpArctanPiTest(LOGICAL,140)@37
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b;
--excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest(LOGICAL,206)@37
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c;
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest(LOGICAL,218)@37
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q;
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= not InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a;
END IF;
END PROCESS;
--signY_uid125_rAtanPi_uid13_fpArctanPiTest(BITSELECT,124)@36
signY_uid125_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q;
signY_uid125_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31);
--signX_uid124_rAtanPi_uid13_fpArctanPiTest(BITSELECT,123)@36
signX_uid124_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q;
signX_uid124_rAtanPi_uid13_fpArctanPiTest_b <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31);
--signR_uid190_rAtanPi_uid13_fpArctanPiTest(LOGICAL,189)@36
signR_uid190_rAtanPi_uid13_fpArctanPiTest_a <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_b;
signR_uid190_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_b;
signR_uid190_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= signR_uid190_rAtanPi_uid13_fpArctanPiTest_a xor signR_uid190_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a(DELAY,666)@37
ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid190_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest(LOGICAL,219)@38
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a <= ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q;
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b <= InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q;
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q <= signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a and signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b;
--ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c(DELAY,670)@38
ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest(BITJOIN,128)@36
add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b;
--reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1(REG,433)@36
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest(BITJOIN,126)@36
add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b;
--reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0(REG,432)@36
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--prod_uid165_rAtanPi_uid13_fpArctanPiTest(MULT,164)@37
prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr <= UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_a) * UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_b);
prod_uid165_rAtanPi_uid13_fpArctanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= (others => '0');
prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= (others => '0');
prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q;
prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q;
prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr);
END IF;
END IF;
END PROCESS;
prod_uid165_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1;
END IF;
END IF;
END PROCESS;
--normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest(BITSELECT,165)@40
normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q;
normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in(47 downto 47);
--roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest(CONSTANT,179)
roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q <= "010";
--fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest(BITSELECT,167)@40
fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(46 downto 0);
fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in(46 downto 23);
--fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest(BITSELECT,168)@40
fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(45 downto 0);
fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in(45 downto 22);
--fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest(MUX,169)@40
fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b;
fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s, en, fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b, fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b)
BEGIN
CASE fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "0" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b;
WHEN "1" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b;
WHEN OTHERS => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest(BITSELECT,177)@40
FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in <= fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q(1 downto 0);
FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in(1 downto 0);
--Prod22_uid172_rAtanPi_uid13_fpArctanPiTest(BITSELECT,171)@40
Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(22 downto 0);
Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in(22 downto 22);
--extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest(MUX,172)@40
extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b;
extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest: PROCESS (extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s, en, GND_q, Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b)
BEGIN
CASE extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "0" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b;
WHEN OTHERS => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest(BITSELECT,170)@40
stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(21 downto 0);
stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b <= stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in(21 downto 0);
--stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest(BITJOIN,173)@40
stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q <= extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q & stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b;
--stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest(LOGICAL,175)@40
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a <= stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q;
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q <= "1" when stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a = stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b else "0";
--sticky_uid177_rAtanPi_uid13_fpArctanPiTest(LOGICAL,176)@40
sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a <= stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q;
sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q <= not sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a;
--lrs_uid179_rAtanPi_uid13_fpArctanPiTest(BITJOIN,178)@40
lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b & sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q;
--roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest(LOGICAL,180)@40
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a <= lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q;
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b <= roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q;
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q <= "1" when roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a = roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b else "0";
--roundBit_uid182_rAtanPi_uid13_fpArctanPiTest(LOGICAL,181)@40
roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a <= roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q;
roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q <= not roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a;
--roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest(BITJOIN,184)@40
roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q <= GND_q & normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b & cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q & roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q;
--reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1(REG,436)@40
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--biasInc_uid163_rAtanPi_uid13_fpArctanPiTest(CONSTANT,162)
biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q <= "0001111111";
--ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b(DELAY,586)@36
ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expY_uid123_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expSum_uid162_rAtanPi_uid13_fpArctanPiTest(ADD,161)@37
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q);
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q);
expSum_uid162_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a) + UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q <= expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o(8 downto 0);
--ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a(DELAY,587)@38
ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest(SUB,163)@39
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q);
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q(9)) & biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q);
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b));
END IF;
END IF;
END PROCESS;
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o(10 downto 0);
--expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest(BITJOIN,182)@40
expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q & fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q;
--reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0(REG,435)@40
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest(ADD,185)@41
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q(34)) & reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q);
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q);
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a) + SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b));
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o(35 downto 0);
--expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest(BITSELECT,187)@41
expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q;
expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in(35 downto 24);
--expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest(BITSELECT,188)@41
expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b(7 downto 0);
expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in(7 downto 0);
--ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d(DELAY,664)@41
ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 2 )
PORT MAP ( xin => expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c(DELAY,659)@37
ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1(REG,437)@41
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid193_rAtanPi_uid13_fpArctanPiTest(COMPARE,192)@42
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q;
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & '0';
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q) & expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin(0);
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b));
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o(14);
--InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest(LOGICAL,157)@37
InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q;
InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a;
--InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest(LOGICAL,158)@37
InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a;
--InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest(LOGICAL,159)@37
InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a;
--exc_R_uid161_rAtanPi_uid13_fpArctanPiTest(LOGICAL,160)@37
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c;
--ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b(DELAY,629)@37
ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest(LOGICAL,141)@37
InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a;
--InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest(LOGICAL,142)@37
InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a;
--InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest(LOGICAL,143)@37
InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a;
--exc_R_uid145_rAtanPi_uid13_fpArctanPiTest(LOGICAL,144)@37
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c;
--ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a(DELAY,628)@37
ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest(LOGICAL,201)@42
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c <= expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c;
--excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest(LOGICAL,200)@37
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q;
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q <= excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a and excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c(DELAY,646)@37
ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest(LOGICAL,199)@37
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q;
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q <= excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a and excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b(DELAY,645)@37
ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest(LOGICAL,198)@37
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q <= excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a and excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a(DELAY,644)@37
ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid203_rAtanPi_uid13_fpArctanPiTest(LOGICAL,202)@42
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q <= excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d;
--expUdf_uid191_rAtanPi_uid13_fpArctanPiTest(COMPARE,190)@42
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q;
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0';
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin(0);
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b));
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o(14);
--excZC3_uid197_rAtanPi_uid13_fpArctanPiTest(LOGICAL,196)@42
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c <= expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c;
--excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest(LOGICAL,195)@37
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q;
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c(DELAY,633)@37
ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest(LOGICAL,194)@37
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b(DELAY,632)@37
ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest(LOGICAL,193)@37
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a(DELAY,631)@37
ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid198_rAtanPi_uid13_fpArctanPiTest(LOGICAL,197)@42
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q <= excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d;
--concExc_uid208_rAtanPi_uid13_fpArctanPiTest(BITJOIN,207)@42
concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q <= ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q & excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q & excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q;
--reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0(REG,439)@42
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid209_rAtanPi_uid13_fpArctanPiTest(LOOKUP,208)@43
excREnc_uid209_rAtanPi_uid13_fpArctanPiTest: PROCESS (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q) IS
WHEN "000" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "01";
WHEN "001" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "010" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "10";
WHEN "011" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "100" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "11";
WHEN "101" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "110" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "111" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN OTHERS =>
excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest(MUX,217)@43
expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q;
expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest: PROCESS (expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q;
WHEN "10" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest(BITSELECT,186)@41
fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q(23 downto 0);
fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b <= fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in(23 downto 1);
--ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d(DELAY,662)@41
ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest(MUX,212)@43
fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q;
fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q;
WHEN "10" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid221_rAtanPi_uid13_fpArctanPiTest(BITJOIN,220)@43
R_uid221_rAtanPi_uid13_fpArctanPiTest_q <= ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q & expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q & fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q;
--xOut(GPOUT,4)@43
q <= R_uid221_rAtanPi_uid13_fpArctanPiTest_q;
end normal;
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-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_2;
USE floating_point_v7_1_2.floating_point_v7_1_2;
ENTITY doHistStretch_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END doHistStretch_ap_fmul_2_max_dsp_32;
ARCHITECTURE doHistStretch_ap_fmul_2_max_dsp_32_arch OF doHistStretch_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF doHistStretch_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_2 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF doHistStretch_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_2,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF doHistStretch_ap_fmul_2_max_dsp_32_arch : ARCHITECTURE IS "doHistStretch_ap_fmul_2_max_dsp_32,floating_point_v7_1_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF doHistStretch_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "doHistStretch_ap_fmul_2_max_dsp_32,floating_point_v7_1_2,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS" &
"=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=2,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C" &
"_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_2
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END doHistStretch_ap_fmul_2_max_dsp_32_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_2;
USE floating_point_v7_1_2.floating_point_v7_1_2;
ENTITY doHistStretch_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END doHistStretch_ap_fmul_2_max_dsp_32;
ARCHITECTURE doHistStretch_ap_fmul_2_max_dsp_32_arch OF doHistStretch_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF doHistStretch_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_2 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF doHistStretch_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_2,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF doHistStretch_ap_fmul_2_max_dsp_32_arch : ARCHITECTURE IS "doHistStretch_ap_fmul_2_max_dsp_32,floating_point_v7_1_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF doHistStretch_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "doHistStretch_ap_fmul_2_max_dsp_32,floating_point_v7_1_2,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS" &
"=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=2,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C" &
"_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_2
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END doHistStretch_ap_fmul_2_max_dsp_32_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_2;
USE floating_point_v7_1_2.floating_point_v7_1_2;
ENTITY doHistStretch_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END doHistStretch_ap_fmul_2_max_dsp_32;
ARCHITECTURE doHistStretch_ap_fmul_2_max_dsp_32_arch OF doHistStretch_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF doHistStretch_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_2 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF doHistStretch_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_2,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF doHistStretch_ap_fmul_2_max_dsp_32_arch : ARCHITECTURE IS "doHistStretch_ap_fmul_2_max_dsp_32,floating_point_v7_1_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF doHistStretch_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "doHistStretch_ap_fmul_2_max_dsp_32,floating_point_v7_1_2,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS" &
"=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=2,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C" &
"_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_2
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END doHistStretch_ap_fmul_2_max_dsp_32_arch;
|
--
-- Verif Package
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016-2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
package Verif is
component Blink is
generic (
FREQUENCY : positive:=25e6;
SECONDS : positive:=1
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
blink_o : out std_logic
);
end component Blink;
component LoopCheck is
generic (
DWIDTH : positive:=8
);
port (
-- Producer side
tx_clk_i : in std_logic;
tx_rst_i : in std_logic;
tx_stb_i : in std_logic;
tx_data_i : in std_logic_vector(DWIDTH-1 downto 0);
tx_data_o : out std_logic_vector(DWIDTH-1 downto 0);
-- Consumer side
rx_clk_i : in std_logic;
rx_rst_i : in std_logic;
rx_stb_i : in std_logic;
rx_data_i : in std_logic_vector(DWIDTH-1 downto 0);
rx_errors_o : out std_logic_vector(4 downto 0)
);
end component LoopCheck;
component TransLoop is
generic (
DBYTES : positive:=4; -- Data bytes
TSIZE : positive:=1e4; -- Total size
FSIZE : positive:=2048 -- Frame size
);
port (
-- TX side
tx_clk_i : in std_logic;
tx_rst_i : in std_logic;
tx_data_i : in std_logic_vector(DBYTES*8-1 downto 0);
tx_data_o : out std_logic_vector(DBYTES*8-1 downto 0);
tx_isk_o : out std_logic_vector(DBYTES-1 downto 0);
tx_ready_i : in std_logic;
-- RX side
rx_clk_i : in std_logic;
rx_rst_i : in std_logic;
rx_data_i : in std_logic_vector(DBYTES*8-1 downto 0);
rx_isk_i : in std_logic_vector(DBYTES-1 downto 0);
rx_errors_o : out std_logic_vector(4 downto 0);
rx_finish_o : out std_logic;
rx_cycles_o : out std_logic_vector(31 downto 0)
);
end component TransLoop;
end package Verif;
|
----------------------------------------------------------------------------
----------------------------------------------------------------------------
--
-- Copyright 2016,2017 International Business Machines
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions AND
-- limitations under the License.
--
----------------------------------------------------------------------------
----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_misc.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
USE work.psl_accel_types.ALL;
PACKAGE action_types IS
CONSTANT C_M_AXI_CARD_MEM0_ID_WIDTH : integer := C_DDR_AXI_ID_WIDTH;
CONSTANT C_M_AXI_CARD_MEM0_ADDR_WIDTH : integer := C_DDR_AXI_ADDR_WIDTH;
CONSTANT C_M_AXI_CARD_MEM0_DATA_WIDTH : integer := C_DDR_AXI_DATA_WIDTH;
CONSTANT C_M_AXI_CARD_MEM0_AWUSER_WIDTH : integer := C_DDR_AXI_AWUSER_WIDTH;
CONSTANT C_M_AXI_CARD_MEM0_ARUSER_WIDTH : integer := C_DDR_AXI_ARUSER_WIDTH;
CONSTANT C_M_AXI_CARD_MEM0_WUSER_WIDTH : integer := C_DDR_AXI_WUSER_WIDTH;
CONSTANT C_M_AXI_CARD_MEM0_RUSER_WIDTH : integer := C_DDR_AXI_RUSER_WIDTH;
CONSTANT C_M_AXI_CARD_MEM0_BUSER_WIDTH : integer := C_DDR_AXI_BUSER_WIDTH;
-- Parameters for HBM ports
CONSTANT C_M_AXI_CARD_HBM_ID_WIDTH : integer := C_AXI_CARD_HBM_ID_WIDTH;
CONSTANT C_M_AXI_CARD_HBM_ADDR_WIDTH : integer := C_AXI_CARD_HBM_ADDR_WIDTH;
CONSTANT C_M_AXI_CARD_HBM_SIM_ADDR_WIDTH : integer := C_AXI_CARD_HBM_SIM_ADDR_WIDTH;
CONSTANT C_M_AXI_CARD_HBM_DATA_WIDTH : integer := C_AXI_CARD_HBM_DATA_WIDTH;
CONSTANT C_M_AXI_CARD_HBM_AWUSER_WIDTH : integer := C_AXI_CARD_HBM_AWUSER_WIDTH;
CONSTANT C_M_AXI_CARD_HBM_ARUSER_WIDTH : integer := C_AXI_CARD_HBM_ARUSER_WIDTH;
CONSTANT C_M_AXI_CARD_HBM_WUSER_WIDTH : integer := C_AXI_CARD_HBM_WUSER_WIDTH;
CONSTANT C_M_AXI_CARD_HBM_RUSER_WIDTH : integer := C_AXI_CARD_HBM_RUSER_WIDTH;
CONSTANT C_M_AXI_CARD_HBM_BUSER_WIDTH : integer := C_AXI_CARD_HBM_BUSER_WIDTH;
-- Parameters for Axi Slave Bus Interface AXI_CTRL_REG
CONSTANT C_S_AXI_CTRL_REG_DATA_WIDTH : integer := C_REG_DATA_WIDTH;
CONSTANT C_S_AXI_CTRL_REG_ADDR_WIDTH : integer := C_REG_ADDR_WIDTH;
-- Parameters for Axi Master Bus Interface AXI_HOST_MEM : to Host memory
CONSTANT C_M_AXI_HOST_MEM_ID_WIDTH : integer := C_HOST_AXI_ID_WIDTH;
CONSTANT C_M_AXI_HOST_MEM_ADDR_WIDTH : integer := C_HOST_AXI_ADDR_WIDTH;
CONSTANT C_M_AXI_HOST_MEM_DATA_WIDTH : integer := C_HOST_AXI_DATA_WIDTH;
CONSTANT C_M_AXI_HOST_MEM_AWUSER_WIDTH : integer := CONTEXT_BITS;
CONSTANT C_M_AXI_HOST_MEM_ARUSER_WIDTH : integer := CONTEXT_BITS;
CONSTANT C_M_AXI_HOST_MEM_WUSER_WIDTH : integer := C_HOST_AXI_WUSER_WIDTH;
CONSTANT C_M_AXI_HOST_MEM_RUSER_WIDTH : integer := C_HOST_AXI_RUSER_WIDTH;
CONSTANT C_M_AXI_HOST_MEM_BUSER_WIDTH : integer := C_HOST_AXI_BUSER_WIDTH;
-- Parameters for Axi Master Bus Interface AXI_NVME : to NVMe controller
CONSTANT C_M_AXI_NVME_ID_WIDTH : integer := C_NVME_AXI_ID_WIDTH;
CONSTANT C_M_AXI_NVME_ADDR_WIDTH : integer := C_NVME_AXI_ADDR_WIDTH;
CONSTANT C_M_AXI_NVME_DATA_WIDTH : integer := C_NVME_AXI_DATA_WIDTH;
CONSTANT C_M_AXI_NVME_AWUSER_WIDTH : integer := C_NVME_AXI_AWUSER_WIDTH;
CONSTANT C_M_AXI_NVME_ARUSER_WIDTH : integer := C_NVME_AXI_ARUSER_WIDTH;
CONSTANT C_M_AXI_NVME_WUSER_WIDTH : integer := C_NVME_AXI_WUSER_WIDTH;
CONSTANT C_M_AXI_NVME_RUSER_WIDTH : integer := C_NVME_AXI_RUSER_WIDTH;
CONSTANT C_M_AXI_NVME_BUSER_WIDTH : integer := C_NVME_AXI_BUSER_WIDTH;
END action_types;
PACKAGE BODY action_types IS
END action_types;
|
architecture rtl of fifo is
begin
GEN_LABEL : case expression generate
when 1 =>
when n_order =>
when others =>
end generate;
GEN_LABEL : CASE expression generate
when 1 =>
when n_order =>
when others =>
end generate;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1938.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n04i01938ent IS
END c07s02b01x00p01n04i01938ent;
ARCHITECTURE c07s02b01x00p01n04i01938arch OF c07s02b01x00p01n04i01938ent IS
BEGIN
TESTING: PROCESS
type array_one is array (positive range <>) of boolean;
variable x : array_one( 1 to 10);
variable y : array_one(1 to 5);
variable z : array_one(1 to 10);
type array_two is array (positive range <>) of bit;
variable a : array_two( 1 to 10);
variable b : array_two(1 to 5);
variable c : array_two(1 to 10);
BEGIN
c := (a or b); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n04i01938 - Operands should be arrays of the same length."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n04i01938arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1938.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n04i01938ent IS
END c07s02b01x00p01n04i01938ent;
ARCHITECTURE c07s02b01x00p01n04i01938arch OF c07s02b01x00p01n04i01938ent IS
BEGIN
TESTING: PROCESS
type array_one is array (positive range <>) of boolean;
variable x : array_one( 1 to 10);
variable y : array_one(1 to 5);
variable z : array_one(1 to 10);
type array_two is array (positive range <>) of bit;
variable a : array_two( 1 to 10);
variable b : array_two(1 to 5);
variable c : array_two(1 to 10);
BEGIN
c := (a or b); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n04i01938 - Operands should be arrays of the same length."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n04i01938arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1938.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n04i01938ent IS
END c07s02b01x00p01n04i01938ent;
ARCHITECTURE c07s02b01x00p01n04i01938arch OF c07s02b01x00p01n04i01938ent IS
BEGIN
TESTING: PROCESS
type array_one is array (positive range <>) of boolean;
variable x : array_one( 1 to 10);
variable y : array_one(1 to 5);
variable z : array_one(1 to 10);
type array_two is array (positive range <>) of bit;
variable a : array_two( 1 to 10);
variable b : array_two(1 to 5);
variable c : array_two(1 to 10);
BEGIN
c := (a or b); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n04i01938 - Operands should be arrays of the same length."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n04i01938arch;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_556 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_556;
architecture augh of mul_556 is
signal tmp_res : signed(45 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(30 downto 0));
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_556 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_556;
architecture augh of mul_556 is
signal tmp_res : signed(45 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(30 downto 0));
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_crc16 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end entity zpuino_crc16;
architecture behave of zpuino_crc16 is
signal crc_q: std_logic_vector(15 downto 0);
signal crcA_q: std_logic_vector(15 downto 0);
signal crcB_q: std_logic_vector(15 downto 0);
signal poly_q: std_logic_vector(15 downto 0);
signal data_q: std_logic_vector(7 downto 0);
signal count_q: integer range 0 to 7;
signal ready_q: std_logic;
begin
wb_ack_o<='1' when ready_q='1' and ( wb_cyc_i='1' and wb_stb_i='1') else '0';
wb_inta_o <= '0';
process(wb_adr_i,crc_q,poly_q, crcA_q, crcB_q)
begin
case wb_adr_i(4 downto 2) is
when "000" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crc_q;
when "001" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= poly_q;
when "100" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcA_q;
when "101" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcB_q;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
poly_q <= x"A001";
crc_q <= x"FFFF";
ready_q <= '1';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' and ready_q='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
crc_q <= wb_dat_i(15 downto 0);
when "001" =>
poly_q <= wb_dat_i(15 downto 0);
when "010" =>
ready_q <= '0';
count_q <= 0;
data_q <= wb_dat_i(7 downto 0);
crcA_q <= crc_q;
crcB_q <= crcA_q;
when others =>
end case;
end if;
if ready_q='0' then
if (crc_q(0) xor data_q(0))='1' then
crc_q <= ( '0' & crc_q(15 downto 1)) xor poly_q;
else
crc_q <= '0' & crc_q(15 downto 1);
end if;
data_q <= '0' & data_q(7 downto 1);
if count_q=7 then
count_q <= 0;
ready_q <= '1';
else
count_q <= count_q + 1;
end if;
end if;
end if;
end if;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_crc16 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end entity zpuino_crc16;
architecture behave of zpuino_crc16 is
signal crc_q: std_logic_vector(15 downto 0);
signal crcA_q: std_logic_vector(15 downto 0);
signal crcB_q: std_logic_vector(15 downto 0);
signal poly_q: std_logic_vector(15 downto 0);
signal data_q: std_logic_vector(7 downto 0);
signal count_q: integer range 0 to 7;
signal ready_q: std_logic;
begin
wb_ack_o<='1' when ready_q='1' and ( wb_cyc_i='1' and wb_stb_i='1') else '0';
wb_inta_o <= '0';
process(wb_adr_i,crc_q,poly_q, crcA_q, crcB_q)
begin
case wb_adr_i(4 downto 2) is
when "000" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crc_q;
when "001" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= poly_q;
when "100" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcA_q;
when "101" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcB_q;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
poly_q <= x"A001";
crc_q <= x"FFFF";
ready_q <= '1';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' and ready_q='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
crc_q <= wb_dat_i(15 downto 0);
when "001" =>
poly_q <= wb_dat_i(15 downto 0);
when "010" =>
ready_q <= '0';
count_q <= 0;
data_q <= wb_dat_i(7 downto 0);
crcA_q <= crc_q;
crcB_q <= crcA_q;
when others =>
end case;
end if;
if ready_q='0' then
if (crc_q(0) xor data_q(0))='1' then
crc_q <= ( '0' & crc_q(15 downto 1)) xor poly_q;
else
crc_q <= '0' & crc_q(15 downto 1);
end if;
data_q <= '0' & data_q(7 downto 1);
if count_q=7 then
count_q <= 0;
ready_q <= '1';
else
count_q <= count_q + 1;
end if;
end if;
end if;
end if;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_crc16 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end entity zpuino_crc16;
architecture behave of zpuino_crc16 is
signal crc_q: std_logic_vector(15 downto 0);
signal crcA_q: std_logic_vector(15 downto 0);
signal crcB_q: std_logic_vector(15 downto 0);
signal poly_q: std_logic_vector(15 downto 0);
signal data_q: std_logic_vector(7 downto 0);
signal count_q: integer range 0 to 7;
signal ready_q: std_logic;
begin
wb_ack_o<='1' when ready_q='1' and ( wb_cyc_i='1' and wb_stb_i='1') else '0';
wb_inta_o <= '0';
process(wb_adr_i,crc_q,poly_q, crcA_q, crcB_q)
begin
case wb_adr_i(4 downto 2) is
when "000" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crc_q;
when "001" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= poly_q;
when "100" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcA_q;
when "101" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcB_q;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
poly_q <= x"A001";
crc_q <= x"FFFF";
ready_q <= '1';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' and ready_q='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
crc_q <= wb_dat_i(15 downto 0);
when "001" =>
poly_q <= wb_dat_i(15 downto 0);
when "010" =>
ready_q <= '0';
count_q <= 0;
data_q <= wb_dat_i(7 downto 0);
crcA_q <= crc_q;
crcB_q <= crcA_q;
when others =>
end case;
end if;
if ready_q='0' then
if (crc_q(0) xor data_q(0))='1' then
crc_q <= ( '0' & crc_q(15 downto 1)) xor poly_q;
else
crc_q <= '0' & crc_q(15 downto 1);
end if;
data_q <= '0' & data_q(7 downto 1);
if count_q=7 then
count_q <= 0;
ready_q <= '1';
else
count_q <= count_q + 1;
end if;
end if;
end if;
end if;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_crc16 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end entity zpuino_crc16;
architecture behave of zpuino_crc16 is
signal crc_q: std_logic_vector(15 downto 0);
signal crcA_q: std_logic_vector(15 downto 0);
signal crcB_q: std_logic_vector(15 downto 0);
signal poly_q: std_logic_vector(15 downto 0);
signal data_q: std_logic_vector(7 downto 0);
signal count_q: integer range 0 to 7;
signal ready_q: std_logic;
begin
wb_ack_o<='1' when ready_q='1' and ( wb_cyc_i='1' and wb_stb_i='1') else '0';
wb_inta_o <= '0';
process(wb_adr_i,crc_q,poly_q, crcA_q, crcB_q)
begin
case wb_adr_i(4 downto 2) is
when "000" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crc_q;
when "001" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= poly_q;
when "100" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcA_q;
when "101" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcB_q;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
poly_q <= x"A001";
crc_q <= x"FFFF";
ready_q <= '1';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' and ready_q='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
crc_q <= wb_dat_i(15 downto 0);
when "001" =>
poly_q <= wb_dat_i(15 downto 0);
when "010" =>
ready_q <= '0';
count_q <= 0;
data_q <= wb_dat_i(7 downto 0);
crcA_q <= crc_q;
crcB_q <= crcA_q;
when others =>
end case;
end if;
if ready_q='0' then
if (crc_q(0) xor data_q(0))='1' then
crc_q <= ( '0' & crc_q(15 downto 1)) xor poly_q;
else
crc_q <= '0' & crc_q(15 downto 1);
end if;
data_q <= '0' & data_q(7 downto 1);
if count_q=7 then
count_q <= 0;
ready_q <= '1';
else
count_q <= count_q + 1;
end if;
end if;
end if;
end if;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_crc16 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end entity zpuino_crc16;
architecture behave of zpuino_crc16 is
signal crc_q: std_logic_vector(15 downto 0);
signal crcA_q: std_logic_vector(15 downto 0);
signal crcB_q: std_logic_vector(15 downto 0);
signal poly_q: std_logic_vector(15 downto 0);
signal data_q: std_logic_vector(7 downto 0);
signal count_q: integer range 0 to 7;
signal ready_q: std_logic;
begin
wb_ack_o<='1' when ready_q='1' and ( wb_cyc_i='1' and wb_stb_i='1') else '0';
wb_inta_o <= '0';
process(wb_adr_i,crc_q,poly_q, crcA_q, crcB_q)
begin
case wb_adr_i(4 downto 2) is
when "000" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crc_q;
when "001" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= poly_q;
when "100" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcA_q;
when "101" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcB_q;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
poly_q <= x"A001";
crc_q <= x"FFFF";
ready_q <= '1';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' and ready_q='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
crc_q <= wb_dat_i(15 downto 0);
when "001" =>
poly_q <= wb_dat_i(15 downto 0);
when "010" =>
ready_q <= '0';
count_q <= 0;
data_q <= wb_dat_i(7 downto 0);
crcA_q <= crc_q;
crcB_q <= crcA_q;
when others =>
end case;
end if;
if ready_q='0' then
if (crc_q(0) xor data_q(0))='1' then
crc_q <= ( '0' & crc_q(15 downto 1)) xor poly_q;
else
crc_q <= '0' & crc_q(15 downto 1);
end if;
data_q <= '0' & data_q(7 downto 1);
if count_q=7 then
count_q <= 0;
ready_q <= '1';
else
count_q <= count_q + 1;
end if;
end if;
end if;
end if;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_crc16 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end entity zpuino_crc16;
architecture behave of zpuino_crc16 is
signal crc_q: std_logic_vector(15 downto 0);
signal crcA_q: std_logic_vector(15 downto 0);
signal crcB_q: std_logic_vector(15 downto 0);
signal poly_q: std_logic_vector(15 downto 0);
signal data_q: std_logic_vector(7 downto 0);
signal count_q: integer range 0 to 7;
signal ready_q: std_logic;
begin
wb_ack_o<='1' when ready_q='1' and ( wb_cyc_i='1' and wb_stb_i='1') else '0';
wb_inta_o <= '0';
process(wb_adr_i,crc_q,poly_q, crcA_q, crcB_q)
begin
case wb_adr_i(4 downto 2) is
when "000" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crc_q;
when "001" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= poly_q;
when "100" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcA_q;
when "101" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcB_q;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
poly_q <= x"A001";
crc_q <= x"FFFF";
ready_q <= '1';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' and ready_q='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
crc_q <= wb_dat_i(15 downto 0);
when "001" =>
poly_q <= wb_dat_i(15 downto 0);
when "010" =>
ready_q <= '0';
count_q <= 0;
data_q <= wb_dat_i(7 downto 0);
crcA_q <= crc_q;
crcB_q <= crcA_q;
when others =>
end case;
end if;
if ready_q='0' then
if (crc_q(0) xor data_q(0))='1' then
crc_q <= ( '0' & crc_q(15 downto 1)) xor poly_q;
else
crc_q <= '0' & crc_q(15 downto 1);
end if;
data_q <= '0' & data_q(7 downto 1);
if count_q=7 then
count_q <= 0;
ready_q <= '1';
else
count_q <= count_q + 1;
end if;
end if;
end if;
end if;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_crc16 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end entity zpuino_crc16;
architecture behave of zpuino_crc16 is
signal crc_q: std_logic_vector(15 downto 0);
signal crcA_q: std_logic_vector(15 downto 0);
signal crcB_q: std_logic_vector(15 downto 0);
signal poly_q: std_logic_vector(15 downto 0);
signal data_q: std_logic_vector(7 downto 0);
signal count_q: integer range 0 to 7;
signal ready_q: std_logic;
begin
wb_ack_o<='1' when ready_q='1' and ( wb_cyc_i='1' and wb_stb_i='1') else '0';
wb_inta_o <= '0';
process(wb_adr_i,crc_q,poly_q, crcA_q, crcB_q)
begin
case wb_adr_i(4 downto 2) is
when "000" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crc_q;
when "001" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= poly_q;
when "100" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcA_q;
when "101" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcB_q;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
poly_q <= x"A001";
crc_q <= x"FFFF";
ready_q <= '1';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' and ready_q='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
crc_q <= wb_dat_i(15 downto 0);
when "001" =>
poly_q <= wb_dat_i(15 downto 0);
when "010" =>
ready_q <= '0';
count_q <= 0;
data_q <= wb_dat_i(7 downto 0);
crcA_q <= crc_q;
crcB_q <= crcA_q;
when others =>
end case;
end if;
if ready_q='0' then
if (crc_q(0) xor data_q(0))='1' then
crc_q <= ( '0' & crc_q(15 downto 1)) xor poly_q;
else
crc_q <= '0' & crc_q(15 downto 1);
end if;
data_q <= '0' & data_q(7 downto 1);
if count_q=7 then
count_q <= 0;
ready_q <= '1';
else
count_q <= count_q + 1;
end if;
end if;
end if;
end if;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_crc16 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end entity zpuino_crc16;
architecture behave of zpuino_crc16 is
signal crc_q: std_logic_vector(15 downto 0);
signal crcA_q: std_logic_vector(15 downto 0);
signal crcB_q: std_logic_vector(15 downto 0);
signal poly_q: std_logic_vector(15 downto 0);
signal data_q: std_logic_vector(7 downto 0);
signal count_q: integer range 0 to 7;
signal ready_q: std_logic;
begin
wb_ack_o<='1' when ready_q='1' and ( wb_cyc_i='1' and wb_stb_i='1') else '0';
wb_inta_o <= '0';
process(wb_adr_i,crc_q,poly_q, crcA_q, crcB_q)
begin
case wb_adr_i(4 downto 2) is
when "000" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crc_q;
when "001" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= poly_q;
when "100" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcA_q;
when "101" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcB_q;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
poly_q <= x"A001";
crc_q <= x"FFFF";
ready_q <= '1';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' and ready_q='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
crc_q <= wb_dat_i(15 downto 0);
when "001" =>
poly_q <= wb_dat_i(15 downto 0);
when "010" =>
ready_q <= '0';
count_q <= 0;
data_q <= wb_dat_i(7 downto 0);
crcA_q <= crc_q;
crcB_q <= crcA_q;
when others =>
end case;
end if;
if ready_q='0' then
if (crc_q(0) xor data_q(0))='1' then
crc_q <= ( '0' & crc_q(15 downto 1)) xor poly_q;
else
crc_q <= '0' & crc_q(15 downto 1);
end if;
data_q <= '0' & data_q(7 downto 1);
if count_q=7 then
count_q <= 0;
ready_q <= '1';
else
count_q <= count_q + 1;
end if;
end if;
end if;
end if;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_crc16 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end entity zpuino_crc16;
architecture behave of zpuino_crc16 is
signal crc_q: std_logic_vector(15 downto 0);
signal crcA_q: std_logic_vector(15 downto 0);
signal crcB_q: std_logic_vector(15 downto 0);
signal poly_q: std_logic_vector(15 downto 0);
signal data_q: std_logic_vector(7 downto 0);
signal count_q: integer range 0 to 7;
signal ready_q: std_logic;
begin
wb_ack_o<='1' when ready_q='1' and ( wb_cyc_i='1' and wb_stb_i='1') else '0';
wb_inta_o <= '0';
process(wb_adr_i,crc_q,poly_q, crcA_q, crcB_q)
begin
case wb_adr_i(4 downto 2) is
when "000" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crc_q;
when "001" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= poly_q;
when "100" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcA_q;
when "101" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcB_q;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
poly_q <= x"A001";
crc_q <= x"FFFF";
ready_q <= '1';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' and ready_q='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
crc_q <= wb_dat_i(15 downto 0);
when "001" =>
poly_q <= wb_dat_i(15 downto 0);
when "010" =>
ready_q <= '0';
count_q <= 0;
data_q <= wb_dat_i(7 downto 0);
crcA_q <= crc_q;
crcB_q <= crcA_q;
when others =>
end case;
end if;
if ready_q='0' then
if (crc_q(0) xor data_q(0))='1' then
crc_q <= ( '0' & crc_q(15 downto 1)) xor poly_q;
else
crc_q <= '0' & crc_q(15 downto 1);
end if;
data_q <= '0' & data_q(7 downto 1);
if count_q=7 then
count_q <= 0;
ready_q <= '1';
else
count_q <= count_q + 1;
end if;
end if;
end if;
end if;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_crc16 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end entity zpuino_crc16;
architecture behave of zpuino_crc16 is
signal crc_q: std_logic_vector(15 downto 0);
signal crcA_q: std_logic_vector(15 downto 0);
signal crcB_q: std_logic_vector(15 downto 0);
signal poly_q: std_logic_vector(15 downto 0);
signal data_q: std_logic_vector(7 downto 0);
signal count_q: integer range 0 to 7;
signal ready_q: std_logic;
begin
wb_ack_o<='1' when ready_q='1' and ( wb_cyc_i='1' and wb_stb_i='1') else '0';
wb_inta_o <= '0';
process(wb_adr_i,crc_q,poly_q, crcA_q, crcB_q)
begin
case wb_adr_i(4 downto 2) is
when "000" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crc_q;
when "001" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= poly_q;
when "100" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcA_q;
when "101" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcB_q;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
poly_q <= x"A001";
crc_q <= x"FFFF";
ready_q <= '1';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' and ready_q='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
crc_q <= wb_dat_i(15 downto 0);
when "001" =>
poly_q <= wb_dat_i(15 downto 0);
when "010" =>
ready_q <= '0';
count_q <= 0;
data_q <= wb_dat_i(7 downto 0);
crcA_q <= crc_q;
crcB_q <= crcA_q;
when others =>
end case;
end if;
if ready_q='0' then
if (crc_q(0) xor data_q(0))='1' then
crc_q <= ( '0' & crc_q(15 downto 1)) xor poly_q;
else
crc_q <= '0' & crc_q(15 downto 1);
end if;
data_q <= '0' & data_q(7 downto 1);
if count_q=7 then
count_q <= 0;
ready_q <= '1';
else
count_q <= count_q + 1;
end if;
end if;
end if;
end if;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_crc16 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end entity zpuino_crc16;
architecture behave of zpuino_crc16 is
signal crc_q: std_logic_vector(15 downto 0);
signal crcA_q: std_logic_vector(15 downto 0);
signal crcB_q: std_logic_vector(15 downto 0);
signal poly_q: std_logic_vector(15 downto 0);
signal data_q: std_logic_vector(7 downto 0);
signal count_q: integer range 0 to 7;
signal ready_q: std_logic;
begin
wb_ack_o<='1' when ready_q='1' and ( wb_cyc_i='1' and wb_stb_i='1') else '0';
wb_inta_o <= '0';
process(wb_adr_i,crc_q,poly_q, crcA_q, crcB_q)
begin
case wb_adr_i(4 downto 2) is
when "000" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crc_q;
when "001" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= poly_q;
when "100" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcA_q;
when "101" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcB_q;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
poly_q <= x"A001";
crc_q <= x"FFFF";
ready_q <= '1';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' and ready_q='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
crc_q <= wb_dat_i(15 downto 0);
when "001" =>
poly_q <= wb_dat_i(15 downto 0);
when "010" =>
ready_q <= '0';
count_q <= 0;
data_q <= wb_dat_i(7 downto 0);
crcA_q <= crc_q;
crcB_q <= crcA_q;
when others =>
end case;
end if;
if ready_q='0' then
if (crc_q(0) xor data_q(0))='1' then
crc_q <= ( '0' & crc_q(15 downto 1)) xor poly_q;
else
crc_q <= '0' & crc_q(15 downto 1);
end if;
data_q <= '0' & data_q(7 downto 1);
if count_q=7 then
count_q <= 0;
ready_q <= '1';
else
count_q <= count_q + 1;
end if;
end if;
end if;
end if;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_crc16 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end entity zpuino_crc16;
architecture behave of zpuino_crc16 is
signal crc_q: std_logic_vector(15 downto 0);
signal crcA_q: std_logic_vector(15 downto 0);
signal crcB_q: std_logic_vector(15 downto 0);
signal poly_q: std_logic_vector(15 downto 0);
signal data_q: std_logic_vector(7 downto 0);
signal count_q: integer range 0 to 7;
signal ready_q: std_logic;
begin
wb_ack_o<='1' when ready_q='1' and ( wb_cyc_i='1' and wb_stb_i='1') else '0';
wb_inta_o <= '0';
process(wb_adr_i,crc_q,poly_q, crcA_q, crcB_q)
begin
case wb_adr_i(4 downto 2) is
when "000" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crc_q;
when "001" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= poly_q;
when "100" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcA_q;
when "101" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcB_q;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
poly_q <= x"A001";
crc_q <= x"FFFF";
ready_q <= '1';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' and ready_q='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
crc_q <= wb_dat_i(15 downto 0);
when "001" =>
poly_q <= wb_dat_i(15 downto 0);
when "010" =>
ready_q <= '0';
count_q <= 0;
data_q <= wb_dat_i(7 downto 0);
crcA_q <= crc_q;
crcB_q <= crcA_q;
when others =>
end case;
end if;
if ready_q='0' then
if (crc_q(0) xor data_q(0))='1' then
crc_q <= ( '0' & crc_q(15 downto 1)) xor poly_q;
else
crc_q <= '0' & crc_q(15 downto 1);
end if;
data_q <= '0' & data_q(7 downto 1);
if count_q=7 then
count_q <= 0;
ready_q <= '1';
else
count_q <= count_q + 1;
end if;
end if;
end if;
end if;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_crc16 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end entity zpuino_crc16;
architecture behave of zpuino_crc16 is
signal crc_q: std_logic_vector(15 downto 0);
signal crcA_q: std_logic_vector(15 downto 0);
signal crcB_q: std_logic_vector(15 downto 0);
signal poly_q: std_logic_vector(15 downto 0);
signal data_q: std_logic_vector(7 downto 0);
signal count_q: integer range 0 to 7;
signal ready_q: std_logic;
begin
wb_ack_o<='1' when ready_q='1' and ( wb_cyc_i='1' and wb_stb_i='1') else '0';
wb_inta_o <= '0';
process(wb_adr_i,crc_q,poly_q, crcA_q, crcB_q)
begin
case wb_adr_i(4 downto 2) is
when "000" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crc_q;
when "001" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= poly_q;
when "100" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcA_q;
when "101" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcB_q;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
poly_q <= x"A001";
crc_q <= x"FFFF";
ready_q <= '1';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' and ready_q='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
crc_q <= wb_dat_i(15 downto 0);
when "001" =>
poly_q <= wb_dat_i(15 downto 0);
when "010" =>
ready_q <= '0';
count_q <= 0;
data_q <= wb_dat_i(7 downto 0);
crcA_q <= crc_q;
crcB_q <= crcA_q;
when others =>
end case;
end if;
if ready_q='0' then
if (crc_q(0) xor data_q(0))='1' then
crc_q <= ( '0' & crc_q(15 downto 1)) xor poly_q;
else
crc_q <= '0' & crc_q(15 downto 1);
end if;
data_q <= '0' & data_q(7 downto 1);
if count_q=7 then
count_q <= 0;
ready_q <= '1';
else
count_q <= count_q + 1;
end if;
end if;
end if;
end if;
end process;
end behave;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2784.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity BODY is
end BODY;
ENTITY c13s09b00x00p99n01i02784ent IS
END c13s09b00x00p99n01i02784ent;
ARCHITECTURE c13s09b00x00p99n01i02784arch OF c13s09b00x00p99n01i02784ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02784 - Reserved word BODY can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02784arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2784.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity BODY is
end BODY;
ENTITY c13s09b00x00p99n01i02784ent IS
END c13s09b00x00p99n01i02784ent;
ARCHITECTURE c13s09b00x00p99n01i02784arch OF c13s09b00x00p99n01i02784ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02784 - Reserved word BODY can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02784arch;
|
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