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-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2784.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity BODY is
end BODY;
ENTITY c13s09b00x00p99n01i02784ent IS
END c13s09b00x00p99n01i02784ent;
ARCHITECTURE c13s09b00x00p99n01i02784arch OF c13s09b00x00p99n01i02784ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02784 - Reserved word BODY can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02784arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity GeneralGenerate is
Port ( G_ik : in STD_LOGIC;
P_ik : in STD_LOGIC;
G_km1_j : in STD_LOGIC;
G_ij : out STD_LOGIC);
end GeneralGenerate;
architecture Behavioral of GeneralGenerate is
begin
G_ij <= G_ik OR (P_ik AND G_km1_j);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:02:23 03/15/2015
-- Design Name:
-- Module Name: SerialSender - RTL
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SerialSender is
port(
clk : in std_logic;
tx : out std_logic := '1';
data : in std_logic_vector(7 downto 0);
send : in std_logic;
sending : out std_logic := '0'
);
end SerialSender;
architecture RTL of SerialSender is
signal temp_data : std_logic_vector(7 downto 0);
signal bit_pos : integer range 0 to 9 := 0;
signal sending : std_logic := '0';
begin
process(clk) begin
if (clk'event and clk = '1') then
-- serial send
if (send = '1') then
sending <= send;
end if;
if (sending = '1') then
case bit_pos is
when 0 =>
tx <= '0';
bit_pos <= bit_pos + 1;
temp_data <= data;
when 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 =>
bit_pos <= bit_pos + 1;
tx <= temp_data(0);
temp_data <= '1' & temp_data(7 downto 1);
when 9 =>
tx <= '1';
bit_pos <= 0;
sending <= '0';
end case;
end if;
out_sending <= sending;
end if;
end process;
end RTL;
|
architecture RTL of ENT is
begin
end RTL;
architecture RTL of ENT is
begin
end RTL;
architecture RTL of ENT is
begin
end RTL;
architecture RTL of ENT is
begin
end;
architecture RTL of ENT is
begin
end architecture;
|
entity issue228 is
generic (G : integer range 0 to 3);
end entity issue228;
use std.textio.all;
architecture test of issue228 is
begin
process
begin
write(OUTPUT, integer'image(G) & LF);
wait;
end process;
end architecture test;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity I2SToAvalonST is
generic (
gDataWidth : natural := 24; -- Avalon ST interface Datawidth
gDataWidthLen : natural := 5 -- Number of bits to represent gDataWidth
);
port (
-- clk and reset
iClk : in std_logic; -- clk
inReset : in std_logic; -- low active reset
-- audio codec interface
iDAT : in std_logic;
iLRC : in std_logic;
iBCLK : in std_logic;
-- Avalon ST source left and right channel
oLeftData : out std_logic_vector(gDataWidth-1 downto 0); -- data
oLeftValid : out std_logic; -- valid
oRightData : out std_logic_vector(gDataWidth-1 downto 0); -- data
oRightValid : out std_logic -- valid
);
end entity;
|
--This is an autogenerated file
--Do not modify it by hand
--Generated at 2017-12-14T16:53:23+13:00
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package enforcement_types_WaterBoilerEnforcer is
type enforced_signals_WaterBoilerEnforcer is record
--put the enforced signals in here
Pboiler : unsigned(7 downto 0);
Fin : unsigned(7 downto 0);
Fout : unsigned(7 downto 0);
Fop : unsigned(7 downto 0);
Lboiler : unsigned(7 downto 0);
Hboiler : std_logic;
Cin : std_logic;
Vin : unsigned(7 downto 0);
Vop : unsigned(7 downto 0);
Vout : unsigned(7 downto 0);
Aop : std_logic;
end record;
end enforcement_types_WaterBoilerEnforcer;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_block: if 0 < depth generate
begin
delay_loop: for i in depth-1 downto 0 generate
begin
async_reset: if reset_kind = "ASYNC" generate
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind = "SYNC" generate
process(clk)
begin
if clk'event and clk='1' then
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
no_reset: if reset_kind = "NONE" generate
process(clk)
begin
if clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
end generate;
end generate;
xout <= delay_signals(0);
end delay;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_sync_reg is
generic (
width1 : natural := 8;
init_value : std_logic_vector;
width2 : natural := 8;
depth : natural := 2;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end entity;
architecture sync_reg of dspba_sync_reg is
type bit_array is array (depth-1 downto 0) of std_logic;
signal iclk_enable : std_logic;
signal iclk_data : std_logic_vector(width1-1 downto 0);
signal oclk_data : std_logic_vector(width2-1 downto 0);
-- For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops
-- For TimeQuest this means: identify these flip-flops as synchronizer to enable aitomatic MTBF analysis
signal sync_regs : bit_array;
attribute altera_attribute : string;
attribute altera_attribute of sync_regs : signal is "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON";
signal oclk_enable : std_logic;
constant init_value_internal : std_logic_vector(width1-1 downto 0) := init_value;
signal counter : UNSIGNED(counter_width-1 downto 0);
signal ena_internal : std_logic;
begin
oclk_enable <= sync_regs(depth-1);
no_multiplication: if pulse_multiplier=1 generate
ena_internal <= ena(0);
end generate;
async_reset: if reset_kind="ASYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if aclr1=reset1_high then
counter <= (others => '0');
elsif clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1, aclr1)
begin
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
elsif clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2, aclr2)
begin
if aclr2=reset2_high then
sync_regs(i) <= '0';
elsif clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2, aclr2)
begin
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind="SYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
counter <= (others => '0');
else
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
else
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
sync_regs(i) <= '0';
else
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
none_reset: if reset_kind="NONE" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
xout <= iclk_data;
sxout <= oclk_data;
end sync_reg;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_block: if 0 < depth generate
begin
delay_loop: for i in depth-1 downto 0 generate
begin
async_reset: if reset_kind = "ASYNC" generate
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind = "SYNC" generate
process(clk)
begin
if clk'event and clk='1' then
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
no_reset: if reset_kind = "NONE" generate
process(clk)
begin
if clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
end generate;
end generate;
xout <= delay_signals(0);
end delay;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_sync_reg is
generic (
width1 : natural := 8;
init_value : std_logic_vector;
width2 : natural := 8;
depth : natural := 2;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end entity;
architecture sync_reg of dspba_sync_reg is
type bit_array is array (depth-1 downto 0) of std_logic;
signal iclk_enable : std_logic;
signal iclk_data : std_logic_vector(width1-1 downto 0);
signal oclk_data : std_logic_vector(width2-1 downto 0);
-- For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops
-- For TimeQuest this means: identify these flip-flops as synchronizer to enable aitomatic MTBF analysis
signal sync_regs : bit_array;
attribute altera_attribute : string;
attribute altera_attribute of sync_regs : signal is "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON";
signal oclk_enable : std_logic;
constant init_value_internal : std_logic_vector(width1-1 downto 0) := init_value;
signal counter : UNSIGNED(counter_width-1 downto 0);
signal ena_internal : std_logic;
begin
oclk_enable <= sync_regs(depth-1);
no_multiplication: if pulse_multiplier=1 generate
ena_internal <= ena(0);
end generate;
async_reset: if reset_kind="ASYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if aclr1=reset1_high then
counter <= (others => '0');
elsif clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1, aclr1)
begin
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
elsif clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2, aclr2)
begin
if aclr2=reset2_high then
sync_regs(i) <= '0';
elsif clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2, aclr2)
begin
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind="SYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
counter <= (others => '0');
else
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
else
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
sync_regs(i) <= '0';
else
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
none_reset: if reset_kind="NONE" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
xout <= iclk_data;
sxout <= oclk_data;
end sync_reg;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_block: if 0 < depth generate
begin
delay_loop: for i in depth-1 downto 0 generate
begin
async_reset: if reset_kind = "ASYNC" generate
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind = "SYNC" generate
process(clk)
begin
if clk'event and clk='1' then
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
no_reset: if reset_kind = "NONE" generate
process(clk)
begin
if clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
end generate;
end generate;
xout <= delay_signals(0);
end delay;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_sync_reg is
generic (
width1 : natural := 8;
init_value : std_logic_vector;
width2 : natural := 8;
depth : natural := 2;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end entity;
architecture sync_reg of dspba_sync_reg is
type bit_array is array (depth-1 downto 0) of std_logic;
signal iclk_enable : std_logic;
signal iclk_data : std_logic_vector(width1-1 downto 0);
signal oclk_data : std_logic_vector(width2-1 downto 0);
-- For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops
-- For TimeQuest this means: identify these flip-flops as synchronizer to enable aitomatic MTBF analysis
signal sync_regs : bit_array;
attribute altera_attribute : string;
attribute altera_attribute of sync_regs : signal is "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON";
signal oclk_enable : std_logic;
constant init_value_internal : std_logic_vector(width1-1 downto 0) := init_value;
signal counter : UNSIGNED(counter_width-1 downto 0);
signal ena_internal : std_logic;
begin
oclk_enable <= sync_regs(depth-1);
no_multiplication: if pulse_multiplier=1 generate
ena_internal <= ena(0);
end generate;
async_reset: if reset_kind="ASYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if aclr1=reset1_high then
counter <= (others => '0');
elsif clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1, aclr1)
begin
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
elsif clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2, aclr2)
begin
if aclr2=reset2_high then
sync_regs(i) <= '0';
elsif clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2, aclr2)
begin
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind="SYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
counter <= (others => '0');
else
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
else
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
sync_regs(i) <= '0';
else
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
none_reset: if reset_kind="NONE" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
xout <= iclk_data;
sxout <= oclk_data;
end sync_reg;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_block: if 0 < depth generate
begin
delay_loop: for i in depth-1 downto 0 generate
begin
async_reset: if reset_kind = "ASYNC" generate
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind = "SYNC" generate
process(clk)
begin
if clk'event and clk='1' then
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
no_reset: if reset_kind = "NONE" generate
process(clk)
begin
if clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
end generate;
end generate;
xout <= delay_signals(0);
end delay;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_sync_reg is
generic (
width1 : natural := 8;
init_value : std_logic_vector;
width2 : natural := 8;
depth : natural := 2;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end entity;
architecture sync_reg of dspba_sync_reg is
type bit_array is array (depth-1 downto 0) of std_logic;
signal iclk_enable : std_logic;
signal iclk_data : std_logic_vector(width1-1 downto 0);
signal oclk_data : std_logic_vector(width2-1 downto 0);
-- For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops
-- For TimeQuest this means: identify these flip-flops as synchronizer to enable aitomatic MTBF analysis
signal sync_regs : bit_array;
attribute altera_attribute : string;
attribute altera_attribute of sync_regs : signal is "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON";
signal oclk_enable : std_logic;
constant init_value_internal : std_logic_vector(width1-1 downto 0) := init_value;
signal counter : UNSIGNED(counter_width-1 downto 0);
signal ena_internal : std_logic;
begin
oclk_enable <= sync_regs(depth-1);
no_multiplication: if pulse_multiplier=1 generate
ena_internal <= ena(0);
end generate;
async_reset: if reset_kind="ASYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if aclr1=reset1_high then
counter <= (others => '0');
elsif clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1, aclr1)
begin
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
elsif clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2, aclr2)
begin
if aclr2=reset2_high then
sync_regs(i) <= '0';
elsif clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2, aclr2)
begin
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind="SYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
counter <= (others => '0');
else
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
else
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
sync_regs(i) <= '0';
else
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
none_reset: if reset_kind="NONE" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
xout <= iclk_data;
sxout <= oclk_data;
end sync_reg;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_block: if 0 < depth generate
begin
delay_loop: for i in depth-1 downto 0 generate
begin
async_reset: if reset_kind = "ASYNC" generate
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind = "SYNC" generate
process(clk)
begin
if clk'event and clk='1' then
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
no_reset: if reset_kind = "NONE" generate
process(clk)
begin
if clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
end generate;
end generate;
xout <= delay_signals(0);
end delay;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_sync_reg is
generic (
width1 : natural := 8;
init_value : std_logic_vector;
width2 : natural := 8;
depth : natural := 2;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end entity;
architecture sync_reg of dspba_sync_reg is
type bit_array is array (depth-1 downto 0) of std_logic;
signal iclk_enable : std_logic;
signal iclk_data : std_logic_vector(width1-1 downto 0);
signal oclk_data : std_logic_vector(width2-1 downto 0);
-- For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops
-- For TimeQuest this means: identify these flip-flops as synchronizer to enable aitomatic MTBF analysis
signal sync_regs : bit_array;
attribute altera_attribute : string;
attribute altera_attribute of sync_regs : signal is "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON";
signal oclk_enable : std_logic;
constant init_value_internal : std_logic_vector(width1-1 downto 0) := init_value;
signal counter : UNSIGNED(counter_width-1 downto 0);
signal ena_internal : std_logic;
begin
oclk_enable <= sync_regs(depth-1);
no_multiplication: if pulse_multiplier=1 generate
ena_internal <= ena(0);
end generate;
async_reset: if reset_kind="ASYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if aclr1=reset1_high then
counter <= (others => '0');
elsif clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1, aclr1)
begin
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
elsif clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2, aclr2)
begin
if aclr2=reset2_high then
sync_regs(i) <= '0';
elsif clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2, aclr2)
begin
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind="SYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
counter <= (others => '0');
else
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
else
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
sync_regs(i) <= '0';
else
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
none_reset: if reset_kind="NONE" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
xout <= iclk_data;
sxout <= oclk_data;
end sync_reg;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_block: if 0 < depth generate
begin
delay_loop: for i in depth-1 downto 0 generate
begin
async_reset: if reset_kind = "ASYNC" generate
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind = "SYNC" generate
process(clk)
begin
if clk'event and clk='1' then
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
no_reset: if reset_kind = "NONE" generate
process(clk)
begin
if clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
end generate;
end generate;
xout <= delay_signals(0);
end delay;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_sync_reg is
generic (
width1 : natural := 8;
init_value : std_logic_vector;
width2 : natural := 8;
depth : natural := 2;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end entity;
architecture sync_reg of dspba_sync_reg is
type bit_array is array (depth-1 downto 0) of std_logic;
signal iclk_enable : std_logic;
signal iclk_data : std_logic_vector(width1-1 downto 0);
signal oclk_data : std_logic_vector(width2-1 downto 0);
-- For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops
-- For TimeQuest this means: identify these flip-flops as synchronizer to enable aitomatic MTBF analysis
signal sync_regs : bit_array;
attribute altera_attribute : string;
attribute altera_attribute of sync_regs : signal is "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON";
signal oclk_enable : std_logic;
constant init_value_internal : std_logic_vector(width1-1 downto 0) := init_value;
signal counter : UNSIGNED(counter_width-1 downto 0);
signal ena_internal : std_logic;
begin
oclk_enable <= sync_regs(depth-1);
no_multiplication: if pulse_multiplier=1 generate
ena_internal <= ena(0);
end generate;
async_reset: if reset_kind="ASYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if aclr1=reset1_high then
counter <= (others => '0');
elsif clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1, aclr1)
begin
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
elsif clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2, aclr2)
begin
if aclr2=reset2_high then
sync_regs(i) <= '0';
elsif clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2, aclr2)
begin
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind="SYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
counter <= (others => '0');
else
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
else
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
sync_regs(i) <= '0';
else
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
none_reset: if reset_kind="NONE" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
xout <= iclk_data;
sxout <= oclk_data;
end sync_reg;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_block: if 0 < depth generate
begin
delay_loop: for i in depth-1 downto 0 generate
begin
async_reset: if reset_kind = "ASYNC" generate
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind = "SYNC" generate
process(clk)
begin
if clk'event and clk='1' then
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
no_reset: if reset_kind = "NONE" generate
process(clk)
begin
if clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
end generate;
end generate;
xout <= delay_signals(0);
end delay;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_sync_reg is
generic (
width1 : natural := 8;
init_value : std_logic_vector;
width2 : natural := 8;
depth : natural := 2;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end entity;
architecture sync_reg of dspba_sync_reg is
type bit_array is array (depth-1 downto 0) of std_logic;
signal iclk_enable : std_logic;
signal iclk_data : std_logic_vector(width1-1 downto 0);
signal oclk_data : std_logic_vector(width2-1 downto 0);
-- For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops
-- For TimeQuest this means: identify these flip-flops as synchronizer to enable aitomatic MTBF analysis
signal sync_regs : bit_array;
attribute altera_attribute : string;
attribute altera_attribute of sync_regs : signal is "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON";
signal oclk_enable : std_logic;
constant init_value_internal : std_logic_vector(width1-1 downto 0) := init_value;
signal counter : UNSIGNED(counter_width-1 downto 0);
signal ena_internal : std_logic;
begin
oclk_enable <= sync_regs(depth-1);
no_multiplication: if pulse_multiplier=1 generate
ena_internal <= ena(0);
end generate;
async_reset: if reset_kind="ASYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if aclr1=reset1_high then
counter <= (others => '0');
elsif clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1, aclr1)
begin
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
elsif clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2, aclr2)
begin
if aclr2=reset2_high then
sync_regs(i) <= '0';
elsif clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2, aclr2)
begin
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind="SYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
counter <= (others => '0');
else
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
else
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
sync_regs(i) <= '0';
else
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
none_reset: if reset_kind="NONE" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
xout <= iclk_data;
sxout <= oclk_data;
end sync_reg;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_block: if 0 < depth generate
begin
delay_loop: for i in depth-1 downto 0 generate
begin
async_reset: if reset_kind = "ASYNC" generate
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind = "SYNC" generate
process(clk)
begin
if clk'event and clk='1' then
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
no_reset: if reset_kind = "NONE" generate
process(clk)
begin
if clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
end generate;
end generate;
xout <= delay_signals(0);
end delay;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_sync_reg is
generic (
width1 : natural := 8;
init_value : std_logic_vector;
width2 : natural := 8;
depth : natural := 2;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end entity;
architecture sync_reg of dspba_sync_reg is
type bit_array is array (depth-1 downto 0) of std_logic;
signal iclk_enable : std_logic;
signal iclk_data : std_logic_vector(width1-1 downto 0);
signal oclk_data : std_logic_vector(width2-1 downto 0);
-- For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops
-- For TimeQuest this means: identify these flip-flops as synchronizer to enable aitomatic MTBF analysis
signal sync_regs : bit_array;
attribute altera_attribute : string;
attribute altera_attribute of sync_regs : signal is "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON";
signal oclk_enable : std_logic;
constant init_value_internal : std_logic_vector(width1-1 downto 0) := init_value;
signal counter : UNSIGNED(counter_width-1 downto 0);
signal ena_internal : std_logic;
begin
oclk_enable <= sync_regs(depth-1);
no_multiplication: if pulse_multiplier=1 generate
ena_internal <= ena(0);
end generate;
async_reset: if reset_kind="ASYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if aclr1=reset1_high then
counter <= (others => '0');
elsif clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1, aclr1)
begin
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
elsif clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2, aclr2)
begin
if aclr2=reset2_high then
sync_regs(i) <= '0';
elsif clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2, aclr2)
begin
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind="SYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
counter <= (others => '0');
else
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
else
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
sync_regs(i) <= '0';
else
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
none_reset: if reset_kind="NONE" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
xout <= iclk_data;
sxout <= oclk_data;
end sync_reg;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_block: if 0 < depth generate
begin
delay_loop: for i in depth-1 downto 0 generate
begin
async_reset: if reset_kind = "ASYNC" generate
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind = "SYNC" generate
process(clk)
begin
if clk'event and clk='1' then
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
no_reset: if reset_kind = "NONE" generate
process(clk)
begin
if clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
end generate;
end generate;
xout <= delay_signals(0);
end delay;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_sync_reg is
generic (
width1 : natural := 8;
init_value : std_logic_vector;
width2 : natural := 8;
depth : natural := 2;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end entity;
architecture sync_reg of dspba_sync_reg is
type bit_array is array (depth-1 downto 0) of std_logic;
signal iclk_enable : std_logic;
signal iclk_data : std_logic_vector(width1-1 downto 0);
signal oclk_data : std_logic_vector(width2-1 downto 0);
-- For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops
-- For TimeQuest this means: identify these flip-flops as synchronizer to enable aitomatic MTBF analysis
signal sync_regs : bit_array;
attribute altera_attribute : string;
attribute altera_attribute of sync_regs : signal is "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON";
signal oclk_enable : std_logic;
constant init_value_internal : std_logic_vector(width1-1 downto 0) := init_value;
signal counter : UNSIGNED(counter_width-1 downto 0);
signal ena_internal : std_logic;
begin
oclk_enable <= sync_regs(depth-1);
no_multiplication: if pulse_multiplier=1 generate
ena_internal <= ena(0);
end generate;
async_reset: if reset_kind="ASYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if aclr1=reset1_high then
counter <= (others => '0');
elsif clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1, aclr1)
begin
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
elsif clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2, aclr2)
begin
if aclr2=reset2_high then
sync_regs(i) <= '0';
elsif clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2, aclr2)
begin
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind="SYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
counter <= (others => '0');
else
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
else
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
sync_regs(i) <= '0';
else
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
none_reset: if reset_kind="NONE" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
xout <= iclk_data;
sxout <= oclk_data;
end sync_reg;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_block: if 0 < depth generate
begin
delay_loop: for i in depth-1 downto 0 generate
begin
async_reset: if reset_kind = "ASYNC" generate
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind = "SYNC" generate
process(clk)
begin
if clk'event and clk='1' then
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
no_reset: if reset_kind = "NONE" generate
process(clk)
begin
if clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
end generate;
end generate;
xout <= delay_signals(0);
end delay;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_sync_reg is
generic (
width1 : natural := 8;
init_value : std_logic_vector;
width2 : natural := 8;
depth : natural := 2;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end entity;
architecture sync_reg of dspba_sync_reg is
type bit_array is array (depth-1 downto 0) of std_logic;
signal iclk_enable : std_logic;
signal iclk_data : std_logic_vector(width1-1 downto 0);
signal oclk_data : std_logic_vector(width2-1 downto 0);
-- For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops
-- For TimeQuest this means: identify these flip-flops as synchronizer to enable aitomatic MTBF analysis
signal sync_regs : bit_array;
attribute altera_attribute : string;
attribute altera_attribute of sync_regs : signal is "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON";
signal oclk_enable : std_logic;
constant init_value_internal : std_logic_vector(width1-1 downto 0) := init_value;
signal counter : UNSIGNED(counter_width-1 downto 0);
signal ena_internal : std_logic;
begin
oclk_enable <= sync_regs(depth-1);
no_multiplication: if pulse_multiplier=1 generate
ena_internal <= ena(0);
end generate;
async_reset: if reset_kind="ASYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if aclr1=reset1_high then
counter <= (others => '0');
elsif clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1, aclr1)
begin
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
elsif clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2, aclr2)
begin
if aclr2=reset2_high then
sync_regs(i) <= '0';
elsif clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2, aclr2)
begin
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind="SYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
counter <= (others => '0');
else
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
else
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
sync_regs(i) <= '0';
else
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
none_reset: if reset_kind="NONE" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
xout <= iclk_data;
sxout <= oclk_data;
end sync_reg;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_block: if 0 < depth generate
begin
delay_loop: for i in depth-1 downto 0 generate
begin
async_reset: if reset_kind = "ASYNC" generate
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind = "SYNC" generate
process(clk)
begin
if clk'event and clk='1' then
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
no_reset: if reset_kind = "NONE" generate
process(clk)
begin
if clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
end generate;
end generate;
xout <= delay_signals(0);
end delay;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_sync_reg is
generic (
width1 : natural := 8;
init_value : std_logic_vector;
width2 : natural := 8;
depth : natural := 2;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end entity;
architecture sync_reg of dspba_sync_reg is
type bit_array is array (depth-1 downto 0) of std_logic;
signal iclk_enable : std_logic;
signal iclk_data : std_logic_vector(width1-1 downto 0);
signal oclk_data : std_logic_vector(width2-1 downto 0);
-- For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops
-- For TimeQuest this means: identify these flip-flops as synchronizer to enable aitomatic MTBF analysis
signal sync_regs : bit_array;
attribute altera_attribute : string;
attribute altera_attribute of sync_regs : signal is "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON";
signal oclk_enable : std_logic;
constant init_value_internal : std_logic_vector(width1-1 downto 0) := init_value;
signal counter : UNSIGNED(counter_width-1 downto 0);
signal ena_internal : std_logic;
begin
oclk_enable <= sync_regs(depth-1);
no_multiplication: if pulse_multiplier=1 generate
ena_internal <= ena(0);
end generate;
async_reset: if reset_kind="ASYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if aclr1=reset1_high then
counter <= (others => '0');
elsif clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1, aclr1)
begin
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
elsif clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2, aclr2)
begin
if aclr2=reset2_high then
sync_regs(i) <= '0';
elsif clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2, aclr2)
begin
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind="SYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
counter <= (others => '0');
else
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
else
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
sync_regs(i) <= '0';
else
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
none_reset: if reset_kind="NONE" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
xout <= iclk_data;
sxout <= oclk_data;
end sync_reg;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_block: if 0 < depth generate
begin
delay_loop: for i in depth-1 downto 0 generate
begin
async_reset: if reset_kind = "ASYNC" generate
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind = "SYNC" generate
process(clk)
begin
if clk'event and clk='1' then
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
no_reset: if reset_kind = "NONE" generate
process(clk)
begin
if clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
end generate;
end generate;
xout <= delay_signals(0);
end delay;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_sync_reg is
generic (
width1 : natural := 8;
init_value : std_logic_vector;
width2 : natural := 8;
depth : natural := 2;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end entity;
architecture sync_reg of dspba_sync_reg is
type bit_array is array (depth-1 downto 0) of std_logic;
signal iclk_enable : std_logic;
signal iclk_data : std_logic_vector(width1-1 downto 0);
signal oclk_data : std_logic_vector(width2-1 downto 0);
-- For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops
-- For TimeQuest this means: identify these flip-flops as synchronizer to enable aitomatic MTBF analysis
signal sync_regs : bit_array;
attribute altera_attribute : string;
attribute altera_attribute of sync_regs : signal is "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON";
signal oclk_enable : std_logic;
constant init_value_internal : std_logic_vector(width1-1 downto 0) := init_value;
signal counter : UNSIGNED(counter_width-1 downto 0);
signal ena_internal : std_logic;
begin
oclk_enable <= sync_regs(depth-1);
no_multiplication: if pulse_multiplier=1 generate
ena_internal <= ena(0);
end generate;
async_reset: if reset_kind="ASYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if aclr1=reset1_high then
counter <= (others => '0');
elsif clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1, aclr1)
begin
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
elsif clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2, aclr2)
begin
if aclr2=reset2_high then
sync_regs(i) <= '0';
elsif clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2, aclr2)
begin
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind="SYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
counter <= (others => '0');
else
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
else
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
sync_regs(i) <= '0';
else
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
none_reset: if reset_kind="NONE" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
xout <= iclk_data;
sxout <= oclk_data;
end sync_reg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2769.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s07b00x00p09n01i02769ent IS
END c13s07b00x00p09n01i02769ent;
ARCHITECTURE c13s07b00x00p09n01i02769arch OF c13s07b00x00p09n01i02769ent IS
constant aaa : bit_vector := B"101101";
constant bbb : bit_vector := O"777";
constant ccc : bit_vector := X"FFFF";
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( aaa'length = 6 and bbb'length = 9 and ccc'length = 16 )
report "***PASSED TEST: c13s07b00x00p09n01i02769"
severity NOTE;
assert ( aaa'length = 6 and bbb'length = 9 and ccc'length = 16 )
report "***FAILED TEST: c13s07b00x00p09n01i02769 - The length of a bit string literal is the length of its string literal value."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s07b00x00p09n01i02769arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2769.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s07b00x00p09n01i02769ent IS
END c13s07b00x00p09n01i02769ent;
ARCHITECTURE c13s07b00x00p09n01i02769arch OF c13s07b00x00p09n01i02769ent IS
constant aaa : bit_vector := B"101101";
constant bbb : bit_vector := O"777";
constant ccc : bit_vector := X"FFFF";
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( aaa'length = 6 and bbb'length = 9 and ccc'length = 16 )
report "***PASSED TEST: c13s07b00x00p09n01i02769"
severity NOTE;
assert ( aaa'length = 6 and bbb'length = 9 and ccc'length = 16 )
report "***FAILED TEST: c13s07b00x00p09n01i02769 - The length of a bit string literal is the length of its string literal value."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s07b00x00p09n01i02769arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2769.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s07b00x00p09n01i02769ent IS
END c13s07b00x00p09n01i02769ent;
ARCHITECTURE c13s07b00x00p09n01i02769arch OF c13s07b00x00p09n01i02769ent IS
constant aaa : bit_vector := B"101101";
constant bbb : bit_vector := O"777";
constant ccc : bit_vector := X"FFFF";
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( aaa'length = 6 and bbb'length = 9 and ccc'length = 16 )
report "***PASSED TEST: c13s07b00x00p09n01i02769"
severity NOTE;
assert ( aaa'length = 6 and bbb'length = 9 and ccc'length = 16 )
report "***FAILED TEST: c13s07b00x00p09n01i02769 - The length of a bit string literal is the length of its string literal value."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s07b00x00p09n01i02769arch;
|
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Mon May 22 02:50:48 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system_wrapper.bd
--Design : system_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_wrapper is
port (
clk_100 : in STD_LOGIC;
hdmi_clk : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
resend : in STD_LOGIC
);
end system_wrapper;
architecture STRUCTURE of system_wrapper is
component system is
port (
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
clk_100 : in STD_LOGIC;
resend : in STD_LOGIC
);
end component system;
begin
system_i: component system
port map (
clk_100 => clk_100,
hdmi_clk => hdmi_clk,
hdmi_d(15 downto 0) => hdmi_d(15 downto 0),
hdmi_de => hdmi_de,
hdmi_hsync => hdmi_hsync,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => hdmi_vsync,
resend => resend
);
end STRUCTURE;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_xilinx_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory generators for Xilinx rams
------------------------------------------------------------------------------
-- parametrisable sync ram generator using UNISIM RAMB16 block rams
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
use unisim.RAMB16_S36;
use unisim.RAMB16_S18;
use unisim.RAMB16_S9;
use unisim.RAMB16_S4;
use unisim.RAMB16_S2;
use unisim.RAMB16_S1;
--pragma translate_on
entity unisim_syncram is
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of unisim_syncram is
component RAMB16_S36_S36
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
component RAMB16_S1
port (
DO : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (13 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S2
port (
DO : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (12 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S4
port (
DO : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (11 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S9
port (
DO : out std_logic_vector (7 downto 0);
DOP : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (10 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (7 downto 0);
DIP : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S18
port (
DO : out std_logic_vector (15 downto 0);
DOP : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (9 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (15 downto 0);
DIP : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S36
port (
DO : out std_logic_vector (31 downto 0);
DOP : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (8 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (31 downto 0);
DIP : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component generic_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic);
end component;
signal gnd : std_ulogic;
signal do, di : std_logic_vector(dbits+72 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= '0'; dataout <= do(dbits-1 downto 0); di(dbits-1 downto 0) <= datain;
di(dbits+72 downto dbits) <= (others => '0'); xa(abits-1 downto 0) <= address;
xa(19 downto abits) <= (others => '0'); ya(abits-1 downto 0) <= address;
ya(19 downto abits) <= (others => '1');
a0 : if (abits <= 5) and (GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) = 0) generate
r0 : generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+72 downto dbits) <= (others => '0');
end generate;
a8 : if ((abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0) and
(abits <= 8)) generate
x : for i in 0 to ((dbits-1)/72) generate
r0 : RAMB16_S36_S36
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do(i*72+36+31 downto i*72+36), do(i*72+31 downto i*72),
do(i*72+36+32+3 downto i*72+36+32), do(i*72+32+3 downto i*72+32),
xa(8 downto 0), ya(8 downto 0), clk, clk,
di(i*72+36+31 downto i*72+36), di(i*72+31 downto i*72),
di(i*72+36+32+3 downto i*72+36+32), di(i*72+32+3 downto i*72+32),
enable, enable, gnd, gnd, write, write);
end generate;
do(dbits+72 downto 72*(((dbits-1)/72)+1)) <= (others => '0');
end generate;
a9 : if (abits = 9) generate
x : for i in 0 to ((dbits-1)/36) generate
r : RAMB16_S36 port map ( do(((i+1)*36)-5 downto i*36),
do(((i+1)*36)-1 downto i*36+32), xa(8 downto 0), clk,
di(((i+1)*36)-5 downto i*36), di(((i+1)*36)-1 downto i*36+32),
enable, gnd, write);
end generate;
do(dbits+72 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
end generate;
a10 : if (abits = 10) generate
x : for i in 0 to ((dbits-1)/18) generate
r : RAMB16_S18 port map ( do(((i+1)*18)-3 downto i*18),
do(((i+1)*18)-1 downto i*18+16), xa(9 downto 0), clk,
di(((i+1)*18)-3 downto i*18), di(((i+1)*18)-1 downto i*18+16),
enable, gnd, write);
end generate;
do(dbits+72 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/9) generate
r : RAMB16_S9 port map ( do(((i+1)*9)-2 downto i*9),
do(((i+1)*9)-1 downto i*9+8), xa(10 downto 0), clk,
di(((i+1)*9)-2 downto i*9), di(((i+1)*9)-1 downto i*9+8),
enable, gnd, write);
end generate;
do(dbits+72 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
end generate;
a12 : if abits = 12 generate
x : for i in 0 to ((dbits-1)/4) generate
r : RAMB16_S4 port map ( do(((i+1)*4)-1 downto i*4), xa(11 downto 0),
clk, di(((i+1)*4)-1 downto i*4), enable, gnd, write);
end generate;
do(dbits+72 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
end generate;
a13 : if abits = 13 generate
x : for i in 0 to ((dbits-1)/2) generate
r : RAMB16_S2 port map ( do(((i+1)*2)-1 downto i*2), xa(12 downto 0),
clk, di(((i+1)*2)-1 downto i*2), enable, gnd, write);
end generate;
do(dbits+72 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
end generate;
a14 : if abits = 14 generate
x : for i in 0 to (dbits-1) generate
r : RAMB16_S1 port map ( do((i+1)-1 downto i), xa(13 downto 0),
clk, di((i+1)-1 downto i), enable, gnd, write);
end generate;
do(dbits+72 downto dbits) <= (others => '0');
end generate;
a15 : if abits > 14 generate
x: generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+72 downto dbits) <= (others => '0');
end generate;
-- pragma translate_off
-- a_to_high : if abits > 14 generate
-- x : process
-- begin
-- assert false
-- report "Address depth larger than 14 not supported for unisim_syncram"
-- severity failure;
-- wait;
-- end process;
-- end generate;
-- pragma translate_on
end;
LIBRARY ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
use unisim.RAMB16_S18_S18;
use unisim.RAMB16_S9_S9;
use unisim.RAMB16_S4_S4;
use unisim.RAMB16_S2_S2;
use unisim.RAMB16_S1_S1;
--pragma translate_on
entity unisim_syncram_dp is
generic (
abits : integer := 4; dbits : integer := 32
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of unisim_syncram_dp is
component RAMB16_S4_S4
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S1_S1
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S2_S2
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S9_S9
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S18_S18
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (15 downto 0);
DOB : out std_logic_vector (15 downto 0);
DOPA : out std_logic_vector (1 downto 0);
DOPB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (15 downto 0);
DIB : in std_logic_vector (15 downto 0);
DIPA : in std_logic_vector (1 downto 0);
DIPB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
component RAMB16_S36_S36
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
signal gnd, vcc : std_ulogic;
signal do1, do2, di1, di2 : std_logic_vector(dbits+36 downto 0);
signal addr1, addr2 : std_logic_vector(19 downto 0);
begin
gnd <= '0'; vcc <= '1';
dataout1 <= do1(dbits-1 downto 0); dataout2 <= do2(dbits-1 downto 0);
di1(dbits-1 downto 0) <= datain1; di1(dbits+36 downto dbits) <= (others => '0');
di2(dbits-1 downto 0) <= datain2; di2(dbits+36 downto dbits) <= (others => '0');
addr1(abits-1 downto 0) <= address1; addr1(19 downto abits) <= (others => '0');
addr2(abits-1 downto 0) <= address2; addr2(19 downto abits) <= (others => '0');
a9 : if abits <= 9 generate
x : for i in 0 to ((dbits-1)/36) generate
r0 : RAMB16_S36_S36
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*36)-5 downto i*36), do2(((i+1)*36)-5 downto i*36),
do1(((i+1)*36)-1 downto i*36+32), do2(((i+1)*36)-1 downto i*36+32),
addr1(8 downto 0), addr2(8 downto 0), clk1, clk2,
di1(((i+1)*36)-5 downto i*36), di2(((i+1)*36)-5 downto i*36),
di1(((i+1)*36)-1 downto i*36+32), di2(((i+1)*36)-1 downto i*36+32),
enable1, enable2, gnd, gnd, write1, write2);
-- vcc, vcc, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
do2(dbits+36 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
end generate;
a10 : if abits = 10 generate
x : for i in 0 to ((dbits-1)/18) generate
r0 : RAMB16_S18_S18
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*18)-3 downto i*18), do2(((i+1)*18)-3 downto i*18),
do1(((i+1)*18)-1 downto i*18+16), do2(((i+1)*18)-1 downto i*18+16),
addr1(9 downto 0), addr2(9 downto 0), clk1, clk2,
di1(((i+1)*18)-3 downto i*18), di2(((i+1)*18)-3 downto i*18),
di1(((i+1)*18)-1 downto i*18+16), di2(((i+1)*18)-1 downto i*18+16),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
do2(dbits+36 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/9) generate
r0 : RAMB16_S9_S9
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*9)-2 downto i*9), do2(((i+1)*9)-2 downto i*9),
do1(((i+1)*9)-1 downto i*9+8), do2(((i+1)*9)-1 downto i*9+8),
addr1(10 downto 0), addr2(10 downto 0), clk1, clk2,
di1(((i+1)*9)-2 downto i*9), di2(((i+1)*9)-2 downto i*9),
di1(((i+1)*9)-1 downto i*9+8), di2(((i+1)*9)-1 downto i*9+8),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
do2(dbits+36 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
end generate;
a12 : if abits = 12 generate
x : for i in 0 to ((dbits-1)/4) generate
r0 : RAMB16_S4_S4
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*4)-1 downto i*4), do2(((i+1)*4)-1 downto i*4),
addr1(11 downto 0), addr2(11 downto 0), clk1, clk2,
di1(((i+1)*4)-1 downto i*4), di2(((i+1)*4)-1 downto i*4),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
do2(dbits+36 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
end generate;
a13 : if abits = 13 generate
x : for i in 0 to ((dbits-1)/2) generate
r0 : RAMB16_S2_S2
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*2)-1 downto i*2), do2(((i+1)*2)-1 downto i*2),
addr1(12 downto 0), addr2(12 downto 0), clk1, clk2,
di1(((i+1)*2)-1 downto i*2), di2(((i+1)*2)-1 downto i*2),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
do2(dbits+36 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
end generate;
a14 : if abits = 14 generate
x : for i in 0 to ((dbits-1)/1) generate
r0 : RAMB16_S1_S1
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*1)-1 downto i*1), do2(((i+1)*1)-1 downto i*1),
addr1(13 downto 0), addr2(13 downto 0), clk1, clk2,
di1(((i+1)*1)-1 downto i*1), di2(((i+1)*1)-1 downto i*1),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto dbits) <= (others => '0');
do2(dbits+36 downto dbits) <= (others => '0');
end generate;
-- pragma translate_off
a_to_high : if abits > 14 generate
x : process
begin
assert false
report "Address depth larger than 14 not supported for unisim_syncram_dp"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
entity unisim_syncram_2p is
generic (abits : integer := 6; dbits : integer := 8; sepclk : integer := 0;
wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end;
architecture behav of unisim_syncram_2p is
component unisim_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component generic_syncram_2p
generic (abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end component;
signal write2, renable2 : std_ulogic;
signal datain2 : std_logic_vector((dbits-1) downto 0);
begin
-- nowf: if wrfst = 0 generate
write2 <= '0'; renable2 <= renable; datain2 <= (others => '0');
-- end generate;
-- wf : if wrfst = 1 generate
-- write2 <= '0' when (waddress /= raddress) else write;
-- renable2 <= renable or write2; datain2 <= datain;
-- end generate;
a0 : if abits <= 5 and GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) = 0 generate
x0 : generic_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, write, dataout);
end generate;
a6 : if abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0 generate
x0 : unisim_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, write, write,
rclk, raddress, datain2, dataout, renable2, write2);
end generate;
end;
-- parametrisable sync ram generator using unisim block rams
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
--pragma translate_on
entity unisim_syncram64 is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end;
architecture behav of unisim_syncram64 is
component unisim_syncram
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component RAMB16_S36_S36
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
signal gnd : std_logic_vector(3 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= "0000";
xa(abits-1 downto 0) <= address; xa(19 downto abits) <= (others => '0');
ya(abits-1 downto 0) <= address; ya(19 downto abits) <= (others => '1');
a8 : if abits <= 8 generate
r0 : RAMB16_S36_S36
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
dataout(63 downto 32), dataout(31 downto 0), open, open,
xa(8 downto 0), ya(8 downto 0), clk, clk,
datain(63 downto 32), datain(31 downto 0), gnd, gnd,
enable(1), enable(0), gnd(0), gnd(0), write(1), write(0));
end generate;
a9 : if abits > 8 generate
x1 : unisim_syncram generic map ( abits, 32)
port map (clk, address, datain(63 downto 32), dataout(63 downto 32),
enable(1), write(1));
x2 : unisim_syncram generic map ( abits, 32)
port map (clk, address, datain(31 downto 0), dataout(31 downto 0),
enable(0), write(0));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity unisim_syncram128 is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (3 downto 0);
write : in std_logic_vector (3 downto 0)
);
end;
architecture behav of unisim_syncram128 is
component unisim_syncram64 is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end component;
begin
x0 : unisim_syncram64 generic map (abits)
port map (clk, address, datain(127 downto 64), dataout(127 downto 64),
enable(3 downto 2), write(3 downto 2));
x1 : unisim_syncram64 generic map (abits)
port map (clk, address, datain(63 downto 0), dataout(63 downto 0),
enable(1 downto 0), write(1 downto 0));
end;
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
--pragma translate_on
entity unisim_syncram128bw is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0)
);
end;
architecture behav of unisim_syncram128bw is
component unisim_syncram
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component RAMB16_S9_S9
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
signal gnd : std_logic_vector(3 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= "0000";
xa(abits-1 downto 0) <= address; xa(19 downto abits) <= (others => '0');
ya(abits-1 downto 0) <= address; ya(19 downto abits) <= (others => '1');
a11 : if abits <= 10 generate
x0 : for i in 0 to 7 generate
r0 : RAMB16_S9_S9
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
dataout(i*8+7+64 downto i*8+64), dataout(i*8+7 downto i*8), open, open,
xa(10 downto 0), ya(10 downto 0), clk, clk,
datain(i*8+7+64 downto i*8+64), datain(i*8+7 downto i*8), gnd(0 downto 0), gnd(0 downto 0),
enable(i+8), enable(i), gnd(0), gnd(0), write(i+8), write(i));
end generate;
end generate;
a12 : if abits > 10 generate
x0 : for i in 0 to 15 generate
x2 : unisim_syncram generic map ( abits, 8)
port map (clk, address, datain(i*8+7 downto i*8),
dataout(i*8+7 downto i*8), enable(i), write(i));
end generate;
end generate;
end;
|
-- NEED RESULT: ARCH00173.P1: Multi inertial transactions occurred on signal asg with indexed name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00173: One inertial transaction occurred on signal asg with indexed name prefixed by a selected name on LHS passed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00173
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00173)
-- ENT00173_Test_Bench(ARCH00173_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00173 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0 =>
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00173.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns,
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 30 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00173" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <= transport
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 100 ns;
--
when 5 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00173" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns,
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 30 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 40 ns ;
--
when 6 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00173" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
-- The following will mark last transaction above
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 40 ns;
--
when 7 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00173" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00173" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
--
end ARCH00173 ;
--
entity ENT00173_Test_Bench is
end ENT00173_Test_Bench ;
--
architecture ARCH00173_Test_Bench of ENT00173_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00173 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00173_Test_Bench ;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
-- Date : Fri Sep 22 14:43:38 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_auto_pc_3_stub.vhdl
-- Design : zqynq_lab_1_design_auto_pc_3
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awid[11:0],m_axi_awaddr[31:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bid[11:0],m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_arid[11:0],m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rid[11:0],m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2.1";
begin
end;
|
context name1;
context name2, name3;
context name4, name5, name6;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nano_cpu_pkg.all;
use work.io_bus_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity nano is
generic (
g_big_endian : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
-- i/o interface
io_addr : out unsigned(7 downto 0);
io_write : out std_logic;
io_read : out std_logic;
io_wdata : out std_logic_vector(15 downto 0);
io_rdata : in std_logic_vector(15 downto 0);
stall : in std_logic;
-- system interface (to write code into the nano)
sys_clock : in std_logic := '0';
sys_reset : in std_logic := '0';
sys_io_req : in t_io_req := c_io_req_init;
sys_io_resp : out t_io_resp );
end entity;
architecture structural of nano is
signal sys_enable : std_logic;
signal sys_bram_addr : std_logic_vector(10 downto 0);
-- instruction/data ram
signal ram_addr : std_logic_vector(9 downto 0);
signal ram_en : std_logic;
signal ram_we : std_logic;
signal ram_wdata : std_logic_vector(15 downto 0);
signal ram_rdata : std_logic_vector(15 downto 0);
signal sys_io_req_bram : t_io_req;
signal sys_io_resp_bram : t_io_resp;
signal sys_io_req_regs : t_io_req;
signal sys_io_resp_regs : t_io_resp;
signal sys_core_reset : std_logic := '1';
signal usb_reset_tig : std_logic := '1';
signal usb_core_reset : std_logic := '1';
signal bram_data : std_logic_vector(7 downto 0);
begin
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 11,
g_range_hi => 11,
g_ports => 2 )
port map (
clock => sys_clock,
req => sys_io_req,
resp => sys_io_resp,
reqs(0) => sys_io_req_bram,
reqs(1) => sys_io_req_regs,
resps(0) => sys_io_resp_bram,
resps(1) => sys_io_resp_regs );
i_core: entity work.nano_cpu
port map (
clock => clock,
reset => usb_core_reset,
-- instruction/data ram
ram_addr => ram_addr,
ram_en => ram_en,
ram_we => ram_we,
ram_wdata => ram_wdata,
ram_rdata => ram_rdata,
-- i/o interface
io_addr => io_addr,
io_write => io_write,
io_read => io_read,
io_wdata => io_wdata,
io_rdata => io_rdata,
stall => stall );
--i_buf_ram: entity work.RAMB16_S9_S18(model)
i_buf_ram: RAMB16_S9_S18
port map (
CLKB => clock,
SSRB => reset,
ENB => ram_en,
WEB => ram_we,
ADDRB => ram_addr,
DIB => ram_wdata,
DIPB => "00",
DOB => ram_rdata,
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_enable,
WEA => sys_io_req_bram.write,
ADDRA => sys_bram_addr,
DIA => sys_io_req_bram.data,
DIPA => "0",
DOA => bram_data );
sys_bram_addr(10 downto 1) <= std_logic_vector(sys_io_req_bram.address(10 downto 1));
sys_bram_addr(0) <= not sys_io_req_bram.address(0) when g_big_endian else sys_io_req_bram.address(0);
sys_enable <= sys_io_req_bram.write or sys_io_req_bram.read;
sys_io_resp_bram.data <= bram_data when sys_io_resp_bram.ack = '1' else X"00";
process(sys_clock)
begin
if rising_edge(sys_clock) then
sys_io_resp_bram.ack <= sys_enable;
sys_io_resp_regs <= c_io_resp_init;
sys_io_resp_regs.ack <= sys_io_req_regs.write or sys_io_req_regs.read;
if sys_io_req_regs.write = '1' then -- any address
sys_core_reset <= not sys_io_req_regs.data(0);
end if;
if sys_reset = '1' then
sys_core_reset <= '1';
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
usb_reset_tig <= sys_core_reset;
usb_core_reset <= usb_reset_tig;
end if;
end process;
end architecture;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY tutorial_proc_sys_reset_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END tutorial_proc_sys_reset_0;
ARCHITECTURE tutorial_proc_sys_reset_0_arch OF tutorial_proc_sys_reset_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_proc_sys_reset_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END tutorial_proc_sys_reset_0_arch;
|
------------------------------------------------------------------------------
-- hyos_plb.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: hyos_plb.vhd
-- Version: 1.00.e
-- Description: Top level design, instantiates library components and user logic.
-- Date: Thu Mar 22 15:43:09 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.soft_reset;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library hyos_plb_v1_00_e;
use hyos_plb_v1_00_e.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity hyos_plb is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex6"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity hyos_plb;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of hyos_plb is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
constant RST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
constant RST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR, -- user logic slave space high address
ZERO_ADDR_PAD & RST_BASEADDR, -- soft reset space base address
ZERO_ADDR_PAD & RST_HIGHADDR -- soft reset space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 8;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant RST_NUM_CE : integer := 1;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG), -- number of ce for user logic slave space
1 => RST_NUM_CE -- number of ce for soft reset space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of triggered reset in bus clocks
------------------------------------------
constant RESET_WIDTH : integer := 4;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant RST_CS_INDEX : integer := 1;
constant RST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, RST_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal rst_Bus2IP_Reset : std_logic;
signal rst_IP2Bus_WrAck : std_logic;
signal rst_IP2Bus_Error : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
------------------------------------------
-- Component declaration for verilog user logic
------------------------------------------
component user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 8
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end component user_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate soft_reset
------------------------------------------
SOFT_RESET_I : entity proc_common_v3_00_a.soft_reset
generic map
(
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_RESET_WIDTH => RESET_WIDTH
)
port map
(
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_WrCE => ipif_Bus2IP_WrCE(RST_CE_INDEX),
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Reset2IP_Reset => rst_Bus2IP_Reset,
Reset2Bus_WrAck => rst_IP2Bus_WrAck,
Reset2Bus_Error => rst_IP2Bus_Error,
Reset2Bus_ToutSup => open
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : component user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => rst_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
begin
case ipif_Bus2IP_CS is
when "10" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "01" => ipif_IP2Bus_Data <= (others => '0');
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or rst_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error or rst_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Justin Nguyen, Quinn Mikelson
--
-- Create Date: 09/29/2017 12:31:58 AM
-- Design Name: RegisterFile
-- Module Name: RegisterFile - Behavioral
-- Project Name: RAT CPU
-- Target Devices: xc7a50tcsg324-1
-- Tool Versions:
-- Description: This is the register component for our RAT CPU. The function of the register is to:
-- - Provide register space for the RAT instructions
-- The RAM is 32x8 memory module with asyc read and synchronous write.
--
-- Dependencies: N/A
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RegisterFile is
Port ( D_IN : in STD_LOGIC_VECTOR (7 downto 0);
DX_OUT : out STD_LOGIC_VECTOR (7 downto 0);
DY_OUT : out STD_LOGIC_VECTOR (7 downto 0);
ADRX : in STD_LOGIC_VECTOR (4 downto 0);
ADRY : in STD_LOGIC_VECTOR (4 downto 0);
WE : in STD_LOGIC;
CLK : in STD_LOGIC);
end RegisterFile;
architecture Behavioral of RegisterFile is
TYPE memory is array (0 to 31) of std_logic_vector(7 downto 0);
SIGNAL REG: memory := (others=>(others=>'0'));
begin
process(clk) begin
if (rising_edge(clk)) then
if (WE = '1') then
REG(conv_integer(ADRX)) <= D_IN;
end if;
end if;
end process;
DX_OUT <= REG(conv_integer(ADRX));
DY_OUT <= REG(conv_integer(ADRY));
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1979.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p01n02i01979ent IS
END c07s02b02x00p01n02i01979ent;
ARCHITECTURE c07s02b02x00p01n02i01979arch OF c07s02b02x00p01n02i01979ent IS
BEGIN
TESTING: PROCESS
variable NUM1 : BIT_VECTOR(0 to 1) := B"01";
variable NUM2 : STRING(1 to 2) := "01";
BEGIN
if (NUM1 = NUM2) then -- Failure_here
NULL;
end if;
assert FALSE
report "***FAILED TEST: c07s02b02x00p01n02i01979 - Operands of a relational operator should be of the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p01n02i01979arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1979.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p01n02i01979ent IS
END c07s02b02x00p01n02i01979ent;
ARCHITECTURE c07s02b02x00p01n02i01979arch OF c07s02b02x00p01n02i01979ent IS
BEGIN
TESTING: PROCESS
variable NUM1 : BIT_VECTOR(0 to 1) := B"01";
variable NUM2 : STRING(1 to 2) := "01";
BEGIN
if (NUM1 = NUM2) then -- Failure_here
NULL;
end if;
assert FALSE
report "***FAILED TEST: c07s02b02x00p01n02i01979 - Operands of a relational operator should be of the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p01n02i01979arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1979.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p01n02i01979ent IS
END c07s02b02x00p01n02i01979ent;
ARCHITECTURE c07s02b02x00p01n02i01979arch OF c07s02b02x00p01n02i01979ent IS
BEGIN
TESTING: PROCESS
variable NUM1 : BIT_VECTOR(0 to 1) := B"01";
variable NUM2 : STRING(1 to 2) := "01";
BEGIN
if (NUM1 = NUM2) then -- Failure_here
NULL;
end if;
assert FALSE
report "***FAILED TEST: c07s02b02x00p01n02i01979 - Operands of a relational operator should be of the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p01n02i01979arch;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_01 is
end entity inline_01;
----------------------------------------------------------------
architecture test of inline_01 is
type std_ulogic is (t1, t2, t3);
subtype std_logic is std_ulogic;
-- code from book:
type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
type std_logic_vector is array ( natural range <>) of std_logic;
-- end of code from book
begin
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_01 is
end entity inline_01;
----------------------------------------------------------------
architecture test of inline_01 is
type std_ulogic is (t1, t2, t3);
subtype std_logic is std_ulogic;
-- code from book:
type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
type std_logic_vector is array ( natural range <>) of std_logic;
-- end of code from book
begin
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_01 is
end entity inline_01;
----------------------------------------------------------------
architecture test of inline_01 is
type std_ulogic is (t1, t2, t3);
subtype std_logic is std_ulogic;
-- code from book:
type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
type std_logic_vector is array ( natural range <>) of std_logic;
-- end of code from book
begin
end architecture test;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
entity RS_Latch_Test is
end RS_Latch_Test;
architecture Beh of RS_Latch_Test is
component RS_Latch_Param
port(
R, S: in std_logic;
Q, nQ: out std_logic
);
end component;
signal stimuli: std_logic_vector(1 downto 0) := (others => '1');
signal response_struct,
response_struct_q
--response_beh,
--response_beh_q
: std_logic;
signal rs_latch_q, rs_latch_q1
--rs_latch_beh_q,
--rs_latch_beh_q1
: std_logic;
signal
sampled_response_struct,
sampled_response_struct_q
--sampled_response_beh,
--sampled_response_beh_q
: std_logic;
--signal error: std_logic;
constant min_time_between_events: time := 6 ns;
constant sampling_period: time := min_time_between_events / 2;
begin
stimuli_generation: process
variable buf : LINE;
begin
--while(true) loop
-- wait for min_time_between_events;
--
-- stimuli <= stimuli + 1;
-- end loop;
stimuli <= "11";
wait for min_time_between_events;
stimuli <= "00";
wait for min_time_between_events;
-- write(buf, "The operation has been completed successfully.");
-- writeline(output, buf);
--wait;
end process;
rs_latch_struct: entity rs_latch_param(struct) port map(
r => stimuli (1),
s => stimuli (0),
q => response_struct,
nq => response_struct_q
);
-- RS_Latch_Beh: entity RS_Latch_Param(Beh) port map(
-- R => stimuli (1),
-- S => stimuli (0),
-- Q => response_beh,
-- nQ => response_beh_q
-- );
rs_latch_q <= response_struct;
--rs_latch_beh_q <= response_beh;
rs_latch_q1 <= response_struct_q;
--rs_latch_beh_q1 <= response_beh_q;
sampled_response_struct <= response_struct after sampling_period;
--sampled_response_beh <= response_beh after sampling_period;
sampled_response_struct_q <= response_struct_q after sampling_period;
--sampled_response_beh_q <= response_beh_q after sampling_period;
--error <= (sampled_response_struct xor sampled_response_beh) and (sampled_response_struct_q xor sampled_response_beh_q);
--assert error /= '1' report "The device doesn't work as expected." severity failure;
end Beh;
|
entity econcat1 is
end econcat1;
architecture behav of econcat1 is
constant c1 : string (1 to 5) := "hello";
constant c2 : string (6 downto 1) := " world";
constant r : string := c1 & c2;
begin
process
begin
case True is
when c1 & c2 = "hello world" => null;
when false => null;
end case;
assert r'left = 1 severity failure;
assert r'right = 11 severity failure;
wait;
end process;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: amba
-- File: amba.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Modified by: Jan Andersson, Aeroflex Gaisler
-- Description: AMBA 2.0 bus signal definitions + support for plug&play
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
package amba is
-------------------------------------------------------------------------------
-- AMBA configuration
-------------------------------------------------------------------------------
-- AHBDW - AHB data with
--
-- Valid values are 32, 64, 128 and 256
--
-- The value here sets the width of the AMBA AHB data vectors for all
-- cores in the library.
--
constant AHBDW : integer := CFG_AHBDW;
-- CORE_ACDM - Enable AMBA Compliant Data Muxing in cores
--
-- Valid values are 0 and 1
--
-- 0: All GRLIB cores that use the ahbread* programs defined in this package
-- will read their data from the low part of the AHB data vector.
--
-- 1: All GRLIB cores that use the ahbread* programs defined in this package
-- will select valid data, as defined in the AMBA AHB standard, from the
-- AHB data vectors based on the address input. If a core uses a function
-- that does not have the address input, a failure will be asserted.
--
constant CORE_ACDM : integer := CFG_AHB_ACDM;
constant NAHBMST : integer := 16; -- maximum AHB masters
constant NAHBSLV : integer := 16; -- maximum AHB slaves
constant NAPBSLV : integer := 16; -- maximum APB slaves
constant NAHBIRQ : integer := 32; -- maximum interrupts
constant NAHBAMR : integer := 4; -- maximum address mapping registers
constant NAHBIR : integer := 4; -- maximum AHB identification registers
constant NAHBCFG : integer := NAHBIR + NAHBAMR; -- words in AHB config block
constant NAPBIR : integer := 1; -- maximum APB configuration words
constant NAPBAMR : integer := 1; -- maximum APB configuration words
constant NAPBCFG : integer := NAPBIR + NAPBAMR; -- words in APB config block
constant NBUS : integer := 4;
-- Number of test vector bits
constant NTESTINBITS : integer := 4+GRLIB_CONFIG_ARRAY(grlib_techmap_testin_extra);
-------------------------------------------------------------------------------
-- AMBA interface type declarations and constant
-------------------------------------------------------------------------------
subtype amba_config_word is std_logic_vector(31 downto 0);
type ahb_config_type is array (0 to NAHBCFG-1) of amba_config_word;
type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word;
-- AHB master inputs
type ahb_mst_in_type is record
hgrant : std_logic_vector(0 to NAHBMST-1); -- bus grant
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(AHBDW-1 downto 0); -- read data bus
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
testen : std_ulogic; -- scan test enable
testrst : std_ulogic; -- scan test reset
scanen : std_ulogic; -- scan enable
testoen : std_ulogic; -- test output enable
testin : std_logic_vector(NTESTINBITS-1 downto 0); -- test vector for syncrams
end record;
-- AHB master outputs
type ahb_mst_out_type is record
hbusreq : std_ulogic; -- bus request
hlock : std_ulogic; -- lock request
htrans : std_logic_vector(1 downto 0); -- transfer type
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hprot : std_logic_vector(3 downto 0); -- protection control
hwdata : std_logic_vector(AHBDW-1 downto 0); -- write data bus
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
hconfig : ahb_config_type; -- memory access reg.
hindex : integer range 0 to NAHBMST-1; -- diagnostic use only
end record;
-- AHB slave inputs
type ahb_slv_in_type is record
hsel : std_logic_vector(0 to NAHBSLV-1); -- slave select
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
htrans : std_logic_vector(1 downto 0); -- transfer type
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hwdata : std_logic_vector(AHBDW-1 downto 0); -- write data bus
hprot : std_logic_vector(3 downto 0); -- protection control
hready : std_ulogic; -- transfer done
hmaster : std_logic_vector(3 downto 0); -- current master
hmastlock : std_ulogic; -- locked access
hmbsel : std_logic_vector(0 to NAHBAMR-1); -- memory bank select
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
testen : std_ulogic; -- scan test enable
testrst : std_ulogic; -- scan test reset
scanen : std_ulogic; -- scan enable
testoen : std_ulogic; -- test output enable
testin : std_logic_vector(NTESTINBITS-1 downto 0); -- test vector for syncrams
end record;
-- AHB slave outputs
type ahb_slv_out_type is record
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(AHBDW-1 downto 0); -- read data bus
hsplit : std_logic_vector(NAHBMST-1 downto 0); -- split completion
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
hconfig : ahb_config_type; -- memory access reg.
hindex : integer range 0 to NAHBSLV-1; -- diagnostic use only
end record;
-- array types
type ahb_mst_out_vector_type is array (natural range <>) of ahb_mst_out_type;
type ahb_mst_in_vector_type is array (natural range <>) of ahb_mst_in_type;
type ahb_slv_out_vector_type is array (natural range <>) of ahb_slv_out_type;
type ahb_slv_in_vector_type is array (natural range <>) of ahb_slv_in_type;
subtype ahb_mst_out_vector is ahb_mst_out_vector_type(NAHBMST-1 downto 0);
subtype ahb_slv_out_vector is ahb_slv_out_vector_type(NAHBSLV-1 downto 0);
subtype ahb_mst_in_vector is ahb_mst_in_vector_type(NAHBMST-1 downto 0);
subtype ahb_slv_in_vector is ahb_slv_in_vector_type(NAHBSLV-1 downto 0);
type ahb_mst_out_bus_vector is array (0 to NBUS-1) of ahb_mst_out_vector;
type ahb_slv_out_bus_vector is array (0 to NBUS-1) of ahb_slv_out_vector;
-- constants
constant HTRANS_IDLE: std_logic_vector(1 downto 0) := "00";
constant HTRANS_BUSY: std_logic_vector(1 downto 0) := "01";
constant HTRANS_NONSEQ: std_logic_vector(1 downto 0) := "10";
constant HTRANS_SEQ: std_logic_vector(1 downto 0) := "11";
constant HBURST_SINGLE: std_logic_vector(2 downto 0) := "000";
constant HBURST_INCR: std_logic_vector(2 downto 0) := "001";
constant HBURST_WRAP4: std_logic_vector(2 downto 0) := "010";
constant HBURST_INCR4: std_logic_vector(2 downto 0) := "011";
constant HBURST_WRAP8: std_logic_vector(2 downto 0) := "100";
constant HBURST_INCR8: std_logic_vector(2 downto 0) := "101";
constant HBURST_WRAP16: std_logic_vector(2 downto 0) := "110";
constant HBURST_INCR16: std_logic_vector(2 downto 0) := "111";
constant HSIZE_BYTE: std_logic_vector(2 downto 0) := "000";
constant HSIZE_HWORD: std_logic_vector(2 downto 0) := "001";
constant HSIZE_WORD: std_logic_vector(2 downto 0) := "010";
constant HSIZE_DWORD: std_logic_vector(2 downto 0) := "011";
constant HSIZE_4WORD: std_logic_vector(2 downto 0) := "100";
constant HSIZE_8WORD: std_logic_vector(2 downto 0) := "101";
constant HSIZE_16WORD: std_logic_vector(2 downto 0) := "110";
constant HSIZE_32WORD: std_logic_vector(2 downto 0) := "111";
constant HRESP_OKAY: std_logic_vector(1 downto 0) := "00";
constant HRESP_ERROR: std_logic_vector(1 downto 0) := "01";
constant HRESP_RETRY: std_logic_vector(1 downto 0) := "10";
constant HRESP_SPLIT: std_logic_vector(1 downto 0) := "11";
-- APB slave inputs
type apb_slv_in_type is record
psel : std_logic_vector(0 to NAPBSLV-1); -- slave select
penable : std_ulogic; -- strobe
paddr : std_logic_vector(31 downto 0); -- address bus (byte)
pwrite : std_ulogic; -- write
pwdata : std_logic_vector(31 downto 0); -- write data bus
pirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
testen : std_ulogic; -- scan test enable
testrst : std_ulogic; -- scan test reset
scanen : std_ulogic; -- scan enable
testoen : std_ulogic; -- test output enable
testin : std_logic_vector(NTESTINBITS-1 downto 0); -- test vector for syncrams
end record;
-- APB slave outputs
type apb_slv_out_type is record
prdata : std_logic_vector(31 downto 0); -- read data bus
pirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
pconfig : apb_config_type; -- memory access reg.
pindex : integer range 0 to NAPBSLV -1; -- diag use only
end record;
-- array types
type apb_slv_out_vector is array (0 to NAPBSLV-1) of apb_slv_out_type;
-- support for plug&play configuration
constant AMBA_CONFIG_VER0 : std_logic_vector(1 downto 0) := "00";
subtype amba_vendor_type is integer range 0 to 16#ff#;
subtype amba_device_type is integer range 0 to 16#3ff#;
subtype amba_version_type is integer range 0 to 16#3f#;
subtype amba_cfgver_type is integer range 0 to 3;
subtype amba_irq_type is integer range 0 to NAHBIRQ-1;
subtype ahb_addr_type is integer range 0 to 16#fff#;
constant zx : std_logic_vector(31 downto 0) := (others => '0');
constant zahbdw : std_logic_vector(AHBDW-1 downto 0) := (others => '0');
constant zxirq : std_logic_vector(NAHBIRQ-1 downto 0) := (others => '0');
constant zy : std_logic_vector(0 to 31) := (others => '0');
constant ztestin : std_logic_vector(NTESTINBITS-1 downto 0) := (others => '0');
constant apb_none : apb_slv_out_type :=
(zx, zxirq(NAHBIRQ-1 downto 0), (others => zx), 0);
constant ahbm_none : ahb_mst_out_type := ( '0', '0', "00", zx,
'0', "000", "000", "0000", zahbdw, zxirq(NAHBIRQ-1 downto 0), (others => zx), 0);
constant ahbm_in_none : ahb_mst_in_type := ((others => '0'), '0', (others => '0'),
zahbdw, zxirq(NAHBIRQ-1 downto 0), '0', '0', '0', '0', ztestin);
constant ahbs_none : ahb_slv_out_type := (
'1', "00", zahbdw, zx(NAHBMST-1 downto 0), zxirq(NAHBIRQ-1 downto 0), (others => zx), 0);
constant ahbs_in_none : ahb_slv_in_type := (
zy(0 to NAHBSLV-1), zx, '0', "00", "000", "000", zahbdw,
"0000", '1', "0000", '0', zy(0 to NAHBAMR-1), zxirq(NAHBIRQ-1 downto 0),
'0', '0', '0', '0', ztestin);
constant ahbsv_none : ahb_slv_out_vector := (others => ahbs_none);
constant apb_slv_in_none : apb_slv_in_type := ((others => '0'), '0', (others => '0'),
'0', (others => '0'), (others => '0'),
'0', '0', '0', '0', ztestin);
-------------------------------------------------------------------------------
-- Subprograms
-------------------------------------------------------------------------------
function ahb_device_reg(vendor : amba_vendor_type; device : amba_device_type;
cfgver : amba_cfgver_type; version : amba_version_type;
interrupt : amba_irq_type)
return std_logic_vector;
function ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type)
return std_logic_vector;
function ahb_membar_opt(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type; enable : integer)
return std_logic_vector;
function ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return std_logic_vector;
function apb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return std_logic_vector;
function ahb_slv_dec_cache(haddr : std_logic_vector(31 downto 0);
ahbso : ahb_slv_out_vector; cached : integer)
return std_ulogic;
function ahb_slv_dec_pfetch(haddr : std_logic_vector(31 downto 0);
ahbso : ahb_slv_out_vector)
return std_ulogic;
function ahb_membar_size (addrmask : ahb_addr_type) return integer;
function ahb_iobar_size (addrmask : ahb_addr_type) return integer;
function ahbdrivedata (hdata : std_logic_vector) return std_logic_vector;
function ahbselectdata (hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2); hsize : std_logic_vector(2 downto 0))
return std_logic_vector;
function ahbreadword (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2))
return std_logic_vector;
procedure ahbreadword (
hdata : in std_logic_vector(AHBDW-1 downto 0);
haddr : in std_logic_vector(4 downto 2);
data : out std_logic_vector(31 downto 0));
function ahbreadword (
hdata : std_logic_vector(AHBDW-1 downto 0))
return std_logic_vector;
procedure ahbreadword (
hdata : in std_logic_vector(AHBDW-1 downto 0);
data : out std_logic_vector(31 downto 0));
function ahbreaddword (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2))
return std_logic_vector;
procedure ahbreaddword (
hdata : in std_logic_vector(AHBDW-1 downto 0);
haddr : in std_logic_vector(4 downto 2);
data : out std_logic_vector(63 downto 0));
function ahbreaddword (
hdata : std_logic_vector(AHBDW-1 downto 0))
return std_logic_vector;
procedure ahbreaddword (
hdata : in std_logic_vector(AHBDW-1 downto 0);
data : out std_logic_vector(63 downto 0));
function ahbread4word (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2))
return std_logic_vector;
procedure ahbread4word (
hdata : in std_logic_vector(AHBDW-1 downto 0);
haddr : in std_logic_vector(4 downto 2);
data : out std_logic_vector(127 downto 0));
function ahbread4word (
hdata : std_logic_vector(AHBDW-1 downto 0))
return std_logic_vector;
procedure ahbread4word (
hdata : in std_logic_vector(AHBDW-1 downto 0);
data : out std_logic_vector(127 downto 0));
function ahbread8word (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2))
return std_logic_vector;
procedure ahbread8word (
hdata : in std_logic_vector(AHBDW-1 downto 0);
haddr : in std_logic_vector(4 downto 2);
data : out std_logic_vector(255 downto 0));
function ahbread8word (
hdata : std_logic_vector(AHBDW-1 downto 0))
return std_logic_vector;
procedure ahbread8word (
hdata : in std_logic_vector(AHBDW-1 downto 0);
data : out std_logic_vector(255 downto 0));
function ahbreaddata (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector;
function ahbreaddata (
hdata : std_logic_vector(AHBDW-1 downto 0);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector;
procedure ahbmomux (
signal ai : in ahb_mst_out_type;
signal ao : out ahb_mst_out_type;
signal en : in std_ulogic);
procedure ahbsomux (
signal ai : in ahb_slv_out_type;
signal ao : out ahb_slv_out_type;
signal en : in std_ulogic);
procedure apbsomux (
signal ai : in apb_slv_out_type;
signal ao : out apb_slv_out_type;
signal en : in std_ulogic);
-------------------------------------------------------------------------------
-- Components
-------------------------------------------------------------------------------
component ahbctrl
generic (
defmast : integer := 0; -- default master
split : integer := 0; -- split support
rrobin : integer := 0; -- round-robin arbitration
timeout : integer range 0 to 255 := 0; -- HREADY timeout
ioaddr : ahb_addr_type := 16#fff#; -- I/O area MSB address
iomask : ahb_addr_type := 16#fff#; -- I/O area address mask
cfgaddr : ahb_addr_type := 16#ff0#; -- config area MSB address
cfgmask : ahb_addr_type := 16#ff0#; -- config area address mask
nahbm : integer range 1 to NAHBMST := NAHBMST; -- number of masters
nahbs : integer range 1 to NAHBSLV := NAHBSLV; -- number of slaves
ioen : integer range 0 to 15 := 1; -- enable I/O area
disirq : integer range 0 to 1 := 0; -- disable interrupt routing
fixbrst : integer range 0 to 1 := 0; -- support fix-length bursts
debug : integer range 0 to 2 := 2; -- print config to console
fpnpen : integer range 0 to 1 := 0; -- full PnP configuration decoding
icheck : integer range 0 to 1 := 1;
devid : integer := 0; -- unique device ID
enbusmon : integer range 0 to 1 := 0; --enable bus monitor
assertwarn : integer range 0 to 1 := 0; --enable assertions for warnings
asserterr : integer range 0 to 1 := 0; --enable assertions for errors
hmstdisable : integer := 0; --disable master checks
hslvdisable : integer := 0; --disable slave checks
arbdisable : integer := 0; --disable arbiter checks
mprio : integer := 0; --master with highest priority
mcheck : integer range 0 to 2 := 1; --check memory map for intersects
ccheck : integer range 0 to 1 := 1; --perform sanity checks on pnp config
acdm : integer := 0; --AMBA compliant data muxing (for hsize > word)
index : integer := 0; --index for trace print-out
ahbtrace : integer := 0; --AHB trace enable
hwdebug : integer := 0;
fourgslv : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
msti : out ahb_mst_in_type;
msto : in ahb_mst_out_vector;
slvi : out ahb_slv_in_type;
slvo : in ahb_slv_out_vector;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
scanen : in std_ulogic := '0';
testoen : in std_ulogic := '1';
testsig : in std_logic_vector(1+GRLIB_CONFIG_ARRAY(grlib_techmap_testin_extra) downto 0) := (others => '0')
);
end component;
component ahbxb is
generic(
defmast : integer := 0; -- default master
timeout : integer range 0 to 255 := 0; -- HREADY timeout
ioaddr : ahb_addr_type := 16#fff#; -- I/O area MSB address
iomask : ahb_addr_type := 16#fff#; -- I/O area address mask
cfgaddr : ahb_addr_type := 16#ff0#; -- config area MSB address
cfgmask : ahb_addr_type := 16#ff0#; -- config area address mask
nahbm : integer range 1 to NAHBMST := NAHBMST; -- number of masters
nahbs : integer range 1 to NAHBSLV := NAHBSLV; -- number of slaves
ioen : integer range 0 to 15 := 1; -- enable I/O area
disirq : integer range 0 to 1 := 0; -- disable interrupt routing
fixbrst : integer range 0 to 1 := 0; -- support fix-length bursts
debug : integer range 0 to 2 := 2; -- report cores to console
fpnpen : integer range 0 to 1 := 0; -- full PnP configuration decoding
icheck : integer range 0 to 1 := 1;
devid : integer := 0; -- unique device ID
enbusmon : integer range 0 to 1 := 0; --enable bus monitor
assertwarn : integer range 0 to 1 := 0; --enable assertions for warnings
asserterr : integer range 0 to 1 := 0; --enable assertions for errors
hmstdisable : integer := 0; --disable master checks
hslvdisable : integer := 0; --disable slave checks
arbdisable : integer := 0; --disable arbiter checks
mprio : integer := 0; --master with highest priority
mcheck : integer range 0 to 2 := 1; --check memory map for intersects
ccheck : integer range 0 to 1 := 1; --perform sanity checks on pnp config
index : integer := 0; --Index for trace print-out
ahbtrace : integer := 0; --AHB trace enable
hwdebug : integer := 0; --Hardware debug
fourgslv : integer := 0; --1=Single slave with single 4 GB bar
l2en : integer := 0; --enable l2 cache multiport decoding
l2bhindex : integer range 0 to NAHBSLV := 0; --base index for the l2 cache slaves
l2num : integer := 4; --ńumber of l2 caches in system
l2linesize : integer := 32;--number of bytes in an l2 cache line
l2hmbsel : integer := 0 --index of L2 memory back
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
msti : out ahb_mst_in_vector;
msto : in ahb_mst_out_vector;
slvi : out ahb_slv_in_vector;
slvo : in ahb_slv_out_vector;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
scanen : in std_ulogic := '0';
testoen : in std_ulogic := '1';
testsig : in std_logic_vector(1+GRLIB_CONFIG_ARRAY(grlib_techmap_testin_extra) downto 0) := (others => '0')
);
end component;
component apbctrl
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
nslaves : integer range 1 to NAPBSLV := NAPBSLV;
debug : integer range 0 to 2 := 2; -- print config to console
icheck : integer range 0 to 1 := 1;
enbusmon : integer range 0 to 1 := 0;
asserterr : integer range 0 to 1 := 0;
assertwarn : integer range 0 to 1 := 0;
pslvdisable : integer := 0;
mcheck : integer range 0 to 1 := 1;
ccheck : integer range 0 to 1 := 1
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_slv_in_type;
ahbo : out ahb_slv_out_type;
apbi : out apb_slv_in_type;
apbo : in apb_slv_out_vector
);
end component;
component ahbctrl_mb
generic (
defmast : integer := 0; -- default master
split : integer := 0; -- split support
rrobin : integer := 0; -- round-robin arbitration
timeout : integer range 0 to 255 := 0; -- HREADY timeout
ioaddr : ahb_addr_type := 16#fff#; -- I/O area MSB address
iomask : ahb_addr_type := 16#fff#; -- I/O area address mask
cfgaddr : ahb_addr_type := 16#ff0#; -- config area MSB address
cfgmask : ahb_addr_type := 16#ff0#; -- config area address mask
nahbm : integer range 1 to NAHBMST := NAHBMST; -- number of masters
nahbs : integer range 1 to NAHBSLV := NAHBSLV; -- number of slaves
ioen : integer range 0 to 15 := 1; -- enable I/O area
disirq : integer range 0 to 1 := 0; -- disable interrupt routing
fixbrst : integer range 0 to 1 := 0; -- support fix-length bursts
debug : integer range 0 to 2 := 2; -- report cores to console
fpnpen : integer range 0 to 1 := 0; -- full PnP configuration decoding
busndx : integer range 0 to 3 := 0;
icheck : integer range 0 to 1 := 1;
devid : integer := 0; -- unique device ID
enbusmon : integer range 0 to 1 := 0; --enable bus monitor
assertwarn : integer range 0 to 1 := 0; --enable assertions for warnings
asserterr : integer range 0 to 1 := 0; --enable assertions for errors
hmstdisable : integer := 0; --disable master checks
hslvdisable : integer := 0; --disable slave checks
arbdisable : integer := 0; --disable arbiter checks
mprio : integer := 0; --master with highest priority
mcheck : integer range 0 to 2 := 1; --check memory map for intersect
ccheck : integer range 0 to 1 := 1; --perform sanity checks on pnp config
acdm : integer := 0 --AMBA compliant data muxing (for hsize > word)
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
msti : out ahb_mst_in_type;
msto : in ahb_mst_out_bus_vector;
slvi : out ahb_slv_in_type;
slvo : in ahb_slv_out_bus_vector;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
scanen : in std_ulogic := '0';
testoen : in std_ulogic := '1'
);
end component;
component ahbdefmst
generic ( hindex : integer range 0 to NAHBMST-1 := 0);
port ( ahbmo : out ahb_mst_out_type);
end component;
type ahb_dma_in_type is record
address : std_logic_vector(31 downto 0);
wdata : std_logic_vector(AHBDW-1 downto 0);
start : std_ulogic;
burst : std_ulogic;
write : std_ulogic;
busy : std_ulogic;
irq : std_ulogic;
size : std_logic_vector(2 downto 0);
end record;
type ahb_dma_out_type is record
start : std_ulogic;
active : std_ulogic;
ready : std_ulogic;
retry : std_ulogic;
mexc : std_ulogic;
haddr : std_logic_vector(9 downto 0);
rdata : std_logic_vector(AHBDW-1 downto 0);
end record;
component ahbmst
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := 1;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : in ahb_dma_in_type;
dmao : out ahb_dma_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end component;
-- pragma translate_off
component ahbmon is
generic(
asserterr : integer range 0 to 1 := 1;
assertwarn : integer range 0 to 1 := 1;
hmstdisable : integer := 0;
hslvdisable : integer := 0;
arbdisable : integer := 0;
nahbm : integer range 0 to NAHBMST := NAHBMST;
nahbs : integer range 0 to NAHBSLV := NAHBSLV;
ebterm : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : in ahb_mst_out_vector;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
err : out std_ulogic);
end component;
component apbmon is
generic(
asserterr : integer range 0 to 1 := 1;
assertwarn : integer range 0 to 1 := 1;
pslvdisable : integer := 0;
napb : integer range 0 to NAPBSLV := NAPBSLV
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : in apb_slv_out_vector;
err : out std_ulogic);
end component;
component ambamon is
generic(
asserterr : integer range 0 to 1 := 1;
assertwarn : integer range 0 to 1 := 1;
hmstdisable : integer := 0;
hslvdisable : integer := 0;
pslvdisable : integer := 0;
arbdisable : integer := 0;
nahbm : integer range 0 to NAHBMST := NAHBMST;
nahbs : integer range 0 to NAHBSLV := NAHBSLV;
napb : integer range 0 to NAPBSLV := NAPBSLV;
ebterm : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : in ahb_mst_out_vector;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
apbi : in apb_slv_in_type;
apbo : in apb_slv_out_vector;
err : out std_ulogic);
end component;
subtype vendor_description is string(1 to 24);
subtype device_description is string(1 to 31);
type device_table_type is array (0 to 1023) of device_description;
type vendor_library_type is record
vendorid : amba_vendor_type;
vendordesc : vendor_description;
device_table : device_table_type;
end record;
type device_array is array (0 to 255) of vendor_library_type;
-- pragma translate_on
end;
package body amba is
function ahb_device_reg(vendor : amba_vendor_type; device : amba_device_type;
cfgver : amba_cfgver_type; version : amba_version_type;
interrupt : amba_irq_type)
return std_logic_vector is
variable cfg : std_logic_vector(31 downto 0);
begin
case cfgver is
when 0 =>
cfg(31 downto 24) := std_logic_vector(to_unsigned(vendor, 8));
cfg(23 downto 12) := std_logic_vector(to_unsigned(device, 12));
cfg(11 downto 10) := std_logic_vector(to_unsigned(cfgver, 2));
cfg( 9 downto 5) := std_logic_vector(to_unsigned(version, 5));
cfg( 4 downto 0) := std_logic_vector(to_unsigned(interrupt, 5));
when others => cfg := (others => '0');
end case;
return(cfg);
end;
function ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type)
return std_logic_vector is
variable cfg : std_logic_vector(31 downto 0);
begin
cfg(31 downto 20) := std_logic_vector(to_unsigned(memaddr, 12));
cfg(19 downto 16) := "00" & prefetch & cache;
cfg(15 downto 4) := std_logic_vector(to_unsigned(addrmask, 12));
cfg( 3 downto 0) := "0010";
return(cfg);
end;
function ahb_membar_opt(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type; enable : integer)
return std_logic_vector is
variable cfg : std_logic_vector(31 downto 0);
begin
cfg := (others => '0');
if enable /= 0 then
return (ahb_membar(memaddr, prefetch, cache, addrmask));
else return(cfg); end if;
end;
function ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return std_logic_vector is
variable cfg : std_logic_vector(31 downto 0);
begin
cfg(31 downto 20) := std_logic_vector(to_unsigned(memaddr, 12));
cfg(19 downto 16) := "0000";
cfg(15 downto 4) := std_logic_vector(to_unsigned(addrmask, 12));
cfg( 3 downto 0) := "0011";
return(cfg);
end;
function apb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return std_logic_vector is
variable cfg : std_logic_vector(31 downto 0);
begin
cfg(31 downto 20) := std_logic_vector(to_unsigned(memaddr, 12));
cfg(19 downto 16) := "0000";
cfg(15 downto 4) := std_logic_vector(to_unsigned(addrmask, 12));
cfg( 3 downto 0) := "0001";
return(cfg);
end;
function ahb_slv_dec_cache(haddr : std_logic_vector(31 downto 0);
ahbso : ahb_slv_out_vector; cached : integer)
return std_ulogic is
variable hcache : std_ulogic;
variable ctbl : std_logic_vector(15 downto 0);
begin
hcache := '0'; ctbl := (others => '0');
if cached = 0 then
for i in 0 to NAHBSLV-1 loop
for j in NAHBAMR to NAHBCFG-1 loop
if (ahbso(i).hconfig(j)(16) = '1') and
(ahbso(i).hconfig(j)(15 downto 4) /= "000000000000")
then
if (haddr(31 downto 20) and ahbso(i).hconfig(j)(15 downto 4)) =
(ahbso(i).hconfig(j)(31 downto 20) and ahbso(i).hconfig(j)(15 downto 4)) then
hcache := '1';
end if;
end if;
end loop;
end loop;
else
ctbl := conv_std_logic_vector(cached, 16);
hcache := ctbl(conv_integer(haddr(31 downto 28)));
end if;
return(hcache);
end;
function ahb_slv_dec_pfetch(haddr : std_logic_vector(31 downto 0);
ahbso : ahb_slv_out_vector)
return std_ulogic is
variable pfetch : std_ulogic;
begin
pfetch := '0';
for i in 0 to NAHBSLV-1 loop
for j in NAHBAMR to NAHBCFG-1 loop
if ((ahbso(i).hconfig(j)(17) = '1') and
(ahbso(i).hconfig(j)(15 downto 4) /= "000000000000"))
then
if (haddr(31 downto 20) and ahbso(i).hconfig(j)(15 downto 4)) =
(ahbso(i).hconfig(j)(31 downto 20) and ahbso(i).hconfig(j)(15 downto 4)) then
pfetch := '1';
end if;
end if;
end loop;
end loop;
return(pfetch);
end;
function ahb_membar_size (addrmask : ahb_addr_type) return integer is
begin
if addrmask = 0 then return 0; end if;
return (4096 - addrmask) * 1024 * 1024;
end;
function ahb_iobar_size (addrmask : ahb_addr_type) return integer is
begin
return (4096 - addrmask) * 256;
end;
-- purpose: Duplicates 'hdata' to suite AHB data width. If the input vector's
-- length exceeds AHBDW the low part is returned.
function ahbdrivedata (
hdata : std_logic_vector)
return std_logic_vector is
variable data : std_logic_vector(AHBDW-1 downto 0);
begin -- ahbdrivedata
if AHBDW < hdata'length then
data := hdata(AHBDW+hdata'low-1 downto hdata'low);
else
for i in 0 to AHBDW/hdata'length-1 loop
data(hdata'length-1+hdata'length*i downto hdata'length*i) := hdata;
end loop;
end if;
return data;
end ahbdrivedata;
-- Takes in AHB data vector 'hdata' and returns valid data on the full
-- data vector output based on 'haddr' and 'hsize' inputs together with
-- GRLIB AHB bus width. The function works down to word granularity.
function ahbselectdata (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector is
variable ret : std_logic_vector(AHBDW-1 downto 0);
begin -- ahbselectdata
ret := hdata;
case hsize is
when HSIZE_8WORD =>
if AHBDW = 256 then ret := hdata; end if;
when HSIZE_4WORD =>
if AHBDW = 256 then
if haddr(4) = '0' then ret := ahbdrivedata(hdata(AHBDW-1 downto AHBDW/2));
else ret := ahbdrivedata(hdata(AHBDW/2-1 downto 0)); end if;
end if;
when HSIZE_DWORD =>
if AHBDW = 256 then
case haddr(4 downto 3) is
when "00" => ret := ahbdrivedata(hdata(4*(AHBDW/4)-1 downto 3*(AHBDW/4)));
when "01" => ret := ahbdrivedata(hdata(3*(AHBDW/4)-1 downto 2*(AHBDW/4)));
when "10" => ret := ahbdrivedata(hdata(2*(AHBDW/4)-1 downto 1*(AHBDW/4)));
when others => ret := ahbdrivedata(hdata(1*(AHBDW/4)-1 downto 0*(AHBDW/4)));
end case;
elsif AHBDW = 128 then
if haddr(3) = '0' then ret := ahbdrivedata(hdata(AHBDW-1 downto AHBDW/2));
else ret := ahbdrivedata(hdata(AHBDW/2-1 downto 0)); end if;
end if;
when others =>
if AHBDW = 256 then
case haddr(4 downto 2) is
when "000" => ret := ahbdrivedata(hdata(8*(AHBDW/8)-1 downto 7*(AHBDW/8)));
when "001" => ret := ahbdrivedata(hdata(7*(AHBDW/8)-1 downto 6*(AHBDW/8)));
when "010" => ret := ahbdrivedata(hdata(6*(AHBDW/8)-1 downto 5*(AHBDW/8)));
when "011" => ret := ahbdrivedata(hdata(5*(AHBDW/8)-1 downto 4*(AHBDW/8)));
when "100" => ret := ahbdrivedata(hdata(4*(AHBDW/8)-1 downto 3*(AHBDW/8)));
when "101" => ret := ahbdrivedata(hdata(3*(AHBDW/8)-1 downto 2*(AHBDW/8)));
when "110" => ret := ahbdrivedata(hdata(2*(AHBDW/8)-1 downto 1*(AHBDW/8)));
when others => ret := ahbdrivedata(hdata(1*(AHBDW/8)-1 downto 0*(AHBDW/8)));
end case;
elsif AHBDW = 128 then
case haddr(3 downto 2) is
when "00" => ret := ahbdrivedata(hdata(4*(AHBDW/4)-1 downto 3*(AHBDW/4)));
when "01" => ret := ahbdrivedata(hdata(3*(AHBDW/4)-1 downto 2*(AHBDW/4)));
when "10" => ret := ahbdrivedata(hdata(2*(AHBDW/4)-1 downto 1*(AHBDW/4)));
when others => ret := ahbdrivedata(hdata(1*(AHBDW/4)-1 downto 0*(AHBDW/4)));
end case;
elsif AHBDW = 64 then
if haddr(2) = '0' then ret := ahbdrivedata(hdata(AHBDW-1 downto AHBDW/2));
else ret := ahbdrivedata(hdata(AHBDW/2-1 downto 0)); end if;
end if;
end case;
return ret;
end ahbselectdata;
-- Description of ahbread* functions and procedures.
--
-- The ahbread* subprograms with an 'haddr' input selects the valid slice of
-- data from the AHB data vector, 'hdata', based on the 'haddr' input if
-- CORE_ACDM is set to 1 (see top of this package). Otherwise the low part of
-- the AHB data vector will be returned.
--
-- The ahbread* subprograms that do not have a 'haddr' input will always
-- return the low slice of the 'hdata' input. These subprograms will assert a
-- failure if CORE_ACDM is set to 1.
--
function ahbreadword (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2))
return std_logic_vector is
variable data : std_logic_vector(31 downto 0);
begin
if CORE_ACDM = 1 then data := ahbselectdata(hdata, haddr, HSIZE_WORD)(31 downto 0);
else data := hdata(31 downto 0); end if;
return data;
end ahbreadword;
procedure ahbreadword (
hdata : in std_logic_vector(AHBDW-1 downto 0);
haddr : in std_logic_vector(4 downto 2);
data : out std_logic_vector(31 downto 0)) is
begin
data := ahbreadword(hdata, haddr);
end ahbreadword;
function ahbreadword (
hdata : std_logic_vector(AHBDW-1 downto 0))
return std_logic_vector is
variable data : std_logic_vector(31 downto 0);
begin
-- pragma translate_off
assert CORE_ACDM = 0
report "ahbreadword without address input used when CORE_ACDM /= 0"
severity failure;
-- pragma translate_on
data := hdata(31 downto 0);
return data;
end ahbreadword;
procedure ahbreadword (
hdata : in std_logic_vector(AHBDW-1 downto 0);
data : out std_logic_vector(31 downto 0)) is
begin
data := ahbreadword(hdata);
end ahbreadword;
function ahbreaddword (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2))
return std_logic_vector is
variable data : std_logic_vector(255 downto 0);
begin
-- pragma translate_off
assert AHBDW > 32
report "ahbreaddword can not be used in system with AHB data width < 64"
severity failure;
-- pragma translate_on
if AHBDW = 256 then
if CORE_ACDM = 1 then
data(AHBDW/4-1 downto 0) :=
ahbselectdata(hdata, haddr, HSIZE_DWORD)(AHBDW/4-1 downto 0);
else
data(AHBDW/4-1 downto 0) := hdata(AHBDW/4-1 downto 0);
end if;
elsif AHBDW = 128 then
if CORE_ACDM = 1 then
data(AHBDW/2-1 downto 0) :=
ahbselectdata(hdata, haddr, HSIZE_DWORD)(AHBDW/2-1 downto 0);
else
data(AHBDW/2-1 downto 0) := hdata(AHBDW/2-1 downto 0);
end if;
elsif AHBDW = 64 then
if CORE_ACDM = 1 then
data(AHBDW-1 downto 0) :=
ahbselectdata(hdata, haddr, HSIZE_DWORD)(AHBDW-1 downto 0);
else
data(AHBDW-1 downto 0) := hdata(AHBDW-1 downto 0);
end if;
end if;
return data(63 downto 0);
end ahbreaddword;
procedure ahbreaddword (
hdata : in std_logic_vector(AHBDW-1 downto 0);
haddr : in std_logic_vector(4 downto 2);
data : out std_logic_vector(63 downto 0)) is
begin
data := ahbreaddword(hdata, haddr);
end ahbreaddword;
function ahbreaddword (
hdata : std_logic_vector(AHBDW-1 downto 0))
return std_logic_vector is
variable data : std_logic_vector(255 downto 0);
begin
-- pragma translate_off
assert AHBDW > 32
report "ahbreaddword can not be used in system with AHB data width < 64"
severity failure;
assert CORE_ACDM = 0
report "ahbreaddword without address input used when CORE_ACDM /= 0"
severity failure;
-- pragma translate_on
if AHBDW = 256 then
data(AHBDW/4-1 downto 0) := hdata(AHBDW/4-1 downto 0);
elsif AHBDW = 128 then
data(AHBDW/2-1 downto 0) := hdata(AHBDW/2-1 downto 0);
elsif AHBDW = 64 then
data(AHBDW-1 downto 0) := hdata(AHBDW-1 downto 0);
end if;
return data(63 downto 0);
end ahbreaddword;
procedure ahbreaddword (
hdata : in std_logic_vector(AHBDW-1 downto 0);
data : out std_logic_vector(63 downto 0)) is
begin
data := ahbreaddword(hdata);
end ahbreaddword;
function ahbread4word (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2))
return std_logic_vector is
variable data : std_logic_vector(255 downto 0);
begin
-- pragma translate_off
assert AHBDW > 64
report "ahbread4word can not be used in system with AHB data width < 128 bits"
severity failure;
-- pragma translate_on
if AHBDW = 256 then
if CORE_ACDM = 1 then
data(AHBDW/2-1 downto 0) :=
ahbselectdata(hdata, haddr, HSIZE_4WORD)(AHBDW/2-1 downto 0);
else
data(AHBDW/2-1 downto 0) := hdata(AHBDW/2-1 downto 0);
end if;
elsif AHBDW = 128 then
if CORE_ACDM = 1 then
data(AHBDW-1 downto 0) :=
ahbselectdata(hdata, haddr, HSIZE_4WORD)(AHBDW-1 downto 0);
else
data(AHBDW-1 downto 0) := hdata(AHBDW-1 downto 0);
end if;
end if;
return data(127 downto 0);
end ahbread4word;
procedure ahbread4word (
hdata : in std_logic_vector(AHBDW-1 downto 0);
haddr : in std_logic_vector(4 downto 2);
data : out std_logic_vector(127 downto 0)) is
begin
data := ahbread4word(hdata, haddr);
end ahbread4word;
function ahbread4word (
hdata : std_logic_vector(AHBDW-1 downto 0))
return std_logic_vector is
variable data : std_logic_vector(255 downto 0);
begin
-- pragma translate_off
assert AHBDW > 64
report "ahbread4word can not be used in system with AHB data width < 128 bits"
severity failure;
assert CORE_ACDM = 0
report "ahbread4word without address input used when CORE_ACDM /= 0"
severity failure;
-- pragma translate_on
if AHBDW = 256 then
data(AHBDW/2-1 downto 0) := hdata(AHBDW/2-1 downto 0);
elsif AHBDW = 128 then
data(AHBDW-1 downto 0) := hdata(AHBDW-1 downto 0);
end if;
return data(127 downto 0);
end ahbread4word;
procedure ahbread4word (
hdata : in std_logic_vector(AHBDW-1 downto 0);
data : out std_logic_vector(127 downto 0)) is
begin
data := ahbread4word(hdata);
end ahbread4word;
function ahbread8word (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2))
return std_logic_vector is
variable data : std_logic_vector(AHBDW-1 downto 0);
begin
-- pragma translate_off
assert AHBDW > 128
report "ahbread8word can not be used in system with AHB data width < 256 bits"
severity failure;
-- pragma translate_on
if CORE_ACDM = 1 then
data(AHBDW-1 downto 0) := ahbselectdata(hdata, haddr, HSIZE_8WORD)(AHBDW-1 downto 0);
else
data(AHBDW-1 downto 0) := hdata(AHBDW-1 downto 0);
end if;
return data;
end ahbread8word;
procedure ahbread8word (
hdata : in std_logic_vector(AHBDW-1 downto 0);
haddr : in std_logic_vector(4 downto 2);
data : out std_logic_vector(255 downto 0)) is
begin
data := ahbread8word(hdata, haddr);
end ahbread8word;
function ahbread8word (
hdata : std_logic_vector(AHBDW-1 downto 0))
return std_logic_vector is
variable data : std_logic_vector(AHBDW-1 downto 0);
begin
-- pragma translate_off
assert AHBDW > 128
report "ahbread8word can not be used in system with AHB data width < 256 bits"
severity failure;
assert CORE_ACDM = 0
report "ahbread8word without address input used when CORE_ACDM /= 0"
severity failure;
-- pragma translate_on
data(AHBDW-1 downto 0) := hdata(AHBDW-1 downto 0);
return data;
end ahbread8word;
procedure ahbread8word (
hdata : in std_logic_vector(AHBDW-1 downto 0);
data : out std_logic_vector(255 downto 0)) is
begin
data := ahbread8word(hdata);
end ahbread8word;
function ahbreaddata (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector is
begin
case hsize is
when HSIZE_8WORD =>
return ahbread8word(hdata, haddr);
when HSIZE_4WORD =>
return ahbread4word(hdata, haddr);
when HSIZE_DWORD =>
return ahbreaddword(hdata, haddr);
when others => null;
end case;
return ahbreadword(hdata, haddr);
end ahbreaddata;
function ahbreaddata (
hdata : std_logic_vector(AHBDW-1 downto 0);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector is
begin
case hsize is
when HSIZE_8WORD =>
return ahbread8word(hdata);
when HSIZE_4WORD =>
return ahbread4word(hdata);
when HSIZE_DWORD =>
return ahbreaddword(hdata);
when others => null;
end case;
return ahbreadword(hdata);
end ahbreaddata;
-- a*mux below drives their amba output records with the amba input record if
-- the en input is '1'. Otherwise the amba output record is driven to an idle
-- state. Plug'n'play information is kept constant.
procedure ahbmomux (
signal ai : in ahb_mst_out_type;
signal ao : out ahb_mst_out_type;
signal en : in std_ulogic) is
begin
if en = '1' then ao <= ai;
else ao <= ahbm_none; end if;
ao.haddr <= ai.haddr;
ao.hwrite <= ai.hwrite;
ao.hsize <= ai.hsize;
ao.hprot <= ai.hprot;
ao.hwdata <= ai.hwdata;
ao.hconfig <= ai.hconfig;
ao.hindex <= ai.hindex;
end ahbmomux;
procedure ahbsomux (
signal ai : in ahb_slv_out_type;
signal ao : out ahb_slv_out_type;
signal en : in std_ulogic) is
begin
if en = '1' then ao <= ai;
else ao <= ahbs_none; end if;
ao.hrdata <= ai.hrdata;
ao.hconfig <= ai.hconfig;
ao.hindex <= ai.hindex;
end ahbsomux;
procedure apbsomux (
signal ai : in apb_slv_out_type;
signal ao : out apb_slv_out_type;
signal en : in std_ulogic) is
begin
if en = '1' then ao <= ai;
else ao <= apb_none; end if;
ao.prdata <= ai.prdata;
ao.pconfig <= ai.pconfig;
ao.pindex <= ai.pindex;
end apbsomux;
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:08:24 06/29/2014
-- Design Name:
-- Module Name: reg_32 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity reg_32 is
port (
clk : in std_logic;
reset : in std_logic;
D : in std_logic_vector(128 downto 0);
Q : out std_logic_vector(128 downto 0)
);
end reg_32;
architecture Behavioral of reg_32 is
begin
REG: process(clk, reset)
begin
if reset = '1' then
Q <= (others => '0');
elsif rising_edge(clk) then
Q <= D;
end if;
end process REG;
end Behavioral;
|
-- NEED RESULT: ARCH00566: Attribute declarations - scalar static subtypes with static initial values passed
-- NEED RESULT: ARCH00566: Attribute declarations - scalar static subtypes with generic initial values passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00566
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.4 (3)
-- 4.4 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00566(ARCH00566)
-- ENT00566_Test_Bench(ARCH00566_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
--
entity ENT00566 is
generic (
i_boolean_1, i_boolean_2 : boolean
:= c_boolean_1 ;
i_bit_1, i_bit_2 : bit
:= c_bit_1 ;
i_severity_level_1, i_severity_level_2 : severity_level
:= c_severity_level_1 ;
i_character_1, i_character_2 : character
:= c_character_1 ;
i_t_enum1_1, i_t_enum1_2 : t_enum1
:= c_t_enum1_1 ;
i_st_enum1_1, i_st_enum1_2 : st_enum1
:= c_st_enum1_1 ;
i_integer_1, i_integer_2 : integer
:= c_integer_1 ;
i_t_int1_1, i_t_int1_2 : t_int1
:= c_t_int1_1 ;
i_st_int1_1, i_st_int1_2 : st_int1
:= c_st_int1_1 ;
i_time_1, i_time_2 : time
:= c_time_1 ;
i_t_phys1_1, i_t_phys1_2 : t_phys1
:= c_t_phys1_1 ;
i_st_phys1_1, i_st_phys1_2 : st_phys1
:= c_st_phys1_1 ;
i_real_1, i_real_2 : real
:= c_real_1 ;
i_t_real1_1, i_t_real1_2 : t_real1
:= c_t_real1_1 ;
i_st_real1_1, i_st_real1_2 : st_real1
:= c_st_real1_1
) ;
attribute at_boolean_1 : boolean ;
attribute at_bit_1 : bit ;
attribute at_severity_level_1 : severity_level ;
attribute at_character_1 : character ;
attribute at_t_enum1_1 : t_enum1 ;
attribute at_st_enum1_1 : st_enum1 ;
attribute at_integer_1 : integer ;
attribute at_t_int1_1 : t_int1 ;
attribute at_st_int1_1 : st_int1 ;
attribute at_time_1 : time ;
attribute at_t_phys1_1 : t_phys1 ;
attribute at_st_phys1_1 : st_phys1 ;
attribute at_real_1 : real ;
attribute at_t_real1_1 : t_real1 ;
attribute at_st_real1_1 : st_real1 ;
end ENT00566 ;
architecture ARCH00566 of ENT00566 is
begin
process
variable correct : boolean := true ;
procedure p1 ;
attribute at_boolean_1 of p1 : procedure is
c_boolean_1 ;
attribute at_bit_1 of p1 : procedure is
c_bit_1 ;
attribute at_severity_level_1 of p1 : procedure is
c_severity_level_1 ;
attribute at_character_1 of p1 : procedure is
c_character_1 ;
attribute at_t_enum1_1 of p1 : procedure is
c_t_enum1_1 ;
attribute at_st_enum1_1 of p1 : procedure is
c_st_enum1_1 ;
attribute at_integer_1 of p1 : procedure is
c_integer_1 ;
attribute at_t_int1_1 of p1 : procedure is
c_t_int1_1 ;
attribute at_st_int1_1 of p1 : procedure is
c_st_int1_1 ;
attribute at_time_1 of p1 : procedure is
c_time_1 ;
attribute at_t_phys1_1 of p1 : procedure is
c_t_phys1_1 ;
attribute at_st_phys1_1 of p1 : procedure is
c_st_phys1_1 ;
attribute at_real_1 of p1 : procedure is
c_real_1 ;
attribute at_t_real1_1 of p1 : procedure is
c_t_real1_1 ;
attribute at_st_real1_1 of p1 : procedure is
c_st_real1_1 ;
procedure p1 is
begin
correct := correct and p1'at_boolean_1
= c_boolean_1 ;
correct := correct and p1'at_bit_1
= c_bit_1 ;
correct := correct and p1'at_severity_level_1
= c_severity_level_1 ;
correct := correct and p1'at_character_1
= c_character_1 ;
correct := correct and p1'at_t_enum1_1
= c_t_enum1_1 ;
correct := correct and p1'at_st_enum1_1
= c_st_enum1_1 ;
correct := correct and p1'at_integer_1
= c_integer_1 ;
correct := correct and p1'at_t_int1_1
= c_t_int1_1 ;
correct := correct and p1'at_st_int1_1
= c_st_int1_1 ;
correct := correct and p1'at_time_1
= c_time_1 ;
correct := correct and p1'at_t_phys1_1
= c_t_phys1_1 ;
correct := correct and p1'at_st_phys1_1
= c_st_phys1_1 ;
correct := correct and p1'at_real_1
= c_real_1 ;
correct := correct and p1'at_t_real1_1
= c_t_real1_1 ;
correct := correct and p1'at_st_real1_1
= c_st_real1_1 ;
test_report ( "ARCH00566" ,
"Attribute declarations - scalar static subtypes"
& " with static initial values" ,
correct) ;
end p1 ;
begin
p1 ;
wait ;
end process ;
process
variable correct : boolean := true ;
procedure p1 ;
attribute at_boolean_1 of p1 : procedure is
i_boolean_1 ;
attribute at_bit_1 of p1 : procedure is
i_bit_1 ;
attribute at_severity_level_1 of p1 : procedure is
i_severity_level_1 ;
attribute at_character_1 of p1 : procedure is
i_character_1 ;
attribute at_t_enum1_1 of p1 : procedure is
i_t_enum1_1 ;
attribute at_st_enum1_1 of p1 : procedure is
i_st_enum1_1 ;
attribute at_integer_1 of p1 : procedure is
i_integer_1 ;
attribute at_t_int1_1 of p1 : procedure is
i_t_int1_1 ;
attribute at_st_int1_1 of p1 : procedure is
i_st_int1_1 ;
attribute at_time_1 of p1 : procedure is
i_time_1 ;
attribute at_t_phys1_1 of p1 : procedure is
i_t_phys1_1 ;
attribute at_st_phys1_1 of p1 : procedure is
i_st_phys1_1 ;
attribute at_real_1 of p1 : procedure is
i_real_1 ;
attribute at_t_real1_1 of p1 : procedure is
i_t_real1_1 ;
attribute at_st_real1_1 of p1 : procedure is
i_st_real1_1 ;
procedure p1 is
begin
correct := correct and p1'at_boolean_1
= c_boolean_1 ;
correct := correct and p1'at_bit_1
= c_bit_1 ;
correct := correct and p1'at_severity_level_1
= c_severity_level_1 ;
correct := correct and p1'at_character_1
= c_character_1 ;
correct := correct and p1'at_t_enum1_1
= c_t_enum1_1 ;
correct := correct and p1'at_st_enum1_1
= c_st_enum1_1 ;
correct := correct and p1'at_integer_1
= c_integer_1 ;
correct := correct and p1'at_t_int1_1
= c_t_int1_1 ;
correct := correct and p1'at_st_int1_1
= c_st_int1_1 ;
correct := correct and p1'at_time_1
= c_time_1 ;
correct := correct and p1'at_t_phys1_1
= c_t_phys1_1 ;
correct := correct and p1'at_st_phys1_1
= c_st_phys1_1 ;
correct := correct and p1'at_real_1
= c_real_1 ;
correct := correct and p1'at_t_real1_1
= c_t_real1_1 ;
correct := correct and p1'at_st_real1_1
= c_st_real1_1 ;
test_report ( "ARCH00566" ,
"Attribute declarations - scalar static subtypes"
& " with generic initial values" ,
correct) ;
end p1 ;
begin
p1 ;
wait ;
end process ;
end ARCH00566 ;
--
entity ENT00566_Test_Bench is
end ENT00566_Test_Bench ;
--
architecture ARCH00566_Test_Bench of ENT00566_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00566 ( ARCH00566 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00566_Test_Bench ;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
package hash_array_pkg is
type hash_array is array(integer range <>) of unsigned(127 downto 0);
type md5_indata_t is
record
data_0 : unsigned(31 downto 0);
data_1 : unsigned(31 downto 0);
start : std_logic;
len : std_logic_vector(7 downto 0);
end record;
type md5_indata_t_array is array(integer range <>) of md5_indata_t;
end hash_array_pkg; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
package hash_array_pkg is
type hash_array is array(integer range <>) of unsigned(127 downto 0);
type md5_indata_t is
record
data_0 : unsigned(31 downto 0);
data_1 : unsigned(31 downto 0);
start : std_logic;
len : std_logic_vector(7 downto 0);
end record;
type md5_indata_t_array is array(integer range <>) of md5_indata_t;
end hash_array_pkg; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
package hash_array_pkg is
type hash_array is array(integer range <>) of unsigned(127 downto 0);
type md5_indata_t is
record
data_0 : unsigned(31 downto 0);
data_1 : unsigned(31 downto 0);
start : std_logic;
len : std_logic_vector(7 downto 0);
end record;
type md5_indata_t_array is array(integer range <>) of md5_indata_t;
end hash_array_pkg; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:20:17 11/21/2016
-- Design Name:
-- Module Name: m8bitRegister - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity m8bitRegister is
Port ( I : in STD_LOGIC_VECTOR (7 downto 0);
O : out STD_LOGIC_VECTOR (7 downto 0);
clr : in STD_LOGIC;
load_en : in STD_LOGIC;
clk : in STD_LOGIC);
end m8bitRegister;
architecture Behavioral of m8bitRegister is
--declared signal
signal S: std_logic_vector(7 downto 0):="00000000";
begin
main: process(clk,clr,I,load_en)
begin
-- this is to make the events synchronous
if clk'event and clk='1' then
if clr='1' then
S:= "00000000";
O <= S;
else
if load_en = '1' then
S:=I;
else
O <= S;
end if ;
end if;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity wb_rom_ram is
generic (
maxbit: integer := maxAddrBit
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
ram_wb_stall_o: out std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0);
rom_wb_stb_i: in std_logic;
rom_wb_stall_o: out std_logic
);
end entity wb_rom_ram;
architecture behave of wb_rom_ram is
component dualport_ram is
generic (
maxbit: integer
);
port (
clk: in std_logic;
memAWriteEnable: in std_logic;
memAWriteMask: in std_logic_vector(3 downto 0);
memAAddr: in std_logic_vector(maxbit downto 2);
memAWrite: in std_logic_vector(31 downto 0);
memARead: out std_logic_vector(31 downto 0);
memAEnable: in std_logic;
memBWriteEnable: in std_logic;
memBWriteMask: in std_logic_vector(3 downto 0);
memBAddr: in std_logic_vector(maxbit downto 2);
memBWrite: in std_logic_vector(31 downto 0);
memBRead: out std_logic_vector(31 downto 0);
memBEnable: in std_logic;
memErr: out std_logic
);
end component dualport_ram;
constant i_maxAddrBit: integer := maxbit; -- maxAddrBit
signal memAWriteEnable: std_logic;
signal memAWriteMask: std_logic_vector(3 downto 0);
signal memAAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memAWrite: std_logic_vector(31 downto 0);
signal memARead: std_logic_vector(31 downto 0);
signal memAEnable: std_logic;
signal memBWriteEnable: std_logic;
signal memBWriteMask: std_logic_vector(3 downto 0);
signal memBAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memBWrite: std_logic_vector(31 downto 0);
signal memBRead: std_logic_vector(31 downto 0);
signal memBEnable: std_logic;
--signal rom_burst: std_logic;
signal rom_do_wait: std_logic;
type ramregs_type is record
do_wait: std_logic;
end record;
signal ramregs: ramregs_type;
signal rom_ack: std_logic;
begin
rom_wb_ack_o <= rom_ack;
rom_wb_stall_o <= '0';-- when rom_wb_cyc_i='0' else not rom_ack;
ram_wb_stall_o <= '0';
-- System ROM/RAM
ramrom: dualport_ram
generic map (
maxbit => maxbit --13--maxAddrBit
)
port map (
clk => ram_wb_clk_i,
memAWriteEnable => memAWriteEnable,
memAWriteMask => memAWriteMask,
memAAddr => memAAddr,
memAWrite => memAWrite,
memARead => memARead,
memAEnable => memAEnable,
memBWriteEnable => memBWriteEnable,
memBWriteMask => memBWriteMask,
memBAddr => memBAddr,
memBWrite => memBWrite,
memBRead => memBRead,
memBEnable => memBEnable
);
memBWrite <= (others => DontCareValue);
memBWriteMask <= (others => DontCareValue);
memBWriteEnable <= '0';
rom_wb_dat_o <= memBRead;
memBAddr <= rom_wb_adr_i(i_maxAddrBit downto 2);
memBEnable <= rom_wb_cyc_i and rom_wb_stb_i;
-- ROM ack
process(rom_wb_clk_i)
begin
if rising_edge(rom_wb_clk_i) then
if rom_wb_rst_i='1' then
rom_ack <= '0';
--rom_burst <= '0';
rom_do_wait<='0';
else
if rom_do_wait='1' then
if true then--rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
rom_ack<='0';
rom_do_wait<='0';
end if;
else
if rom_wb_cyc_i='1' and rom_wb_stb_i='1' then
if true then --rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
--rom_burst<='0';
rom_do_wait<='1';
rom_ack<='1';
end if;
elsif rom_wb_cyc_i='0' then
rom_ack<='0';
end if;
end if;
end if;
end if;
end process;
-- RAM
memAWrite <= ram_wb_dat_i;
memAWriteMask <= (others => '1');
ram_wb_dat_o <= memARead;
memAAddr <= ram_wb_adr_i(i_maxAddrBit downto 2);
memAEnable <= ram_wb_cyc_i and ram_wb_stb_i;
-- RAM ack
process(ram_wb_clk_i, ramregs, ram_wb_rst_i,
ram_wb_stb_i, ram_wb_cyc_i, ram_wb_we_i)
variable w: ramregs_type;
begin
w:=ramregs;
--ram_wb_ack_o<='0';
--memAWriteEnable <= '0';
ram_wb_ack_o<='0';
memAWriteEnable <= '0';
if ramregs.do_wait='1' then
w.do_wait:='0';
ram_wb_ack_o<='1';
if ram_wb_we_i='1' then
memAWriteEnable <= '1';
end if;
else
if ram_wb_stb_i='1' and ram_wb_cyc_i='1' then
-- if ram_wb_we_i='1' then
-- memAWriteEnable <= '1';
-- ram_wb_ack_o<='1';
-- else
w.do_wait:='1';
-- end if;
end if;
end if;
if ram_wb_rst_i='1' then
w.do_wait:='0';
end if;
if rising_edge(ram_wb_clk_i) then
ramregs<=w;
end if;
end process;
--ram_wb_ack_o <= '1' when ram_wb_cyc_i='1' and ram_wb_stb_i='1' and ram_wb_we_i='1' else ram_wb_ack_o_i;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity wb_rom_ram is
generic (
maxbit: integer := maxAddrBit
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
ram_wb_stall_o: out std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0);
rom_wb_stb_i: in std_logic;
rom_wb_stall_o: out std_logic
);
end entity wb_rom_ram;
architecture behave of wb_rom_ram is
component dualport_ram is
generic (
maxbit: integer
);
port (
clk: in std_logic;
memAWriteEnable: in std_logic;
memAWriteMask: in std_logic_vector(3 downto 0);
memAAddr: in std_logic_vector(maxbit downto 2);
memAWrite: in std_logic_vector(31 downto 0);
memARead: out std_logic_vector(31 downto 0);
memAEnable: in std_logic;
memBWriteEnable: in std_logic;
memBWriteMask: in std_logic_vector(3 downto 0);
memBAddr: in std_logic_vector(maxbit downto 2);
memBWrite: in std_logic_vector(31 downto 0);
memBRead: out std_logic_vector(31 downto 0);
memBEnable: in std_logic;
memErr: out std_logic
);
end component dualport_ram;
constant i_maxAddrBit: integer := maxbit; -- maxAddrBit
signal memAWriteEnable: std_logic;
signal memAWriteMask: std_logic_vector(3 downto 0);
signal memAAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memAWrite: std_logic_vector(31 downto 0);
signal memARead: std_logic_vector(31 downto 0);
signal memAEnable: std_logic;
signal memBWriteEnable: std_logic;
signal memBWriteMask: std_logic_vector(3 downto 0);
signal memBAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memBWrite: std_logic_vector(31 downto 0);
signal memBRead: std_logic_vector(31 downto 0);
signal memBEnable: std_logic;
--signal rom_burst: std_logic;
signal rom_do_wait: std_logic;
type ramregs_type is record
do_wait: std_logic;
end record;
signal ramregs: ramregs_type;
signal rom_ack: std_logic;
begin
rom_wb_ack_o <= rom_ack;
rom_wb_stall_o <= '0';-- when rom_wb_cyc_i='0' else not rom_ack;
ram_wb_stall_o <= '0';
-- System ROM/RAM
ramrom: dualport_ram
generic map (
maxbit => maxbit --13--maxAddrBit
)
port map (
clk => ram_wb_clk_i,
memAWriteEnable => memAWriteEnable,
memAWriteMask => memAWriteMask,
memAAddr => memAAddr,
memAWrite => memAWrite,
memARead => memARead,
memAEnable => memAEnable,
memBWriteEnable => memBWriteEnable,
memBWriteMask => memBWriteMask,
memBAddr => memBAddr,
memBWrite => memBWrite,
memBRead => memBRead,
memBEnable => memBEnable
);
memBWrite <= (others => DontCareValue);
memBWriteMask <= (others => DontCareValue);
memBWriteEnable <= '0';
rom_wb_dat_o <= memBRead;
memBAddr <= rom_wb_adr_i(i_maxAddrBit downto 2);
memBEnable <= rom_wb_cyc_i and rom_wb_stb_i;
-- ROM ack
process(rom_wb_clk_i)
begin
if rising_edge(rom_wb_clk_i) then
if rom_wb_rst_i='1' then
rom_ack <= '0';
--rom_burst <= '0';
rom_do_wait<='0';
else
if rom_do_wait='1' then
if true then--rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
rom_ack<='0';
rom_do_wait<='0';
end if;
else
if rom_wb_cyc_i='1' and rom_wb_stb_i='1' then
if true then --rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
--rom_burst<='0';
rom_do_wait<='1';
rom_ack<='1';
end if;
elsif rom_wb_cyc_i='0' then
rom_ack<='0';
end if;
end if;
end if;
end if;
end process;
-- RAM
memAWrite <= ram_wb_dat_i;
memAWriteMask <= (others => '1');
ram_wb_dat_o <= memARead;
memAAddr <= ram_wb_adr_i(i_maxAddrBit downto 2);
memAEnable <= ram_wb_cyc_i and ram_wb_stb_i;
-- RAM ack
process(ram_wb_clk_i, ramregs, ram_wb_rst_i,
ram_wb_stb_i, ram_wb_cyc_i, ram_wb_we_i)
variable w: ramregs_type;
begin
w:=ramregs;
--ram_wb_ack_o<='0';
--memAWriteEnable <= '0';
ram_wb_ack_o<='0';
memAWriteEnable <= '0';
if ramregs.do_wait='1' then
w.do_wait:='0';
ram_wb_ack_o<='1';
if ram_wb_we_i='1' then
memAWriteEnable <= '1';
end if;
else
if ram_wb_stb_i='1' and ram_wb_cyc_i='1' then
-- if ram_wb_we_i='1' then
-- memAWriteEnable <= '1';
-- ram_wb_ack_o<='1';
-- else
w.do_wait:='1';
-- end if;
end if;
end if;
if ram_wb_rst_i='1' then
w.do_wait:='0';
end if;
if rising_edge(ram_wb_clk_i) then
ramregs<=w;
end if;
end process;
--ram_wb_ack_o <= '1' when ram_wb_cyc_i='1' and ram_wb_stb_i='1' and ram_wb_we_i='1' else ram_wb_ack_o_i;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity wb_rom_ram is
generic (
maxbit: integer := maxAddrBit
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
ram_wb_stall_o: out std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0);
rom_wb_stb_i: in std_logic;
rom_wb_stall_o: out std_logic
);
end entity wb_rom_ram;
architecture behave of wb_rom_ram is
component dualport_ram is
generic (
maxbit: integer
);
port (
clk: in std_logic;
memAWriteEnable: in std_logic;
memAWriteMask: in std_logic_vector(3 downto 0);
memAAddr: in std_logic_vector(maxbit downto 2);
memAWrite: in std_logic_vector(31 downto 0);
memARead: out std_logic_vector(31 downto 0);
memAEnable: in std_logic;
memBWriteEnable: in std_logic;
memBWriteMask: in std_logic_vector(3 downto 0);
memBAddr: in std_logic_vector(maxbit downto 2);
memBWrite: in std_logic_vector(31 downto 0);
memBRead: out std_logic_vector(31 downto 0);
memBEnable: in std_logic;
memErr: out std_logic
);
end component dualport_ram;
constant i_maxAddrBit: integer := maxbit; -- maxAddrBit
signal memAWriteEnable: std_logic;
signal memAWriteMask: std_logic_vector(3 downto 0);
signal memAAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memAWrite: std_logic_vector(31 downto 0);
signal memARead: std_logic_vector(31 downto 0);
signal memAEnable: std_logic;
signal memBWriteEnable: std_logic;
signal memBWriteMask: std_logic_vector(3 downto 0);
signal memBAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memBWrite: std_logic_vector(31 downto 0);
signal memBRead: std_logic_vector(31 downto 0);
signal memBEnable: std_logic;
--signal rom_burst: std_logic;
signal rom_do_wait: std_logic;
type ramregs_type is record
do_wait: std_logic;
end record;
signal ramregs: ramregs_type;
signal rom_ack: std_logic;
begin
rom_wb_ack_o <= rom_ack;
rom_wb_stall_o <= '0';-- when rom_wb_cyc_i='0' else not rom_ack;
ram_wb_stall_o <= '0';
-- System ROM/RAM
ramrom: dualport_ram
generic map (
maxbit => maxbit --13--maxAddrBit
)
port map (
clk => ram_wb_clk_i,
memAWriteEnable => memAWriteEnable,
memAWriteMask => memAWriteMask,
memAAddr => memAAddr,
memAWrite => memAWrite,
memARead => memARead,
memAEnable => memAEnable,
memBWriteEnable => memBWriteEnable,
memBWriteMask => memBWriteMask,
memBAddr => memBAddr,
memBWrite => memBWrite,
memBRead => memBRead,
memBEnable => memBEnable
);
memBWrite <= (others => DontCareValue);
memBWriteMask <= (others => DontCareValue);
memBWriteEnable <= '0';
rom_wb_dat_o <= memBRead;
memBAddr <= rom_wb_adr_i(i_maxAddrBit downto 2);
memBEnable <= rom_wb_cyc_i and rom_wb_stb_i;
-- ROM ack
process(rom_wb_clk_i)
begin
if rising_edge(rom_wb_clk_i) then
if rom_wb_rst_i='1' then
rom_ack <= '0';
--rom_burst <= '0';
rom_do_wait<='0';
else
if rom_do_wait='1' then
if true then--rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
rom_ack<='0';
rom_do_wait<='0';
end if;
else
if rom_wb_cyc_i='1' and rom_wb_stb_i='1' then
if true then --rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
--rom_burst<='0';
rom_do_wait<='1';
rom_ack<='1';
end if;
elsif rom_wb_cyc_i='0' then
rom_ack<='0';
end if;
end if;
end if;
end if;
end process;
-- RAM
memAWrite <= ram_wb_dat_i;
memAWriteMask <= (others => '1');
ram_wb_dat_o <= memARead;
memAAddr <= ram_wb_adr_i(i_maxAddrBit downto 2);
memAEnable <= ram_wb_cyc_i and ram_wb_stb_i;
-- RAM ack
process(ram_wb_clk_i, ramregs, ram_wb_rst_i,
ram_wb_stb_i, ram_wb_cyc_i, ram_wb_we_i)
variable w: ramregs_type;
begin
w:=ramregs;
--ram_wb_ack_o<='0';
--memAWriteEnable <= '0';
ram_wb_ack_o<='0';
memAWriteEnable <= '0';
if ramregs.do_wait='1' then
w.do_wait:='0';
ram_wb_ack_o<='1';
if ram_wb_we_i='1' then
memAWriteEnable <= '1';
end if;
else
if ram_wb_stb_i='1' and ram_wb_cyc_i='1' then
-- if ram_wb_we_i='1' then
-- memAWriteEnable <= '1';
-- ram_wb_ack_o<='1';
-- else
w.do_wait:='1';
-- end if;
end if;
end if;
if ram_wb_rst_i='1' then
w.do_wait:='0';
end if;
if rising_edge(ram_wb_clk_i) then
ramregs<=w;
end if;
end process;
--ram_wb_ack_o <= '1' when ram_wb_cyc_i='1' and ram_wb_stb_i='1' and ram_wb_we_i='1' else ram_wb_ack_o_i;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity wb_rom_ram is
generic (
maxbit: integer := maxAddrBit
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
ram_wb_stall_o: out std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0);
rom_wb_stb_i: in std_logic;
rom_wb_stall_o: out std_logic
);
end entity wb_rom_ram;
architecture behave of wb_rom_ram is
component dualport_ram is
generic (
maxbit: integer
);
port (
clk: in std_logic;
memAWriteEnable: in std_logic;
memAWriteMask: in std_logic_vector(3 downto 0);
memAAddr: in std_logic_vector(maxbit downto 2);
memAWrite: in std_logic_vector(31 downto 0);
memARead: out std_logic_vector(31 downto 0);
memAEnable: in std_logic;
memBWriteEnable: in std_logic;
memBWriteMask: in std_logic_vector(3 downto 0);
memBAddr: in std_logic_vector(maxbit downto 2);
memBWrite: in std_logic_vector(31 downto 0);
memBRead: out std_logic_vector(31 downto 0);
memBEnable: in std_logic;
memErr: out std_logic
);
end component dualport_ram;
constant i_maxAddrBit: integer := maxbit; -- maxAddrBit
signal memAWriteEnable: std_logic;
signal memAWriteMask: std_logic_vector(3 downto 0);
signal memAAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memAWrite: std_logic_vector(31 downto 0);
signal memARead: std_logic_vector(31 downto 0);
signal memAEnable: std_logic;
signal memBWriteEnable: std_logic;
signal memBWriteMask: std_logic_vector(3 downto 0);
signal memBAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memBWrite: std_logic_vector(31 downto 0);
signal memBRead: std_logic_vector(31 downto 0);
signal memBEnable: std_logic;
--signal rom_burst: std_logic;
signal rom_do_wait: std_logic;
type ramregs_type is record
do_wait: std_logic;
end record;
signal ramregs: ramregs_type;
signal rom_ack: std_logic;
begin
rom_wb_ack_o <= rom_ack;
rom_wb_stall_o <= '0';-- when rom_wb_cyc_i='0' else not rom_ack;
ram_wb_stall_o <= '0';
-- System ROM/RAM
ramrom: dualport_ram
generic map (
maxbit => maxbit --13--maxAddrBit
)
port map (
clk => ram_wb_clk_i,
memAWriteEnable => memAWriteEnable,
memAWriteMask => memAWriteMask,
memAAddr => memAAddr,
memAWrite => memAWrite,
memARead => memARead,
memAEnable => memAEnable,
memBWriteEnable => memBWriteEnable,
memBWriteMask => memBWriteMask,
memBAddr => memBAddr,
memBWrite => memBWrite,
memBRead => memBRead,
memBEnable => memBEnable
);
memBWrite <= (others => DontCareValue);
memBWriteMask <= (others => DontCareValue);
memBWriteEnable <= '0';
rom_wb_dat_o <= memBRead;
memBAddr <= rom_wb_adr_i(i_maxAddrBit downto 2);
memBEnable <= rom_wb_cyc_i and rom_wb_stb_i;
-- ROM ack
process(rom_wb_clk_i)
begin
if rising_edge(rom_wb_clk_i) then
if rom_wb_rst_i='1' then
rom_ack <= '0';
--rom_burst <= '0';
rom_do_wait<='0';
else
if rom_do_wait='1' then
if true then--rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
rom_ack<='0';
rom_do_wait<='0';
end if;
else
if rom_wb_cyc_i='1' and rom_wb_stb_i='1' then
if true then --rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
--rom_burst<='0';
rom_do_wait<='1';
rom_ack<='1';
end if;
elsif rom_wb_cyc_i='0' then
rom_ack<='0';
end if;
end if;
end if;
end if;
end process;
-- RAM
memAWrite <= ram_wb_dat_i;
memAWriteMask <= (others => '1');
ram_wb_dat_o <= memARead;
memAAddr <= ram_wb_adr_i(i_maxAddrBit downto 2);
memAEnable <= ram_wb_cyc_i and ram_wb_stb_i;
-- RAM ack
process(ram_wb_clk_i, ramregs, ram_wb_rst_i,
ram_wb_stb_i, ram_wb_cyc_i, ram_wb_we_i)
variable w: ramregs_type;
begin
w:=ramregs;
--ram_wb_ack_o<='0';
--memAWriteEnable <= '0';
ram_wb_ack_o<='0';
memAWriteEnable <= '0';
if ramregs.do_wait='1' then
w.do_wait:='0';
ram_wb_ack_o<='1';
if ram_wb_we_i='1' then
memAWriteEnable <= '1';
end if;
else
if ram_wb_stb_i='1' and ram_wb_cyc_i='1' then
-- if ram_wb_we_i='1' then
-- memAWriteEnable <= '1';
-- ram_wb_ack_o<='1';
-- else
w.do_wait:='1';
-- end if;
end if;
end if;
if ram_wb_rst_i='1' then
w.do_wait:='0';
end if;
if rising_edge(ram_wb_clk_i) then
ramregs<=w;
end if;
end process;
--ram_wb_ack_o <= '1' when ram_wb_cyc_i='1' and ram_wb_stb_i='1' and ram_wb_we_i='1' else ram_wb_ack_o_i;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity wb_rom_ram is
generic (
maxbit: integer := maxAddrBit
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
ram_wb_stall_o: out std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0);
rom_wb_stb_i: in std_logic;
rom_wb_stall_o: out std_logic
);
end entity wb_rom_ram;
architecture behave of wb_rom_ram is
component dualport_ram is
generic (
maxbit: integer
);
port (
clk: in std_logic;
memAWriteEnable: in std_logic;
memAWriteMask: in std_logic_vector(3 downto 0);
memAAddr: in std_logic_vector(maxbit downto 2);
memAWrite: in std_logic_vector(31 downto 0);
memARead: out std_logic_vector(31 downto 0);
memAEnable: in std_logic;
memBWriteEnable: in std_logic;
memBWriteMask: in std_logic_vector(3 downto 0);
memBAddr: in std_logic_vector(maxbit downto 2);
memBWrite: in std_logic_vector(31 downto 0);
memBRead: out std_logic_vector(31 downto 0);
memBEnable: in std_logic;
memErr: out std_logic
);
end component dualport_ram;
constant i_maxAddrBit: integer := maxbit; -- maxAddrBit
signal memAWriteEnable: std_logic;
signal memAWriteMask: std_logic_vector(3 downto 0);
signal memAAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memAWrite: std_logic_vector(31 downto 0);
signal memARead: std_logic_vector(31 downto 0);
signal memAEnable: std_logic;
signal memBWriteEnable: std_logic;
signal memBWriteMask: std_logic_vector(3 downto 0);
signal memBAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memBWrite: std_logic_vector(31 downto 0);
signal memBRead: std_logic_vector(31 downto 0);
signal memBEnable: std_logic;
--signal rom_burst: std_logic;
signal rom_do_wait: std_logic;
type ramregs_type is record
do_wait: std_logic;
end record;
signal ramregs: ramregs_type;
signal rom_ack: std_logic;
begin
rom_wb_ack_o <= rom_ack;
rom_wb_stall_o <= '0';-- when rom_wb_cyc_i='0' else not rom_ack;
ram_wb_stall_o <= '0';
-- System ROM/RAM
ramrom: dualport_ram
generic map (
maxbit => maxbit --13--maxAddrBit
)
port map (
clk => ram_wb_clk_i,
memAWriteEnable => memAWriteEnable,
memAWriteMask => memAWriteMask,
memAAddr => memAAddr,
memAWrite => memAWrite,
memARead => memARead,
memAEnable => memAEnable,
memBWriteEnable => memBWriteEnable,
memBWriteMask => memBWriteMask,
memBAddr => memBAddr,
memBWrite => memBWrite,
memBRead => memBRead,
memBEnable => memBEnable
);
memBWrite <= (others => DontCareValue);
memBWriteMask <= (others => DontCareValue);
memBWriteEnable <= '0';
rom_wb_dat_o <= memBRead;
memBAddr <= rom_wb_adr_i(i_maxAddrBit downto 2);
memBEnable <= rom_wb_cyc_i and rom_wb_stb_i;
-- ROM ack
process(rom_wb_clk_i)
begin
if rising_edge(rom_wb_clk_i) then
if rom_wb_rst_i='1' then
rom_ack <= '0';
--rom_burst <= '0';
rom_do_wait<='0';
else
if rom_do_wait='1' then
if true then--rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
rom_ack<='0';
rom_do_wait<='0';
end if;
else
if rom_wb_cyc_i='1' and rom_wb_stb_i='1' then
if true then --rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
--rom_burst<='0';
rom_do_wait<='1';
rom_ack<='1';
end if;
elsif rom_wb_cyc_i='0' then
rom_ack<='0';
end if;
end if;
end if;
end if;
end process;
-- RAM
memAWrite <= ram_wb_dat_i;
memAWriteMask <= (others => '1');
ram_wb_dat_o <= memARead;
memAAddr <= ram_wb_adr_i(i_maxAddrBit downto 2);
memAEnable <= ram_wb_cyc_i and ram_wb_stb_i;
-- RAM ack
process(ram_wb_clk_i, ramregs, ram_wb_rst_i,
ram_wb_stb_i, ram_wb_cyc_i, ram_wb_we_i)
variable w: ramregs_type;
begin
w:=ramregs;
--ram_wb_ack_o<='0';
--memAWriteEnable <= '0';
ram_wb_ack_o<='0';
memAWriteEnable <= '0';
if ramregs.do_wait='1' then
w.do_wait:='0';
ram_wb_ack_o<='1';
if ram_wb_we_i='1' then
memAWriteEnable <= '1';
end if;
else
if ram_wb_stb_i='1' and ram_wb_cyc_i='1' then
-- if ram_wb_we_i='1' then
-- memAWriteEnable <= '1';
-- ram_wb_ack_o<='1';
-- else
w.do_wait:='1';
-- end if;
end if;
end if;
if ram_wb_rst_i='1' then
w.do_wait:='0';
end if;
if rising_edge(ram_wb_clk_i) then
ramregs<=w;
end if;
end process;
--ram_wb_ack_o <= '1' when ram_wb_cyc_i='1' and ram_wb_stb_i='1' and ram_wb_we_i='1' else ram_wb_ack_o_i;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity wb_rom_ram is
generic (
maxbit: integer := maxAddrBit
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
ram_wb_stall_o: out std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0);
rom_wb_stb_i: in std_logic;
rom_wb_stall_o: out std_logic
);
end entity wb_rom_ram;
architecture behave of wb_rom_ram is
component dualport_ram is
generic (
maxbit: integer
);
port (
clk: in std_logic;
memAWriteEnable: in std_logic;
memAWriteMask: in std_logic_vector(3 downto 0);
memAAddr: in std_logic_vector(maxbit downto 2);
memAWrite: in std_logic_vector(31 downto 0);
memARead: out std_logic_vector(31 downto 0);
memAEnable: in std_logic;
memBWriteEnable: in std_logic;
memBWriteMask: in std_logic_vector(3 downto 0);
memBAddr: in std_logic_vector(maxbit downto 2);
memBWrite: in std_logic_vector(31 downto 0);
memBRead: out std_logic_vector(31 downto 0);
memBEnable: in std_logic;
memErr: out std_logic
);
end component dualport_ram;
constant i_maxAddrBit: integer := maxbit; -- maxAddrBit
signal memAWriteEnable: std_logic;
signal memAWriteMask: std_logic_vector(3 downto 0);
signal memAAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memAWrite: std_logic_vector(31 downto 0);
signal memARead: std_logic_vector(31 downto 0);
signal memAEnable: std_logic;
signal memBWriteEnable: std_logic;
signal memBWriteMask: std_logic_vector(3 downto 0);
signal memBAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memBWrite: std_logic_vector(31 downto 0);
signal memBRead: std_logic_vector(31 downto 0);
signal memBEnable: std_logic;
--signal rom_burst: std_logic;
signal rom_do_wait: std_logic;
type ramregs_type is record
do_wait: std_logic;
end record;
signal ramregs: ramregs_type;
signal rom_ack: std_logic;
begin
rom_wb_ack_o <= rom_ack;
rom_wb_stall_o <= '0';-- when rom_wb_cyc_i='0' else not rom_ack;
ram_wb_stall_o <= '0';
-- System ROM/RAM
ramrom: dualport_ram
generic map (
maxbit => maxbit --13--maxAddrBit
)
port map (
clk => ram_wb_clk_i,
memAWriteEnable => memAWriteEnable,
memAWriteMask => memAWriteMask,
memAAddr => memAAddr,
memAWrite => memAWrite,
memARead => memARead,
memAEnable => memAEnable,
memBWriteEnable => memBWriteEnable,
memBWriteMask => memBWriteMask,
memBAddr => memBAddr,
memBWrite => memBWrite,
memBRead => memBRead,
memBEnable => memBEnable
);
memBWrite <= (others => DontCareValue);
memBWriteMask <= (others => DontCareValue);
memBWriteEnable <= '0';
rom_wb_dat_o <= memBRead;
memBAddr <= rom_wb_adr_i(i_maxAddrBit downto 2);
memBEnable <= rom_wb_cyc_i and rom_wb_stb_i;
-- ROM ack
process(rom_wb_clk_i)
begin
if rising_edge(rom_wb_clk_i) then
if rom_wb_rst_i='1' then
rom_ack <= '0';
--rom_burst <= '0';
rom_do_wait<='0';
else
if rom_do_wait='1' then
if true then--rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
rom_ack<='0';
rom_do_wait<='0';
end if;
else
if rom_wb_cyc_i='1' and rom_wb_stb_i='1' then
if true then --rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
--rom_burst<='0';
rom_do_wait<='1';
rom_ack<='1';
end if;
elsif rom_wb_cyc_i='0' then
rom_ack<='0';
end if;
end if;
end if;
end if;
end process;
-- RAM
memAWrite <= ram_wb_dat_i;
memAWriteMask <= (others => '1');
ram_wb_dat_o <= memARead;
memAAddr <= ram_wb_adr_i(i_maxAddrBit downto 2);
memAEnable <= ram_wb_cyc_i and ram_wb_stb_i;
-- RAM ack
process(ram_wb_clk_i, ramregs, ram_wb_rst_i,
ram_wb_stb_i, ram_wb_cyc_i, ram_wb_we_i)
variable w: ramregs_type;
begin
w:=ramregs;
--ram_wb_ack_o<='0';
--memAWriteEnable <= '0';
ram_wb_ack_o<='0';
memAWriteEnable <= '0';
if ramregs.do_wait='1' then
w.do_wait:='0';
ram_wb_ack_o<='1';
if ram_wb_we_i='1' then
memAWriteEnable <= '1';
end if;
else
if ram_wb_stb_i='1' and ram_wb_cyc_i='1' then
-- if ram_wb_we_i='1' then
-- memAWriteEnable <= '1';
-- ram_wb_ack_o<='1';
-- else
w.do_wait:='1';
-- end if;
end if;
end if;
if ram_wb_rst_i='1' then
w.do_wait:='0';
end if;
if rising_edge(ram_wb_clk_i) then
ramregs<=w;
end if;
end process;
--ram_wb_ack_o <= '1' when ram_wb_cyc_i='1' and ram_wb_stb_i='1' and ram_wb_we_i='1' else ram_wb_ack_o_i;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity wb_rom_ram is
generic (
maxbit: integer := maxAddrBit
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
ram_wb_stall_o: out std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0);
rom_wb_stb_i: in std_logic;
rom_wb_stall_o: out std_logic
);
end entity wb_rom_ram;
architecture behave of wb_rom_ram is
component dualport_ram is
generic (
maxbit: integer
);
port (
clk: in std_logic;
memAWriteEnable: in std_logic;
memAWriteMask: in std_logic_vector(3 downto 0);
memAAddr: in std_logic_vector(maxbit downto 2);
memAWrite: in std_logic_vector(31 downto 0);
memARead: out std_logic_vector(31 downto 0);
memAEnable: in std_logic;
memBWriteEnable: in std_logic;
memBWriteMask: in std_logic_vector(3 downto 0);
memBAddr: in std_logic_vector(maxbit downto 2);
memBWrite: in std_logic_vector(31 downto 0);
memBRead: out std_logic_vector(31 downto 0);
memBEnable: in std_logic;
memErr: out std_logic
);
end component dualport_ram;
constant i_maxAddrBit: integer := maxbit; -- maxAddrBit
signal memAWriteEnable: std_logic;
signal memAWriteMask: std_logic_vector(3 downto 0);
signal memAAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memAWrite: std_logic_vector(31 downto 0);
signal memARead: std_logic_vector(31 downto 0);
signal memAEnable: std_logic;
signal memBWriteEnable: std_logic;
signal memBWriteMask: std_logic_vector(3 downto 0);
signal memBAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memBWrite: std_logic_vector(31 downto 0);
signal memBRead: std_logic_vector(31 downto 0);
signal memBEnable: std_logic;
--signal rom_burst: std_logic;
signal rom_do_wait: std_logic;
type ramregs_type is record
do_wait: std_logic;
end record;
signal ramregs: ramregs_type;
signal rom_ack: std_logic;
begin
rom_wb_ack_o <= rom_ack;
rom_wb_stall_o <= '0';-- when rom_wb_cyc_i='0' else not rom_ack;
ram_wb_stall_o <= '0';
-- System ROM/RAM
ramrom: dualport_ram
generic map (
maxbit => maxbit --13--maxAddrBit
)
port map (
clk => ram_wb_clk_i,
memAWriteEnable => memAWriteEnable,
memAWriteMask => memAWriteMask,
memAAddr => memAAddr,
memAWrite => memAWrite,
memARead => memARead,
memAEnable => memAEnable,
memBWriteEnable => memBWriteEnable,
memBWriteMask => memBWriteMask,
memBAddr => memBAddr,
memBWrite => memBWrite,
memBRead => memBRead,
memBEnable => memBEnable
);
memBWrite <= (others => DontCareValue);
memBWriteMask <= (others => DontCareValue);
memBWriteEnable <= '0';
rom_wb_dat_o <= memBRead;
memBAddr <= rom_wb_adr_i(i_maxAddrBit downto 2);
memBEnable <= rom_wb_cyc_i and rom_wb_stb_i;
-- ROM ack
process(rom_wb_clk_i)
begin
if rising_edge(rom_wb_clk_i) then
if rom_wb_rst_i='1' then
rom_ack <= '0';
--rom_burst <= '0';
rom_do_wait<='0';
else
if rom_do_wait='1' then
if true then--rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
rom_ack<='0';
rom_do_wait<='0';
end if;
else
if rom_wb_cyc_i='1' and rom_wb_stb_i='1' then
if true then --rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
--rom_burst<='0';
rom_do_wait<='1';
rom_ack<='1';
end if;
elsif rom_wb_cyc_i='0' then
rom_ack<='0';
end if;
end if;
end if;
end if;
end process;
-- RAM
memAWrite <= ram_wb_dat_i;
memAWriteMask <= (others => '1');
ram_wb_dat_o <= memARead;
memAAddr <= ram_wb_adr_i(i_maxAddrBit downto 2);
memAEnable <= ram_wb_cyc_i and ram_wb_stb_i;
-- RAM ack
process(ram_wb_clk_i, ramregs, ram_wb_rst_i,
ram_wb_stb_i, ram_wb_cyc_i, ram_wb_we_i)
variable w: ramregs_type;
begin
w:=ramregs;
--ram_wb_ack_o<='0';
--memAWriteEnable <= '0';
ram_wb_ack_o<='0';
memAWriteEnable <= '0';
if ramregs.do_wait='1' then
w.do_wait:='0';
ram_wb_ack_o<='1';
if ram_wb_we_i='1' then
memAWriteEnable <= '1';
end if;
else
if ram_wb_stb_i='1' and ram_wb_cyc_i='1' then
-- if ram_wb_we_i='1' then
-- memAWriteEnable <= '1';
-- ram_wb_ack_o<='1';
-- else
w.do_wait:='1';
-- end if;
end if;
end if;
if ram_wb_rst_i='1' then
w.do_wait:='0';
end if;
if rising_edge(ram_wb_clk_i) then
ramregs<=w;
end if;
end process;
--ram_wb_ack_o <= '1' when ram_wb_cyc_i='1' and ram_wb_stb_i='1' and ram_wb_we_i='1' else ram_wb_ack_o_i;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity wb_rom_ram is
generic (
maxbit: integer := maxAddrBit
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
ram_wb_stall_o: out std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0);
rom_wb_stb_i: in std_logic;
rom_wb_stall_o: out std_logic
);
end entity wb_rom_ram;
architecture behave of wb_rom_ram is
component dualport_ram is
generic (
maxbit: integer
);
port (
clk: in std_logic;
memAWriteEnable: in std_logic;
memAWriteMask: in std_logic_vector(3 downto 0);
memAAddr: in std_logic_vector(maxbit downto 2);
memAWrite: in std_logic_vector(31 downto 0);
memARead: out std_logic_vector(31 downto 0);
memAEnable: in std_logic;
memBWriteEnable: in std_logic;
memBWriteMask: in std_logic_vector(3 downto 0);
memBAddr: in std_logic_vector(maxbit downto 2);
memBWrite: in std_logic_vector(31 downto 0);
memBRead: out std_logic_vector(31 downto 0);
memBEnable: in std_logic;
memErr: out std_logic
);
end component dualport_ram;
constant i_maxAddrBit: integer := maxbit; -- maxAddrBit
signal memAWriteEnable: std_logic;
signal memAWriteMask: std_logic_vector(3 downto 0);
signal memAAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memAWrite: std_logic_vector(31 downto 0);
signal memARead: std_logic_vector(31 downto 0);
signal memAEnable: std_logic;
signal memBWriteEnable: std_logic;
signal memBWriteMask: std_logic_vector(3 downto 0);
signal memBAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memBWrite: std_logic_vector(31 downto 0);
signal memBRead: std_logic_vector(31 downto 0);
signal memBEnable: std_logic;
--signal rom_burst: std_logic;
signal rom_do_wait: std_logic;
type ramregs_type is record
do_wait: std_logic;
end record;
signal ramregs: ramregs_type;
signal rom_ack: std_logic;
begin
rom_wb_ack_o <= rom_ack;
rom_wb_stall_o <= '0';-- when rom_wb_cyc_i='0' else not rom_ack;
ram_wb_stall_o <= '0';
-- System ROM/RAM
ramrom: dualport_ram
generic map (
maxbit => maxbit --13--maxAddrBit
)
port map (
clk => ram_wb_clk_i,
memAWriteEnable => memAWriteEnable,
memAWriteMask => memAWriteMask,
memAAddr => memAAddr,
memAWrite => memAWrite,
memARead => memARead,
memAEnable => memAEnable,
memBWriteEnable => memBWriteEnable,
memBWriteMask => memBWriteMask,
memBAddr => memBAddr,
memBWrite => memBWrite,
memBRead => memBRead,
memBEnable => memBEnable
);
memBWrite <= (others => DontCareValue);
memBWriteMask <= (others => DontCareValue);
memBWriteEnable <= '0';
rom_wb_dat_o <= memBRead;
memBAddr <= rom_wb_adr_i(i_maxAddrBit downto 2);
memBEnable <= rom_wb_cyc_i and rom_wb_stb_i;
-- ROM ack
process(rom_wb_clk_i)
begin
if rising_edge(rom_wb_clk_i) then
if rom_wb_rst_i='1' then
rom_ack <= '0';
--rom_burst <= '0';
rom_do_wait<='0';
else
if rom_do_wait='1' then
if true then--rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
rom_ack<='0';
rom_do_wait<='0';
end if;
else
if rom_wb_cyc_i='1' and rom_wb_stb_i='1' then
if true then --rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
--rom_burst<='0';
rom_do_wait<='1';
rom_ack<='1';
end if;
elsif rom_wb_cyc_i='0' then
rom_ack<='0';
end if;
end if;
end if;
end if;
end process;
-- RAM
memAWrite <= ram_wb_dat_i;
memAWriteMask <= (others => '1');
ram_wb_dat_o <= memARead;
memAAddr <= ram_wb_adr_i(i_maxAddrBit downto 2);
memAEnable <= ram_wb_cyc_i and ram_wb_stb_i;
-- RAM ack
process(ram_wb_clk_i, ramregs, ram_wb_rst_i,
ram_wb_stb_i, ram_wb_cyc_i, ram_wb_we_i)
variable w: ramregs_type;
begin
w:=ramregs;
--ram_wb_ack_o<='0';
--memAWriteEnable <= '0';
ram_wb_ack_o<='0';
memAWriteEnable <= '0';
if ramregs.do_wait='1' then
w.do_wait:='0';
ram_wb_ack_o<='1';
if ram_wb_we_i='1' then
memAWriteEnable <= '1';
end if;
else
if ram_wb_stb_i='1' and ram_wb_cyc_i='1' then
-- if ram_wb_we_i='1' then
-- memAWriteEnable <= '1';
-- ram_wb_ack_o<='1';
-- else
w.do_wait:='1';
-- end if;
end if;
end if;
if ram_wb_rst_i='1' then
w.do_wait:='0';
end if;
if rising_edge(ram_wb_clk_i) then
ramregs<=w;
end if;
end process;
--ram_wb_ack_o <= '1' when ram_wb_cyc_i='1' and ram_wb_stb_i='1' and ram_wb_we_i='1' else ram_wb_ack_o_i;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity wb_rom_ram is
generic (
maxbit: integer := maxAddrBit
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
ram_wb_stall_o: out std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0);
rom_wb_stb_i: in std_logic;
rom_wb_stall_o: out std_logic
);
end entity wb_rom_ram;
architecture behave of wb_rom_ram is
component dualport_ram is
generic (
maxbit: integer
);
port (
clk: in std_logic;
memAWriteEnable: in std_logic;
memAWriteMask: in std_logic_vector(3 downto 0);
memAAddr: in std_logic_vector(maxbit downto 2);
memAWrite: in std_logic_vector(31 downto 0);
memARead: out std_logic_vector(31 downto 0);
memAEnable: in std_logic;
memBWriteEnable: in std_logic;
memBWriteMask: in std_logic_vector(3 downto 0);
memBAddr: in std_logic_vector(maxbit downto 2);
memBWrite: in std_logic_vector(31 downto 0);
memBRead: out std_logic_vector(31 downto 0);
memBEnable: in std_logic;
memErr: out std_logic
);
end component dualport_ram;
constant i_maxAddrBit: integer := maxbit; -- maxAddrBit
signal memAWriteEnable: std_logic;
signal memAWriteMask: std_logic_vector(3 downto 0);
signal memAAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memAWrite: std_logic_vector(31 downto 0);
signal memARead: std_logic_vector(31 downto 0);
signal memAEnable: std_logic;
signal memBWriteEnable: std_logic;
signal memBWriteMask: std_logic_vector(3 downto 0);
signal memBAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memBWrite: std_logic_vector(31 downto 0);
signal memBRead: std_logic_vector(31 downto 0);
signal memBEnable: std_logic;
--signal rom_burst: std_logic;
signal rom_do_wait: std_logic;
type ramregs_type is record
do_wait: std_logic;
end record;
signal ramregs: ramregs_type;
signal rom_ack: std_logic;
begin
rom_wb_ack_o <= rom_ack;
rom_wb_stall_o <= '0';-- when rom_wb_cyc_i='0' else not rom_ack;
ram_wb_stall_o <= '0';
-- System ROM/RAM
ramrom: dualport_ram
generic map (
maxbit => maxbit --13--maxAddrBit
)
port map (
clk => ram_wb_clk_i,
memAWriteEnable => memAWriteEnable,
memAWriteMask => memAWriteMask,
memAAddr => memAAddr,
memAWrite => memAWrite,
memARead => memARead,
memAEnable => memAEnable,
memBWriteEnable => memBWriteEnable,
memBWriteMask => memBWriteMask,
memBAddr => memBAddr,
memBWrite => memBWrite,
memBRead => memBRead,
memBEnable => memBEnable
);
memBWrite <= (others => DontCareValue);
memBWriteMask <= (others => DontCareValue);
memBWriteEnable <= '0';
rom_wb_dat_o <= memBRead;
memBAddr <= rom_wb_adr_i(i_maxAddrBit downto 2);
memBEnable <= rom_wb_cyc_i and rom_wb_stb_i;
-- ROM ack
process(rom_wb_clk_i)
begin
if rising_edge(rom_wb_clk_i) then
if rom_wb_rst_i='1' then
rom_ack <= '0';
--rom_burst <= '0';
rom_do_wait<='0';
else
if rom_do_wait='1' then
if true then--rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
rom_ack<='0';
rom_do_wait<='0';
end if;
else
if rom_wb_cyc_i='1' and rom_wb_stb_i='1' then
if true then --rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
--rom_burst<='0';
rom_do_wait<='1';
rom_ack<='1';
end if;
elsif rom_wb_cyc_i='0' then
rom_ack<='0';
end if;
end if;
end if;
end if;
end process;
-- RAM
memAWrite <= ram_wb_dat_i;
memAWriteMask <= (others => '1');
ram_wb_dat_o <= memARead;
memAAddr <= ram_wb_adr_i(i_maxAddrBit downto 2);
memAEnable <= ram_wb_cyc_i and ram_wb_stb_i;
-- RAM ack
process(ram_wb_clk_i, ramregs, ram_wb_rst_i,
ram_wb_stb_i, ram_wb_cyc_i, ram_wb_we_i)
variable w: ramregs_type;
begin
w:=ramregs;
--ram_wb_ack_o<='0';
--memAWriteEnable <= '0';
ram_wb_ack_o<='0';
memAWriteEnable <= '0';
if ramregs.do_wait='1' then
w.do_wait:='0';
ram_wb_ack_o<='1';
if ram_wb_we_i='1' then
memAWriteEnable <= '1';
end if;
else
if ram_wb_stb_i='1' and ram_wb_cyc_i='1' then
-- if ram_wb_we_i='1' then
-- memAWriteEnable <= '1';
-- ram_wb_ack_o<='1';
-- else
w.do_wait:='1';
-- end if;
end if;
end if;
if ram_wb_rst_i='1' then
w.do_wait:='0';
end if;
if rising_edge(ram_wb_clk_i) then
ramregs<=w;
end if;
end process;
--ram_wb_ack_o <= '1' when ram_wb_cyc_i='1' and ram_wb_stb_i='1' and ram_wb_we_i='1' else ram_wb_ack_o_i;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity wb_rom_ram is
generic (
maxbit: integer := maxAddrBit
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
ram_wb_stall_o: out std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0);
rom_wb_stb_i: in std_logic;
rom_wb_stall_o: out std_logic
);
end entity wb_rom_ram;
architecture behave of wb_rom_ram is
component dualport_ram is
generic (
maxbit: integer
);
port (
clk: in std_logic;
memAWriteEnable: in std_logic;
memAWriteMask: in std_logic_vector(3 downto 0);
memAAddr: in std_logic_vector(maxbit downto 2);
memAWrite: in std_logic_vector(31 downto 0);
memARead: out std_logic_vector(31 downto 0);
memAEnable: in std_logic;
memBWriteEnable: in std_logic;
memBWriteMask: in std_logic_vector(3 downto 0);
memBAddr: in std_logic_vector(maxbit downto 2);
memBWrite: in std_logic_vector(31 downto 0);
memBRead: out std_logic_vector(31 downto 0);
memBEnable: in std_logic;
memErr: out std_logic
);
end component dualport_ram;
constant i_maxAddrBit: integer := maxbit; -- maxAddrBit
signal memAWriteEnable: std_logic;
signal memAWriteMask: std_logic_vector(3 downto 0);
signal memAAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memAWrite: std_logic_vector(31 downto 0);
signal memARead: std_logic_vector(31 downto 0);
signal memAEnable: std_logic;
signal memBWriteEnable: std_logic;
signal memBWriteMask: std_logic_vector(3 downto 0);
signal memBAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memBWrite: std_logic_vector(31 downto 0);
signal memBRead: std_logic_vector(31 downto 0);
signal memBEnable: std_logic;
--signal rom_burst: std_logic;
signal rom_do_wait: std_logic;
type ramregs_type is record
do_wait: std_logic;
end record;
signal ramregs: ramregs_type;
signal rom_ack: std_logic;
begin
rom_wb_ack_o <= rom_ack;
rom_wb_stall_o <= '0';-- when rom_wb_cyc_i='0' else not rom_ack;
ram_wb_stall_o <= '0';
-- System ROM/RAM
ramrom: dualport_ram
generic map (
maxbit => maxbit --13--maxAddrBit
)
port map (
clk => ram_wb_clk_i,
memAWriteEnable => memAWriteEnable,
memAWriteMask => memAWriteMask,
memAAddr => memAAddr,
memAWrite => memAWrite,
memARead => memARead,
memAEnable => memAEnable,
memBWriteEnable => memBWriteEnable,
memBWriteMask => memBWriteMask,
memBAddr => memBAddr,
memBWrite => memBWrite,
memBRead => memBRead,
memBEnable => memBEnable
);
memBWrite <= (others => DontCareValue);
memBWriteMask <= (others => DontCareValue);
memBWriteEnable <= '0';
rom_wb_dat_o <= memBRead;
memBAddr <= rom_wb_adr_i(i_maxAddrBit downto 2);
memBEnable <= rom_wb_cyc_i and rom_wb_stb_i;
-- ROM ack
process(rom_wb_clk_i)
begin
if rising_edge(rom_wb_clk_i) then
if rom_wb_rst_i='1' then
rom_ack <= '0';
--rom_burst <= '0';
rom_do_wait<='0';
else
if rom_do_wait='1' then
if true then--rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
rom_ack<='0';
rom_do_wait<='0';
end if;
else
if rom_wb_cyc_i='1' and rom_wb_stb_i='1' then
if true then --rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
--rom_burst<='0';
rom_do_wait<='1';
rom_ack<='1';
end if;
elsif rom_wb_cyc_i='0' then
rom_ack<='0';
end if;
end if;
end if;
end if;
end process;
-- RAM
memAWrite <= ram_wb_dat_i;
memAWriteMask <= (others => '1');
ram_wb_dat_o <= memARead;
memAAddr <= ram_wb_adr_i(i_maxAddrBit downto 2);
memAEnable <= ram_wb_cyc_i and ram_wb_stb_i;
-- RAM ack
process(ram_wb_clk_i, ramregs, ram_wb_rst_i,
ram_wb_stb_i, ram_wb_cyc_i, ram_wb_we_i)
variable w: ramregs_type;
begin
w:=ramregs;
--ram_wb_ack_o<='0';
--memAWriteEnable <= '0';
ram_wb_ack_o<='0';
memAWriteEnable <= '0';
if ramregs.do_wait='1' then
w.do_wait:='0';
ram_wb_ack_o<='1';
if ram_wb_we_i='1' then
memAWriteEnable <= '1';
end if;
else
if ram_wb_stb_i='1' and ram_wb_cyc_i='1' then
-- if ram_wb_we_i='1' then
-- memAWriteEnable <= '1';
-- ram_wb_ack_o<='1';
-- else
w.do_wait:='1';
-- end if;
end if;
end if;
if ram_wb_rst_i='1' then
w.do_wait:='0';
end if;
if rising_edge(ram_wb_clk_i) then
ramregs<=w;
end if;
end process;
--ram_wb_ack_o <= '1' when ram_wb_cyc_i='1' and ram_wb_stb_i='1' and ram_wb_we_i='1' else ram_wb_ack_o_i;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity wb_rom_ram is
generic (
maxbit: integer := maxAddrBit
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
ram_wb_stall_o: out std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0);
rom_wb_stb_i: in std_logic;
rom_wb_stall_o: out std_logic
);
end entity wb_rom_ram;
architecture behave of wb_rom_ram is
component dualport_ram is
generic (
maxbit: integer
);
port (
clk: in std_logic;
memAWriteEnable: in std_logic;
memAWriteMask: in std_logic_vector(3 downto 0);
memAAddr: in std_logic_vector(maxbit downto 2);
memAWrite: in std_logic_vector(31 downto 0);
memARead: out std_logic_vector(31 downto 0);
memAEnable: in std_logic;
memBWriteEnable: in std_logic;
memBWriteMask: in std_logic_vector(3 downto 0);
memBAddr: in std_logic_vector(maxbit downto 2);
memBWrite: in std_logic_vector(31 downto 0);
memBRead: out std_logic_vector(31 downto 0);
memBEnable: in std_logic;
memErr: out std_logic
);
end component dualport_ram;
constant i_maxAddrBit: integer := maxbit; -- maxAddrBit
signal memAWriteEnable: std_logic;
signal memAWriteMask: std_logic_vector(3 downto 0);
signal memAAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memAWrite: std_logic_vector(31 downto 0);
signal memARead: std_logic_vector(31 downto 0);
signal memAEnable: std_logic;
signal memBWriteEnable: std_logic;
signal memBWriteMask: std_logic_vector(3 downto 0);
signal memBAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memBWrite: std_logic_vector(31 downto 0);
signal memBRead: std_logic_vector(31 downto 0);
signal memBEnable: std_logic;
--signal rom_burst: std_logic;
signal rom_do_wait: std_logic;
type ramregs_type is record
do_wait: std_logic;
end record;
signal ramregs: ramregs_type;
signal rom_ack: std_logic;
begin
rom_wb_ack_o <= rom_ack;
rom_wb_stall_o <= '0';-- when rom_wb_cyc_i='0' else not rom_ack;
ram_wb_stall_o <= '0';
-- System ROM/RAM
ramrom: dualport_ram
generic map (
maxbit => maxbit --13--maxAddrBit
)
port map (
clk => ram_wb_clk_i,
memAWriteEnable => memAWriteEnable,
memAWriteMask => memAWriteMask,
memAAddr => memAAddr,
memAWrite => memAWrite,
memARead => memARead,
memAEnable => memAEnable,
memBWriteEnable => memBWriteEnable,
memBWriteMask => memBWriteMask,
memBAddr => memBAddr,
memBWrite => memBWrite,
memBRead => memBRead,
memBEnable => memBEnable
);
memBWrite <= (others => DontCareValue);
memBWriteMask <= (others => DontCareValue);
memBWriteEnable <= '0';
rom_wb_dat_o <= memBRead;
memBAddr <= rom_wb_adr_i(i_maxAddrBit downto 2);
memBEnable <= rom_wb_cyc_i and rom_wb_stb_i;
-- ROM ack
process(rom_wb_clk_i)
begin
if rising_edge(rom_wb_clk_i) then
if rom_wb_rst_i='1' then
rom_ack <= '0';
--rom_burst <= '0';
rom_do_wait<='0';
else
if rom_do_wait='1' then
if true then--rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
rom_ack<='0';
rom_do_wait<='0';
end if;
else
if rom_wb_cyc_i='1' and rom_wb_stb_i='1' then
if true then --rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
--rom_burst<='0';
rom_do_wait<='1';
rom_ack<='1';
end if;
elsif rom_wb_cyc_i='0' then
rom_ack<='0';
end if;
end if;
end if;
end if;
end process;
-- RAM
memAWrite <= ram_wb_dat_i;
memAWriteMask <= (others => '1');
ram_wb_dat_o <= memARead;
memAAddr <= ram_wb_adr_i(i_maxAddrBit downto 2);
memAEnable <= ram_wb_cyc_i and ram_wb_stb_i;
-- RAM ack
process(ram_wb_clk_i, ramregs, ram_wb_rst_i,
ram_wb_stb_i, ram_wb_cyc_i, ram_wb_we_i)
variable w: ramregs_type;
begin
w:=ramregs;
--ram_wb_ack_o<='0';
--memAWriteEnable <= '0';
ram_wb_ack_o<='0';
memAWriteEnable <= '0';
if ramregs.do_wait='1' then
w.do_wait:='0';
ram_wb_ack_o<='1';
if ram_wb_we_i='1' then
memAWriteEnable <= '1';
end if;
else
if ram_wb_stb_i='1' and ram_wb_cyc_i='1' then
-- if ram_wb_we_i='1' then
-- memAWriteEnable <= '1';
-- ram_wb_ack_o<='1';
-- else
w.do_wait:='1';
-- end if;
end if;
end if;
if ram_wb_rst_i='1' then
w.do_wait:='0';
end if;
if rising_edge(ram_wb_clk_i) then
ramregs<=w;
end if;
end process;
--ram_wb_ack_o <= '1' when ram_wb_cyc_i='1' and ram_wb_stb_i='1' and ram_wb_we_i='1' else ram_wb_ack_o_i;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity wb_rom_ram is
generic (
maxbit: integer := maxAddrBit
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
ram_wb_stall_o: out std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0);
rom_wb_stb_i: in std_logic;
rom_wb_stall_o: out std_logic
);
end entity wb_rom_ram;
architecture behave of wb_rom_ram is
component dualport_ram is
generic (
maxbit: integer
);
port (
clk: in std_logic;
memAWriteEnable: in std_logic;
memAWriteMask: in std_logic_vector(3 downto 0);
memAAddr: in std_logic_vector(maxbit downto 2);
memAWrite: in std_logic_vector(31 downto 0);
memARead: out std_logic_vector(31 downto 0);
memAEnable: in std_logic;
memBWriteEnable: in std_logic;
memBWriteMask: in std_logic_vector(3 downto 0);
memBAddr: in std_logic_vector(maxbit downto 2);
memBWrite: in std_logic_vector(31 downto 0);
memBRead: out std_logic_vector(31 downto 0);
memBEnable: in std_logic;
memErr: out std_logic
);
end component dualport_ram;
constant i_maxAddrBit: integer := maxbit; -- maxAddrBit
signal memAWriteEnable: std_logic;
signal memAWriteMask: std_logic_vector(3 downto 0);
signal memAAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memAWrite: std_logic_vector(31 downto 0);
signal memARead: std_logic_vector(31 downto 0);
signal memAEnable: std_logic;
signal memBWriteEnable: std_logic;
signal memBWriteMask: std_logic_vector(3 downto 0);
signal memBAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memBWrite: std_logic_vector(31 downto 0);
signal memBRead: std_logic_vector(31 downto 0);
signal memBEnable: std_logic;
--signal rom_burst: std_logic;
signal rom_do_wait: std_logic;
type ramregs_type is record
do_wait: std_logic;
end record;
signal ramregs: ramregs_type;
signal rom_ack: std_logic;
begin
rom_wb_ack_o <= rom_ack;
rom_wb_stall_o <= '0';-- when rom_wb_cyc_i='0' else not rom_ack;
ram_wb_stall_o <= '0';
-- System ROM/RAM
ramrom: dualport_ram
generic map (
maxbit => maxbit --13--maxAddrBit
)
port map (
clk => ram_wb_clk_i,
memAWriteEnable => memAWriteEnable,
memAWriteMask => memAWriteMask,
memAAddr => memAAddr,
memAWrite => memAWrite,
memARead => memARead,
memAEnable => memAEnable,
memBWriteEnable => memBWriteEnable,
memBWriteMask => memBWriteMask,
memBAddr => memBAddr,
memBWrite => memBWrite,
memBRead => memBRead,
memBEnable => memBEnable
);
memBWrite <= (others => DontCareValue);
memBWriteMask <= (others => DontCareValue);
memBWriteEnable <= '0';
rom_wb_dat_o <= memBRead;
memBAddr <= rom_wb_adr_i(i_maxAddrBit downto 2);
memBEnable <= rom_wb_cyc_i and rom_wb_stb_i;
-- ROM ack
process(rom_wb_clk_i)
begin
if rising_edge(rom_wb_clk_i) then
if rom_wb_rst_i='1' then
rom_ack <= '0';
--rom_burst <= '0';
rom_do_wait<='0';
else
if rom_do_wait='1' then
if true then--rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
rom_ack<='0';
rom_do_wait<='0';
end if;
else
if rom_wb_cyc_i='1' and rom_wb_stb_i='1' then
if true then --rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
--rom_burst<='0';
rom_do_wait<='1';
rom_ack<='1';
end if;
elsif rom_wb_cyc_i='0' then
rom_ack<='0';
end if;
end if;
end if;
end if;
end process;
-- RAM
memAWrite <= ram_wb_dat_i;
memAWriteMask <= (others => '1');
ram_wb_dat_o <= memARead;
memAAddr <= ram_wb_adr_i(i_maxAddrBit downto 2);
memAEnable <= ram_wb_cyc_i and ram_wb_stb_i;
-- RAM ack
process(ram_wb_clk_i, ramregs, ram_wb_rst_i,
ram_wb_stb_i, ram_wb_cyc_i, ram_wb_we_i)
variable w: ramregs_type;
begin
w:=ramregs;
--ram_wb_ack_o<='0';
--memAWriteEnable <= '0';
ram_wb_ack_o<='0';
memAWriteEnable <= '0';
if ramregs.do_wait='1' then
w.do_wait:='0';
ram_wb_ack_o<='1';
if ram_wb_we_i='1' then
memAWriteEnable <= '1';
end if;
else
if ram_wb_stb_i='1' and ram_wb_cyc_i='1' then
-- if ram_wb_we_i='1' then
-- memAWriteEnable <= '1';
-- ram_wb_ack_o<='1';
-- else
w.do_wait:='1';
-- end if;
end if;
end if;
if ram_wb_rst_i='1' then
w.do_wait:='0';
end if;
if rising_edge(ram_wb_clk_i) then
ramregs<=w;
end if;
end process;
--ram_wb_ack_o <= '1' when ram_wb_cyc_i='1' and ram_wb_stb_i='1' and ram_wb_we_i='1' else ram_wb_ack_o_i;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity wb_rom_ram is
generic (
maxbit: integer := maxAddrBit
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
ram_wb_stall_o: out std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0);
rom_wb_stb_i: in std_logic;
rom_wb_stall_o: out std_logic
);
end entity wb_rom_ram;
architecture behave of wb_rom_ram is
component dualport_ram is
generic (
maxbit: integer
);
port (
clk: in std_logic;
memAWriteEnable: in std_logic;
memAWriteMask: in std_logic_vector(3 downto 0);
memAAddr: in std_logic_vector(maxbit downto 2);
memAWrite: in std_logic_vector(31 downto 0);
memARead: out std_logic_vector(31 downto 0);
memAEnable: in std_logic;
memBWriteEnable: in std_logic;
memBWriteMask: in std_logic_vector(3 downto 0);
memBAddr: in std_logic_vector(maxbit downto 2);
memBWrite: in std_logic_vector(31 downto 0);
memBRead: out std_logic_vector(31 downto 0);
memBEnable: in std_logic;
memErr: out std_logic
);
end component dualport_ram;
constant i_maxAddrBit: integer := maxbit; -- maxAddrBit
signal memAWriteEnable: std_logic;
signal memAWriteMask: std_logic_vector(3 downto 0);
signal memAAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memAWrite: std_logic_vector(31 downto 0);
signal memARead: std_logic_vector(31 downto 0);
signal memAEnable: std_logic;
signal memBWriteEnable: std_logic;
signal memBWriteMask: std_logic_vector(3 downto 0);
signal memBAddr: std_logic_vector(i_maxAddrBit downto 2);
signal memBWrite: std_logic_vector(31 downto 0);
signal memBRead: std_logic_vector(31 downto 0);
signal memBEnable: std_logic;
--signal rom_burst: std_logic;
signal rom_do_wait: std_logic;
type ramregs_type is record
do_wait: std_logic;
end record;
signal ramregs: ramregs_type;
signal rom_ack: std_logic;
begin
rom_wb_ack_o <= rom_ack;
rom_wb_stall_o <= '0';-- when rom_wb_cyc_i='0' else not rom_ack;
ram_wb_stall_o <= '0';
-- System ROM/RAM
ramrom: dualport_ram
generic map (
maxbit => maxbit --13--maxAddrBit
)
port map (
clk => ram_wb_clk_i,
memAWriteEnable => memAWriteEnable,
memAWriteMask => memAWriteMask,
memAAddr => memAAddr,
memAWrite => memAWrite,
memARead => memARead,
memAEnable => memAEnable,
memBWriteEnable => memBWriteEnable,
memBWriteMask => memBWriteMask,
memBAddr => memBAddr,
memBWrite => memBWrite,
memBRead => memBRead,
memBEnable => memBEnable
);
memBWrite <= (others => DontCareValue);
memBWriteMask <= (others => DontCareValue);
memBWriteEnable <= '0';
rom_wb_dat_o <= memBRead;
memBAddr <= rom_wb_adr_i(i_maxAddrBit downto 2);
memBEnable <= rom_wb_cyc_i and rom_wb_stb_i;
-- ROM ack
process(rom_wb_clk_i)
begin
if rising_edge(rom_wb_clk_i) then
if rom_wb_rst_i='1' then
rom_ack <= '0';
--rom_burst <= '0';
rom_do_wait<='0';
else
if rom_do_wait='1' then
if true then--rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
rom_ack<='0';
rom_do_wait<='0';
end if;
else
if rom_wb_cyc_i='1' and rom_wb_stb_i='1' then
if true then --rom_wb_cti_i=CTI_CYCLE_INCRADDR then
--rom_burst<='1';
rom_do_wait<='0';
rom_ack<='1';
else
--rom_burst<='0';
rom_do_wait<='1';
rom_ack<='1';
end if;
elsif rom_wb_cyc_i='0' then
rom_ack<='0';
end if;
end if;
end if;
end if;
end process;
-- RAM
memAWrite <= ram_wb_dat_i;
memAWriteMask <= (others => '1');
ram_wb_dat_o <= memARead;
memAAddr <= ram_wb_adr_i(i_maxAddrBit downto 2);
memAEnable <= ram_wb_cyc_i and ram_wb_stb_i;
-- RAM ack
process(ram_wb_clk_i, ramregs, ram_wb_rst_i,
ram_wb_stb_i, ram_wb_cyc_i, ram_wb_we_i)
variable w: ramregs_type;
begin
w:=ramregs;
--ram_wb_ack_o<='0';
--memAWriteEnable <= '0';
ram_wb_ack_o<='0';
memAWriteEnable <= '0';
if ramregs.do_wait='1' then
w.do_wait:='0';
ram_wb_ack_o<='1';
if ram_wb_we_i='1' then
memAWriteEnable <= '1';
end if;
else
if ram_wb_stb_i='1' and ram_wb_cyc_i='1' then
-- if ram_wb_we_i='1' then
-- memAWriteEnable <= '1';
-- ram_wb_ack_o<='1';
-- else
w.do_wait:='1';
-- end if;
end if;
end if;
if ram_wb_rst_i='1' then
w.do_wait:='0';
end if;
if rising_edge(ram_wb_clk_i) then
ramregs<=w;
end if;
end process;
--ram_wb_ack_o <= '1' when ram_wb_cyc_i='1' and ram_wb_stb_i='1' and ram_wb_we_i='1' else ram_wb_ack_o_i;
end behave;
|
-- ======================================================================
-- AES encryption/decryption
-- Copyright (C) 2019 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.aes_pkg.all;
entity aes_dec is
generic (
design_type : string := "ITER"
);
port (
reset_i : in std_logic; -- async reset
clk_i : in std_logic; -- clock
key_i : in std_logic_vector(0 to 127); -- key input
data_i : in std_logic_vector(0 to 127); -- data input
valid_i : in std_logic; -- input key/data valid flag
accept_o : out std_logic;
data_o : out std_logic_vector(0 to 127); -- data output
valid_o : out std_logic; -- output data valid flag
accept_i : in std_logic
);
end entity aes_dec;
architecture rtl of aes_dec is
begin
IterG : if design_type = "ITER" generate
signal s_round : t_dec_rounds;
begin
DeCryptP : process (reset_i, clk_i) is
variable v_state : t_datatable2d;
type t_key_array is array (0 to 10) of t_key;
variable v_round_keys : t_key_array;
begin
if (reset_i = '0') then
v_state := (others => (others => (others => '0')));
s_round <= 0;
accept_o <= '0';
data_o <= (others => '0');
valid_o <= '0';
elsif (rising_edge(clk_i)) then
case s_round is
when 0 =>
accept_o <= '1';
if (accept_o = '1' and valid_i = '1') then
accept_o <= '0';
v_state := set_state(data_i);
v_round_keys(0) := set_key(key_i);
for i in t_key_rounds'low to t_key_rounds'high loop
v_round_keys(i+1) := key_round(v_round_keys(i), i);
end loop;
s_round <= s_round + 1;
end if;
when 1 =>
v_state := addroundkey(v_state, v_round_keys(v_round_keys'length-s_round));
s_round <= s_round + 1;
when t_dec_rounds'high-1 =>
v_state := invshiftrow(v_state);
v_state := invsubbytes(v_state);
v_state := addroundkey(v_state, v_round_keys(v_round_keys'length-s_round));
s_round <= s_round + 1;
-- set data & valid to save one cycle
valid_o <= '1';
data_o <= get_state(v_state);
when t_dec_rounds'high =>
if (valid_o = '1' and accept_i = '1') then
valid_o <= '0';
data_o <= (others => '0');
s_round <= 0;
-- Set accept to save one cycle
accept_o <= '1';
end if;
when others =>
v_state := invshiftrow(v_state);
v_state := invsubbytes(v_state);
v_state := addroundkey(v_state, v_round_keys(v_round_keys'length-s_round));
v_state := invmixcolumns(v_state);
s_round <= s_round + 1;
end case;
end if;
end process DeCryptP;
psl : block is
signal s_key , s_din, s_dout : std_logic_vector(0 to 127) := (others => '0');
begin
process (clk_i) is
begin
if (rising_edge(clk_i)) then
s_key <= key_i;
s_din <= data_i;
s_dout <= data_o;
end if;
end process;
default clock is rising_edge(clk_i);
-- initial reset
restrict {not reset_i; reset_i[+]}[*1];
-- constraints
assume always (valid_i and not accept_o -> next valid_i);
assume always (valid_i and not accept_o -> next key_i = s_key);
assume always (valid_i and not accept_o -> next data_i = s_din);
ACCEPTO_c : cover {accept_o};
ACCEPT_IN_ROUND_0_ONLY_a : assert always (accept_o -> s_round = 0);
VALIDI_AND_ACCEPTO_c : cover {valid_i and accept_o};
ACCEPT_OFF_WHEN_VALID_a : assert always (valid_i and accept_o -> next not accept_o);
VALIDO_c : cover {valid_o};
VALID_IN_LAST_ROUND_ONLY_a : assert always (valid_o -> s_round = t_enc_rounds'high);
VALIDO_AND_ACCEPTI_c : cover {valid_o and accept_i};
VALID_OFF_WHEN_ACCEPTED_a : assert always (valid_o and accept_i -> next not valid_o);
VALIDO_AND_NOT_ACCEPTI_c : cover {valid_o and not accept_i};
VALID_STABLE_WHEN_NOT_ACCEPTED_a : assert always (valid_o and not accept_i -> next valid_o);
DATA_STABLE_WHEN_NOT_ACCEPTED_a : assert always (valid_o and not accept_i -> next data_o = s_dout);
end block psl;
end generate IterG;
end architecture rtl;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file spartan3adsp_dmem.vhd when simulating
-- the core, spartan3adsp_dmem. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY spartan3adsp_dmem IS
port (
clka: IN std_logic;
ena: IN std_logic;
wea: IN std_logic_VECTOR(1 downto 0);
addra: IN std_logic_VECTOR(9 downto 0);
dina: IN std_logic_VECTOR(15 downto 0);
douta: OUT std_logic_VECTOR(15 downto 0));
END spartan3adsp_dmem;
ARCHITECTURE spartan3adsp_dmem_a OF spartan3adsp_dmem IS
-- synthesis translate_off
component wrapped_spartan3adsp_dmem
port (
clka: IN std_logic;
ena: IN std_logic;
wea: IN std_logic_VECTOR(1 downto 0);
addra: IN std_logic_VECTOR(9 downto 0);
dina: IN std_logic_VECTOR(15 downto 0);
douta: OUT std_logic_VECTOR(15 downto 0));
end component;
-- Configuration specification
for all : wrapped_spartan3adsp_dmem use entity XilinxCoreLib.blk_mem_gen_v3_3(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 0,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 16,
c_initb_val => "0",
c_family => "spartan3",
c_read_width_a => 16,
c_disable_warn_bhv_coll => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "no_coe_file_loaded",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 0,
c_xdevicefamily => "spartan3adsp",
c_write_depth_b => 1024,
c_write_depth_a => 1024,
c_has_rstb => 0,
c_has_rsta => 0,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 10,
c_addrb_width => 10,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 16,
c_write_width_a => 16,
c_read_depth_b => 1024,
c_read_depth_a => 1024,
c_byte_size => 8,
c_sim_collision_check => "ALL",
c_common_clk => 0,
c_wea_width => 2,
c_has_enb => 0,
c_web_width => 2,
c_has_ena => 1,
c_use_byte_web => 1,
c_use_byte_wea => 1,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_spartan3adsp_dmem
port map (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta);
-- synthesis translate_on
END spartan3adsp_dmem_a;
|
library IEEE;
use IEEE.Std_Logic_1164.all;
--Multiplexador 16x1 32bits
entity mux16x1_32 is
port (IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7,IN8,IN9,IN10,IN11,IN12,IN13,IN14,IN15: in std_logic_vector(31 downto 0);
REG: out std_logic_vector(31 downto 0);
UP_DOWN: in std_logic_vector(3 downto 0)
);
end mux16x1_32;
--Definicao Arquitetura
architecture circuito of mux16x1_32 is
begin
REG <= IN0 when UP_DOWN = "0000" else
IN1 when UP_DOWN = "0001" else
IN2 when UP_DOWN = "0010" else
IN3 when UP_DOWN = "0011" else
IN4 when UP_DOWN = "0100" else
IN5 when UP_DOWN = "0101" else
IN6 when UP_DOWN = "0110" else
IN7 when UP_DOWN = "0111" else
IN8 when UP_DOWN = "1000" else
IN9 when UP_DOWN = "1001" else
IN10 when UP_DOWN = "1010" else
IN11 when UP_DOWN = "1011" else
IN12 when UP_DOWN = "1100" else
IN13 when UP_DOWN = "1101" else
IN14 when UP_DOWN = "1110" else
IN15;
end circuito; |
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`protect end_protected
|
-- $Id: tst_serloop.vhd 1203 2019-08-19 21:41:03Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tst_serloop - syn
-- Description: simple stand-alone tester for serport components
--
-- Dependencies: -
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 13.1-14.7; viv 2014.4-2019.1; ghdl 0.29-0.36
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-08-17 1203 1.0.3 fix for ghdl V0.36 -Whide warnings
-- 2011-12-10 438 1.0.2 clr fecnt when abact; add rxui(cnt|dat) regs
-- 2011-12-09 437 1.0.1 rename serport stat->moni port
-- 2011-11-06 420 1.0 Initial version
-- 2011-10-14 416 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.tst_serlooplib.all;
-- ----------------------------------------------------------------------------
entity tst_serloop is -- tester for serport components
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_MSEC : in slbit; -- msec pulse
HIO_CNTL : in hio_cntl_type; -- humanio controls
HIO_STAT : out hio_stat_type; -- humanio status
SER_MONI : in serport_moni_type; -- serport monitor
RXDATA : in slv8; -- receiver data out
RXVAL : in slbit; -- receiver data valid
RXHOLD : out slbit; -- receiver data hold
TXDATA : out slv8; -- transmit data in
TXENA : out slbit; -- transmit data enable
TXBUSY : in slbit -- transmit busy
);
end tst_serloop;
architecture syn of tst_serloop is
type regs_type is record
rxdata : slv8; -- next rx char
txdata : slv8; -- next tx char
rxfecnt : slv16; -- rx frame error counter
rxoecnt : slv16; -- rx overrun error counter
rxsecnt : slv16; -- rx sequence error counter
rxcnt : slv32; -- rx char counter
txcnt : slv32; -- tx char counter
rxuicnt : slv8; -- rx unsolicited input counter
rxuidat : slv8; -- rx unsolicited input data
rxokcnt : slv16; -- rxok 1->0 transition counter
txokcnt : slv16; -- txok 1->0 transition counter
rxok_1 : slbit; -- rxok last cycle
txok_1 : slbit; -- txok last cycle
rxthrottle : slbit; -- rx throttle flag
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'), -- rxdata
(others=>'0'), -- txdata
(others=>'0'), -- rxfecnt
(others=>'0'), -- rxoecnt
(others=>'0'), -- rxsecnt
(others=>'0'), -- rxcnt
(others=>'0'), -- txcnt
(others=>'0'), -- rxuicnt
(others=>'0'), -- rxuidat
(others=>'0'), -- rxokcnt
(others=>'0'), -- txokcnt
'0','0', -- rxok_1,txok_1
'0' -- rxthrottle
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_MSEC, HIO_CNTL, SER_MONI,
RXDATA, RXVAL, TXBUSY)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irxhold : slbit := '1';
variable itxena : slbit := '0';
variable itxdata : slv8 := (others=>'0');
variable skipxon : slbit := '0';
function nextchar(pskipxon: in slbit; pdata: in slv8) return slv8 is
variable inc : slv8 := (others=>'0');
begin
inc := "00000001";
if pskipxon='1' and (pdata=c_serport_xon or pdata=c_serport_xoff) then
inc := "00000010";
end if;
return slv(unsigned(pdata)+unsigned(inc));
end function nextchar;
begin
r := R_REGS;
n := R_REGS;
irxhold := '1';
itxena := '0';
itxdata := RXDATA;
if HIO_CNTL.mode = c_mode_txblast then
itxdata := r.txdata;
end if;
skipxon := '0';
if HIO_CNTL.enaxon='1' and HIO_CNTL.enaesc='0' then
skipxon := '1';
end if;
if HIO_CNTL.enathrottle = '1' then
if CE_MSEC = '1' then
n.rxthrottle := not r.rxthrottle;
end if;
else
n.rxthrottle := '0';
end if;
case HIO_CNTL.mode is
when c_mode_idle =>
null;
when c_mode_rxblast =>
if RXVAL='1' and r.rxthrottle='0' then
irxhold := '0';
if RXDATA /= r.rxdata then
n.rxsecnt := slv(unsigned(r.rxsecnt) + 1);
end if;
n.rxdata := nextchar(skipxon, RXDATA);
end if;
when c_mode_txblast =>
if TXBUSY = '0' then
itxena := '1';
n.txdata := nextchar(skipxon, r.txdata);
end if;
irxhold := '0';
if RXVAL = '1' then
n.rxuicnt := slv(unsigned(r.rxuicnt) + 1);
n.rxuidat := RXDATA;
end if;
when c_mode_loop =>
if RXVAL='1' and r.rxthrottle='0' and TXBUSY = '0' then
irxhold := '0';
itxena := '1';
end if;
when others => null;
end case;
if SER_MONI.abact = '1' then -- if auto bauder active
n.rxfecnt := (others=>'0'); -- reset frame error counter
else -- otherwise
if SER_MONI.rxerr = '1' then -- count rx frame errors
n.rxfecnt := slv(unsigned(r.rxfecnt) + 1);
end if;
end if;
if SER_MONI.rxovr = '1' then
n.rxoecnt := slv(unsigned(r.rxoecnt) + 1);
end if;
if RXVAL='1' and irxhold='0' then
n.rxcnt := slv(unsigned(r.rxcnt) + 1);
end if;
if itxena = '1' then
n.txcnt := slv(unsigned(r.txcnt) + 1);
end if;
n.rxok_1 := SER_MONI.rxok;
n.txok_1 := SER_MONI.txok;
if SER_MONI.rxok='0' and r.rxok_1='1' then
n.rxokcnt := slv(unsigned(r.rxokcnt) + 1);
end if;
if SER_MONI.txok='0' and r.txok_1='1' then
n.txokcnt := slv(unsigned(r.txokcnt) + 1);
end if;
N_REGS <= n;
RXHOLD <= irxhold;
TXENA <= itxena;
TXDATA <= itxdata;
HIO_STAT.rxfecnt <= r.rxfecnt;
HIO_STAT.rxoecnt <= r.rxoecnt;
HIO_STAT.rxsecnt <= r.rxsecnt;
HIO_STAT.rxcnt <= r.rxcnt;
HIO_STAT.txcnt <= r.txcnt;
HIO_STAT.rxuicnt <= r.rxuicnt;
HIO_STAT.rxuidat <= r.rxuidat;
HIO_STAT.rxokcnt <= r.rxokcnt;
HIO_STAT.txokcnt <= r.txokcnt;
end process proc_next;
end syn;
|
--------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- Generated from component ID: xilinx.com:ip:blk_mem_gen:4.3
-- You must compile the wrapper file DualPortMem.vhd when simulating
-- the core, DualPortMem. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY DualPortMem IS
port (
clka: in std_logic;
wea: in std_logic_vector(0 downto 0);
addra: in std_logic_vector(7 downto 0);
dina: in std_logic_vector(31 downto 0);
douta: out std_logic_vector(31 downto 0);
clkb: in std_logic;
web: in std_logic_vector(0 downto 0);
addrb: in std_logic_vector(9 downto 0);
dinb: in std_logic_vector(7 downto 0);
doutb: out std_logic_vector(7 downto 0));
END DualPortMem;
ARCHITECTURE DualPortMem_a OF DualPortMem IS
-- synthesis translate_off
component wrapped_DualPortMem
port (
clka: in std_logic;
wea: in std_logic_vector(0 downto 0);
addra: in std_logic_vector(7 downto 0);
dina: in std_logic_vector(31 downto 0);
douta: out std_logic_vector(31 downto 0);
clkb: in std_logic;
web: in std_logic_vector(0 downto 0);
addrb: in std_logic_vector(9 downto 0);
dinb: in std_logic_vector(7 downto 0);
doutb: out std_logic_vector(7 downto 0));
end component;
-- Configuration specification
for all : wrapped_DualPortMem use entity XilinxCoreLib.blk_mem_gen_v4_3(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 2,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 8,
c_initb_val => "0",
c_family => "spartan6",
c_read_width_a => 32,
c_disable_warn_bhv_coll => 0,
c_use_softecc => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "no_coe_file_loaded",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_softecc_output_regs_b => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 0,
c_xdevicefamily => "spartan6",
c_write_depth_b => 1024,
c_write_depth_a => 256,
c_has_rstb => 0,
c_has_rsta => 0,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 8,
c_has_softecc_input_regs_a => 0,
c_addrb_width => 10,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 8,
c_write_width_a => 32,
c_read_depth_b => 1024,
c_read_depth_a => 256,
c_byte_size => 9,
c_sim_collision_check => "ALL",
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_DualPortMem
port map (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb);
-- synthesis translate_on
END DualPortMem_a;
|
------------------------------------------------------------------------------
--
-- File: HandshakeData.vhd
-- Author: Elod Gyorgy
-- Original Project: Atlys2 User Demo
-- Date: 29 June 20116
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module passes parallel data from the input clock domain (InClk) to the
-- output clock domain (OutClk) by the means of handshake signals. A
-- low-to-high transition on iPush will register iData inside the module
-- and will start propagating the handshake signals towards the output domain.
-- The data will appear on oData and is valid when oValid pulses high.
-- The reception of data by the receiver on the OutClk domain is signaled
-- by a pulse on oAck. This will propagate back to the input domain and
-- assert iRdy signaling to the sender that a new data can be pushed though.
-- If oData is always read when oValid pulses, oAck may be tied permanently
-- high.
-- Only assert iPush when iRdy is high!
--
-- Changelog:
-- 2016-Jun-29: Fixed oValid not being a pulse.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity HandshakeData is
Generic (
kDataWidth : natural := 8);
Port (
InClk : in STD_LOGIC;
OutClk : in STD_LOGIC;
iData : in STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
oData : out STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
iPush : in STD_LOGIC;
iRdy : out STD_LOGIC;
oAck : in STD_LOGIC := '1';
oValid : out STD_LOGIC;
aReset : in std_logic);
end HandshakeData;
architecture Behavioral of HandshakeData is
signal iPush_q, iPushRising, iPushT, iPushTBack, iReset : std_logic;
signal iData_int : std_logic_vector(kDataWidth-1 downto 0);
signal oPushT, oPushT_q, oPushTBack, oPushTChanged : std_logic;
attribute DONT_TOUCH : string;
attribute DONT_TOUCH of aReset: signal is "TRUE";
begin
DetectPush: process(aReset, InClk)
begin
if (aReset = '1') then
iPush_q <= '0';
elsif Rising_Edge(InClk) then
iPush_q <= iPush;
end if;
end process DetectPush;
iPushRising <= iPush and not iPush_q;
-- Register data when iPush is rising and toggle internal flag
LatchData: process(aReset, InClk)
begin
if (aReset = '1') then
iData_int <= (others => '0');
iPushT <= '0';
elsif Rising_Edge(InClk) then
if (iPushRising = '1') then
iData_int <= iData;
iPushT <= not iPushT;
end if;
end if;
end process;
-- Cross toggle flag through synchronizer
SyncAsyncPushT: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aReset => aReset,
aIn => iPushT,
OutClk => OutClk,
oOut => oPushT);
-- Detect a push edge in the OutClk domain
-- If receiver acknowledges receipt, we can propagate the push signal back
-- towards the input, where it will be used to generate iRdy
DetectToggle: process(aReset, OutClk)
begin
if (aReset = '1') then
oPushT_q <= '0';
oPushTBack <= '0';
elsif Rising_Edge(OutClk) then
oPushT_q <= oPushT;
if (oAck = '1') then
oPushTBack <= oPushT_q;
end if;
end if;
end process DetectToggle;
oPushTChanged <= '1' when oPushT_q /= oPushT else '0';
-- Cross data from InClk domain reg (iData_in) to OutClk domain
-- The enable for this register is the propagated and sync'd to the OutClk domain
-- We assume here that the time it took iPush to propagate to oPushTChanged is
-- more than the time it takes iData_int to propagate to the oData register's D pin
OutputData: process (aReset, OutClk)
begin
if (aReset = '1') then
oData <= (others => '0');
oValid <= '0';
elsif Rising_Edge(OutClk) then
if (oPushTChanged = '1') then
oData <= iData_int;
end if;
oValid <= oPushTChanged;
end if;
end process OutputData;
-- Cross toggle flag back through synchronizer
SyncAsyncPushTBack: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aReset => aReset,
aIn => oPushTBack,
OutClk => InClk,
oOut => iPushTBack);
-- Synchronize aReset into the InClk domain
-- We need it to keep iRdy low, when aReset de-asserts
SyncReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aReset,
OutClk => InClk,
oRst => iReset);
ReadySignal: process(aReset, InClk)
begin
if (aReset = '1') then
iRdy <= '0';
elsif Rising_Edge(InClk) then
iRdy <= not iPush and (iPushTBack xnor iPushT) and not iReset;
end if;
end process ReadySignal;
end Behavioral;
|
-- NEED RESULT: ARCH00099.P1: Multi transport transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00099.P2: Multi transport transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00099.P3: Multi transport transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00099: One transport transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00099: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00099: One transport transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00099: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00099: One transport transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00099: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00099
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00099(ARCH00099)
-- ENT00099_Test_Bench(ARCH00099_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00099 is
port (
s_st_arr1_vector : inout st_arr1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
end ENT00099 ;
--
architecture ARCH00099 of ENT00099 is
begin
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_arr1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_arr1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0 =>
s_st_arr1_vector(lowb) (
st_arr1'Left) <= transport
c_st_arr1_vector_2(highb) (
st_arr1'Right) after 10 ns,
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_2(highb) (
st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_1(highb) (
st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00099.P1" ,
"Multi transport transactions occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (
st_arr1'Left) <= transport
c_st_arr1_vector_2(highb) (
st_arr1'Right) after 10 ns,
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 20 ns,
c_st_arr1_vector_2(highb) (
st_arr1'Right) after 30 ns,
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_2(highb) (
st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1_vector(lowb) (
st_arr1'Left) <= transport
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_1(highb) (
st_arr1'Right) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00099" ,
"One transport transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00099" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00099" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_arr2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_arr2_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0 =>
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <= transport
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00099.P2" ,
"Multi transport transactions occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <= transport
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns,
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 30 ns,
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <= transport
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00099" ,
"One transport transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00099" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00099" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_st_arr3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_st_arr3_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0 =>
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <= transport
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00099.P3" ,
"Multi transport transactions occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <= transport
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns,
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 30 ns,
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <= transport
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00099" ,
"One transport transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00099" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00099" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P3 ;
--
--
end ARCH00099 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00099_Test_Bench is
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
end ENT00099_Test_Bench ;
--
architecture ARCH00099_Test_Bench of ENT00099_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_arr1_vector : inout st_arr1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00099 ( ARCH00099 ) ;
begin
CIS1 : UUT
port map (
s_st_arr1_vector
, s_st_arr2_vector
, s_st_arr3_vector
) ;
end block L1 ;
end ARCH00099_Test_Bench ;
|
entity simple is
end;
architecture behav of simple is
begin
assert false report "Hello" severity note;
end;
|
entity simple is
end;
architecture behav of simple is
begin
assert false report "Hello" severity note;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iopad_ds
-- File: iopad_ds.vhd
-- Author: Nils Johan Wessman - Gaisler Research
-- Description: differential io pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iopad_ds is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0; term : integer := 0);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of iopad_ds is
signal oen : std_ulogic;
begin
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_ds_pads(tech) = 0 or
tech = axcel or tech = axdsp or tech = rhlib18t or
tech = ut25 or tech = ut130 generate
padp <= transport i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0' and slew = 0 else i when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(oen)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
padn <= transport not i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0' and slew = 0 else not i when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(oen)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
o <= to_X01(padp)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if is_unisim(tech) = 1 generate
x0 : unisim_iopad_ds generic map (level, slew, voltage, strength)
port map (padp, padn, i, oen, o);
end generate;
pa3 : if (tech = apa3) generate
x0 : apa3_iopad_ds generic map (level)
port map (padp, padn, i, oen, o);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_iopad_ds generic map (level)
port map (padp, padn, i, oen, o);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_iopad_ds generic map (level)
port map (padp, padn, i, oen, o);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_iopad_ds generic map (level)
port map (padp, padn, i, oen, o);
end generate;
n2x : if (tech = easic45) generate
x0 : n2x_iopad_ds generic map (level, slew, voltage, strength)
port map (padp, padn, i, oen, o);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_dsv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp, padn : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iopad_dsv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en, o(j));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_dsvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp, padn : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iopad_dsvv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en(j), o(j));
end generate;
end;
|
-------------------------------------------------------------------------------
--! @project Unrolled (3) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Ascon_StateUpdate is
port(
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset (synchronous)
-- ExtInputs
Start : in std_logic;
Mode : in std_logic_vector(3 downto 0);
Size : in std_logic_vector(2 downto 0); -- only matters for last block decryption
IV : in std_logic_vector(127 downto 0);
Key : in std_logic_vector(127 downto 0);
DataIn : in std_logic_vector(63 downto 0);
Busy : out std_logic;
DataOut : out std_logic_vector(127 downto 0));
end entity Ascon_StateUpdate;
architecture structural of Ascon_StateUpdate is
-- Control signals
signal RoundNr : std_logic_vector(3 downto 0); -- biggest round is 12
signal sel1,sel2,sel3,sel4 : std_logic_vector(1 downto 0);
signal sel0 : std_logic_vector(2 downto 0);
signal selout : std_logic;
signal Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : std_logic;
signal ActivateGen : std_logic;
signal GenSize : std_logic_vector(2 downto 0);
begin
control: entity work.Ascon_StateUpdate_control port map (Clk, Reset, RoundNr, sel1, sel2, sel3, sel4, sel0, selout, Reg0En,
Reg1En, Reg2En, Reg3En, Reg4En, RegOutEn, ActivateGen, GenSize, Start, Mode, Size, Busy);
datapath: entity work.Ascon_StateUpdate_datapath port map (Clk, Reset, RoundNr, sel1, sel2, sel3, sel4, sel0, selout, Reg0En,
Reg1En, Reg2En, Reg3En, Reg4En, RegOutEn, ActivateGen, GenSize, IV, Key, DataIn, DataOut);
end architecture structural;
|
-------------------------------------------------------------------------------
-- clock_generator_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library clock_generator_v3_02_a;
use clock_generator_v3_02_a.all;
entity clock_generator_0_wrapper is
port (
CLKIN : in std_logic;
CLKFBIN : in std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUT6 : out std_logic;
CLKOUT7 : out std_logic;
CLKOUT8 : out std_logic;
CLKOUT9 : out std_logic;
CLKOUT10 : out std_logic;
CLKOUT11 : out std_logic;
CLKOUT12 : out std_logic;
CLKOUT13 : out std_logic;
CLKOUT14 : out std_logic;
CLKOUT15 : out std_logic;
CLKFBOUT : out std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSDONE : out std_logic;
RST : in std_logic;
LOCKED : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of clock_generator_0_wrapper : entity is "clock_generator_v3_02_a";
end clock_generator_0_wrapper;
architecture STRUCTURE of clock_generator_0_wrapper is
component clock_generator is
generic (
C_FAMILY : STRING;
C_SPEEDGRADE : STRING;
C_EXT_RESET_HIGH : INTEGER;
C_CLK_GEN : STRING;
C_CLKOUT0_MODULE : STRING;
C_CLKOUT0_PORT : STRING;
C_CLKOUT1_MODULE : STRING;
C_CLKOUT1_PORT : STRING;
C_CLKOUT2_MODULE : STRING;
C_CLKOUT2_PORT : STRING;
C_CLKOUT3_MODULE : STRING;
C_CLKOUT3_PORT : STRING;
C_CLKOUT4_MODULE : STRING;
C_CLKOUT4_PORT : STRING;
C_CLKOUT5_MODULE : STRING;
C_CLKOUT5_PORT : STRING;
C_CLKOUT6_MODULE : STRING;
C_CLKOUT6_PORT : STRING;
C_CLKOUT7_MODULE : STRING;
C_CLKOUT7_PORT : STRING;
C_CLKOUT8_MODULE : STRING;
C_CLKOUT8_PORT : STRING;
C_CLKOUT9_MODULE : STRING;
C_CLKOUT9_PORT : STRING;
C_CLKOUT10_MODULE : STRING;
C_CLKOUT10_PORT : STRING;
C_CLKOUT11_MODULE : STRING;
C_CLKOUT11_PORT : STRING;
C_CLKOUT12_MODULE : STRING;
C_CLKOUT12_PORT : STRING;
C_CLKOUT13_MODULE : STRING;
C_CLKOUT13_PORT : STRING;
C_CLKOUT14_MODULE : STRING;
C_CLKOUT14_PORT : STRING;
C_CLKOUT15_MODULE : STRING;
C_CLKOUT15_PORT : STRING;
C_CLKFBOUT_MODULE : STRING;
C_CLKFBOUT_PORT : STRING;
C_PSDONE_MODULE : STRING;
C_PLL0_DIVCLK_DIVIDE : INTEGER;
C_PLL0_CLKFBOUT_MULT : INTEGER;
C_PLL0_CLKFBOUT_PHASE : REAL;
C_PLL0_CLKIN1_PERIOD : REAL;
C_PLL0_CLKOUT0_DIVIDE : INTEGER;
C_PLL0_CLKOUT0_DUTY_CYCLE : REAL;
C_PLL0_CLKOUT0_PHASE : REAL;
C_PLL0_CLKOUT1_DIVIDE : INTEGER;
C_PLL0_CLKOUT1_DUTY_CYCLE : REAL;
C_PLL0_CLKOUT1_PHASE : REAL;
C_PLL0_CLKOUT2_DIVIDE : INTEGER;
C_PLL0_CLKOUT2_DUTY_CYCLE : REAL;
C_PLL0_CLKOUT2_PHASE : REAL;
C_PLL0_CLKOUT3_DIVIDE : INTEGER;
C_PLL0_CLKOUT3_DUTY_CYCLE : REAL;
C_PLL0_CLKOUT3_PHASE : REAL;
C_PLL0_CLKOUT4_DIVIDE : INTEGER;
C_PLL0_CLKOUT4_DUTY_CYCLE : REAL;
C_PLL0_CLKOUT4_PHASE : REAL;
C_PLL0_CLKOUT5_DIVIDE : INTEGER;
C_PLL0_CLKOUT5_DUTY_CYCLE : REAL;
C_PLL0_CLKOUT5_PHASE : REAL;
C_PLL0_BANDWIDTH : STRING;
C_PLL0_COMPENSATION : STRING;
C_PLL0_REF_JITTER : REAL;
C_PLL0_RESET_ON_LOSS_OF_LOCK : BOOLEAN;
C_PLL0_RST_DEASSERT_CLK : STRING;
C_PLL0_EXT_RESET_HIGH : INTEGER;
C_PLL0_FAMILY : STRING;
C_PLL0_CLKOUT0_DESKEW_ADJUST : STRING;
C_PLL0_CLKOUT1_DESKEW_ADJUST : STRING;
C_PLL0_CLKOUT2_DESKEW_ADJUST : STRING;
C_PLL0_CLKOUT3_DESKEW_ADJUST : STRING;
C_PLL0_CLKOUT4_DESKEW_ADJUST : STRING;
C_PLL0_CLKOUT5_DESKEW_ADJUST : STRING;
C_PLL0_CLKFBOUT_DESKEW_ADJUST : STRING;
C_PLL0_CLKIN1_BUF : BOOLEAN;
C_PLL0_CLKFBOUT_BUF : BOOLEAN;
C_PLL0_CLKOUT0_BUF : BOOLEAN;
C_PLL0_CLKOUT1_BUF : BOOLEAN;
C_PLL0_CLKOUT2_BUF : BOOLEAN;
C_PLL0_CLKOUT3_BUF : BOOLEAN;
C_PLL0_CLKOUT4_BUF : BOOLEAN;
C_PLL0_CLKOUT5_BUF : BOOLEAN;
C_PLL0_CLKIN1_MODULE : STRING;
C_PLL0_CLKIN1_PORT : STRING;
C_PLL0_CLKFBIN_MODULE : STRING;
C_PLL0_CLKFBIN_PORT : STRING;
C_PLL0_RST_MODULE : STRING;
C_PLL1_DIVCLK_DIVIDE : INTEGER;
C_PLL1_CLKFBOUT_MULT : INTEGER;
C_PLL1_CLKFBOUT_PHASE : REAL;
C_PLL1_CLKIN1_PERIOD : REAL;
C_PLL1_CLKOUT0_DIVIDE : INTEGER;
C_PLL1_CLKOUT0_DUTY_CYCLE : REAL;
C_PLL1_CLKOUT0_PHASE : REAL;
C_PLL1_CLKOUT1_DIVIDE : INTEGER;
C_PLL1_CLKOUT1_DUTY_CYCLE : REAL;
C_PLL1_CLKOUT1_PHASE : REAL;
C_PLL1_CLKOUT2_DIVIDE : INTEGER;
C_PLL1_CLKOUT2_DUTY_CYCLE : REAL;
C_PLL1_CLKOUT2_PHASE : REAL;
C_PLL1_CLKOUT3_DIVIDE : INTEGER;
C_PLL1_CLKOUT3_DUTY_CYCLE : REAL;
C_PLL1_CLKOUT3_PHASE : REAL;
C_PLL1_CLKOUT4_DIVIDE : INTEGER;
C_PLL1_CLKOUT4_DUTY_CYCLE : REAL;
C_PLL1_CLKOUT4_PHASE : REAL;
C_PLL1_CLKOUT5_DIVIDE : INTEGER;
C_PLL1_CLKOUT5_DUTY_CYCLE : REAL;
C_PLL1_CLKOUT5_PHASE : REAL;
C_PLL1_BANDWIDTH : STRING;
C_PLL1_COMPENSATION : STRING;
C_PLL1_REF_JITTER : REAL;
C_PLL1_RESET_ON_LOSS_OF_LOCK : BOOLEAN;
C_PLL1_RST_DEASSERT_CLK : STRING;
C_PLL1_EXT_RESET_HIGH : INTEGER;
C_PLL1_FAMILY : STRING;
C_PLL1_CLKOUT0_DESKEW_ADJUST : STRING;
C_PLL1_CLKOUT1_DESKEW_ADJUST : STRING;
C_PLL1_CLKOUT2_DESKEW_ADJUST : STRING;
C_PLL1_CLKOUT3_DESKEW_ADJUST : STRING;
C_PLL1_CLKOUT4_DESKEW_ADJUST : STRING;
C_PLL1_CLKOUT5_DESKEW_ADJUST : STRING;
C_PLL1_CLKFBOUT_DESKEW_ADJUST : STRING;
C_PLL1_CLKIN1_BUF : BOOLEAN;
C_PLL1_CLKFBOUT_BUF : BOOLEAN;
C_PLL1_CLKOUT0_BUF : BOOLEAN;
C_PLL1_CLKOUT1_BUF : BOOLEAN;
C_PLL1_CLKOUT2_BUF : BOOLEAN;
C_PLL1_CLKOUT3_BUF : BOOLEAN;
C_PLL1_CLKOUT4_BUF : BOOLEAN;
C_PLL1_CLKOUT5_BUF : BOOLEAN;
C_PLL1_CLKIN1_MODULE : STRING;
C_PLL1_CLKIN1_PORT : STRING;
C_PLL1_CLKFBIN_MODULE : STRING;
C_PLL1_CLKFBIN_PORT : STRING;
C_PLL1_RST_MODULE : STRING;
C_DCM0_DFS_FREQUENCY_MODE : STRING;
C_DCM0_DLL_FREQUENCY_MODE : STRING;
C_DCM0_DUTY_CYCLE_CORRECTION : BOOLEAN;
C_DCM0_CLKIN_DIVIDE_BY_2 : BOOLEAN;
C_DCM0_CLK_FEEDBACK : STRING;
C_DCM0_CLKOUT_PHASE_SHIFT : STRING;
C_DCM0_DSS_MODE : STRING;
C_DCM0_STARTUP_WAIT : BOOLEAN;
C_DCM0_PHASE_SHIFT : INTEGER;
C_DCM0_CLKFX_MULTIPLY : INTEGER;
C_DCM0_CLKFX_DIVIDE : INTEGER;
C_DCM0_CLKDV_DIVIDE : REAL;
C_DCM0_CLKIN_PERIOD : REAL;
C_DCM0_DESKEW_ADJUST : STRING;
C_DCM0_CLKIN_BUF : BOOLEAN;
C_DCM0_CLKFB_BUF : BOOLEAN;
C_DCM0_CLK0_BUF : BOOLEAN;
C_DCM0_CLK90_BUF : BOOLEAN;
C_DCM0_CLK180_BUF : BOOLEAN;
C_DCM0_CLK270_BUF : BOOLEAN;
C_DCM0_CLKDV_BUF : BOOLEAN;
C_DCM0_CLKDV180_BUF : BOOLEAN;
C_DCM0_CLK2X_BUF : BOOLEAN;
C_DCM0_CLK2X180_BUF : BOOLEAN;
C_DCM0_CLKFX_BUF : BOOLEAN;
C_DCM0_CLKFX180_BUF : BOOLEAN;
C_DCM0_EXT_RESET_HIGH : INTEGER;
C_DCM0_FAMILY : STRING;
C_DCM0_CLKIN_MODULE : STRING;
C_DCM0_CLKIN_PORT : STRING;
C_DCM0_CLKFB_MODULE : STRING;
C_DCM0_CLKFB_PORT : STRING;
C_DCM0_RST_MODULE : STRING;
C_DCM1_DFS_FREQUENCY_MODE : STRING;
C_DCM1_DLL_FREQUENCY_MODE : STRING;
C_DCM1_DUTY_CYCLE_CORRECTION : BOOLEAN;
C_DCM1_CLKIN_DIVIDE_BY_2 : BOOLEAN;
C_DCM1_CLK_FEEDBACK : STRING;
C_DCM1_CLKOUT_PHASE_SHIFT : STRING;
C_DCM1_DSS_MODE : STRING;
C_DCM1_STARTUP_WAIT : BOOLEAN;
C_DCM1_PHASE_SHIFT : INTEGER;
C_DCM1_CLKFX_MULTIPLY : INTEGER;
C_DCM1_CLKFX_DIVIDE : INTEGER;
C_DCM1_CLKDV_DIVIDE : REAL;
C_DCM1_CLKIN_PERIOD : REAL;
C_DCM1_DESKEW_ADJUST : STRING;
C_DCM1_CLKIN_BUF : BOOLEAN;
C_DCM1_CLKFB_BUF : BOOLEAN;
C_DCM1_CLK0_BUF : BOOLEAN;
C_DCM1_CLK90_BUF : BOOLEAN;
C_DCM1_CLK180_BUF : BOOLEAN;
C_DCM1_CLK270_BUF : BOOLEAN;
C_DCM1_CLKDV_BUF : BOOLEAN;
C_DCM1_CLKDV180_BUF : BOOLEAN;
C_DCM1_CLK2X_BUF : BOOLEAN;
C_DCM1_CLK2X180_BUF : BOOLEAN;
C_DCM1_CLKFX_BUF : BOOLEAN;
C_DCM1_CLKFX180_BUF : BOOLEAN;
C_DCM1_EXT_RESET_HIGH : INTEGER;
C_DCM1_FAMILY : STRING;
C_DCM1_CLKIN_MODULE : STRING;
C_DCM1_CLKIN_PORT : STRING;
C_DCM1_CLKFB_MODULE : STRING;
C_DCM1_CLKFB_PORT : STRING;
C_DCM1_RST_MODULE : STRING;
C_DCM2_DFS_FREQUENCY_MODE : STRING;
C_DCM2_DLL_FREQUENCY_MODE : STRING;
C_DCM2_DUTY_CYCLE_CORRECTION : BOOLEAN;
C_DCM2_CLKIN_DIVIDE_BY_2 : BOOLEAN;
C_DCM2_CLK_FEEDBACK : STRING;
C_DCM2_CLKOUT_PHASE_SHIFT : STRING;
C_DCM2_DSS_MODE : STRING;
C_DCM2_STARTUP_WAIT : BOOLEAN;
C_DCM2_PHASE_SHIFT : INTEGER;
C_DCM2_CLKFX_MULTIPLY : INTEGER;
C_DCM2_CLKFX_DIVIDE : INTEGER;
C_DCM2_CLKDV_DIVIDE : REAL;
C_DCM2_CLKIN_PERIOD : REAL;
C_DCM2_DESKEW_ADJUST : STRING;
C_DCM2_CLKIN_BUF : BOOLEAN;
C_DCM2_CLKFB_BUF : BOOLEAN;
C_DCM2_CLK0_BUF : BOOLEAN;
C_DCM2_CLK90_BUF : BOOLEAN;
C_DCM2_CLK180_BUF : BOOLEAN;
C_DCM2_CLK270_BUF : BOOLEAN;
C_DCM2_CLKDV_BUF : BOOLEAN;
C_DCM2_CLKDV180_BUF : BOOLEAN;
C_DCM2_CLK2X_BUF : BOOLEAN;
C_DCM2_CLK2X180_BUF : BOOLEAN;
C_DCM2_CLKFX_BUF : BOOLEAN;
C_DCM2_CLKFX180_BUF : BOOLEAN;
C_DCM2_EXT_RESET_HIGH : INTEGER;
C_DCM2_FAMILY : STRING;
C_DCM2_CLKIN_MODULE : STRING;
C_DCM2_CLKIN_PORT : STRING;
C_DCM2_CLKFB_MODULE : STRING;
C_DCM2_CLKFB_PORT : STRING;
C_DCM2_RST_MODULE : STRING;
C_DCM3_DFS_FREQUENCY_MODE : STRING;
C_DCM3_DLL_FREQUENCY_MODE : STRING;
C_DCM3_DUTY_CYCLE_CORRECTION : BOOLEAN;
C_DCM3_CLKIN_DIVIDE_BY_2 : BOOLEAN;
C_DCM3_CLK_FEEDBACK : STRING;
C_DCM3_CLKOUT_PHASE_SHIFT : STRING;
C_DCM3_DSS_MODE : STRING;
C_DCM3_STARTUP_WAIT : BOOLEAN;
C_DCM3_PHASE_SHIFT : INTEGER;
C_DCM3_CLKFX_MULTIPLY : INTEGER;
C_DCM3_CLKFX_DIVIDE : INTEGER;
C_DCM3_CLKDV_DIVIDE : REAL;
C_DCM3_CLKIN_PERIOD : REAL;
C_DCM3_DESKEW_ADJUST : STRING;
C_DCM3_CLKIN_BUF : BOOLEAN;
C_DCM3_CLKFB_BUF : BOOLEAN;
C_DCM3_CLK0_BUF : BOOLEAN;
C_DCM3_CLK90_BUF : BOOLEAN;
C_DCM3_CLK180_BUF : BOOLEAN;
C_DCM3_CLK270_BUF : BOOLEAN;
C_DCM3_CLKDV_BUF : BOOLEAN;
C_DCM3_CLKDV180_BUF : BOOLEAN;
C_DCM3_CLK2X_BUF : BOOLEAN;
C_DCM3_CLK2X180_BUF : BOOLEAN;
C_DCM3_CLKFX_BUF : BOOLEAN;
C_DCM3_CLKFX180_BUF : BOOLEAN;
C_DCM3_EXT_RESET_HIGH : INTEGER;
C_DCM3_FAMILY : STRING;
C_DCM3_CLKIN_MODULE : STRING;
C_DCM3_CLKIN_PORT : STRING;
C_DCM3_CLKFB_MODULE : STRING;
C_DCM3_CLKFB_PORT : STRING;
C_DCM3_RST_MODULE : STRING;
C_MMCM0_BANDWIDTH : STRING;
C_MMCM0_CLKFBOUT_MULT_F : REAL;
C_MMCM0_CLKFBOUT_PHASE : REAL;
C_MMCM0_CLKFBOUT_USE_FINE_PS : BOOLEAN;
C_MMCM0_CLKIN1_PERIOD : REAL;
C_MMCM0_CLKOUT0_DIVIDE_F : REAL;
C_MMCM0_CLKOUT0_DUTY_CYCLE : REAL;
C_MMCM0_CLKOUT0_PHASE : REAL;
C_MMCM0_CLKOUT1_DIVIDE : INTEGER;
C_MMCM0_CLKOUT1_DUTY_CYCLE : REAL;
C_MMCM0_CLKOUT1_PHASE : REAL;
C_MMCM0_CLKOUT2_DIVIDE : INTEGER;
C_MMCM0_CLKOUT2_DUTY_CYCLE : REAL;
C_MMCM0_CLKOUT2_PHASE : REAL;
C_MMCM0_CLKOUT3_DIVIDE : INTEGER;
C_MMCM0_CLKOUT3_DUTY_CYCLE : REAL;
C_MMCM0_CLKOUT3_PHASE : REAL;
C_MMCM0_CLKOUT4_DIVIDE : INTEGER;
C_MMCM0_CLKOUT4_DUTY_CYCLE : REAL;
C_MMCM0_CLKOUT4_PHASE : REAL;
C_MMCM0_CLKOUT4_CASCADE : BOOLEAN;
C_MMCM0_CLKOUT5_DIVIDE : INTEGER;
C_MMCM0_CLKOUT5_DUTY_CYCLE : REAL;
C_MMCM0_CLKOUT5_PHASE : REAL;
C_MMCM0_CLKOUT6_DIVIDE : INTEGER;
C_MMCM0_CLKOUT6_DUTY_CYCLE : REAL;
C_MMCM0_CLKOUT6_PHASE : REAL;
C_MMCM0_CLKOUT0_USE_FINE_PS : BOOLEAN;
C_MMCM0_CLKOUT1_USE_FINE_PS : BOOLEAN;
C_MMCM0_CLKOUT2_USE_FINE_PS : BOOLEAN;
C_MMCM0_CLKOUT3_USE_FINE_PS : BOOLEAN;
C_MMCM0_CLKOUT4_USE_FINE_PS : BOOLEAN;
C_MMCM0_CLKOUT5_USE_FINE_PS : BOOLEAN;
C_MMCM0_CLKOUT6_USE_FINE_PS : BOOLEAN;
C_MMCM0_COMPENSATION : STRING;
C_MMCM0_DIVCLK_DIVIDE : INTEGER;
C_MMCM0_REF_JITTER1 : REAL;
C_MMCM0_CLKIN1_BUF : BOOLEAN;
C_MMCM0_CLKFBOUT_BUF : BOOLEAN;
C_MMCM0_CLOCK_HOLD : BOOLEAN;
C_MMCM0_STARTUP_WAIT : BOOLEAN;
C_MMCM0_EXT_RESET_HIGH : INTEGER;
C_MMCM0_FAMILY : STRING;
C_MMCM0_CLKOUT0_BUF : BOOLEAN;
C_MMCM0_CLKOUT1_BUF : BOOLEAN;
C_MMCM0_CLKOUT2_BUF : BOOLEAN;
C_MMCM0_CLKOUT3_BUF : BOOLEAN;
C_MMCM0_CLKOUT4_BUF : BOOLEAN;
C_MMCM0_CLKOUT5_BUF : BOOLEAN;
C_MMCM0_CLKOUT6_BUF : BOOLEAN;
C_MMCM0_CLKIN1_MODULE : STRING;
C_MMCM0_CLKIN1_PORT : STRING;
C_MMCM0_CLKFBIN_MODULE : STRING;
C_MMCM0_CLKFBIN_PORT : STRING;
C_MMCM0_RST_MODULE : STRING;
C_MMCM1_BANDWIDTH : STRING;
C_MMCM1_CLKFBOUT_MULT_F : REAL;
C_MMCM1_CLKFBOUT_PHASE : REAL;
C_MMCM1_CLKFBOUT_USE_FINE_PS : BOOLEAN;
C_MMCM1_CLKIN1_PERIOD : REAL;
C_MMCM1_CLKOUT0_DIVIDE_F : REAL;
C_MMCM1_CLKOUT0_DUTY_CYCLE : REAL;
C_MMCM1_CLKOUT0_PHASE : REAL;
C_MMCM1_CLKOUT1_DIVIDE : INTEGER;
C_MMCM1_CLKOUT1_DUTY_CYCLE : REAL;
C_MMCM1_CLKOUT1_PHASE : REAL;
C_MMCM1_CLKOUT2_DIVIDE : INTEGER;
C_MMCM1_CLKOUT2_DUTY_CYCLE : REAL;
C_MMCM1_CLKOUT2_PHASE : REAL;
C_MMCM1_CLKOUT3_DIVIDE : INTEGER;
C_MMCM1_CLKOUT3_DUTY_CYCLE : REAL;
C_MMCM1_CLKOUT3_PHASE : REAL;
C_MMCM1_CLKOUT4_DIVIDE : INTEGER;
C_MMCM1_CLKOUT4_DUTY_CYCLE : REAL;
C_MMCM1_CLKOUT4_PHASE : REAL;
C_MMCM1_CLKOUT4_CASCADE : BOOLEAN;
C_MMCM1_CLKOUT5_DIVIDE : INTEGER;
C_MMCM1_CLKOUT5_DUTY_CYCLE : REAL;
C_MMCM1_CLKOUT5_PHASE : REAL;
C_MMCM1_CLKOUT6_DIVIDE : INTEGER;
C_MMCM1_CLKOUT6_DUTY_CYCLE : REAL;
C_MMCM1_CLKOUT6_PHASE : REAL;
C_MMCM1_CLKOUT0_USE_FINE_PS : BOOLEAN;
C_MMCM1_CLKOUT1_USE_FINE_PS : BOOLEAN;
C_MMCM1_CLKOUT2_USE_FINE_PS : BOOLEAN;
C_MMCM1_CLKOUT3_USE_FINE_PS : BOOLEAN;
C_MMCM1_CLKOUT4_USE_FINE_PS : BOOLEAN;
C_MMCM1_CLKOUT5_USE_FINE_PS : BOOLEAN;
C_MMCM1_CLKOUT6_USE_FINE_PS : BOOLEAN;
C_MMCM1_COMPENSATION : STRING;
C_MMCM1_DIVCLK_DIVIDE : INTEGER;
C_MMCM1_REF_JITTER1 : REAL;
C_MMCM1_CLKIN1_BUF : BOOLEAN;
C_MMCM1_CLKFBOUT_BUF : BOOLEAN;
C_MMCM1_CLOCK_HOLD : BOOLEAN;
C_MMCM1_STARTUP_WAIT : BOOLEAN;
C_MMCM1_EXT_RESET_HIGH : INTEGER;
C_MMCM1_FAMILY : STRING;
C_MMCM1_CLKOUT0_BUF : BOOLEAN;
C_MMCM1_CLKOUT1_BUF : BOOLEAN;
C_MMCM1_CLKOUT2_BUF : BOOLEAN;
C_MMCM1_CLKOUT3_BUF : BOOLEAN;
C_MMCM1_CLKOUT4_BUF : BOOLEAN;
C_MMCM1_CLKOUT5_BUF : BOOLEAN;
C_MMCM1_CLKOUT6_BUF : BOOLEAN;
C_MMCM1_CLKIN1_MODULE : STRING;
C_MMCM1_CLKIN1_PORT : STRING;
C_MMCM1_CLKFBIN_MODULE : STRING;
C_MMCM1_CLKFBIN_PORT : STRING;
C_MMCM1_RST_MODULE : STRING;
C_MMCM2_BANDWIDTH : STRING;
C_MMCM2_CLKFBOUT_MULT_F : REAL;
C_MMCM2_CLKFBOUT_PHASE : REAL;
C_MMCM2_CLKFBOUT_USE_FINE_PS : BOOLEAN;
C_MMCM2_CLKIN1_PERIOD : REAL;
C_MMCM2_CLKOUT0_DIVIDE_F : REAL;
C_MMCM2_CLKOUT0_DUTY_CYCLE : REAL;
C_MMCM2_CLKOUT0_PHASE : REAL;
C_MMCM2_CLKOUT1_DIVIDE : INTEGER;
C_MMCM2_CLKOUT1_DUTY_CYCLE : REAL;
C_MMCM2_CLKOUT1_PHASE : REAL;
C_MMCM2_CLKOUT2_DIVIDE : INTEGER;
C_MMCM2_CLKOUT2_DUTY_CYCLE : REAL;
C_MMCM2_CLKOUT2_PHASE : REAL;
C_MMCM2_CLKOUT3_DIVIDE : INTEGER;
C_MMCM2_CLKOUT3_DUTY_CYCLE : REAL;
C_MMCM2_CLKOUT3_PHASE : REAL;
C_MMCM2_CLKOUT4_DIVIDE : INTEGER;
C_MMCM2_CLKOUT4_DUTY_CYCLE : REAL;
C_MMCM2_CLKOUT4_PHASE : REAL;
C_MMCM2_CLKOUT4_CASCADE : BOOLEAN;
C_MMCM2_CLKOUT5_DIVIDE : INTEGER;
C_MMCM2_CLKOUT5_DUTY_CYCLE : REAL;
C_MMCM2_CLKOUT5_PHASE : REAL;
C_MMCM2_CLKOUT6_DIVIDE : INTEGER;
C_MMCM2_CLKOUT6_DUTY_CYCLE : REAL;
C_MMCM2_CLKOUT6_PHASE : REAL;
C_MMCM2_CLKOUT0_USE_FINE_PS : BOOLEAN;
C_MMCM2_CLKOUT1_USE_FINE_PS : BOOLEAN;
C_MMCM2_CLKOUT2_USE_FINE_PS : BOOLEAN;
C_MMCM2_CLKOUT3_USE_FINE_PS : BOOLEAN;
C_MMCM2_CLKOUT4_USE_FINE_PS : BOOLEAN;
C_MMCM2_CLKOUT5_USE_FINE_PS : BOOLEAN;
C_MMCM2_CLKOUT6_USE_FINE_PS : BOOLEAN;
C_MMCM2_COMPENSATION : STRING;
C_MMCM2_DIVCLK_DIVIDE : INTEGER;
C_MMCM2_REF_JITTER1 : REAL;
C_MMCM2_CLKIN1_BUF : BOOLEAN;
C_MMCM2_CLKFBOUT_BUF : BOOLEAN;
C_MMCM2_CLOCK_HOLD : BOOLEAN;
C_MMCM2_STARTUP_WAIT : BOOLEAN;
C_MMCM2_EXT_RESET_HIGH : INTEGER;
C_MMCM2_FAMILY : STRING;
C_MMCM2_CLKOUT0_BUF : BOOLEAN;
C_MMCM2_CLKOUT1_BUF : BOOLEAN;
C_MMCM2_CLKOUT2_BUF : BOOLEAN;
C_MMCM2_CLKOUT3_BUF : BOOLEAN;
C_MMCM2_CLKOUT4_BUF : BOOLEAN;
C_MMCM2_CLKOUT5_BUF : BOOLEAN;
C_MMCM2_CLKOUT6_BUF : BOOLEAN;
C_MMCM2_CLKIN1_MODULE : STRING;
C_MMCM2_CLKIN1_PORT : STRING;
C_MMCM2_CLKFBIN_MODULE : STRING;
C_MMCM2_CLKFBIN_PORT : STRING;
C_MMCM2_RST_MODULE : STRING;
C_MMCM3_BANDWIDTH : STRING;
C_MMCM3_CLKFBOUT_MULT_F : REAL;
C_MMCM3_CLKFBOUT_PHASE : REAL;
C_MMCM3_CLKFBOUT_USE_FINE_PS : BOOLEAN;
C_MMCM3_CLKIN1_PERIOD : REAL;
C_MMCM3_CLKOUT0_DIVIDE_F : REAL;
C_MMCM3_CLKOUT0_DUTY_CYCLE : REAL;
C_MMCM3_CLKOUT0_PHASE : REAL;
C_MMCM3_CLKOUT1_DIVIDE : INTEGER;
C_MMCM3_CLKOUT1_DUTY_CYCLE : REAL;
C_MMCM3_CLKOUT1_PHASE : REAL;
C_MMCM3_CLKOUT2_DIVIDE : INTEGER;
C_MMCM3_CLKOUT2_DUTY_CYCLE : REAL;
C_MMCM3_CLKOUT2_PHASE : REAL;
C_MMCM3_CLKOUT3_DIVIDE : INTEGER;
C_MMCM3_CLKOUT3_DUTY_CYCLE : REAL;
C_MMCM3_CLKOUT3_PHASE : REAL;
C_MMCM3_CLKOUT4_DIVIDE : INTEGER;
C_MMCM3_CLKOUT4_DUTY_CYCLE : REAL;
C_MMCM3_CLKOUT4_PHASE : REAL;
C_MMCM3_CLKOUT4_CASCADE : BOOLEAN;
C_MMCM3_CLKOUT5_DIVIDE : INTEGER;
C_MMCM3_CLKOUT5_DUTY_CYCLE : REAL;
C_MMCM3_CLKOUT5_PHASE : REAL;
C_MMCM3_CLKOUT6_DIVIDE : INTEGER;
C_MMCM3_CLKOUT6_DUTY_CYCLE : REAL;
C_MMCM3_CLKOUT6_PHASE : REAL;
C_MMCM3_CLKOUT0_USE_FINE_PS : BOOLEAN;
C_MMCM3_CLKOUT1_USE_FINE_PS : BOOLEAN;
C_MMCM3_CLKOUT2_USE_FINE_PS : BOOLEAN;
C_MMCM3_CLKOUT3_USE_FINE_PS : BOOLEAN;
C_MMCM3_CLKOUT4_USE_FINE_PS : BOOLEAN;
C_MMCM3_CLKOUT5_USE_FINE_PS : BOOLEAN;
C_MMCM3_CLKOUT6_USE_FINE_PS : BOOLEAN;
C_MMCM3_COMPENSATION : STRING;
C_MMCM3_DIVCLK_DIVIDE : INTEGER;
C_MMCM3_REF_JITTER1 : REAL;
C_MMCM3_CLKIN1_BUF : BOOLEAN;
C_MMCM3_CLKFBOUT_BUF : BOOLEAN;
C_MMCM3_CLOCK_HOLD : BOOLEAN;
C_MMCM3_STARTUP_WAIT : BOOLEAN;
C_MMCM3_EXT_RESET_HIGH : INTEGER;
C_MMCM3_FAMILY : STRING;
C_MMCM3_CLKOUT0_BUF : BOOLEAN;
C_MMCM3_CLKOUT1_BUF : BOOLEAN;
C_MMCM3_CLKOUT2_BUF : BOOLEAN;
C_MMCM3_CLKOUT3_BUF : BOOLEAN;
C_MMCM3_CLKOUT4_BUF : BOOLEAN;
C_MMCM3_CLKOUT5_BUF : BOOLEAN;
C_MMCM3_CLKOUT6_BUF : BOOLEAN;
C_MMCM3_CLKIN1_MODULE : STRING;
C_MMCM3_CLKIN1_PORT : STRING;
C_MMCM3_CLKFBIN_MODULE : STRING;
C_MMCM3_CLKFBIN_PORT : STRING;
C_MMCM3_RST_MODULE : STRING
);
port (
CLKIN : in std_logic;
CLKFBIN : in std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUT6 : out std_logic;
CLKOUT7 : out std_logic;
CLKOUT8 : out std_logic;
CLKOUT9 : out std_logic;
CLKOUT10 : out std_logic;
CLKOUT11 : out std_logic;
CLKOUT12 : out std_logic;
CLKOUT13 : out std_logic;
CLKOUT14 : out std_logic;
CLKOUT15 : out std_logic;
CLKFBOUT : out std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSDONE : out std_logic;
RST : in std_logic;
LOCKED : out std_logic
);
end component;
begin
clock_generator_0 : clock_generator
generic map (
C_FAMILY => "virtex5",
C_SPEEDGRADE => "-1",
C_EXT_RESET_HIGH => 0,
C_CLK_GEN => "PASSED",
C_CLKOUT0_MODULE => "PLL0",
C_CLKOUT0_PORT => "CLKOUT0B",
C_CLKOUT1_MODULE => "PLL0",
C_CLKOUT1_PORT => "CLKOUT1B",
C_CLKOUT2_MODULE => "PLL0",
C_CLKOUT2_PORT => "CLKOUT2B",
C_CLKOUT3_MODULE => "PLL0",
C_CLKOUT3_PORT => "CLKOUT3B",
C_CLKOUT4_MODULE => "NONE",
C_CLKOUT4_PORT => "NONE",
C_CLKOUT5_MODULE => "NONE",
C_CLKOUT5_PORT => "NONE",
C_CLKOUT6_MODULE => "NONE",
C_CLKOUT6_PORT => "NONE",
C_CLKOUT7_MODULE => "NONE",
C_CLKOUT7_PORT => "NONE",
C_CLKOUT8_MODULE => "NONE",
C_CLKOUT8_PORT => "NONE",
C_CLKOUT9_MODULE => "NONE",
C_CLKOUT9_PORT => "NONE",
C_CLKOUT10_MODULE => "NONE",
C_CLKOUT10_PORT => "NONE",
C_CLKOUT11_MODULE => "NONE",
C_CLKOUT11_PORT => "NONE",
C_CLKOUT12_MODULE => "NONE",
C_CLKOUT12_PORT => "NONE",
C_CLKOUT13_MODULE => "NONE",
C_CLKOUT13_PORT => "NONE",
C_CLKOUT14_MODULE => "NONE",
C_CLKOUT14_PORT => "NONE",
C_CLKOUT15_MODULE => "NONE",
C_CLKOUT15_PORT => "NONE",
C_CLKFBOUT_MODULE => "NONE",
C_CLKFBOUT_PORT => "NONE",
C_PSDONE_MODULE => "NONE",
C_PLL0_DIVCLK_DIVIDE => 1,
C_PLL0_CLKFBOUT_MULT => 10,
C_PLL0_CLKFBOUT_PHASE => 0.000000,
C_PLL0_CLKIN1_PERIOD => 10.000000,
C_PLL0_CLKOUT0_DIVIDE => 8,
C_PLL0_CLKOUT0_DUTY_CYCLE => 0.500000,
C_PLL0_CLKOUT0_PHASE => 90.000000,
C_PLL0_CLKOUT1_DIVIDE => 8,
C_PLL0_CLKOUT1_DUTY_CYCLE => 0.500000,
C_PLL0_CLKOUT1_PHASE => 0.000000,
C_PLL0_CLKOUT2_DIVIDE => 5,
C_PLL0_CLKOUT2_DUTY_CYCLE => 0.500000,
C_PLL0_CLKOUT2_PHASE => 0.000000,
C_PLL0_CLKOUT3_DIVIDE => 4,
C_PLL0_CLKOUT3_DUTY_CYCLE => 0.500000,
C_PLL0_CLKOUT3_PHASE => 0.000000,
C_PLL0_CLKOUT4_DIVIDE => 1,
C_PLL0_CLKOUT4_DUTY_CYCLE => 0.500000,
C_PLL0_CLKOUT4_PHASE => 0.000000,
C_PLL0_CLKOUT5_DIVIDE => 1,
C_PLL0_CLKOUT5_DUTY_CYCLE => 0.500000,
C_PLL0_CLKOUT5_PHASE => 0.000000,
C_PLL0_BANDWIDTH => "OPTIMIZED",
C_PLL0_COMPENSATION => "SYSTEM_SYNCHRONOUS",
C_PLL0_REF_JITTER => 0.100000,
C_PLL0_RESET_ON_LOSS_OF_LOCK => false,
C_PLL0_RST_DEASSERT_CLK => "CLKIN1",
C_PLL0_EXT_RESET_HIGH => 0,
C_PLL0_FAMILY => "virtex5",
C_PLL0_CLKOUT0_DESKEW_ADJUST => "PPC",
C_PLL0_CLKOUT1_DESKEW_ADJUST => "PPC",
C_PLL0_CLKOUT2_DESKEW_ADJUST => "NONE",
C_PLL0_CLKOUT3_DESKEW_ADJUST => "NONE",
C_PLL0_CLKOUT4_DESKEW_ADJUST => "NONE",
C_PLL0_CLKOUT5_DESKEW_ADJUST => "NONE",
C_PLL0_CLKFBOUT_DESKEW_ADJUST => "NONE",
C_PLL0_CLKIN1_BUF => false,
C_PLL0_CLKFBOUT_BUF => TRUE,
C_PLL0_CLKOUT0_BUF => TRUE,
C_PLL0_CLKOUT1_BUF => TRUE,
C_PLL0_CLKOUT2_BUF => TRUE,
C_PLL0_CLKOUT3_BUF => TRUE,
C_PLL0_CLKOUT4_BUF => false,
C_PLL0_CLKOUT5_BUF => false,
C_PLL0_CLKIN1_MODULE => "CLKGEN",
C_PLL0_CLKIN1_PORT => "CLKIN",
C_PLL0_CLKFBIN_MODULE => "PLL0",
C_PLL0_CLKFBIN_PORT => "CLKFBOUT",
C_PLL0_RST_MODULE => "CLKGEN",
C_PLL1_DIVCLK_DIVIDE => 1,
C_PLL1_CLKFBOUT_MULT => 1,
C_PLL1_CLKFBOUT_PHASE => 0.000000,
C_PLL1_CLKIN1_PERIOD => 0.000000,
C_PLL1_CLKOUT0_DIVIDE => 1,
C_PLL1_CLKOUT0_DUTY_CYCLE => 0.500000,
C_PLL1_CLKOUT0_PHASE => 0.000000,
C_PLL1_CLKOUT1_DIVIDE => 1,
C_PLL1_CLKOUT1_DUTY_CYCLE => 0.500000,
C_PLL1_CLKOUT1_PHASE => 0.000000,
C_PLL1_CLKOUT2_DIVIDE => 1,
C_PLL1_CLKOUT2_DUTY_CYCLE => 0.500000,
C_PLL1_CLKOUT2_PHASE => 0.000000,
C_PLL1_CLKOUT3_DIVIDE => 1,
C_PLL1_CLKOUT3_DUTY_CYCLE => 0.500000,
C_PLL1_CLKOUT3_PHASE => 0.000000,
C_PLL1_CLKOUT4_DIVIDE => 1,
C_PLL1_CLKOUT4_DUTY_CYCLE => 0.500000,
C_PLL1_CLKOUT4_PHASE => 0.000000,
C_PLL1_CLKOUT5_DIVIDE => 1,
C_PLL1_CLKOUT5_DUTY_CYCLE => 0.500000,
C_PLL1_CLKOUT5_PHASE => 0.000000,
C_PLL1_BANDWIDTH => "OPTIMIZED",
C_PLL1_COMPENSATION => "SYSTEM_SYNCHRONOUS",
C_PLL1_REF_JITTER => 0.100000,
C_PLL1_RESET_ON_LOSS_OF_LOCK => false,
C_PLL1_RST_DEASSERT_CLK => "CLKIN1",
C_PLL1_EXT_RESET_HIGH => 1,
C_PLL1_FAMILY => "virtex5",
C_PLL1_CLKOUT0_DESKEW_ADJUST => "NONE",
C_PLL1_CLKOUT1_DESKEW_ADJUST => "NONE",
C_PLL1_CLKOUT2_DESKEW_ADJUST => "NONE",
C_PLL1_CLKOUT3_DESKEW_ADJUST => "NONE",
C_PLL1_CLKOUT4_DESKEW_ADJUST => "NONE",
C_PLL1_CLKOUT5_DESKEW_ADJUST => "NONE",
C_PLL1_CLKFBOUT_DESKEW_ADJUST => "NONE",
C_PLL1_CLKIN1_BUF => false,
C_PLL1_CLKFBOUT_BUF => false,
C_PLL1_CLKOUT0_BUF => false,
C_PLL1_CLKOUT1_BUF => false,
C_PLL1_CLKOUT2_BUF => false,
C_PLL1_CLKOUT3_BUF => false,
C_PLL1_CLKOUT4_BUF => false,
C_PLL1_CLKOUT5_BUF => false,
C_PLL1_CLKIN1_MODULE => "NONE",
C_PLL1_CLKIN1_PORT => "NONE",
C_PLL1_CLKFBIN_MODULE => "NONE",
C_PLL1_CLKFBIN_PORT => "NONE",
C_PLL1_RST_MODULE => "NONE",
C_DCM0_DFS_FREQUENCY_MODE => "LOW",
C_DCM0_DLL_FREQUENCY_MODE => "LOW",
C_DCM0_DUTY_CYCLE_CORRECTION => true,
C_DCM0_CLKIN_DIVIDE_BY_2 => false,
C_DCM0_CLK_FEEDBACK => "1X",
C_DCM0_CLKOUT_PHASE_SHIFT => "NONE",
C_DCM0_DSS_MODE => "NONE",
C_DCM0_STARTUP_WAIT => false,
C_DCM0_PHASE_SHIFT => 0,
C_DCM0_CLKFX_MULTIPLY => 4,
C_DCM0_CLKFX_DIVIDE => 1,
C_DCM0_CLKDV_DIVIDE => 2.000000,
C_DCM0_CLKIN_PERIOD => 0.000000,
C_DCM0_DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
C_DCM0_CLKIN_BUF => false,
C_DCM0_CLKFB_BUF => false,
C_DCM0_CLK0_BUF => false,
C_DCM0_CLK90_BUF => false,
C_DCM0_CLK180_BUF => false,
C_DCM0_CLK270_BUF => false,
C_DCM0_CLKDV_BUF => false,
C_DCM0_CLKDV180_BUF => false,
C_DCM0_CLK2X_BUF => false,
C_DCM0_CLK2X180_BUF => false,
C_DCM0_CLKFX_BUF => false,
C_DCM0_CLKFX180_BUF => false,
C_DCM0_EXT_RESET_HIGH => 1,
C_DCM0_FAMILY => "virtex5",
C_DCM0_CLKIN_MODULE => "NONE",
C_DCM0_CLKIN_PORT => "NONE",
C_DCM0_CLKFB_MODULE => "NONE",
C_DCM0_CLKFB_PORT => "NONE",
C_DCM0_RST_MODULE => "NONE",
C_DCM1_DFS_FREQUENCY_MODE => "LOW",
C_DCM1_DLL_FREQUENCY_MODE => "LOW",
C_DCM1_DUTY_CYCLE_CORRECTION => true,
C_DCM1_CLKIN_DIVIDE_BY_2 => false,
C_DCM1_CLK_FEEDBACK => "1X",
C_DCM1_CLKOUT_PHASE_SHIFT => "NONE",
C_DCM1_DSS_MODE => "NONE",
C_DCM1_STARTUP_WAIT => false,
C_DCM1_PHASE_SHIFT => 0,
C_DCM1_CLKFX_MULTIPLY => 4,
C_DCM1_CLKFX_DIVIDE => 1,
C_DCM1_CLKDV_DIVIDE => 2.000000,
C_DCM1_CLKIN_PERIOD => 0.000000,
C_DCM1_DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
C_DCM1_CLKIN_BUF => false,
C_DCM1_CLKFB_BUF => false,
C_DCM1_CLK0_BUF => false,
C_DCM1_CLK90_BUF => false,
C_DCM1_CLK180_BUF => false,
C_DCM1_CLK270_BUF => false,
C_DCM1_CLKDV_BUF => false,
C_DCM1_CLKDV180_BUF => false,
C_DCM1_CLK2X_BUF => false,
C_DCM1_CLK2X180_BUF => false,
C_DCM1_CLKFX_BUF => false,
C_DCM1_CLKFX180_BUF => false,
C_DCM1_EXT_RESET_HIGH => 1,
C_DCM1_FAMILY => "virtex5",
C_DCM1_CLKIN_MODULE => "NONE",
C_DCM1_CLKIN_PORT => "NONE",
C_DCM1_CLKFB_MODULE => "NONE",
C_DCM1_CLKFB_PORT => "NONE",
C_DCM1_RST_MODULE => "NONE",
C_DCM2_DFS_FREQUENCY_MODE => "LOW",
C_DCM2_DLL_FREQUENCY_MODE => "LOW",
C_DCM2_DUTY_CYCLE_CORRECTION => true,
C_DCM2_CLKIN_DIVIDE_BY_2 => false,
C_DCM2_CLK_FEEDBACK => "1X",
C_DCM2_CLKOUT_PHASE_SHIFT => "NONE",
C_DCM2_DSS_MODE => "NONE",
C_DCM2_STARTUP_WAIT => false,
C_DCM2_PHASE_SHIFT => 0,
C_DCM2_CLKFX_MULTIPLY => 4,
C_DCM2_CLKFX_DIVIDE => 1,
C_DCM2_CLKDV_DIVIDE => 2.000000,
C_DCM2_CLKIN_PERIOD => 0.000000,
C_DCM2_DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
C_DCM2_CLKIN_BUF => false,
C_DCM2_CLKFB_BUF => false,
C_DCM2_CLK0_BUF => false,
C_DCM2_CLK90_BUF => false,
C_DCM2_CLK180_BUF => false,
C_DCM2_CLK270_BUF => false,
C_DCM2_CLKDV_BUF => false,
C_DCM2_CLKDV180_BUF => false,
C_DCM2_CLK2X_BUF => false,
C_DCM2_CLK2X180_BUF => false,
C_DCM2_CLKFX_BUF => false,
C_DCM2_CLKFX180_BUF => false,
C_DCM2_EXT_RESET_HIGH => 1,
C_DCM2_FAMILY => "virtex5",
C_DCM2_CLKIN_MODULE => "NONE",
C_DCM2_CLKIN_PORT => "NONE",
C_DCM2_CLKFB_MODULE => "NONE",
C_DCM2_CLKFB_PORT => "NONE",
C_DCM2_RST_MODULE => "NONE",
C_DCM3_DFS_FREQUENCY_MODE => "LOW",
C_DCM3_DLL_FREQUENCY_MODE => "LOW",
C_DCM3_DUTY_CYCLE_CORRECTION => true,
C_DCM3_CLKIN_DIVIDE_BY_2 => false,
C_DCM3_CLK_FEEDBACK => "1X",
C_DCM3_CLKOUT_PHASE_SHIFT => "NONE",
C_DCM3_DSS_MODE => "NONE",
C_DCM3_STARTUP_WAIT => false,
C_DCM3_PHASE_SHIFT => 0,
C_DCM3_CLKFX_MULTIPLY => 4,
C_DCM3_CLKFX_DIVIDE => 1,
C_DCM3_CLKDV_DIVIDE => 2.000000,
C_DCM3_CLKIN_PERIOD => 0.000000,
C_DCM3_DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
C_DCM3_CLKIN_BUF => false,
C_DCM3_CLKFB_BUF => false,
C_DCM3_CLK0_BUF => false,
C_DCM3_CLK90_BUF => false,
C_DCM3_CLK180_BUF => false,
C_DCM3_CLK270_BUF => false,
C_DCM3_CLKDV_BUF => false,
C_DCM3_CLKDV180_BUF => false,
C_DCM3_CLK2X_BUF => false,
C_DCM3_CLK2X180_BUF => false,
C_DCM3_CLKFX_BUF => false,
C_DCM3_CLKFX180_BUF => false,
C_DCM3_EXT_RESET_HIGH => 1,
C_DCM3_FAMILY => "virtex5",
C_DCM3_CLKIN_MODULE => "NONE",
C_DCM3_CLKIN_PORT => "NONE",
C_DCM3_CLKFB_MODULE => "NONE",
C_DCM3_CLKFB_PORT => "NONE",
C_DCM3_RST_MODULE => "NONE",
C_MMCM0_BANDWIDTH => "OPTIMIZED",
C_MMCM0_CLKFBOUT_MULT_F => 1.000000,
C_MMCM0_CLKFBOUT_PHASE => 0.000000,
C_MMCM0_CLKFBOUT_USE_FINE_PS => false,
C_MMCM0_CLKIN1_PERIOD => 0.000000,
C_MMCM0_CLKOUT0_DIVIDE_F => 1.000000,
C_MMCM0_CLKOUT0_DUTY_CYCLE => 0.500000,
C_MMCM0_CLKOUT0_PHASE => 0.000000,
C_MMCM0_CLKOUT1_DIVIDE => 1,
C_MMCM0_CLKOUT1_DUTY_CYCLE => 0.500000,
C_MMCM0_CLKOUT1_PHASE => 0.000000,
C_MMCM0_CLKOUT2_DIVIDE => 1,
C_MMCM0_CLKOUT2_DUTY_CYCLE => 0.500000,
C_MMCM0_CLKOUT2_PHASE => 0.000000,
C_MMCM0_CLKOUT3_DIVIDE => 1,
C_MMCM0_CLKOUT3_DUTY_CYCLE => 0.500000,
C_MMCM0_CLKOUT3_PHASE => 0.000000,
C_MMCM0_CLKOUT4_DIVIDE => 1,
C_MMCM0_CLKOUT4_DUTY_CYCLE => 0.500000,
C_MMCM0_CLKOUT4_PHASE => 0.000000,
C_MMCM0_CLKOUT4_CASCADE => false,
C_MMCM0_CLKOUT5_DIVIDE => 1,
C_MMCM0_CLKOUT5_DUTY_CYCLE => 0.500000,
C_MMCM0_CLKOUT5_PHASE => 0.000000,
C_MMCM0_CLKOUT6_DIVIDE => 1,
C_MMCM0_CLKOUT6_DUTY_CYCLE => 0.500000,
C_MMCM0_CLKOUT6_PHASE => 0.000000,
C_MMCM0_CLKOUT0_USE_FINE_PS => false,
C_MMCM0_CLKOUT1_USE_FINE_PS => false,
C_MMCM0_CLKOUT2_USE_FINE_PS => false,
C_MMCM0_CLKOUT3_USE_FINE_PS => false,
C_MMCM0_CLKOUT4_USE_FINE_PS => false,
C_MMCM0_CLKOUT5_USE_FINE_PS => false,
C_MMCM0_CLKOUT6_USE_FINE_PS => false,
C_MMCM0_COMPENSATION => "ZHOLD",
C_MMCM0_DIVCLK_DIVIDE => 1,
C_MMCM0_REF_JITTER1 => 0.010000,
C_MMCM0_CLKIN1_BUF => false,
C_MMCM0_CLKFBOUT_BUF => false,
C_MMCM0_CLOCK_HOLD => false,
C_MMCM0_STARTUP_WAIT => false,
C_MMCM0_EXT_RESET_HIGH => 1,
C_MMCM0_FAMILY => "virtex5",
C_MMCM0_CLKOUT0_BUF => false,
C_MMCM0_CLKOUT1_BUF => false,
C_MMCM0_CLKOUT2_BUF => false,
C_MMCM0_CLKOUT3_BUF => false,
C_MMCM0_CLKOUT4_BUF => false,
C_MMCM0_CLKOUT5_BUF => false,
C_MMCM0_CLKOUT6_BUF => false,
C_MMCM0_CLKIN1_MODULE => "NONE",
C_MMCM0_CLKIN1_PORT => "NONE",
C_MMCM0_CLKFBIN_MODULE => "NONE",
C_MMCM0_CLKFBIN_PORT => "NONE",
C_MMCM0_RST_MODULE => "NONE",
C_MMCM1_BANDWIDTH => "OPTIMIZED",
C_MMCM1_CLKFBOUT_MULT_F => 1.000000,
C_MMCM1_CLKFBOUT_PHASE => 0.000000,
C_MMCM1_CLKFBOUT_USE_FINE_PS => false,
C_MMCM1_CLKIN1_PERIOD => 0.000000,
C_MMCM1_CLKOUT0_DIVIDE_F => 1.000000,
C_MMCM1_CLKOUT0_DUTY_CYCLE => 0.500000,
C_MMCM1_CLKOUT0_PHASE => 0.000000,
C_MMCM1_CLKOUT1_DIVIDE => 1,
C_MMCM1_CLKOUT1_DUTY_CYCLE => 0.500000,
C_MMCM1_CLKOUT1_PHASE => 0.000000,
C_MMCM1_CLKOUT2_DIVIDE => 1,
C_MMCM1_CLKOUT2_DUTY_CYCLE => 0.500000,
C_MMCM1_CLKOUT2_PHASE => 0.000000,
C_MMCM1_CLKOUT3_DIVIDE => 1,
C_MMCM1_CLKOUT3_DUTY_CYCLE => 0.500000,
C_MMCM1_CLKOUT3_PHASE => 0.000000,
C_MMCM1_CLKOUT4_DIVIDE => 1,
C_MMCM1_CLKOUT4_DUTY_CYCLE => 0.500000,
C_MMCM1_CLKOUT4_PHASE => 0.000000,
C_MMCM1_CLKOUT4_CASCADE => false,
C_MMCM1_CLKOUT5_DIVIDE => 1,
C_MMCM1_CLKOUT5_DUTY_CYCLE => 0.500000,
C_MMCM1_CLKOUT5_PHASE => 0.000000,
C_MMCM1_CLKOUT6_DIVIDE => 1,
C_MMCM1_CLKOUT6_DUTY_CYCLE => 0.500000,
C_MMCM1_CLKOUT6_PHASE => 0.000000,
C_MMCM1_CLKOUT0_USE_FINE_PS => false,
C_MMCM1_CLKOUT1_USE_FINE_PS => false,
C_MMCM1_CLKOUT2_USE_FINE_PS => false,
C_MMCM1_CLKOUT3_USE_FINE_PS => false,
C_MMCM1_CLKOUT4_USE_FINE_PS => false,
C_MMCM1_CLKOUT5_USE_FINE_PS => false,
C_MMCM1_CLKOUT6_USE_FINE_PS => false,
C_MMCM1_COMPENSATION => "ZHOLD",
C_MMCM1_DIVCLK_DIVIDE => 1,
C_MMCM1_REF_JITTER1 => 0.010000,
C_MMCM1_CLKIN1_BUF => false,
C_MMCM1_CLKFBOUT_BUF => false,
C_MMCM1_CLOCK_HOLD => false,
C_MMCM1_STARTUP_WAIT => false,
C_MMCM1_EXT_RESET_HIGH => 1,
C_MMCM1_FAMILY => "virtex5",
C_MMCM1_CLKOUT0_BUF => false,
C_MMCM1_CLKOUT1_BUF => false,
C_MMCM1_CLKOUT2_BUF => false,
C_MMCM1_CLKOUT3_BUF => false,
C_MMCM1_CLKOUT4_BUF => false,
C_MMCM1_CLKOUT5_BUF => false,
C_MMCM1_CLKOUT6_BUF => false,
C_MMCM1_CLKIN1_MODULE => "NONE",
C_MMCM1_CLKIN1_PORT => "NONE",
C_MMCM1_CLKFBIN_MODULE => "NONE",
C_MMCM1_CLKFBIN_PORT => "NONE",
C_MMCM1_RST_MODULE => "NONE",
C_MMCM2_BANDWIDTH => "OPTIMIZED",
C_MMCM2_CLKFBOUT_MULT_F => 1.000000,
C_MMCM2_CLKFBOUT_PHASE => 0.000000,
C_MMCM2_CLKFBOUT_USE_FINE_PS => false,
C_MMCM2_CLKIN1_PERIOD => 0.000000,
C_MMCM2_CLKOUT0_DIVIDE_F => 1.000000,
C_MMCM2_CLKOUT0_DUTY_CYCLE => 0.500000,
C_MMCM2_CLKOUT0_PHASE => 0.000000,
C_MMCM2_CLKOUT1_DIVIDE => 1,
C_MMCM2_CLKOUT1_DUTY_CYCLE => 0.500000,
C_MMCM2_CLKOUT1_PHASE => 0.000000,
C_MMCM2_CLKOUT2_DIVIDE => 1,
C_MMCM2_CLKOUT2_DUTY_CYCLE => 0.500000,
C_MMCM2_CLKOUT2_PHASE => 0.000000,
C_MMCM2_CLKOUT3_DIVIDE => 1,
C_MMCM2_CLKOUT3_DUTY_CYCLE => 0.500000,
C_MMCM2_CLKOUT3_PHASE => 0.000000,
C_MMCM2_CLKOUT4_DIVIDE => 1,
C_MMCM2_CLKOUT4_DUTY_CYCLE => 0.500000,
C_MMCM2_CLKOUT4_PHASE => 0.000000,
C_MMCM2_CLKOUT4_CASCADE => false,
C_MMCM2_CLKOUT5_DIVIDE => 1,
C_MMCM2_CLKOUT5_DUTY_CYCLE => 0.500000,
C_MMCM2_CLKOUT5_PHASE => 0.000000,
C_MMCM2_CLKOUT6_DIVIDE => 1,
C_MMCM2_CLKOUT6_DUTY_CYCLE => 0.500000,
C_MMCM2_CLKOUT6_PHASE => 0.000000,
C_MMCM2_CLKOUT0_USE_FINE_PS => false,
C_MMCM2_CLKOUT1_USE_FINE_PS => false,
C_MMCM2_CLKOUT2_USE_FINE_PS => false,
C_MMCM2_CLKOUT3_USE_FINE_PS => false,
C_MMCM2_CLKOUT4_USE_FINE_PS => false,
C_MMCM2_CLKOUT5_USE_FINE_PS => false,
C_MMCM2_CLKOUT6_USE_FINE_PS => false,
C_MMCM2_COMPENSATION => "ZHOLD",
C_MMCM2_DIVCLK_DIVIDE => 1,
C_MMCM2_REF_JITTER1 => 0.010000,
C_MMCM2_CLKIN1_BUF => false,
C_MMCM2_CLKFBOUT_BUF => false,
C_MMCM2_CLOCK_HOLD => false,
C_MMCM2_STARTUP_WAIT => false,
C_MMCM2_EXT_RESET_HIGH => 1,
C_MMCM2_FAMILY => "virtex5",
C_MMCM2_CLKOUT0_BUF => false,
C_MMCM2_CLKOUT1_BUF => false,
C_MMCM2_CLKOUT2_BUF => false,
C_MMCM2_CLKOUT3_BUF => false,
C_MMCM2_CLKOUT4_BUF => false,
C_MMCM2_CLKOUT5_BUF => false,
C_MMCM2_CLKOUT6_BUF => false,
C_MMCM2_CLKIN1_MODULE => "NONE",
C_MMCM2_CLKIN1_PORT => "NONE",
C_MMCM2_CLKFBIN_MODULE => "NONE",
C_MMCM2_CLKFBIN_PORT => "NONE",
C_MMCM2_RST_MODULE => "NONE",
C_MMCM3_BANDWIDTH => "OPTIMIZED",
C_MMCM3_CLKFBOUT_MULT_F => 1.000000,
C_MMCM3_CLKFBOUT_PHASE => 0.000000,
C_MMCM3_CLKFBOUT_USE_FINE_PS => false,
C_MMCM3_CLKIN1_PERIOD => 0.000000,
C_MMCM3_CLKOUT0_DIVIDE_F => 1.000000,
C_MMCM3_CLKOUT0_DUTY_CYCLE => 0.500000,
C_MMCM3_CLKOUT0_PHASE => 0.000000,
C_MMCM3_CLKOUT1_DIVIDE => 1,
C_MMCM3_CLKOUT1_DUTY_CYCLE => 0.500000,
C_MMCM3_CLKOUT1_PHASE => 0.000000,
C_MMCM3_CLKOUT2_DIVIDE => 1,
C_MMCM3_CLKOUT2_DUTY_CYCLE => 0.500000,
C_MMCM3_CLKOUT2_PHASE => 0.000000,
C_MMCM3_CLKOUT3_DIVIDE => 1,
C_MMCM3_CLKOUT3_DUTY_CYCLE => 0.500000,
C_MMCM3_CLKOUT3_PHASE => 0.000000,
C_MMCM3_CLKOUT4_DIVIDE => 1,
C_MMCM3_CLKOUT4_DUTY_CYCLE => 0.500000,
C_MMCM3_CLKOUT4_PHASE => 0.000000,
C_MMCM3_CLKOUT4_CASCADE => false,
C_MMCM3_CLKOUT5_DIVIDE => 1,
C_MMCM3_CLKOUT5_DUTY_CYCLE => 0.500000,
C_MMCM3_CLKOUT5_PHASE => 0.000000,
C_MMCM3_CLKOUT6_DIVIDE => 1,
C_MMCM3_CLKOUT6_DUTY_CYCLE => 0.500000,
C_MMCM3_CLKOUT6_PHASE => 0.000000,
C_MMCM3_CLKOUT0_USE_FINE_PS => false,
C_MMCM3_CLKOUT1_USE_FINE_PS => false,
C_MMCM3_CLKOUT2_USE_FINE_PS => false,
C_MMCM3_CLKOUT3_USE_FINE_PS => false,
C_MMCM3_CLKOUT4_USE_FINE_PS => false,
C_MMCM3_CLKOUT5_USE_FINE_PS => false,
C_MMCM3_CLKOUT6_USE_FINE_PS => false,
C_MMCM3_COMPENSATION => "ZHOLD",
C_MMCM3_DIVCLK_DIVIDE => 1,
C_MMCM3_REF_JITTER1 => 0.010000,
C_MMCM3_CLKIN1_BUF => false,
C_MMCM3_CLKFBOUT_BUF => false,
C_MMCM3_CLOCK_HOLD => false,
C_MMCM3_STARTUP_WAIT => false,
C_MMCM3_EXT_RESET_HIGH => 1,
C_MMCM3_FAMILY => "virtex5",
C_MMCM3_CLKOUT0_BUF => false,
C_MMCM3_CLKOUT1_BUF => false,
C_MMCM3_CLKOUT2_BUF => false,
C_MMCM3_CLKOUT3_BUF => false,
C_MMCM3_CLKOUT4_BUF => false,
C_MMCM3_CLKOUT5_BUF => false,
C_MMCM3_CLKOUT6_BUF => false,
C_MMCM3_CLKIN1_MODULE => "NONE",
C_MMCM3_CLKIN1_PORT => "NONE",
C_MMCM3_CLKFBIN_MODULE => "NONE",
C_MMCM3_CLKFBIN_PORT => "NONE",
C_MMCM3_RST_MODULE => "NONE"
)
port map (
CLKIN => CLKIN,
CLKFBIN => CLKFBIN,
CLKOUT0 => CLKOUT0,
CLKOUT1 => CLKOUT1,
CLKOUT2 => CLKOUT2,
CLKOUT3 => CLKOUT3,
CLKOUT4 => CLKOUT4,
CLKOUT5 => CLKOUT5,
CLKOUT6 => CLKOUT6,
CLKOUT7 => CLKOUT7,
CLKOUT8 => CLKOUT8,
CLKOUT9 => CLKOUT9,
CLKOUT10 => CLKOUT10,
CLKOUT11 => CLKOUT11,
CLKOUT12 => CLKOUT12,
CLKOUT13 => CLKOUT13,
CLKOUT14 => CLKOUT14,
CLKOUT15 => CLKOUT15,
CLKFBOUT => CLKFBOUT,
PSCLK => PSCLK,
PSEN => PSEN,
PSINCDEC => PSINCDEC,
PSDONE => PSDONE,
RST => RST,
LOCKED => LOCKED
);
end architecture STRUCTURE;
|
architecture RTL of FIFO is
function func1 return integer is begin end function func1;
function func1 return integer is begin end function func1;
function func1 return integer is begin end function func1;
begin
end architecture RTL;
|
architecture RTL of FIFO is
function func1 return integer is begin end function func1;
function func1 return integer is begin end function func1;
function func1 return integer is begin end function func1;
begin
end architecture RTL;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:37:07 07/06/2015
-- Design Name:
-- Module Name: waveGenerator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity waveGenerator is
Port ( pitch : in STD_LOGIC_VECTOR (15 downto 0);
mode : in STD_LOGIC_VECTOR (1 downto 0);
clk : in STD_LOGIC;
O : out STD_LOGIC_VECTOR (15 downto 0));
end waveGenerator;
architecture Behavioral of waveGenerator is
begin
end Behavioral;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY PSelect IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(799 DOWNTO 0)
);
END PSelect;
ARCHITECTURE PSelect_arch OF PSelect IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF PSelect_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(799 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(799 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(799 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(799 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(799 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(799 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "PSelect.mif",
C_INIT_FILE => "PSelect.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 800,
C_READ_WIDTH_A => 800,
C_WRITE_DEPTH_A => 600,
C_READ_DEPTH_A => 600,
C_ADDRA_WIDTH => 10,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 800,
C_READ_WIDTH_B => 800,
C_WRITE_DEPTH_B => 600,
C_READ_DEPTH_B => 600,
C_ADDRB_WIDTH => 10,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "22",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 60.4532 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 800)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 800)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 800)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END PSelect_arch;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DIVNORND.VHD ***
--*** ***
--*** Function: Output Stage, No Rounding ***
--*** ***
--*** ***
--*** 24/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 22/04/09 - added NAN support, IEEE NAN ***
--*** output ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 1 ***
--***************************************************
ENTITY hcc_divnornd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
satin, zipin, nanin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1)
);
END hcc_divnornd;
ARCHITECTURE rtl OF hcc_divnornd IS
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (51 DOWNTO 1);
signal signff : STD_LOGIC;
signal nanff : STD_LOGIC;
signal dividebyzeroff : STD_LOGIC;
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal infinitygen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO 51 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
signff <= signin;
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= (mantissain(k+1) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentff(k) <= (exponentin(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- '1' when true for all cases
-- infinity if exponent >= 255
infinitygen(1) <= exponentin(1);
gia: FOR k IN 2 TO 11 GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponentin(k);
END GENERATE;
-- 12/05/09 - make sure exponentin = -1 doesnt make infinity
infinitygen(12) <= (infinitygen(11) AND NOT(exponentin(12)) AND NOT(exponentin(13))) OR
satin OR (exponentin(12) AND NOT(exponentin(13))); -- '1' if infinity
-- zero if exponent <= 0
zerogen(1) <= exponentin(1);
gza: FOR k IN 2 TO 11 GENERATE
zerogen(k) <= zerogen(k-1) OR exponentin(k);
END GENERATE;
zerogen(12) <= NOT(zerogen(11)) OR zipin OR exponentin(13); -- '1' if zero
-- set mantissa to 0 when infinity or zero condition
setmanzero <= infinitygen(12) OR zerogen(12);
setmanmax <= nanin;
-- set exponent to 0 when zero condition
setexpzero <= zerogen(12);
-- set exponent to "11..11" infinity
setexpmax <= infinitygen(12) OR nanin;
--***************
--*** OUTPUTS ***
--***************
signout <= signff;
mantissaout <= mantissaff;
exponentout <= exponentff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DIVNORND.VHD ***
--*** ***
--*** Function: Output Stage, No Rounding ***
--*** ***
--*** ***
--*** 24/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 22/04/09 - added NAN support, IEEE NAN ***
--*** output ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 1 ***
--***************************************************
ENTITY hcc_divnornd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
satin, zipin, nanin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1)
);
END hcc_divnornd;
ARCHITECTURE rtl OF hcc_divnornd IS
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (51 DOWNTO 1);
signal signff : STD_LOGIC;
signal nanff : STD_LOGIC;
signal dividebyzeroff : STD_LOGIC;
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal infinitygen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO 51 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
signff <= signin;
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= (mantissain(k+1) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentff(k) <= (exponentin(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- '1' when true for all cases
-- infinity if exponent >= 255
infinitygen(1) <= exponentin(1);
gia: FOR k IN 2 TO 11 GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponentin(k);
END GENERATE;
-- 12/05/09 - make sure exponentin = -1 doesnt make infinity
infinitygen(12) <= (infinitygen(11) AND NOT(exponentin(12)) AND NOT(exponentin(13))) OR
satin OR (exponentin(12) AND NOT(exponentin(13))); -- '1' if infinity
-- zero if exponent <= 0
zerogen(1) <= exponentin(1);
gza: FOR k IN 2 TO 11 GENERATE
zerogen(k) <= zerogen(k-1) OR exponentin(k);
END GENERATE;
zerogen(12) <= NOT(zerogen(11)) OR zipin OR exponentin(13); -- '1' if zero
-- set mantissa to 0 when infinity or zero condition
setmanzero <= infinitygen(12) OR zerogen(12);
setmanmax <= nanin;
-- set exponent to 0 when zero condition
setexpzero <= zerogen(12);
-- set exponent to "11..11" infinity
setexpmax <= infinitygen(12) OR nanin;
--***************
--*** OUTPUTS ***
--***************
signout <= signff;
mantissaout <= mantissaff;
exponentout <= exponentff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DIVNORND.VHD ***
--*** ***
--*** Function: Output Stage, No Rounding ***
--*** ***
--*** ***
--*** 24/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 22/04/09 - added NAN support, IEEE NAN ***
--*** output ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 1 ***
--***************************************************
ENTITY hcc_divnornd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
satin, zipin, nanin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1)
);
END hcc_divnornd;
ARCHITECTURE rtl OF hcc_divnornd IS
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (51 DOWNTO 1);
signal signff : STD_LOGIC;
signal nanff : STD_LOGIC;
signal dividebyzeroff : STD_LOGIC;
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal infinitygen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO 51 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
signff <= signin;
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= (mantissain(k+1) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentff(k) <= (exponentin(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- '1' when true for all cases
-- infinity if exponent >= 255
infinitygen(1) <= exponentin(1);
gia: FOR k IN 2 TO 11 GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponentin(k);
END GENERATE;
-- 12/05/09 - make sure exponentin = -1 doesnt make infinity
infinitygen(12) <= (infinitygen(11) AND NOT(exponentin(12)) AND NOT(exponentin(13))) OR
satin OR (exponentin(12) AND NOT(exponentin(13))); -- '1' if infinity
-- zero if exponent <= 0
zerogen(1) <= exponentin(1);
gza: FOR k IN 2 TO 11 GENERATE
zerogen(k) <= zerogen(k-1) OR exponentin(k);
END GENERATE;
zerogen(12) <= NOT(zerogen(11)) OR zipin OR exponentin(13); -- '1' if zero
-- set mantissa to 0 when infinity or zero condition
setmanzero <= infinitygen(12) OR zerogen(12);
setmanmax <= nanin;
-- set exponent to 0 when zero condition
setexpzero <= zerogen(12);
-- set exponent to "11..11" infinity
setexpmax <= infinitygen(12) OR nanin;
--***************
--*** OUTPUTS ***
--***************
signout <= signff;
mantissaout <= mantissaff;
exponentout <= exponentff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DIVNORND.VHD ***
--*** ***
--*** Function: Output Stage, No Rounding ***
--*** ***
--*** ***
--*** 24/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 22/04/09 - added NAN support, IEEE NAN ***
--*** output ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 1 ***
--***************************************************
ENTITY hcc_divnornd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
satin, zipin, nanin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1)
);
END hcc_divnornd;
ARCHITECTURE rtl OF hcc_divnornd IS
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (51 DOWNTO 1);
signal signff : STD_LOGIC;
signal nanff : STD_LOGIC;
signal dividebyzeroff : STD_LOGIC;
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal infinitygen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO 51 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
signff <= signin;
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= (mantissain(k+1) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentff(k) <= (exponentin(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- '1' when true for all cases
-- infinity if exponent >= 255
infinitygen(1) <= exponentin(1);
gia: FOR k IN 2 TO 11 GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponentin(k);
END GENERATE;
-- 12/05/09 - make sure exponentin = -1 doesnt make infinity
infinitygen(12) <= (infinitygen(11) AND NOT(exponentin(12)) AND NOT(exponentin(13))) OR
satin OR (exponentin(12) AND NOT(exponentin(13))); -- '1' if infinity
-- zero if exponent <= 0
zerogen(1) <= exponentin(1);
gza: FOR k IN 2 TO 11 GENERATE
zerogen(k) <= zerogen(k-1) OR exponentin(k);
END GENERATE;
zerogen(12) <= NOT(zerogen(11)) OR zipin OR exponentin(13); -- '1' if zero
-- set mantissa to 0 when infinity or zero condition
setmanzero <= infinitygen(12) OR zerogen(12);
setmanmax <= nanin;
-- set exponent to 0 when zero condition
setexpzero <= zerogen(12);
-- set exponent to "11..11" infinity
setexpmax <= infinitygen(12) OR nanin;
--***************
--*** OUTPUTS ***
--***************
signout <= signff;
mantissaout <= mantissaff;
exponentout <= exponentff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DIVNORND.VHD ***
--*** ***
--*** Function: Output Stage, No Rounding ***
--*** ***
--*** ***
--*** 24/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 22/04/09 - added NAN support, IEEE NAN ***
--*** output ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 1 ***
--***************************************************
ENTITY hcc_divnornd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
satin, zipin, nanin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1)
);
END hcc_divnornd;
ARCHITECTURE rtl OF hcc_divnornd IS
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (51 DOWNTO 1);
signal signff : STD_LOGIC;
signal nanff : STD_LOGIC;
signal dividebyzeroff : STD_LOGIC;
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal infinitygen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO 51 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
signff <= signin;
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= (mantissain(k+1) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentff(k) <= (exponentin(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- '1' when true for all cases
-- infinity if exponent >= 255
infinitygen(1) <= exponentin(1);
gia: FOR k IN 2 TO 11 GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponentin(k);
END GENERATE;
-- 12/05/09 - make sure exponentin = -1 doesnt make infinity
infinitygen(12) <= (infinitygen(11) AND NOT(exponentin(12)) AND NOT(exponentin(13))) OR
satin OR (exponentin(12) AND NOT(exponentin(13))); -- '1' if infinity
-- zero if exponent <= 0
zerogen(1) <= exponentin(1);
gza: FOR k IN 2 TO 11 GENERATE
zerogen(k) <= zerogen(k-1) OR exponentin(k);
END GENERATE;
zerogen(12) <= NOT(zerogen(11)) OR zipin OR exponentin(13); -- '1' if zero
-- set mantissa to 0 when infinity or zero condition
setmanzero <= infinitygen(12) OR zerogen(12);
setmanmax <= nanin;
-- set exponent to 0 when zero condition
setexpzero <= zerogen(12);
-- set exponent to "11..11" infinity
setexpmax <= infinitygen(12) OR nanin;
--***************
--*** OUTPUTS ***
--***************
signout <= signff;
mantissaout <= mantissaff;
exponentout <= exponentff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DIVNORND.VHD ***
--*** ***
--*** Function: Output Stage, No Rounding ***
--*** ***
--*** ***
--*** 24/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 22/04/09 - added NAN support, IEEE NAN ***
--*** output ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 1 ***
--***************************************************
ENTITY hcc_divnornd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
satin, zipin, nanin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1)
);
END hcc_divnornd;
ARCHITECTURE rtl OF hcc_divnornd IS
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (51 DOWNTO 1);
signal signff : STD_LOGIC;
signal nanff : STD_LOGIC;
signal dividebyzeroff : STD_LOGIC;
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal infinitygen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO 51 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
signff <= signin;
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= (mantissain(k+1) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentff(k) <= (exponentin(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- '1' when true for all cases
-- infinity if exponent >= 255
infinitygen(1) <= exponentin(1);
gia: FOR k IN 2 TO 11 GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponentin(k);
END GENERATE;
-- 12/05/09 - make sure exponentin = -1 doesnt make infinity
infinitygen(12) <= (infinitygen(11) AND NOT(exponentin(12)) AND NOT(exponentin(13))) OR
satin OR (exponentin(12) AND NOT(exponentin(13))); -- '1' if infinity
-- zero if exponent <= 0
zerogen(1) <= exponentin(1);
gza: FOR k IN 2 TO 11 GENERATE
zerogen(k) <= zerogen(k-1) OR exponentin(k);
END GENERATE;
zerogen(12) <= NOT(zerogen(11)) OR zipin OR exponentin(13); -- '1' if zero
-- set mantissa to 0 when infinity or zero condition
setmanzero <= infinitygen(12) OR zerogen(12);
setmanmax <= nanin;
-- set exponent to 0 when zero condition
setexpzero <= zerogen(12);
-- set exponent to "11..11" infinity
setexpmax <= infinitygen(12) OR nanin;
--***************
--*** OUTPUTS ***
--***************
signout <= signff;
mantissaout <= mantissaff;
exponentout <= exponentff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DIVNORND.VHD ***
--*** ***
--*** Function: Output Stage, No Rounding ***
--*** ***
--*** ***
--*** 24/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 22/04/09 - added NAN support, IEEE NAN ***
--*** output ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 1 ***
--***************************************************
ENTITY hcc_divnornd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
satin, zipin, nanin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1)
);
END hcc_divnornd;
ARCHITECTURE rtl OF hcc_divnornd IS
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (51 DOWNTO 1);
signal signff : STD_LOGIC;
signal nanff : STD_LOGIC;
signal dividebyzeroff : STD_LOGIC;
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal infinitygen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO 51 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
signff <= signin;
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= (mantissain(k+1) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentff(k) <= (exponentin(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- '1' when true for all cases
-- infinity if exponent >= 255
infinitygen(1) <= exponentin(1);
gia: FOR k IN 2 TO 11 GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponentin(k);
END GENERATE;
-- 12/05/09 - make sure exponentin = -1 doesnt make infinity
infinitygen(12) <= (infinitygen(11) AND NOT(exponentin(12)) AND NOT(exponentin(13))) OR
satin OR (exponentin(12) AND NOT(exponentin(13))); -- '1' if infinity
-- zero if exponent <= 0
zerogen(1) <= exponentin(1);
gza: FOR k IN 2 TO 11 GENERATE
zerogen(k) <= zerogen(k-1) OR exponentin(k);
END GENERATE;
zerogen(12) <= NOT(zerogen(11)) OR zipin OR exponentin(13); -- '1' if zero
-- set mantissa to 0 when infinity or zero condition
setmanzero <= infinitygen(12) OR zerogen(12);
setmanmax <= nanin;
-- set exponent to 0 when zero condition
setexpzero <= zerogen(12);
-- set exponent to "11..11" infinity
setexpmax <= infinitygen(12) OR nanin;
--***************
--*** OUTPUTS ***
--***************
signout <= signff;
mantissaout <= mantissaff;
exponentout <= exponentff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DIVNORND.VHD ***
--*** ***
--*** Function: Output Stage, No Rounding ***
--*** ***
--*** ***
--*** 24/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 22/04/09 - added NAN support, IEEE NAN ***
--*** output ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 1 ***
--***************************************************
ENTITY hcc_divnornd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
satin, zipin, nanin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1)
);
END hcc_divnornd;
ARCHITECTURE rtl OF hcc_divnornd IS
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (51 DOWNTO 1);
signal signff : STD_LOGIC;
signal nanff : STD_LOGIC;
signal dividebyzeroff : STD_LOGIC;
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal infinitygen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO 51 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
signff <= signin;
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= (mantissain(k+1) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentff(k) <= (exponentin(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- '1' when true for all cases
-- infinity if exponent >= 255
infinitygen(1) <= exponentin(1);
gia: FOR k IN 2 TO 11 GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponentin(k);
END GENERATE;
-- 12/05/09 - make sure exponentin = -1 doesnt make infinity
infinitygen(12) <= (infinitygen(11) AND NOT(exponentin(12)) AND NOT(exponentin(13))) OR
satin OR (exponentin(12) AND NOT(exponentin(13))); -- '1' if infinity
-- zero if exponent <= 0
zerogen(1) <= exponentin(1);
gza: FOR k IN 2 TO 11 GENERATE
zerogen(k) <= zerogen(k-1) OR exponentin(k);
END GENERATE;
zerogen(12) <= NOT(zerogen(11)) OR zipin OR exponentin(13); -- '1' if zero
-- set mantissa to 0 when infinity or zero condition
setmanzero <= infinitygen(12) OR zerogen(12);
setmanmax <= nanin;
-- set exponent to 0 when zero condition
setexpzero <= zerogen(12);
-- set exponent to "11..11" infinity
setexpmax <= infinitygen(12) OR nanin;
--***************
--*** OUTPUTS ***
--***************
signout <= signff;
mantissaout <= mantissaff;
exponentout <= exponentff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DIVNORND.VHD ***
--*** ***
--*** Function: Output Stage, No Rounding ***
--*** ***
--*** ***
--*** 24/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 22/04/09 - added NAN support, IEEE NAN ***
--*** output ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 1 ***
--***************************************************
ENTITY hcc_divnornd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
satin, zipin, nanin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1)
);
END hcc_divnornd;
ARCHITECTURE rtl OF hcc_divnornd IS
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (51 DOWNTO 1);
signal signff : STD_LOGIC;
signal nanff : STD_LOGIC;
signal dividebyzeroff : STD_LOGIC;
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal infinitygen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO 51 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
signff <= signin;
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= (mantissain(k+1) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentff(k) <= (exponentin(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- '1' when true for all cases
-- infinity if exponent >= 255
infinitygen(1) <= exponentin(1);
gia: FOR k IN 2 TO 11 GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponentin(k);
END GENERATE;
-- 12/05/09 - make sure exponentin = -1 doesnt make infinity
infinitygen(12) <= (infinitygen(11) AND NOT(exponentin(12)) AND NOT(exponentin(13))) OR
satin OR (exponentin(12) AND NOT(exponentin(13))); -- '1' if infinity
-- zero if exponent <= 0
zerogen(1) <= exponentin(1);
gza: FOR k IN 2 TO 11 GENERATE
zerogen(k) <= zerogen(k-1) OR exponentin(k);
END GENERATE;
zerogen(12) <= NOT(zerogen(11)) OR zipin OR exponentin(13); -- '1' if zero
-- set mantissa to 0 when infinity or zero condition
setmanzero <= infinitygen(12) OR zerogen(12);
setmanmax <= nanin;
-- set exponent to 0 when zero condition
setexpzero <= zerogen(12);
-- set exponent to "11..11" infinity
setexpmax <= infinitygen(12) OR nanin;
--***************
--*** OUTPUTS ***
--***************
signout <= signff;
mantissaout <= mantissaff;
exponentout <= exponentff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DIVNORND.VHD ***
--*** ***
--*** Function: Output Stage, No Rounding ***
--*** ***
--*** ***
--*** 24/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 22/04/09 - added NAN support, IEEE NAN ***
--*** output ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 1 ***
--***************************************************
ENTITY hcc_divnornd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
satin, zipin, nanin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1)
);
END hcc_divnornd;
ARCHITECTURE rtl OF hcc_divnornd IS
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (51 DOWNTO 1);
signal signff : STD_LOGIC;
signal nanff : STD_LOGIC;
signal dividebyzeroff : STD_LOGIC;
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal infinitygen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO 51 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
signff <= signin;
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= (mantissain(k+1) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentff(k) <= (exponentin(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- '1' when true for all cases
-- infinity if exponent >= 255
infinitygen(1) <= exponentin(1);
gia: FOR k IN 2 TO 11 GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponentin(k);
END GENERATE;
-- 12/05/09 - make sure exponentin = -1 doesnt make infinity
infinitygen(12) <= (infinitygen(11) AND NOT(exponentin(12)) AND NOT(exponentin(13))) OR
satin OR (exponentin(12) AND NOT(exponentin(13))); -- '1' if infinity
-- zero if exponent <= 0
zerogen(1) <= exponentin(1);
gza: FOR k IN 2 TO 11 GENERATE
zerogen(k) <= zerogen(k-1) OR exponentin(k);
END GENERATE;
zerogen(12) <= NOT(zerogen(11)) OR zipin OR exponentin(13); -- '1' if zero
-- set mantissa to 0 when infinity or zero condition
setmanzero <= infinitygen(12) OR zerogen(12);
setmanmax <= nanin;
-- set exponent to 0 when zero condition
setexpzero <= zerogen(12);
-- set exponent to "11..11" infinity
setexpmax <= infinitygen(12) OR nanin;
--***************
--*** OUTPUTS ***
--***************
signout <= signff;
mantissaout <= mantissaff;
exponentout <= exponentff;
END rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : in std_logic;
B : in std_logic;
carryIn : in std_logic;
carryOut : out std_logic;
fnord : out std_logic;
sum : out std_logic);
end adder;
architecture behv of adder is
begin
-- sum <= A xor B xor carryIn;
sum <= '0';
carryOut <= (a and b) or
(b and carryIn) or
(a and carryIn);
fnord <= ('1' or '0') and '1';
end behv;
|
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Vivado by Xilinx
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is the interface between the instantiation of an adder an its core. It exists to make it
/ possible to use external std_ulogic_vector which contain the numeric values while having modules
/ which are able to manipulate this data as fixed point types (either u_ufixed or u_sfixed).
/ As std_ulogic_vector have a natural range and the u_ufixed and u_sfixed types have an integer
/ range ('high downto 0 is the integer part and -1 downto 'low is the fractional part) it is needed
/ a solution so as to represent the negative indexes in the std_ulogic_vector. A solution is
/ adopted where the integer indexes of the fixed point types are moved to the natural space with a
/ transformation. This consists in limiting the indexes of the fixed point data to +-2**30 and
/ adding 2**30 to obtain the std_ulogic_vector's indexes. [-2**30, 2**30]->[0, 2**31]. For example,
/ fixed point indexes (3 donwto -2) would become (1073741827, 1073741822) in a std_ulogic_vector
/ Additionally, the generics' consistency and correctness are checked in here.
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.adder_pkg.all;
use work.fixed_generic_pkg.all;
use work.average_calculator_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity average_calculator_core_s is
generic(
DATA_IMM_AFTER_START_opt : boolean;
SPEED_opt : T_speed;
ROUND_STYLE_opt : T_round_style;
ROUND_TO_BIT_opt : integer_exc;
MAX_ERROR_PCT_opt : real_exc;
S : positive;
P : positive;
input_high : integer;
input_low : integer
);
port(
input : in u_sfixed_v(1 to P);
clk : in std_ulogic;
start : in std_ulogic;
valid_input : in std_ulogic;
output : out u_sfixed(average_calculator_OH(false, --UNSIGNED_2COMP_opt,
ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
S,
P,
input_high,
input_low)
downto
average_calculator_OL(false, --UNSIGNED_2COMP_opt,
ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
S,
P,
input_high,
input_low)
);
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture average_calculator_core_s1 of average_calculator_core_s is
constant INTER_HIGH : integer := average_calculator_IH(S,
P,
input_high);
constant INTER_LOW : integer := average_calculator_IL(ROUND_TO_BIT_opt,
input_low);
constant OUT_HIGH : integer := average_calculator_OH(false, --UNSIGNED_2COMP_opt,
ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
S,
P,
input_high,
input_low);
constant OUT_LOW : integer := average_calculator_OL(false, --UNSIGNED_2COMP_opt,
ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
S,
P,
input_high,
input_low);
signal inter : u_sfixed(INTER_HIGH downto INTER_LOW);
signal valid_output_inter : std_ulogic;
/*================================================================================================*/
/*================================================================================================*/
begin
check_if_1:
if P = 1 generate
begin
output <= input(1);
valid_output <= valid_input; --need update when implementing pipelines
end;
else generate
begin
adder_s1:
entity work.adder_s
generic map(
--DATA_IMM_AFTER_START_opt => ,
--SPEED_opt => , --to do
--MAX_POSSIBLE_BIT_opt => ,
TRUNCATE_TO_BIT_opt => ROUND_TO_BIT_opt,
S => S
)
port map(
input => input,
clk => clk,
start => start,
valid_input => valid_input,
output => inter,
valid_output => valid_output_inter
);
real_const_mult_s1:
entity work.real_const_mult_s
generic map(
--SPEED_opt => SPEED_opt, --to do
ROUND_STYLE_opt => ROUND_STYLE_opt,
ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
MULTIPLICANDS => (1 => 1.0/(S*P))
)
port map(
input => inter,
clk => clk,
valid_input => valid_output_inter,
output(1) => output,
valid_output => valid_output
);
end;
end generate;
end architecture; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/21/2017 05:18:09 PM
-- Design Name:
-- Module Name: immortal_volt_monitor_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity immortal_volt_monitor_tb is
end immortal_volt_monitor_tb;
architecture Behavioral of immortal_volt_monitor_tb is
constant tck_period : time := 10 ns;
constant HALF_SEPARATOR : time := 2*tck_period;
constant FULL_SEPARATOR : time := 8*tck_period;
signal toSI : STD_LOGIC;
signal fromSO : STD_LOGIC;
signal SE : STD_LOGIC;
signal CE : STD_LOGIC;
signal UE : STD_LOGIC;
signal TCK : STD_LOGIC;
signal RST : STD_LOGIC;
signal SEL : STD_LOGIC;
signal toF : STD_LOGIC;
signal toC : STD_LOGIC;
signal volt_control : std_logic_vector (2 downto 0);
signal volt_data : std_logic_vector (31 downto 0);
component immortal_volt_monitor_instrument is
port (
-- IJTAG connection
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic;
-- Monitor connections
control : out std_logic_vector(2 downto 0);
data : in std_logic_vector(31 downto 0)
);
end component;
begin
volt_monitor : immortal_volt_monitor_instrument
port map (
-- IJTAG connection
TCK => TCK,
RST => RST,
SEL => SEL,
SI => toSI,
SE => SE,
UE => UE,
CE => CE,
SO => fromSO,
toF => toF,
toC => toC,
-- Monitor connections
control => volt_control,
data => volt_data
);
ijtag_shift_proc: process
-- Generate a number of TCK ticks
procedure tck_tick (number_of_tick : in positive) is
begin
for i in 1 to number_of_tick loop
TCK <= '0';
wait for TCK_period/2;
TCK <= '1';
wait for TCK_period/2;
end loop;
end procedure tck_tick;
procedure tck_halftick_high is
begin
TCK <= '1';
wait for TCK_period/2;
end procedure tck_halftick_high;
procedure tck_halftick_low is
begin
TCK <= '0';
wait for TCK_period/2;
end procedure tck_halftick_low;
-- Shifts in specified data (Capture -> Shift -> Update)
procedure shift_data (data : in std_logic_vector) is
begin
--Capture phase
CE <= '1';
tck_tick(1);
CE <= '0';
--Shift phase
SE <= '1';
for i in data'range loop
toSI <= data(i);
tck_tick(1);
end loop;
SE <= '0';
-- Update phase
--tck_tick(1);
tck_halftick_low;
UE <= '1';
tck_halftick_high;
tck_halftick_low;
UE <= '0';
tck_halftick_high;
end procedure shift_data;
-- Returns all zeroes std_logic_vector of specified size
function all_zeroes (number_of_zeroes : in positive) return std_logic_vector is
variable zero_array : std_logic_vector(0 to number_of_zeroes-1);
begin
for i in zero_array'range loop
zero_array(i) := '0';
end loop;
return zero_array;
end function all_zeroes;
begin
volt_data <= "00000000000000000000000000001111";
UE <= '0';
CE <= '0';
SE <= '0';
toSI <= '0';
-- Reset iJTAG chain and Instruments
RST <= '1';
wait for tck_period;
RST <= '0';
SEL <= '1';
tck_tick(4);
--shift_data("00000000000000000000000000000000");
--shift_data("11100000000000000000000000000000"); -- shift in threshold H without update enable
shift_data("00001"&"11100"&"1"&"1"&"1"&"0000000000000001111"); -- shift in threshold H without update
tck_tick(4);
volt_data <= "00000000000000000000000000000000";
tck_tick(1);
volt_data <= "00000000000000000000000000000001";
tck_tick(1);
volt_data <= "00000000000000000000000000000011";
tck_tick(1);
volt_data <= "00000000000000000000000000000111";
tck_tick(1);
volt_data <= "00000000000000000000000000001111";
tck_tick(1);
volt_data <= "00000000000000000000000000011111";
tck_tick(1);
volt_data <= "00000000000000000000000000111111";
tck_tick(1);
volt_data <= "00000000000000000000000001111111";
tck_tick(1);
volt_data <= "00000000000000000000000011111111";
tck_tick(1);
volt_data <= "00000000000000000000000111111111";
tck_tick(1);
volt_data <= "00000000000000000000001111111111";
tck_tick(1);
volt_data <= "00000000000000000000011111111111";
tck_tick(1);
volt_data <= "00000000000000000000111111111111";
tck_tick(1);
volt_data <= "00000000000000000001111111111111";
tck_tick(1);
volt_data <= "00000000000000000011111111111111";
tck_tick(1);
volt_data <= "00000000000000000111111111111111";
tck_tick(1);
volt_data <= "00000000000000001111111111111111";
tck_tick(1);
volt_data <= "00000000000000011111111111111111";
tck_tick(1);
volt_data <= "00000000000000111111111111111111";
tck_tick(1);
volt_data <= "00000000000001111111111111111111";
tck_tick(1);
volt_data <= "00000000000011111111111111111111";
tck_tick(1);
volt_data <= "00000000000111111111111111111111";
tck_tick(1);
volt_data <= "00000000001111111111111111111111";
tck_tick(1);
volt_data <= "00000000011111111111111111111111";
tck_tick(1);
volt_data <= "00000000111111111111111111111111";
tck_tick(1);
volt_data <= "00000001111111111111111111111111";
tck_tick(1);
volt_data <= "00000011111111111111111111111111";
tck_tick(1);
volt_data <= "00000111111111111111111111111111";
tck_tick(1);
volt_data <= "00001111111111111111111111111111";
tck_tick(1);
volt_data <= "00011111111111111111111111111111";
tck_tick(1);
volt_data <= "00111111111111111111111111111111";
tck_tick(1);
volt_data <= "01111111111111111111111111111111";
tck_tick(1);
volt_data <= "11111111111111111111111111111111";
tck_tick(1);
wait;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/21/2017 05:18:09 PM
-- Design Name:
-- Module Name: immortal_volt_monitor_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity immortal_volt_monitor_tb is
end immortal_volt_monitor_tb;
architecture Behavioral of immortal_volt_monitor_tb is
constant tck_period : time := 10 ns;
constant HALF_SEPARATOR : time := 2*tck_period;
constant FULL_SEPARATOR : time := 8*tck_period;
signal toSI : STD_LOGIC;
signal fromSO : STD_LOGIC;
signal SE : STD_LOGIC;
signal CE : STD_LOGIC;
signal UE : STD_LOGIC;
signal TCK : STD_LOGIC;
signal RST : STD_LOGIC;
signal SEL : STD_LOGIC;
signal toF : STD_LOGIC;
signal toC : STD_LOGIC;
signal volt_control : std_logic_vector (2 downto 0);
signal volt_data : std_logic_vector (31 downto 0);
component immortal_volt_monitor_instrument is
port (
-- IJTAG connection
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic;
-- Monitor connections
control : out std_logic_vector(2 downto 0);
data : in std_logic_vector(31 downto 0)
);
end component;
begin
volt_monitor : immortal_volt_monitor_instrument
port map (
-- IJTAG connection
TCK => TCK,
RST => RST,
SEL => SEL,
SI => toSI,
SE => SE,
UE => UE,
CE => CE,
SO => fromSO,
toF => toF,
toC => toC,
-- Monitor connections
control => volt_control,
data => volt_data
);
ijtag_shift_proc: process
-- Generate a number of TCK ticks
procedure tck_tick (number_of_tick : in positive) is
begin
for i in 1 to number_of_tick loop
TCK <= '0';
wait for TCK_period/2;
TCK <= '1';
wait for TCK_period/2;
end loop;
end procedure tck_tick;
procedure tck_halftick_high is
begin
TCK <= '1';
wait for TCK_period/2;
end procedure tck_halftick_high;
procedure tck_halftick_low is
begin
TCK <= '0';
wait for TCK_period/2;
end procedure tck_halftick_low;
-- Shifts in specified data (Capture -> Shift -> Update)
procedure shift_data (data : in std_logic_vector) is
begin
--Capture phase
CE <= '1';
tck_tick(1);
CE <= '0';
--Shift phase
SE <= '1';
for i in data'range loop
toSI <= data(i);
tck_tick(1);
end loop;
SE <= '0';
-- Update phase
--tck_tick(1);
tck_halftick_low;
UE <= '1';
tck_halftick_high;
tck_halftick_low;
UE <= '0';
tck_halftick_high;
end procedure shift_data;
-- Returns all zeroes std_logic_vector of specified size
function all_zeroes (number_of_zeroes : in positive) return std_logic_vector is
variable zero_array : std_logic_vector(0 to number_of_zeroes-1);
begin
for i in zero_array'range loop
zero_array(i) := '0';
end loop;
return zero_array;
end function all_zeroes;
begin
volt_data <= "00000000000000000000000000001111";
UE <= '0';
CE <= '0';
SE <= '0';
toSI <= '0';
-- Reset iJTAG chain and Instruments
RST <= '1';
wait for tck_period;
RST <= '0';
SEL <= '1';
tck_tick(4);
--shift_data("00000000000000000000000000000000");
--shift_data("11100000000000000000000000000000"); -- shift in threshold H without update enable
shift_data("00001"&"11100"&"1"&"1"&"1"&"0000000000000001111"); -- shift in threshold H without update
tck_tick(4);
volt_data <= "00000000000000000000000000000000";
tck_tick(1);
volt_data <= "00000000000000000000000000000001";
tck_tick(1);
volt_data <= "00000000000000000000000000000011";
tck_tick(1);
volt_data <= "00000000000000000000000000000111";
tck_tick(1);
volt_data <= "00000000000000000000000000001111";
tck_tick(1);
volt_data <= "00000000000000000000000000011111";
tck_tick(1);
volt_data <= "00000000000000000000000000111111";
tck_tick(1);
volt_data <= "00000000000000000000000001111111";
tck_tick(1);
volt_data <= "00000000000000000000000011111111";
tck_tick(1);
volt_data <= "00000000000000000000000111111111";
tck_tick(1);
volt_data <= "00000000000000000000001111111111";
tck_tick(1);
volt_data <= "00000000000000000000011111111111";
tck_tick(1);
volt_data <= "00000000000000000000111111111111";
tck_tick(1);
volt_data <= "00000000000000000001111111111111";
tck_tick(1);
volt_data <= "00000000000000000011111111111111";
tck_tick(1);
volt_data <= "00000000000000000111111111111111";
tck_tick(1);
volt_data <= "00000000000000001111111111111111";
tck_tick(1);
volt_data <= "00000000000000011111111111111111";
tck_tick(1);
volt_data <= "00000000000000111111111111111111";
tck_tick(1);
volt_data <= "00000000000001111111111111111111";
tck_tick(1);
volt_data <= "00000000000011111111111111111111";
tck_tick(1);
volt_data <= "00000000000111111111111111111111";
tck_tick(1);
volt_data <= "00000000001111111111111111111111";
tck_tick(1);
volt_data <= "00000000011111111111111111111111";
tck_tick(1);
volt_data <= "00000000111111111111111111111111";
tck_tick(1);
volt_data <= "00000001111111111111111111111111";
tck_tick(1);
volt_data <= "00000011111111111111111111111111";
tck_tick(1);
volt_data <= "00000111111111111111111111111111";
tck_tick(1);
volt_data <= "00001111111111111111111111111111";
tck_tick(1);
volt_data <= "00011111111111111111111111111111";
tck_tick(1);
volt_data <= "00111111111111111111111111111111";
tck_tick(1);
volt_data <= "01111111111111111111111111111111";
tck_tick(1);
volt_data <= "11111111111111111111111111111111";
tck_tick(1);
wait;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/21/2017 05:18:09 PM
-- Design Name:
-- Module Name: immortal_volt_monitor_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity immortal_volt_monitor_tb is
end immortal_volt_monitor_tb;
architecture Behavioral of immortal_volt_monitor_tb is
constant tck_period : time := 10 ns;
constant HALF_SEPARATOR : time := 2*tck_period;
constant FULL_SEPARATOR : time := 8*tck_period;
signal toSI : STD_LOGIC;
signal fromSO : STD_LOGIC;
signal SE : STD_LOGIC;
signal CE : STD_LOGIC;
signal UE : STD_LOGIC;
signal TCK : STD_LOGIC;
signal RST : STD_LOGIC;
signal SEL : STD_LOGIC;
signal toF : STD_LOGIC;
signal toC : STD_LOGIC;
signal volt_control : std_logic_vector (2 downto 0);
signal volt_data : std_logic_vector (31 downto 0);
component immortal_volt_monitor_instrument is
port (
-- IJTAG connection
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic;
-- Monitor connections
control : out std_logic_vector(2 downto 0);
data : in std_logic_vector(31 downto 0)
);
end component;
begin
volt_monitor : immortal_volt_monitor_instrument
port map (
-- IJTAG connection
TCK => TCK,
RST => RST,
SEL => SEL,
SI => toSI,
SE => SE,
UE => UE,
CE => CE,
SO => fromSO,
toF => toF,
toC => toC,
-- Monitor connections
control => volt_control,
data => volt_data
);
ijtag_shift_proc: process
-- Generate a number of TCK ticks
procedure tck_tick (number_of_tick : in positive) is
begin
for i in 1 to number_of_tick loop
TCK <= '0';
wait for TCK_period/2;
TCK <= '1';
wait for TCK_period/2;
end loop;
end procedure tck_tick;
procedure tck_halftick_high is
begin
TCK <= '1';
wait for TCK_period/2;
end procedure tck_halftick_high;
procedure tck_halftick_low is
begin
TCK <= '0';
wait for TCK_period/2;
end procedure tck_halftick_low;
-- Shifts in specified data (Capture -> Shift -> Update)
procedure shift_data (data : in std_logic_vector) is
begin
--Capture phase
CE <= '1';
tck_tick(1);
CE <= '0';
--Shift phase
SE <= '1';
for i in data'range loop
toSI <= data(i);
tck_tick(1);
end loop;
SE <= '0';
-- Update phase
--tck_tick(1);
tck_halftick_low;
UE <= '1';
tck_halftick_high;
tck_halftick_low;
UE <= '0';
tck_halftick_high;
end procedure shift_data;
-- Returns all zeroes std_logic_vector of specified size
function all_zeroes (number_of_zeroes : in positive) return std_logic_vector is
variable zero_array : std_logic_vector(0 to number_of_zeroes-1);
begin
for i in zero_array'range loop
zero_array(i) := '0';
end loop;
return zero_array;
end function all_zeroes;
begin
volt_data <= "00000000000000000000000000001111";
UE <= '0';
CE <= '0';
SE <= '0';
toSI <= '0';
-- Reset iJTAG chain and Instruments
RST <= '1';
wait for tck_period;
RST <= '0';
SEL <= '1';
tck_tick(4);
--shift_data("00000000000000000000000000000000");
--shift_data("11100000000000000000000000000000"); -- shift in threshold H without update enable
shift_data("00001"&"11100"&"1"&"1"&"1"&"0000000000000001111"); -- shift in threshold H without update
tck_tick(4);
volt_data <= "00000000000000000000000000000000";
tck_tick(1);
volt_data <= "00000000000000000000000000000001";
tck_tick(1);
volt_data <= "00000000000000000000000000000011";
tck_tick(1);
volt_data <= "00000000000000000000000000000111";
tck_tick(1);
volt_data <= "00000000000000000000000000001111";
tck_tick(1);
volt_data <= "00000000000000000000000000011111";
tck_tick(1);
volt_data <= "00000000000000000000000000111111";
tck_tick(1);
volt_data <= "00000000000000000000000001111111";
tck_tick(1);
volt_data <= "00000000000000000000000011111111";
tck_tick(1);
volt_data <= "00000000000000000000000111111111";
tck_tick(1);
volt_data <= "00000000000000000000001111111111";
tck_tick(1);
volt_data <= "00000000000000000000011111111111";
tck_tick(1);
volt_data <= "00000000000000000000111111111111";
tck_tick(1);
volt_data <= "00000000000000000001111111111111";
tck_tick(1);
volt_data <= "00000000000000000011111111111111";
tck_tick(1);
volt_data <= "00000000000000000111111111111111";
tck_tick(1);
volt_data <= "00000000000000001111111111111111";
tck_tick(1);
volt_data <= "00000000000000011111111111111111";
tck_tick(1);
volt_data <= "00000000000000111111111111111111";
tck_tick(1);
volt_data <= "00000000000001111111111111111111";
tck_tick(1);
volt_data <= "00000000000011111111111111111111";
tck_tick(1);
volt_data <= "00000000000111111111111111111111";
tck_tick(1);
volt_data <= "00000000001111111111111111111111";
tck_tick(1);
volt_data <= "00000000011111111111111111111111";
tck_tick(1);
volt_data <= "00000000111111111111111111111111";
tck_tick(1);
volt_data <= "00000001111111111111111111111111";
tck_tick(1);
volt_data <= "00000011111111111111111111111111";
tck_tick(1);
volt_data <= "00000111111111111111111111111111";
tck_tick(1);
volt_data <= "00001111111111111111111111111111";
tck_tick(1);
volt_data <= "00011111111111111111111111111111";
tck_tick(1);
volt_data <= "00111111111111111111111111111111";
tck_tick(1);
volt_data <= "01111111111111111111111111111111";
tck_tick(1);
volt_data <= "11111111111111111111111111111111";
tck_tick(1);
wait;
end process;
end Behavioral;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_a_e
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:41:45 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../constant.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-e.vhd,v 1.3 2004/08/18 10:47:00 wig Exp $
-- $Date: 2004/08/18 10:47:00 $
-- $Log: inst_a_e-e.vhd,v $
-- Revision 1.3 2004/08/18 10:47:00 wig
-- reworked some testcases
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.32 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_a_e
--
entity inst_a_e is
-- Generics:
-- No Generated Generics for Entity inst_a_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_a_e
end inst_a_e;
--
-- End of Generated Entity inst_a_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
use IEEE.numeric_std.all;
use work.MurmurHashUtils.ALL;
entity ImplementationTest1 is
port(
--entradas
clk : in std_logic;
inputData : in std_logic_vector(7 downto 0);
--salidas
canAccept_output : out std_logic;
resultReady_output : out std_logic;
result_output : out std_logic_vector(31 downto 0)
);
end entity ImplementationTest1;
architecture structural of ImplementationTest1 is
-- generar un registro de salto en la entrada para generar las entradas
-- al modulo
type registroEntradas is array (27 downto 0) of std_logic_vector(7 downto 0);
signal registro : registroEntradas;
signal resultID_output : std_logic_vector(31 downto 0);
-- signal dataStep1_dbg : std_logic_vector(31 downto 0);
-- signal dataStep2_dbg : std_logic_vector(31 downto 0);
-- signal dataStep3_dbg : std_logic_vector(31 downto 0);
-- signal dataStep4_dbg : std_logic_vector(31 downto 0);
-- signal dataStep5_dbg : std_logic_vector(31 downto 0);
-- signal dataStep1_ID_dbg : std_logic_vector(31 downto 0);
-- signal dataStep2_ID_dbg : std_logic_vector(31 downto 0);
-- signal dataStep3_ID_dbg : std_logic_vector(31 downto 0);
-- signal dataStep4_ID_dbg : std_logic_vector(31 downto 0);
-- signal dataStep5_ID_dbg : std_logic_vector(31 downto 0);
-- signal finalStep1_dbg : out std_logic_vector(31 downto 0);
-- signal finalStep2_dbg : out std_logic_vector(31 downto 0);
-- signal finalStep3_dbg : out std_logic_vector(31 downto 0);
-- signal finalStep4_dbg : out std_logic_vector(31 downto 0);
-- signal finalStep5_dbg : out std_logic_vector(31 downto 0)
-- signal finalStep1_ID_dbg : out std_logic_vector(31 downto 0);
-- signal finalStep2_ID_dbg : out std_logic_vector(31 downto 0);
-- signal finalStep3_ID_dbg : out std_logic_vector(31 downto 0);
-- signal finalStep4_ID_dbg : out std_logic_vector(31 downto 0);
-- signal finalStep5_ID_dbg : out std_logic_vector(31 downto 0)
signal inputBlock : std_logic_vector(31 downto 0);
signal operationID : std_logic_vector(31 downto 0);
signal seed : std_logic_vector(31 downto 0);
begin
-- generar al logica del registro de salto
--EntradaDatos: process( clk, registro, inputData) begin
-- if rising_edge(clk) then
-- end if;--clk
--end process EntradaDatos;
salto: for i in 0 to 27 generate
first_reg: if i=0 generate
clk0: process(clk, inputData) begin
if rising_edge(clk)then
registro(0)<= inputData;
end if;
end process clk0;
end generate first_reg;
restOf_reg: if i>0 generate
clkall: process(clk, registro) begin
if rising_edge(clk)then
registro(i)<= registro(i-1);
end if;
end process clkall;
end generate restOf_reg;
end generate salto;
inputBlock <= registro(0)®istro(1)®istro(2)®istro(3);
operationID <= registro(8)®istro(9)®istro(10)®istro(11);
seed <= registro(12)®istro(13)®istro(14)®istro(15);
--instanciar el modulo a probar
hashGenerator: work.MurmurHashUtils.MurmurHash32Generator port map
(
--entradas
inputBlock => inputBlock ,
readInput => registro(4)(0),
blockLength => registro(5)(1 downto 0),
finalBlock => registro(6)(0),
start => registro(7)(0),
operationID => (others => '-'),
seed => seed,
--salidas
canAccept => canAccept_output,
resultReady => resultReady_output,
result => open,
resultID => open,
clk => clk,
dataStep1_dbg => open,
dataStep2_dbg => open,
dataStep3_dbg => open,
dataStep4_dbg => open,
dataStep5_dbg => open,
dataStep1_ID_dbg => open,
dataStep2_ID_dbg => open,
dataStep3_ID_dbg => open,
dataStep4_ID_dbg => open,
dataStep5_ID_dbg => open,
finalStep1_dbg => open,
finalStep2_dbg => open,
finalStep3_dbg => open,
finalStep4_dbg => open,
finalStep5_dbg => open,
finalStep1_ID_dbg => open,
finalStep2_ID_dbg => open,
finalStep3_ID_dbg => open,
finalStep4_ID_dbg => open,
finalStep5_ID_dbg => open
);
end architecture structural;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2379.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p03n01i02379ent IS
END c07s03b02x00p03n01i02379ent;
ARCHITECTURE c07s03b02x00p03n01i02379arch OF c07s03b02x00p03n01i02379ent IS
BEGIN
TESTING: PROCESS
type T1 is array (1 to 5) of integer;
constant C1 : T1 := (1 => 0, 2 => 2,others 4) ; -- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x00p03n01i02379 - Missing operator."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p03n01i02379arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2379.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p03n01i02379ent IS
END c07s03b02x00p03n01i02379ent;
ARCHITECTURE c07s03b02x00p03n01i02379arch OF c07s03b02x00p03n01i02379ent IS
BEGIN
TESTING: PROCESS
type T1 is array (1 to 5) of integer;
constant C1 : T1 := (1 => 0, 2 => 2,others 4) ; -- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x00p03n01i02379 - Missing operator."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p03n01i02379arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2379.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p03n01i02379ent IS
END c07s03b02x00p03n01i02379ent;
ARCHITECTURE c07s03b02x00p03n01i02379arch OF c07s03b02x00p03n01i02379ent IS
BEGIN
TESTING: PROCESS
type T1 is array (1 to 5) of integer;
constant C1 : T1 := (1 => 0, 2 => 2,others 4) ; -- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x00p03n01i02379 - Missing operator."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p03n01i02379arch;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Package: Project specific configuration.
--
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------
-- This file was created from the template file:
--
-- <PoCRoot>/src/common/my_config.template.vhdl
--
-- and customized for:
--
-- Spartan-3 Starter Kit with a XC3S1000 FPGA
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "S3SK"; -- Spartan-3 Starter Kit
constant MY_DEVICE : string := "XC3S1000-FT2564C";
-- For internal use only
constant MY_VERBOSE : boolean := true;
end package;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Package: Project specific configuration.
--
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------
-- This file was created from the template file:
--
-- <PoCRoot>/src/common/my_config.template.vhdl
--
-- and customized for:
--
-- Spartan-3 Starter Kit with a XC3S1000 FPGA
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "S3SK"; -- Spartan-3 Starter Kit
constant MY_DEVICE : string := "XC3S1000-FT2564C";
-- For internal use only
constant MY_VERBOSE : boolean := true;
end package;
|
library ieee;
use ieee.std_logic_1164.all;
entity LFSR_In is
generic (n:integer := 2);
port(
CLK: in std_logic;
RST: in std_logic;
LS: in std_logic;
Pin: in std_logic_vector(0 to 2**n-1);
Pout: out std_logic_vector(0 to 2**n-1)
);
end LFSR_In;
architecture behavior of LFSR_In is
signal sreg: std_logic_vector(0 to 2**n-1);
signal sdat: std_logic_vector(0 to 2**n-1);
signal buf: std_logic;
Begin
Main: process (CLK, RST, sdat)
begin
if RST = '1' then
sreg <= (others => '0');
elsif rising_edge(CLK) then
sreg <= sdat;
end if;
end process;
Data: process (LS, Pin, sreg)
begin
if LS = '0' then
sdat <= Pin;
else
buf <= sreg(0) xor sreg(2**n-1);
sdat <= sreg(2**n-1) & sreg(0 to 2**n-2);
sdat(2) <= buf;
end if;
end process;
Pout <= sreg;
End behavior; |
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